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Save exception registers on stack.

This commit is contained in:
imi415 2022-05-02 13:19:54 +08:00
parent 4011c08237
commit 644ee17b3d
Signed by: imi415
GPG Key ID: 885EC2B5A8A6F8A7
1 changed files with 140 additions and 8 deletions
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148
BSP/Startup/startup_ch32v30x_D8C.S
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@ -11,120 +11,225 @@
.section .vectors,"ax",@progbits
.global _start
.align 4
.option push
.option norvc
_start:
j Reset_Handler /* Go! */
/**
* The only mode WCH didn't break is MODE 0, non-vectored exception.
* We place the jump table here, but processed by software.
*
* We use `jr t1` to locate the vector table, pop t1 from stack before jumping.
*/
.align 8
.option push
.option norvc
_vectors:
nop
j Exception_Handler /* 0: Exception */
lw t1, 0(sp)
j Default_Handler /* 1: Reserved */
lw t1, 0(sp)
j NMI_Handler /* 2: NMI */
lw t1, 0(sp)
j Default_Handler /* 3: Reserved */
lw t1, 0(sp)
j Default_Handler /* 4: Reserved */
lw t1, 0(sp)
j Default_Handler /* 5: Reserved */
lw t1, 0(sp)
j Default_Handler /* 6: Reserved */
lw t1, 0(sp)
j Default_Handler /* 7: Reserved */
lw t1, 0(sp)
j Default_Handler /* 8: Reserved */
lw t1, 0(sp)
j Default_Handler /* 9: Reserved */
lw t1, 0(sp)
j Default_Handler /* 10: Reserved */
lw t1, 0(sp)
j Default_Handler /* 11: Reserved */
lw t1, 0(sp)
j SysTick_Handler /* 12: SysTick */
lw t1, 0(sp)
j Default_Handler /* 13: Reserved */
lw t1, 0(sp)
j SW_Handler /* 14: Software */
lw t1, 0(sp)
j Default_Handler /* 15: Reserved */
lw t1, 0(sp)
j WWDG_IRQHandler /* 16: Window Watchdog */
lw t1, 0(sp)
j PVD_IRQHandler /* 17: PVD through EXTI Line detect */
lw t1, 0(sp)
j TAMPER_IRQHandler /* 18: TAMPER */
lw t1, 0(sp)
j RTC_IRQHandler /* 19: RTC */
lw t1, 0(sp)
j FLASH_IRQHandler /* 20: Flash */
lw t1, 0(sp)
j RCC_IRQHandler /* 21: RCC */
lw t1, 0(sp)
j EXTI0_IRQHandler /* 22: EXTI Line 0 */
lw t1, 0(sp)
j EXTI1_IRQHandler /* 23: EXTI Line 1 */
lw t1, 0(sp)
j EXTI2_IRQHandler /* 24: EXTI Line 2 */
lw t1, 0(sp)
j EXTI3_IRQHandler /* 25: EXTI Line 3 */
lw t1, 0(sp)
j EXTI4_IRQHandler /* 26: EXTI Line 4 */
lw t1, 0(sp)
j DMA1_Channel1_IRQHandler /* 27: DMA1 Channel 1 */
lw t1, 0(sp)
j DMA1_Channel2_IRQHandler /* 28: DMA1 Channel 2 */
lw t1, 0(sp)
j DMA1_Channel3_IRQHandler /* 29: DMA1 Channel 3 */
lw t1, 0(sp)
j DMA1_Channel4_IRQHandler /* 30: DMA1 Channel 4 */
lw t1, 0(sp)
j DMA1_Channel5_IRQHandler /* 31: DMA1 Channel 5 */
lw t1, 0(sp)
j DMA1_Channel6_IRQHandler /* 32: DMA1 Channel 6 */
lw t1, 0(sp)
j DMA1_Channel7_IRQHandler /* 33: DMA1 Channel 7 */
lw t1, 0(sp)
j ADC1_2_IRQHandler /* 34: ADC1_2 */
lw t1, 0(sp)
j USB_HP_CAN1_TX_IRQHandler /* 35: USB HP and CAN1 TX */
lw t1, 0(sp)
j USB_LP_CAN1_RX0_IRQHandler /* 36: USB LP and CAN1RX0 */
lw t1, 0(sp)
j CAN1_RX1_IRQHandler /* 37: CAN1 RX1 */
lw t1, 0(sp)
j CAN1_SCE_IRQHandler /* 38: CAN1 SCE */
lw t1, 0(sp)
j EXTI9_5_IRQHandler /* 39: EXTI Line 9..5 */
lw t1, 0(sp)
j TIM1_BRK_IRQHandler /* 40: TIM1 Break */
lw t1, 0(sp)
j TIM1_UP_IRQHandler /* 41: TIM1 Update */
lw t1, 0(sp)
j TIM1_TRG_COM_IRQHandler /* 42: TIM1 Trigger and Commutation */
lw t1, 0(sp)
j TIM1_CC_IRQHandler /* 43: TIM1 Capture Compare */
lw t1, 0(sp)
j TIM2_IRQHandler /* 44: TIM2 */
lw t1, 0(sp)
j TIM3_IRQHandler /* 45: TIM3 */
lw t1, 0(sp)
j TIM4_IRQHandler /* 46: TIM4 */
lw t1, 0(sp)
j I2C1_EV_IRQHandler /* 47: I2C1 Event */
lw t1, 0(sp)
j I2C1_ER_IRQHandler /* 48: I2C1 Error */
lw t1, 0(sp)
j I2C2_EV_IRQHandler /* 49: I2C2 Event */
lw t1, 0(sp)
j I2C2_ER_IRQHandler /* 50: I2C2 Error */
lw t1, 0(sp)
j SPI1_IRQHandler /* 51: SPI1 */
lw t1, 0(sp)
j SPI2_IRQHandler /* 52: SPI2 */
lw t1, 0(sp)
j USART1_IRQHandler /* 53: USART1 */
lw t1, 0(sp)
j USART2_IRQHandler /* 54: USART2 */
lw t1, 0(sp)
j USART3_IRQHandler /* 55: USART3 */
lw t1, 0(sp)
j EXTI15_10_IRQHandler /* 56: EXTI Line 15..10 */
lw t1, 0(sp)
j RTCAlarm_IRQHandler /* 57: RTC Alarm through EXTI Line */
lw t1, 0(sp)
j USBWakeUp_IRQHandler /* 58: USB Wakeup from suspend */
lw t1, 0(sp)
j TIM8_BRK_IRQHandler /* 59: TIM8 Break */
lw t1, 0(sp)
j TIM8_UP_IRQHandler /* 60: TIM8 Update */
lw t1, 0(sp)
j TIM8_TRG_COM_IRQHandler /* 61: TIM8 Trigger and Commutation */
lw t1, 0(sp)
j TIM8_CC_IRQHandler /* 62: TIM8 Capture Compare */
lw t1, 0(sp)
j RNG_IRQHandler /* 63: RNG */
lw t1, 0(sp)
j FSMC_IRQHandler /* 64: FSMC */
lw t1, 0(sp)
j SDIO_IRQHandler /* 65: SDIO */
lw t1, 0(sp)
j TIM5_IRQHandler /* 66: TIM5 */
lw t1, 0(sp)
j SPI3_IRQHandler /* 67: SPI3 */
lw t1, 0(sp)
j UART4_IRQHandler /* 68: UART4 */
lw t1, 0(sp)
j UART5_IRQHandler /* 69: UART5 */
lw t1, 0(sp)
j TIM6_IRQHandler /* 70: TIM6 */
lw t1, 0(sp)
j TIM7_IRQHandler /* 71: TIM7 */
lw t1, 0(sp)
j DMA2_Channel1_IRQHandler /* 72: DMA2 Channel 1 */
lw t1, 0(sp)
j DMA2_Channel2_IRQHandler /* 73: DMA2 Channel 2 */
lw t1, 0(sp)
j DMA2_Channel3_IRQHandler /* 74: DMA2 Channel 3 */
lw t1, 0(sp)
j DMA2_Channel4_IRQHandler /* 75: DMA2 Channel 4 */
lw t1, 0(sp)
j DMA2_Channel5_IRQHandler /* 76: DMA2 Channel 5 */
lw t1, 0(sp)
j ETH_IRQHandler /* 77: ETH */
lw t1, 0(sp)
j ETH_WKUP_IRQHandler /* 78: ETH WakeUp */
lw t1, 0(sp)
j CAN2_TX_IRQHandler /* 79: CAN2 TX */
lw t1, 0(sp)
j CAN2_RX0_IRQHandler /* 80: CAN2 RX0 */
lw t1, 0(sp)
j CAN2_RX1_IRQHandler /* 81: CAN2 RX1 */
lw t1, 0(sp)
j CAN2_SCE_IRQHandler /* 82: CAN2 SCE */
lw t1, 0(sp)
j OTG_FS_IRQHandler /* 83: OTGFS */
lw t1, 0(sp)
j USBHSWakeup_IRQHandler /* 84: USBHS Wakeup */
lw t1, 0(sp)
j USBHS_IRQHandler /* 85: USBHS */
lw t1, 0(sp)
j DVP_IRQHandler /* 86: DVP */
lw t1, 0(sp)
j UART6_IRQHandler /* 87: UART6 */
lw t1, 0(sp)
j UART7_IRQHandler /* 88: UART7 */
lw t1, 0(sp)
j UART8_IRQHandler /* 89: UART8 */
lw t1, 0(sp)
j TIM9_BRK_IRQHandler /* 90: TIM9 Break */
lw t1, 0(sp)
j TIM9_UP_IRQHandler /* 91: TIM9 Update */
lw t1, 0(sp)
j TIM9_TRG_COM_IRQHandler /* 92: TIM9 Trigger and Commutation */
lw t1, 0(sp)
j TIM9_CC_IRQHandler /* 93: TIM9 Capture Compare */
lw t1, 0(sp)
j TIM10_BRK_IRQHandler /* 94: TIM10 Break */
lw t1, 0(sp)
j TIM10_UP_IRQHandler /* 95: TIM10 Update */
lw t1, 0(sp)
j TIM10_TRG_COM_IRQHandler /* 96: TIM10 Trigger and Commutation */
lw t1, 0(sp)
j TIM10_CC_IRQHandler /* 97: TIM10 Capture Compare */
lw t1, 0(sp)
j DMA2_Channel6_IRQHandler /* 98: DMA2 Channel 6 */
lw t1, 0(sp)
j DMA2_Channel7_IRQHandler /* 99: DMA2 Channel 7 */
lw t1, 0(sp)
j DMA2_Channel8_IRQHandler /* 100: DMA2 Channel 8 */
lw t1, 0(sp)
j DMA2_Channel9_IRQHandler /* 101: DMA2 Channel 9 */
lw t1, 0(sp)
j DMA2_Channel10_IRQHandler /* 102: DMA2 Channel 10 */
lw t1, 0(sp)
j DMA2_Channel11_IRQHandler /* 103: DMA2 Channel 11 */
.option pop
@ -189,16 +294,43 @@ dead_loop:
j dead_loop
Exception_Handler:
addi sp, sp, -8
sw t0, 4(sp)
sw t1, 8(sp)
csrr t0, mcause
ble t0, x0, Interrupt_Handler /* Check interrupt */
ble t0, x0, interrupt_handler /* Check interrupt */
li t1, 11 /* Find an M mode ecall (11) */
beq t1, t0, Ecall_M_Handler
beq t1, t0, ecall_m_handler
li t1, 8
beq t1, t0, Ecall_U_Handler
beq t1, t0, ecall_u_handler
j fault_handler
ecall_m_handler:
lw t0, 4(sp)
lw t1, 8(sp)
addi sp, sp, 8
j Ecall_M_Handler
ecall_u_handler:
lw t0, 4(sp)
lw t1, 8(sp)
addi sp, sp, 8
j Ecall_U_Handler
fault_handler:
lw t0, 4(sp)
lw t1, 8(sp)
addi sp, sp, 8
j Fault_Handler
Interrupt_Handler: /* Home made vector table */
slli t0, t0, 2
interrupt_handler: /* Home made vector table */
slli t0, t0, 3 /* t0 = t0 * 8 */
la t1, _vectors
add t1, t1, t0
lw t0, 4(sp)
addi sp, sp, 8
jr t1