134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v30x_dvp.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : This file provides all the DVP firmware functions.
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#include "ch32v30x_dvp.h"
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/*********************************************************************
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* @fn DVP_INTCfg
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*
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* @brief DVP interrupt configuration
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*
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* @param s - interrupt enable
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* ENABLE
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* DISABLE
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* i - interrupt type
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* RB_DVP_IE_STP_FRM
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* RB_DVP_IE_FIFO_OV
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* RB_DVP_IE_FRM_DONE
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* RB_DVP_IE_ROW_DONE
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* RB_DVP_IE_STR_FRM
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*
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* @return none
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*/
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void DVP_INTCfg(uint8_t s, uint8_t i)
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{
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if(s)
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{
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DVP->IER |= i;
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}
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else
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{
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DVP->IER &= ~i;
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}
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}
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/*********************************************************************
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* @fn DVP_Mode
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*
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* @brief DVP mode
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*
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* @param s - data bit width
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* RB_DVP_D8_MOD
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* RB_DVP_D10_MOD
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* RB_DVP_D12_MOD
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* i - interrupt type
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* Video_Mode
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* JPEG_Mode
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*
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* @return none
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*/
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void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
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{
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DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
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if(s)
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{
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DVP->CR0 |= s;
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}
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else
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{
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DVP->CR0 &= ~(3 << 4);
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}
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if(i)
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{
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DVP->CR0 |= RB_DVP_JPEG;
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}
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else
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{
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DVP->CR0 &= ~RB_DVP_JPEG;
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}
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}
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/*********************************************************************
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* @fn DVP_Cfg
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*
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* @brief DVP configuration
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*
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* @param s - DMA enable control
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* DVP_DMA_Enable
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* DVP_DMA_Disable
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* i - DVP all clear
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* DVP_FLAG_FIFO_RESET_Enable
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* DVP_FLAG_FIFO_RESET_Disable
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* j - receive reset enable
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* DVP_RX_RESET_Enable
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* DVP_RX_RESET_Disable
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*
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* @return none
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*/
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void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
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{
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switch(s)
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{
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case DVP_DMA_Enable:
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DVP->CR1 |= RB_DVP_DMA_EN;
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break;
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case DVP_DMA_Disable:
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DVP->CR1 &= ~RB_DVP_DMA_EN;
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break;
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default:
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break;
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}
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switch(i)
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{
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case DVP_RX_RESET_Enable:
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DVP->CR1 |= RB_DVP_ALL_CLR;
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break;
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case DVP_RX_RESET_Disable:
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DVP->CR1 &= ~RB_DVP_ALL_CLR;
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break;
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default:
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break;
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}
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switch(j)
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{
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case DVP_RX_RESET_Enable:
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DVP->CR1 |= RB_DVP_RCV_CLR;
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break;
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case DVP_RX_RESET_Disable:
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DVP->CR1 &= ~RB_DVP_RCV_CLR;
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break;
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default:
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break;
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}
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}
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