From d8c9bfc8fedc8d7b214fc20b83a0e456c15329d2 Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Wed, 28 Feb 2024 15:36:54 +0800 Subject: [PATCH] Added original FSP BSP. Signed-off-by: Yilin Sun --- .clang-format | 12 + .gitignore | 5 + .gitmodules | 3 + CMakeLists.txt | 33 +- GCC/RA6M5_1M/memory_regions.ld | 29 ++ GCC/fsp_flash.ld | 766 ++++++++++++++++++++++++++++++ GCC/fsp_ram.ld | 766 ++++++++++++++++++++++++++++++ SDK/CMSIS | 1 + arm-none-eabi.cmake | 4 +- board/board.c | 9 + board/bsp/board_cfg.h | 13 + board/bsp/bsp_cfg.h | 62 +++ board/bsp/bsp_clock_cfg.h | 35 ++ board/bsp/bsp_mcu_device_cfg.h | 5 + board/bsp/bsp_mcu_device_pn_cfg.h | 11 + board/bsp/bsp_mcu_family_cfg.h | 390 +++++++++++++++ board/bsp/bsp_pin_cfg.h | 19 + board/bsp/r_ioport_cfg.h | 13 + board/common_data.c | 8 + board/common_data.h | 20 + board/hal_data.c | 6 + board/hal_data.h | 11 + board/pin_data.c | 54 +++ board/vector_data.c | 17 + board/vector_data.h | 20 + 25 files changed, 2308 insertions(+), 4 deletions(-) create mode 100644 .clang-format create mode 100644 .gitignore create mode 100644 GCC/RA6M5_1M/memory_regions.ld create mode 100644 GCC/fsp_flash.ld create mode 100644 GCC/fsp_ram.ld create mode 160000 SDK/CMSIS create mode 100644 board/board.c create mode 100644 board/bsp/board_cfg.h create mode 100644 board/bsp/bsp_cfg.h create mode 100644 board/bsp/bsp_clock_cfg.h create mode 100644 board/bsp/bsp_mcu_device_cfg.h create mode 100644 board/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 board/bsp/bsp_mcu_family_cfg.h create mode 100644 board/bsp/bsp_pin_cfg.h create mode 100644 board/bsp/r_ioport_cfg.h create mode 100644 board/common_data.c create mode 100644 board/common_data.h create mode 100644 board/hal_data.c create mode 100644 board/hal_data.h create mode 100644 board/pin_data.c create mode 100644 board/vector_data.c create mode 100644 board/vector_data.h diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..214adf0 --- /dev/null +++ b/.clang-format @@ -0,0 +1,12 @@ +BasedOnStyle: Google +IndentWidth: 4 +AlignConsecutiveMacros: Consecutive +AlignConsecutiveDeclarations: Consecutive +AlignConsecutiveAssignments: Consecutive +AllowShortFunctionsOnASingleLine: None +BreakBeforeBraces: Custom +BraceWrapping: + AfterEnum: false + AfterStruct: false + SplitEmptyFunction: false +ColumnLimit: 120 \ No newline at end of file diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..2da6168 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +/cmake-build-* +/build +/board/*.bak +/.vscode + diff --git a/.gitmodules b/.gitmodules index 76d460f..4468c45 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "SDK/fsp"] path = SDK/fsp url = https://github.com/renesas/fsp.git +[submodule "SDK/CMSIS"] + path = SDK/CMSIS + url = https://github.com/ARM-software/CMSIS_6.git diff --git a/CMakeLists.txt b/CMakeLists.txt index e175a4e..9133b0f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -6,17 +6,45 @@ enable_language(CXX) enable_language(ASM) # Different linker scripts -set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/app_flash.ld") -set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/app_ram.ld") +set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/GCC/fsp_flash.ld") +set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/GCC/fsp_ram.ld") set(TARGET_SOURCES + "SDK/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c" + "SDK/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c" + "SDK/fsp/ra/fsp/src/r_ioport/r_ioport.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c" + "SDK/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c" + "board/board.c" + "board/common_data.c" + "board/hal_data.c" + "board/pin_data.c" + "board/vector_data.c" "src/main.c" ) set(TARGET_C_DEFINES + "_RENESAS_RA_" + "_RA_CORE=CM33" + "_RA_ORDINAL=1" ) set(TARGET_C_INCLUDES + "SDK/CMSIS/CMSIS/Core/Include" + "SDK/fsp/ra/fsp/inc" + "SDK/fsp/ra/fsp/inc/api" + "SDK/fsp/ra/fsp/inc/instances" + "board" + "board/bsp" "include" ) @@ -29,6 +57,7 @@ set(TARGET_LIBS # Shared library and linker script search paths set(TARGET_LIB_DIRECTORIES + "GCC/RA6M5_1M" ) # Conditional flags diff --git a/GCC/RA6M5_1M/memory_regions.ld b/GCC/RA6M5_1M/memory_regions.ld new file mode 100644 index 0000000..5a0461f --- /dev/null +++ b/GCC/RA6M5_1M/memory_regions.ld @@ -0,0 +1,29 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x00080000; /* 512kB */ + +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x00100000; /* 1MB */ + +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x00002000; + +OPTION_SETTING_START = 0x0100A100; +OPTION_SETTING_LENGTH = 0x00000100; + +OPTION_SETTING_S_START = 0x0100A200; +OPTION_SETTING_S_LENGTH = 0x00000100; + +ID_CODE_START = 0x00000000; +ID_CODE_LENGTH = 0x00000000; + +SDRAM_START = 0x80010000; +SDRAM_LENGTH = 0x00000000; + +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x04000000; + +OSPI_DEVICE_0_START = 0x68000000; +OSPI_DEVICE_0_LENGTH = 0x08000000; + +OSPI_DEVICE_1_START = 0x70000000; +OSPI_DEVICE_1_LENGTH = 0x10000000; diff --git a/GCC/fsp_flash.ld b/GCC/fsp_flash.ld new file mode 100644 index 0000000..4eaf66f --- /dev/null +++ b/GCC/fsp_flash.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + . = ALIGN(128); + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} \ No newline at end of file diff --git a/GCC/fsp_ram.ld b/GCC/fsp_ram.ld new file mode 100644 index 0000000..4eaf66f --- /dev/null +++ b/GCC/fsp_ram.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + . = ALIGN(128); + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} \ No newline at end of file diff --git a/SDK/CMSIS b/SDK/CMSIS new file mode 160000 index 0000000..4d18b8d --- /dev/null +++ b/SDK/CMSIS @@ -0,0 +1 @@ +Subproject commit 4d18b8de66ce12e38c3d933a9e5fbe642b71763d diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake index 2b68248..be090f8 100644 --- a/arm-none-eabi.cmake +++ b/arm-none-eabi.cmake @@ -9,8 +9,8 @@ set(CMAKE_CXX_COMPILER arm-none-eabi-g++) # Optionally set size binary name, for elf section size reporting. set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size) -set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m0plus -mthumb -mfloat-abi=soft") -set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m0plus -mthumb -mfloat-abi=soft") +set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard") +set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard") set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments") # Make CMake happy about those compilers diff --git a/board/board.c b/board/board.c new file mode 100644 index 0000000..b330407 --- /dev/null +++ b/board/board.c @@ -0,0 +1,9 @@ +#include "hal_data.h" + +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + } + if (BSP_WARM_START_POST_C == event) { + IOPORT_CFG_OPEN(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); + } +} diff --git a/board/bsp/board_cfg.h b/board/bsp/board_cfg.h new file mode 100644 index 0000000..e257725 --- /dev/null +++ b/board/bsp/board_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +void bsp_init(void *p_args); + +#ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/board/bsp/bsp_cfg.h b/board/bsp/bsp_cfg.h new file mode 100644 index 0000000..f7e1787 --- /dev/null +++ b/board/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else +#define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/board/bsp/bsp_clock_cfg.h b/board/bsp/bsp_clock_cfg.h new file mode 100644 index 0000000..f6e0eb4 --- /dev/null +++ b/board/bsp/bsp_clock_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/board/bsp/bsp_mcu_device_cfg.h b/board/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000..41b40ab --- /dev/null +++ b/board/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/board/bsp/bsp_mcu_device_pn_cfg.h b/board/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000..8c00573 --- /dev/null +++ b/board/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BF2CBG +#define BSP_MCU_FEATURE_SET ('B') +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_BGA +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/board/bsp/bsp_mcu_family_cfg.h b/board/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 0000000..4700aa7 --- /dev/null +++ b/board/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,390 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +/* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL +#define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/board/bsp/bsp_pin_cfg.h b/board/bsp/bsp_pin_cfg.h new file mode 100644 index 0000000..03d1d24 --- /dev/null +++ b/board/bsp/bsp_pin_cfg.h @@ -0,0 +1,19 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#if __has_include("r_ioport.h") +#include "r_ioport.h" +#elif __has_include("r_ioport_b.h") +#include "r_ioport_b.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BF2CBG.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/board/bsp/r_ioport_cfg.h b/board/bsp/r_ioport_cfg.h new file mode 100644 index 0000000..8b8a39e --- /dev/null +++ b/board/bsp/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/board/common_data.c b/board/common_data.c new file mode 100644 index 0000000..7eb163c --- /dev/null +++ b/board/common_data.c @@ -0,0 +1,8 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) +{ +} diff --git a/board/common_data.h b/board/common_data.h new file mode 100644 index 0000000..fa1c88e --- /dev/null +++ b/board/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/board/hal_data.c b/board/hal_data.c new file mode 100644 index 0000000..6ad1c2a --- /dev/null +++ b/board/hal_data.c @@ -0,0 +1,6 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +void g_hal_init(void) +{ + g_common_init (); +} diff --git a/board/hal_data.h b/board/hal_data.h new file mode 100644 index 0000000..14f3147 --- /dev/null +++ b/board/hal_data.h @@ -0,0 +1,11 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +FSP_HEADER +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/board/pin_data.c b/board/pin_data.c new file mode 100644 index 0000000..1cc9139 --- /dev/null +++ b/board/pin_data.c @@ -0,0 +1,54 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#if __has_include("r_ioport.h") +#include "r_ioport.h" +#elif __has_include("r_ioport_b.h") +#include "r_ioport_b.h" +#endif + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = + { + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_DEBUG) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if __has_include("r_ioport.h") +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif +#endif diff --git a/board/vector_data.c b/board/vector_data.c new file mode 100644 index 0000000..a80c6d3 --- /dev/null +++ b/board/vector_data.c @@ -0,0 +1,17 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 + #if __has_include("r_ioport.h") + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + }; + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = + { + }; + #elif __has_include("r_ioport_b.h") + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_IRQ_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + }; + #endif + #endif diff --git a/board/vector_data.h b/board/vector_data.h new file mode 100644 index 0000000..e8c2d61 --- /dev/null +++ b/board/vector_data.h @@ -0,0 +1,20 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +#ifdef __cplusplus + extern "C" { + #endif +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (0) +#endif +/* ISR prototypes */ + +#if __has_include("r_ioport.h") + /* Vector table allocations */ + #endif + +#ifdef __cplusplus + } + #endif +#endif /* VECTOR_DATA_H */