1349 lines
89 KiB
XML
1349 lines
89 KiB
XML
<?xml version="1.0" encoding= "UTF-8" ?>
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<configuration name="MCXN947" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_15 http://mcuxpresso.nxp.com/XSD/mex_configuration_15.xsd" uuid="61a550ca-b811-4a3a-aabb-19904e9c2f70" version="15" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_15" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<common>
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<processor>MCXN947</processor>
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<package>MCXN947VDF</package>
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<mcu_data>ksdk2_0</mcu_data>
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<cores selected="cm33_core0">
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<core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
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<core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
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</cores>
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<description></description>
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</common>
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<preferences>
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<validate_boot_init_only>true</validate_boot_init_only>
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<generate_extended_information>false</generate_extended_information>
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<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
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<update_include_paths>true</update_include_paths>
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<generate_registers_defines>false</generate_registers_defines>
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</preferences>
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<tools>
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<pins name="Pins" version="15.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/pin_mux.c" update_enabled="true"/>
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<file path="board/pin_mux.h" update_enabled="true"/>
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</generated_project_files>
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<pins_profile>
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<processor_version>15.1.0</processor_version>
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</pins_profile>
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<functions_list>
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<function name="BOARD_InitDbgUARTPins">
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<description>Configures pin routing and optionally pin electrical features.</description>
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<options>
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<callFromInitBoot>true</callFromInitBoot>
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<coreID>cm33_core0</coreID>
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<enableClock>true</enableClock>
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</options>
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<dependencies>
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<dependency resourceType="Peripheral" resourceId="LP_FLEXCOMM4" description="Peripheral LP_FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDbgUARTPins">
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<feature name="initialized" evaluation="equal">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDbgUARTPins">
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<feature name="initialized" evaluation="equal">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDbgUARTPins">
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<feature name="enabled" evaluation="equal" configuration="cm33_core0">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitDbgUARTPins">
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<feature name="enabled" evaluation="equal" configuration="cm33_core0">
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<data>true</data>
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</feature>
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</dependency>
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</dependencies>
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<pins>
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<pin peripheral="LP_FLEXCOMM4" signal="LPFLEXCOMM_P0" pin_num="A1" pin_signal="PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8">
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<pin_features>
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<pin_feature name="slew_rate" value="fast"/>
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<pin_feature name="open_drain" value="disable"/>
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<pin_feature name="drive_strength" value="low"/>
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<pin_feature name="pull_select" value="down"/>
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<pin_feature name="pull_enable" value="disable"/>
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<pin_feature name="passive_filter" value="disable"/>
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<pin_feature name="pull_value" value="low"/>
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<pin_feature name="input_buffer" value="enable"/>
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<pin_feature name="invert_input" value="normal"/>
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</pin_features>
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</pin>
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<pin peripheral="LP_FLEXCOMM4" signal="LPFLEXCOMM_P1" pin_num="B1" pin_signal="PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9">
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<pin_features>
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<pin_feature name="slew_rate" value="fast"/>
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<pin_feature name="open_drain" value="disable"/>
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<pin_feature name="drive_strength" value="low"/>
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<pin_feature name="pull_select" value="down"/>
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<pin_feature name="pull_enable" value="disable"/>
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<pin_feature name="passive_filter" value="disable"/>
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<pin_feature name="input_buffer" value="enable"/>
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<pin_feature name="invert_input" value="normal"/>
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</pin_features>
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</pin>
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<pin peripheral="SWD" signal="SWO" pin_num="B16" pin_signal="PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR">
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<pin_features>
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<pin_feature name="slew_rate" value="fast"/>
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<pin_feature name="open_drain" value="disable"/>
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<pin_feature name="drive_strength" value="high"/>
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<pin_feature name="pull_select" value="down"/>
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<pin_feature name="pull_enable" value="disable"/>
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<pin_feature name="input_buffer" value="enable"/>
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<pin_feature name="invert_input" value="normal"/>
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</pin_features>
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</pin>
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</pins>
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</function>
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</functions_list>
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</pins>
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<clocks name="Clocks" version="13.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/clock_config.c" update_enabled="true"/>
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<file path="board/clock_config.h" update_enabled="true"/>
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</generated_project_files>
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<clocks_profile>
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<processor_version>15.1.0</processor_version>
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</clocks_profile>
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<clock_configurations>
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<clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false">
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<description></description>
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<options/>
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<dependencies>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core1">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core0">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core1">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core0">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core1">
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<data>true</data>
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</feature>
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</dependency>
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<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
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<feature name="enabled" evaluation="equal" configuration="cm33_core0">
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<data>true</data>
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</feature>
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</dependency>
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</dependencies>
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<clock_sources/>
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<clock_outputs>
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<clock_output id="CLK_144M_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
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<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
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<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
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<clock_output id="FRO_HF_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
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<clock_output id="MAIN_clock.outFreq" value="150 MHz" locked="false" accuracy=""/>
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<clock_output id="PLL0_CLK_clock.outFreq" value="150 MHz" locked="false" accuracy=""/>
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<clock_output id="Slow_clock.outFreq" value="37.5 MHz" locked="false" accuracy=""/>
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<clock_output id="System_clock.outFreq" value="150 MHz" locked="false" accuracy=""/>
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<clock_output id="gdet_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
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<clock_output id="trng_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
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</clock_outputs>
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<clock_settings>
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<setting id="PLL0_Mode" value="Normal" locked="false"/>
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<setting id="RunPowerMode" value="OD" locked="false"/>
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<setting id="SCGMode" value="PLL0" locked="false"/>
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<setting id="SCG.PLL0M_MULT.scale" value="50" locked="true"/>
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<setting id="SCG.PLL0SRCSEL.sel" value="SCG.FIRC_48M" locked="false"/>
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<setting id="SCG.PLL0_NDIV.scale" value="8" locked="true"/>
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<setting id="SCG.SCSSEL.sel" value="SCG.PLL0_CLK" locked="false"/>
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<setting id="SYSCON.FLEXSPICLKSEL.sel" value="NO_CLOCK" locked="false"/>
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<setting id="SYSCON.FREQMEREFCLKSEL.sel" value="SYSCON.evtg_out0a" locked="false"/>
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<setting id="SYSCON.FREQMETARGETCLKSEL.sel" value="SYSCON.evtg_out0a" locked="false"/>
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</clock_settings>
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<called_from_default_init>true</called_from_default_init>
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</clock_configuration>
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</clock_configurations>
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</clocks>
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<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
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<generated_project_files/>
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<dcdx_profile>
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<processor_version>N/A</processor_version>
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</dcdx_profile>
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<dcdx_configurations/>
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</dcdx>
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<periphs name="Peripherals" version="14.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/peripherals.c" update_enabled="true"/>
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<file path="board/peripherals.h" update_enabled="true"/>
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</generated_project_files>
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<peripherals_profile>
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<processor_version>15.1.0</processor_version>
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</peripherals_profile>
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<functional_groups>
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<functional_group name="BOARD_InitPeripherals" uuid="d81bd7c9-7989-4ab0-a36e-0428ebb64fd6" called_from_default_init="true" id_prefix="" core="cm33_core0">
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<description></description>
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<options/>
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<dependencies/>
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<instances>
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<instance name="NVIC" uuid="0371275d-a957-4de6-bea5-19e7b05c08ba" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
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<config_set name="nvic">
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<array name="interrupt_table"/>
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<array name="interrupts"/>
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</config_set>
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</instance>
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</instances>
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</functional_group>
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</functional_groups>
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<components>
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<component name="system" uuid="2c78f6ea-4217-4c5d-87b0-b766298c415f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
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<config_set_global name="global_system_definitions">
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<setting name="user_definitions" value=""/>
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<setting name="user_includes" value=""/>
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<setting name="global_init" value=""/>
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</config_set_global>
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</component>
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<component name="generic_enet" uuid="223849eb-45e9-475f-b722-a62ca928f55e" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
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<config_set_global name="global_enet"/>
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</component>
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<component name="gpio_adapter_common" uuid="74daf651-863f-4b8b-94ca-9f6b112bc6fc" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
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<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
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</component>
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<component name="generic_uart" uuid="382f97dc-c1b8-4f0e-943b-955a7d58af00" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
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<config_set_global name="global_uart"/>
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</component>
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<component name="msg" uuid="f50e2c2d-90db-4d76-89d8-5040d3d16fdf" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
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<config_set_global name="global_messages"/>
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</component>
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<component name="uart_cmsis_common" uuid="8f5573b3-bd3f-4281-b1be-3cd2453f2230" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
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<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
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</component>
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<component name="generic_can" uuid="b5076902-4d46-4899-bb1f-9fbd52bef50f" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
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<config_set_global name="global_can"/>
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</component>
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</components>
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</periphs>
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<tee name="TEE" version="6.0" enabled="false" update_project_code="true">
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<generated_project_files/>
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<tee_profile>
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<processor_version>N/A</processor_version>
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<tool_options>
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<option id="_output_type_" value="c_code"/>
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<option id="_legacy_source_names_" value="yes"/>
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<option id="_resilient_code_reg_writes_" value="no"/>
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</tool_options>
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</tee_profile>
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<functional_group name="BOARD_InitTEE" called_from_default_init="true" id_prefix="" prefix_user_defined="false">
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<description></description>
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<options/>
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<ahbsc_rwx>
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<relative_region start="0" size="1048576" security="s_priv" memory="PROGRAM_FLASH0"/>
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<relative_region start="0" size="1048576" security="s_priv" memory="PROGRAM_FLASH1"/>
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<relative_region start="0" size="65536" security="s_priv" memory="FlashBank_IFR0"/>
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<relative_region start="0" size="16384" security="s_priv" memory="FlashBank_IFR1"/>
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<relative_region start="0" size="262144" security="s_priv" memory="BootROM"/>
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<relative_region start="0" size="98304" security="s_priv" memory="SRAMX"/>
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<relative_region start="0" size="32768" security="s_priv" memory="SRAMA"/>
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<relative_region start="0" size="32768" security="s_priv" memory="SRAMB"/>
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<relative_region start="0" size="65536" security="s_priv" memory="SRAMC"/>
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<relative_region start="0" size="65536" security="s_priv" memory="SRAMD"/>
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<relative_region start="0" size="65536" security="s_priv" memory="SRAME"/>
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<relative_region start="0" size="65536" security="s_priv" memory="SRAMF"/>
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<relative_region start="0" size="65536" security="s_priv" memory="SRAMG"/>
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<relative_region start="0" size="32768" security="s_priv" memory="SRAMH"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="SPI_FILTER"/>
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<relative_region start="0" size="4096" security="s_priv" memory="OSTIMER0"/>
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|
<relative_region start="0" size="4096" security="s_priv" memory="TRO0"/>
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|
<relative_region start="0" size="4096" security="s_priv" memory="PKC_RAM"/>
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|
<relative_region start="0" size="4096" security="s_priv" memory="USB_RAM"/>
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|
<relative_region start="0" size="4096" security="s_priv" memory="NPU"/>
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|
<relative_region start="0" size="4096" security="s_priv" memory="SFA"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="MBC"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN0_RULE1"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN0_RULE2"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN0_RULE3"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN1_RULE1"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN1_RULE2"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="CAN1_RULE3"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="MTR0"/>
|
|
<relative_region start="0" size="4096" security="s_priv" memory="ATX0"/>
|
|
<relative_region start="0" size="268435456" security="s_priv" memory="FlexSPI0_0"/>
|
|
<relative_region start="0" size="268435456" security="s_priv" memory="FlexSPI0_1"/>
|
|
<masters>
|
|
<master id="COOLFLUXI" security="ns_user"/>
|
|
<master id="CPU1" security="ns_user"/>
|
|
<master id="DMA3_0" security="ns_user"/>
|
|
<master id="DMA3_1" security="ns_user"/>
|
|
<master id="ETHERNET" security="ns_user"/>
|
|
<master id="NPUO" security="ns_user"/>
|
|
<master id="PKC" security="ns_user"/>
|
|
<master id="PQ" security="ns_user"/>
|
|
<master id="SMARTDMA" security="ns_user"/>
|
|
<master id="USB_FS" security="ns_user"/>
|
|
<master id="USB_HS" security="ns_user"/>
|
|
<master id="USDHC" security="ns_user"/>
|
|
</masters>
|
|
<peripherals>
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|
<peripheral id="ADC0" security="s_priv"/>
|
|
<peripheral id="ADC1" security="s_priv"/>
|
|
<peripheral id="AHBSC" security="s_priv"/>
|
|
<peripheral id="AHBSC_ALIAS1" security="s_priv"/>
|
|
<peripheral id="AHBSC_ALIAS2" security="s_priv"/>
|
|
<peripheral id="AHBSC_ALIAS3" security="s_priv"/>
|
|
<peripheral id="BSP32_0" security="s_priv"/>
|
|
<peripheral id="CACHE64_POLSEL0" security="s_priv"/>
|
|
<peripheral id="CAN0" security="s_priv"/>
|
|
<peripheral id="CAN1" security="s_priv"/>
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|
<peripheral id="CDOG0" security="s_priv"/>
|
|
<peripheral id="CDOG1" security="s_priv"/>
|
|
<peripheral id="CMP0" security="s_priv"/>
|
|
<peripheral id="CMP1" security="s_priv"/>
|
|
<peripheral id="CMP2" security="s_priv"/>
|
|
<peripheral id="CMX_PERFMON0" security="s_priv"/>
|
|
<peripheral id="CMX_PERFMON1" security="s_priv"/>
|
|
<peripheral id="CRC0" security="s_priv"/>
|
|
<peripheral id="CTIMER0" security="s_priv"/>
|
|
<peripheral id="CTIMER1" security="s_priv"/>
|
|
<peripheral id="CTIMER2" security="s_priv"/>
|
|
<peripheral id="CTIMER3" security="s_priv"/>
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|
<peripheral id="CTIMER4" security="s_priv"/>
|
|
<peripheral id="DAC0" security="s_priv"/>
|
|
<peripheral id="DAC1" security="s_priv"/>
|
|
<peripheral id="DAC2" security="s_priv"/>
|
|
<peripheral id="DM0" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS0" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS1" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS10" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS11" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS12" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS13" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS14" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS15" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS16" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS2" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS3" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS4" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS5" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS6" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS7" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS8" security="s_priv"/>
|
|
<peripheral id="DMA0_TEE_ALIAS9" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS0" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS1" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS10" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS11" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS12" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS13" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS14" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS15" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS16" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS2" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS3" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS4" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS5" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS6" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS7" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS8" security="s_priv"/>
|
|
<peripheral id="DMA1_TEE_ALIAS9" security="s_priv"/>
|
|
<peripheral id="EIM0" security="s_priv"/>
|
|
<peripheral id="ELS" security="s_priv"/>
|
|
<peripheral id="ELS_ALIAS1" security="s_priv"/>
|
|
<peripheral id="ELS_ALIAS2" security="s_priv"/>
|
|
<peripheral id="ELS_ALIAS3" security="s_priv"/>
|
|
<peripheral id="EMVSIM0" security="s_priv"/>
|
|
<peripheral id="EMVSIM1" security="s_priv"/>
|
|
<peripheral id="ENC0" security="s_priv"/>
|
|
<peripheral id="ENC1" security="s_priv"/>
|
|
<peripheral id="ENET0" security="s_priv"/>
|
|
<peripheral id="ERM0" security="s_priv"/>
|
|
<peripheral id="EVTG0" security="s_priv"/>
|
|
<peripheral id="EWM0" security="s_priv"/>
|
|
<peripheral id="FLEXIO0" security="s_priv"/>
|
|
<peripheral id="FLEXSPI0" security="s_priv"/>
|
|
<peripheral id="FMU0" security="s_priv"/>
|
|
<peripheral id="FMU0TEST" security="s_priv"/>
|
|
<peripheral id="FREQME0" security="s_priv"/>
|
|
<peripheral id="GDET1" security="s_priv"/>
|
|
<peripheral id="GPIO0" security="s_priv"/>
|
|
<peripheral id="GPIO0_ALIAS1" security="s_priv"/>
|
|
<peripheral id="GPIO1" security="s_priv"/>
|
|
<peripheral id="GPIO1_ALIAS1" security="s_priv"/>
|
|
<peripheral id="GPIO2" security="s_priv"/>
|
|
<peripheral id="GPIO2_ALIAS1" security="s_priv"/>
|
|
<peripheral id="GPIO3" security="s_priv"/>
|
|
<peripheral id="GPIO3_ALIAS1" security="s_priv"/>
|
|
<peripheral id="GPIO4" security="s_priv"/>
|
|
<peripheral id="GPIO4_ALIAS1" security="s_priv"/>
|
|
<peripheral id="GPIO5" security="s_priv"/>
|
|
<peripheral id="GPIO5_ALIAS1" security="s_priv"/>
|
|
<peripheral id="I3C0" security="s_priv"/>
|
|
<peripheral id="I3C1" security="s_priv"/>
|
|
<peripheral id="INPUTMUX0" security="s_priv"/>
|
|
<peripheral id="INTM0" security="s_priv"/>
|
|
<peripheral id="ITRC0" security="s_priv"/>
|
|
<peripheral id="LPTMR0" security="s_priv"/>
|
|
<peripheral id="LPTMR1" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM0" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM1" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM2" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM3" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM4" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM5" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM6" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM7" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM8" security="s_priv"/>
|
|
<peripheral id="LP_FLEXCOMM9" security="s_priv"/>
|
|
<peripheral id="MAILBOX" security="s_priv"/>
|
|
<peripheral id="MRT0" security="s_priv"/>
|
|
<peripheral id="NPX0" security="s_priv"/>
|
|
<peripheral id="OPAMP0" security="s_priv"/>
|
|
<peripheral id="OPAMP1" security="s_priv"/>
|
|
<peripheral id="OPAMP2" security="s_priv"/>
|
|
<peripheral id="OTPC0" security="s_priv"/>
|
|
<peripheral id="PDM" security="s_priv"/>
|
|
<peripheral id="PINT0" security="s_priv"/>
|
|
<peripheral id="PKC0" security="s_priv"/>
|
|
<peripheral id="PLU0" security="s_priv"/>
|
|
<peripheral id="PORT0" security="s_priv"/>
|
|
<peripheral id="PORT1" security="s_priv"/>
|
|
<peripheral id="PORT2" security="s_priv"/>
|
|
<peripheral id="PORT3" security="s_priv"/>
|
|
<peripheral id="PORT4" security="s_priv"/>
|
|
<peripheral id="PORT5" security="s_priv"/>
|
|
<peripheral id="POWERQUAD" security="s_priv"/>
|
|
<peripheral id="PUF" security="s_priv"/>
|
|
<peripheral id="PUF_ALIAS1" security="s_priv"/>
|
|
<peripheral id="PUF_ALIAS2" security="s_priv"/>
|
|
<peripheral id="PUF_ALIAS3" security="s_priv"/>
|
|
<peripheral id="PWM0" security="s_priv"/>
|
|
<peripheral id="PWM1" security="s_priv"/>
|
|
<peripheral id="RTC0" security="s_priv"/>
|
|
<peripheral id="SAI0" security="s_priv"/>
|
|
<peripheral id="SAI1" security="s_priv"/>
|
|
<peripheral id="SCG0" security="s_priv"/>
|
|
<peripheral id="SCT0" security="s_priv"/>
|
|
<peripheral id="SEMA42_0" security="s_priv"/>
|
|
<peripheral id="SINC0" security="s_priv"/>
|
|
<peripheral id="SM3_0" security="s_priv"/>
|
|
<peripheral id="SMARTDMA0" security="s_priv"/>
|
|
<peripheral id="SPC0" security="s_priv"/>
|
|
<peripheral id="SYSCON0" security="s_priv"/>
|
|
<peripheral id="TDET0" security="s_priv"/>
|
|
<peripheral id="TRNG0" security="s_priv"/>
|
|
<peripheral id="TSI0" security="s_priv"/>
|
|
<peripheral id="USBDCD0" security="s_priv"/>
|
|
<peripheral id="USBFS0" security="s_priv"/>
|
|
<peripheral id="USBHS1__USBC" security="s_priv"/>
|
|
<peripheral id="USBPHY" security="s_priv"/>
|
|
<peripheral id="USDHC0" security="s_priv"/>
|
|
<peripheral id="UTICK0" security="s_priv"/>
|
|
<peripheral id="VBAT0" security="s_priv"/>
|
|
<peripheral id="VREF0" security="s_priv"/>
|
|
<peripheral id="WUU0" security="s_priv"/>
|
|
<peripheral id="WWDT0" security="s_priv"/>
|
|
<peripheral id="WWDT1" security="s_priv"/>
|
|
</peripherals>
|
|
<interrupts>
|
|
<masking>
|
|
<interrupt id="ADC0_IRQn" masked="Masked"/>
|
|
<interrupt id="ADC1_IRQn" masked="Masked"/>
|
|
<interrupt id="BSP32_IRQn" masked="Masked"/>
|
|
<interrupt id="CAN0_IRQn" masked="Masked"/>
|
|
<interrupt id="CAN1_IRQn" masked="Masked"/>
|
|
<interrupt id="CDOG0_IRQn" masked="Masked"/>
|
|
<interrupt id="CDOG1_IRQn" masked="Masked"/>
|
|
<interrupt id="CMC0_IRQn" masked="Masked"/>
|
|
<interrupt id="CTI0_IRQn" masked="Masked"/>
|
|
<interrupt id="CTIMER0_IRQn" masked="Masked"/>
|
|
<interrupt id="CTIMER1_IRQn" masked="Masked"/>
|
|
<interrupt id="CTIMER2_IRQn" masked="Masked"/>
|
|
<interrupt id="CTIMER3_IRQn" masked="Masked"/>
|
|
<interrupt id="CTIMER4_IRQn" masked="Masked"/>
|
|
<interrupt id="DAC0_IRQn" masked="Masked"/>
|
|
<interrupt id="DAC1_IRQn" masked="Masked"/>
|
|
<interrupt id="DAC2_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH0_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH10_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH11_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH12_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH13_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH14_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH15_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH1_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH2_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH3_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH4_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH5_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH6_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH7_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH8_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_0_CH9_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH0_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH10_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH11_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH12_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH13_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH14_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH153_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH1_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH2_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH3_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH4_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH5_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH6_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH7_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH8_IRQn" masked="Masked"/>
|
|
<interrupt id="EDMA_1_CH9_IRQn" masked="Masked"/>
|
|
<interrupt id="ELS_ERR_IRQn" masked="Masked"/>
|
|
<interrupt id="ELS_IRQn" masked="Masked"/>
|
|
<interrupt id="EMVSIM0_IRQn" masked="Masked"/>
|
|
<interrupt id="EMVSIM1_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC0_COMPARE_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC0_HOME_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC0_IDX_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC0_WDG_SAB_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC1_COMPARE_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC1_HOME_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC1_IDX_IRQn" masked="Masked"/>
|
|
<interrupt id="ENC1_WDG_SAB_IRQn" masked="Masked"/>
|
|
<interrupt id="ERM_MULTI_BIT_ERROR_IRQn" masked="Masked"/>
|
|
<interrupt id="ERM_SINGLE_BIT_ERROR_IRQn" masked="Masked"/>
|
|
<interrupt id="ETB0_IRQn" masked="Masked"/>
|
|
<interrupt id="ETHERNET_IRQn" masked="Masked"/>
|
|
<interrupt id="ETHERNET_MACLP_IRQn" masked="Masked"/>
|
|
<interrupt id="ETHERNET_PMT_IRQn" masked="Masked"/>
|
|
<interrupt id="EWM0_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXIO_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_FAULT_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_RELOAD_ERROR_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE0_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE1_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE2_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE3_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_FAULT_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_RELOAD_ERROR_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE0_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE1_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE2_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE3_IRQn" masked="Masked"/>
|
|
<interrupt id="FLEXSPI0_IRQn" masked="Masked"/>
|
|
<interrupt id="FMU0_IRQn" masked="Masked"/>
|
|
<interrupt id="Freqme_IRQn" masked="Masked"/>
|
|
<interrupt id="GDET_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO00_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO01_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO10_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO11_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO20_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO21_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO30_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO31_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO40_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO41_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO50_IRQn" masked="Masked"/>
|
|
<interrupt id="GPIO51_IRQn" masked="Masked"/>
|
|
<interrupt id="HSCMP0_IRQn" masked="Masked"/>
|
|
<interrupt id="HSCMP1_IRQn" masked="Masked"/>
|
|
<interrupt id="HSCMP2_IRQn" masked="Masked"/>
|
|
<interrupt id="I3C0_IRQn" masked="Masked"/>
|
|
<interrupt id="I3C1_IRQn" masked="Masked"/>
|
|
<interrupt id="ITRC0_IRQn" masked="Masked"/>
|
|
<interrupt id="LPTMR0_IRQn" masked="Masked"/>
|
|
<interrupt id="LPTMR1_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM0_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM1_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM2_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM3_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM4_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM5_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM6_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM7_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM8_IRQn" masked="Masked"/>
|
|
<interrupt id="LP_FLEXCOMM9_IRQn" masked="Masked"/>
|
|
<interrupt id="MAILBOX_IRQn" masked="Masked"/>
|
|
<interrupt id="MRT0_IRQn" masked="Masked"/>
|
|
<interrupt id="OS_EVENT_IRQn" masked="Masked"/>
|
|
<interrupt id="PDM_EVENT_IRQn" masked="Masked"/>
|
|
<interrupt id="PINT0_IRQn" masked="Masked"/>
|
|
<interrupt id="PKC_ERR_IRQn" masked="Masked"/>
|
|
<interrupt id="PKC_IRQn" masked="Masked"/>
|
|
<interrupt id="PLU_IRQn" masked="Masked"/>
|
|
<interrupt id="PORT_EFT_IRQn" masked="Masked"/>
|
|
<interrupt id="PQ_IRQn" masked="Masked"/>
|
|
<interrupt id="PUF_IRQn" masked="Masked"/>
|
|
<interrupt id="RTC_IRQn" masked="Masked"/>
|
|
<interrupt id="SAI0_IRQn" masked="Masked"/>
|
|
<interrupt id="SAI1_IRQn" masked="Masked"/>
|
|
<interrupt id="SCG_IRQn" masked="Masked"/>
|
|
<interrupt id="SCT0_IRQn" masked="Masked"/>
|
|
<interrupt id="SEC_HYPERVISOR_CALL_IRQn" masked="Masked"/>
|
|
<interrupt id="SEC_VIO_IRQn" masked="Masked"/>
|
|
<interrupt id="SINC_FILTER_IRQn" masked="Masked"/>
|
|
<interrupt id="SM3_IRQn" masked="Masked"/>
|
|
<interrupt id="SMARTDMA_IRQn" masked="Masked"/>
|
|
<interrupt id="SPC_IRQn" masked="Masked"/>
|
|
<interrupt id="TRNG0_IRQn" masked="Masked"/>
|
|
<interrupt id="TSI_END_OF_SCAN_IRQn" masked="Masked"/>
|
|
<interrupt id="TSI_OUT_OF_SCAN_IRQn" masked="Masked"/>
|
|
<interrupt id="USB0_DCD_IRQn" masked="Masked"/>
|
|
<interrupt id="USB0_FS_IRQn" masked="Masked"/>
|
|
<interrupt id="USB1_HS_IRQn" masked="Masked"/>
|
|
<interrupt id="USB1_HS_PHY_IRQn" masked="Masked"/>
|
|
<interrupt id="USDHC0_IRQn" masked="Masked"/>
|
|
<interrupt id="UTICK0_IRQn" masked="Masked"/>
|
|
<interrupt id="VBAT0_IRQn" masked="Masked"/>
|
|
<interrupt id="WUU_IRQn" masked="Masked"/>
|
|
<interrupt id="WWDT0_IRQn" masked="Masked"/>
|
|
<interrupt id="WWDT1_IRQn" masked="Masked"/>
|
|
</masking>
|
|
<security>
|
|
<interrupt id="ADC0_IRQn" secure="Secure"/>
|
|
<interrupt id="ADC1_IRQn" secure="Secure"/>
|
|
<interrupt id="BSP32_IRQn" secure="Secure"/>
|
|
<interrupt id="CAN0_IRQn" secure="Secure"/>
|
|
<interrupt id="CAN1_IRQn" secure="Secure"/>
|
|
<interrupt id="CDOG0_IRQn" secure="Secure"/>
|
|
<interrupt id="CDOG1_IRQn" secure="Secure"/>
|
|
<interrupt id="CMC0_IRQn" secure="Secure"/>
|
|
<interrupt id="CTI0_IRQn" secure="Secure"/>
|
|
<interrupt id="CTIMER0_IRQn" secure="Secure"/>
|
|
<interrupt id="CTIMER1_IRQn" secure="Secure"/>
|
|
<interrupt id="CTIMER2_IRQn" secure="Secure"/>
|
|
<interrupt id="CTIMER3_IRQn" secure="Secure"/>
|
|
<interrupt id="CTIMER4_IRQn" secure="Secure"/>
|
|
<interrupt id="DAC0_IRQn" secure="Secure"/>
|
|
<interrupt id="DAC1_IRQn" secure="Secure"/>
|
|
<interrupt id="DAC2_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH0_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH10_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH11_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH12_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH13_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH14_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH15_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH1_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH2_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH3_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH4_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH5_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH6_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH7_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH8_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_0_CH9_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH0_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH10_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH11_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH12_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH13_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH14_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH153_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH1_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH2_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH3_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH4_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH5_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH6_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH7_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH8_IRQn" secure="Secure"/>
|
|
<interrupt id="EDMA_1_CH9_IRQn" secure="Secure"/>
|
|
<interrupt id="ELS_ERR_IRQn" secure="Secure"/>
|
|
<interrupt id="ELS_IRQn" secure="Secure"/>
|
|
<interrupt id="EMVSIM0_IRQn" secure="Secure"/>
|
|
<interrupt id="EMVSIM1_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC0_COMPARE_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC0_HOME_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC0_IDX_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC0_WDG_SAB_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC1_COMPARE_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC1_HOME_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC1_IDX_IRQn" secure="Secure"/>
|
|
<interrupt id="ENC1_WDG_SAB_IRQn" secure="Secure"/>
|
|
<interrupt id="ERM_MULTI_BIT_ERROR_IRQn" secure="Secure"/>
|
|
<interrupt id="ERM_SINGLE_BIT_ERROR_IRQn" secure="Secure"/>
|
|
<interrupt id="ETB0_IRQn" secure="Secure"/>
|
|
<interrupt id="ETHERNET_IRQn" secure="Secure"/>
|
|
<interrupt id="ETHERNET_MACLP_IRQn" secure="Secure"/>
|
|
<interrupt id="ETHERNET_PMT_IRQn" secure="Secure"/>
|
|
<interrupt id="EWM0_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXIO_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_FAULT_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_RELOAD_ERROR_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE0_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE1_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE2_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM0_SUBMODULE3_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_FAULT_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_RELOAD_ERROR_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE0_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE1_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE2_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXPWM1_SUBMODULE3_IRQn" secure="Secure"/>
|
|
<interrupt id="FLEXSPI0_IRQn" secure="Secure"/>
|
|
<interrupt id="FMU0_IRQn" secure="Secure"/>
|
|
<interrupt id="Freqme_IRQn" secure="Secure"/>
|
|
<interrupt id="GDET_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO00_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO01_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO10_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO11_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO20_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO21_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO30_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO31_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO40_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO41_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO50_IRQn" secure="Secure"/>
|
|
<interrupt id="GPIO51_IRQn" secure="Secure"/>
|
|
<interrupt id="HSCMP0_IRQn" secure="Secure"/>
|
|
<interrupt id="HSCMP1_IRQn" secure="Secure"/>
|
|
<interrupt id="HSCMP2_IRQn" secure="Secure"/>
|
|
<interrupt id="I3C0_IRQn" secure="Secure"/>
|
|
<interrupt id="I3C1_IRQn" secure="Secure"/>
|
|
<interrupt id="ITRC0_IRQn" secure="Secure"/>
|
|
<interrupt id="LPTMR0_IRQn" secure="Secure"/>
|
|
<interrupt id="LPTMR1_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM0_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM1_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM2_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM3_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM4_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM5_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM6_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM7_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM8_IRQn" secure="Secure"/>
|
|
<interrupt id="LP_FLEXCOMM9_IRQn" secure="Secure"/>
|
|
<interrupt id="MAILBOX_IRQn" secure="Secure"/>
|
|
<interrupt id="MRT0_IRQn" secure="Secure"/>
|
|
<interrupt id="OS_EVENT_IRQn" secure="Secure"/>
|
|
<interrupt id="PDM_EVENT_IRQn" secure="Secure"/>
|
|
<interrupt id="PINT0_IRQn" secure="Secure"/>
|
|
<interrupt id="PKC_ERR_IRQn" secure="Secure"/>
|
|
<interrupt id="PKC_IRQn" secure="Secure"/>
|
|
<interrupt id="PLU_IRQn" secure="Secure"/>
|
|
<interrupt id="PORT_EFT_IRQn" secure="Secure"/>
|
|
<interrupt id="PQ_IRQn" secure="Secure"/>
|
|
<interrupt id="PUF_IRQn" secure="Secure"/>
|
|
<interrupt id="RTC_IRQn" secure="Secure"/>
|
|
<interrupt id="SAI0_IRQn" secure="Secure"/>
|
|
<interrupt id="SAI1_IRQn" secure="Secure"/>
|
|
<interrupt id="SCG_IRQn" secure="Secure"/>
|
|
<interrupt id="SCT0_IRQn" secure="Secure"/>
|
|
<interrupt id="SEC_HYPERVISOR_CALL_IRQn" secure="Secure"/>
|
|
<interrupt id="SEC_VIO_IRQn" secure="Secure"/>
|
|
<interrupt id="SINC_FILTER_IRQn" secure="Secure"/>
|
|
<interrupt id="SM3_IRQn" secure="Secure"/>
|
|
<interrupt id="SMARTDMA_IRQn" secure="Secure"/>
|
|
<interrupt id="SPC_IRQn" secure="Secure"/>
|
|
<interrupt id="TRNG0_IRQn" secure="Secure"/>
|
|
<interrupt id="TSI_END_OF_SCAN_IRQn" secure="Secure"/>
|
|
<interrupt id="TSI_OUT_OF_SCAN_IRQn" secure="Secure"/>
|
|
<interrupt id="USB0_DCD_IRQn" secure="Secure"/>
|
|
<interrupt id="USB0_FS_IRQn" secure="Secure"/>
|
|
<interrupt id="USB1_HS_IRQn" secure="Secure"/>
|
|
<interrupt id="USB1_HS_PHY_IRQn" secure="Secure"/>
|
|
<interrupt id="USDHC0_IRQn" secure="Secure"/>
|
|
<interrupt id="UTICK0_IRQn" secure="Secure"/>
|
|
<interrupt id="VBAT0_IRQn" secure="Secure"/>
|
|
<interrupt id="WUU_IRQn" secure="Secure"/>
|
|
<interrupt id="WWDT0_IRQn" secure="Secure"/>
|
|
<interrupt id="WWDT1_IRQn" secure="Secure"/>
|
|
</security>
|
|
</interrupts>
|
|
<ports>
|
|
<port id="GPIO0">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="GPIO1">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="GPIO2">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="GPIO3">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="GPIO4">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="GPIO5">
|
|
<pin_security id="0" security="s_priv"/>
|
|
<pin_security id="1" security="s_priv"/>
|
|
<pin_security id="10" security="s_priv"/>
|
|
<pin_security id="11" security="s_priv"/>
|
|
<pin_security id="12" security="s_priv"/>
|
|
<pin_security id="13" security="s_priv"/>
|
|
<pin_security id="14" security="s_priv"/>
|
|
<pin_security id="15" security="s_priv"/>
|
|
<pin_security id="16" security="s_priv"/>
|
|
<pin_security id="17" security="s_priv"/>
|
|
<pin_security id="18" security="s_priv"/>
|
|
<pin_security id="19" security="s_priv"/>
|
|
<pin_security id="2" security="s_priv"/>
|
|
<pin_security id="20" security="s_priv"/>
|
|
<pin_security id="21" security="s_priv"/>
|
|
<pin_security id="22" security="s_priv"/>
|
|
<pin_security id="23" security="s_priv"/>
|
|
<pin_security id="24" security="s_priv"/>
|
|
<pin_security id="25" security="s_priv"/>
|
|
<pin_security id="26" security="s_priv"/>
|
|
<pin_security id="27" security="s_priv"/>
|
|
<pin_security id="28" security="s_priv"/>
|
|
<pin_security id="29" security="s_priv"/>
|
|
<pin_security id="3" security="s_priv"/>
|
|
<pin_security id="30" security="s_priv"/>
|
|
<pin_security id="31" security="s_priv"/>
|
|
<pin_security id="4" security="s_priv"/>
|
|
<pin_security id="5" security="s_priv"/>
|
|
<pin_security id="6" security="s_priv"/>
|
|
<pin_security id="7" security="s_priv"/>
|
|
<pin_security id="8" security="s_priv"/>
|
|
<pin_security id="9" security="s_priv"/>
|
|
<pin_interrupt_security id="0" security="s_priv"/>
|
|
<pin_interrupt_security id="1" security="s_priv"/>
|
|
</port>
|
|
<port id="pio0">
|
|
<pin_mask id="0" masked="Masked"/>
|
|
<pin_mask id="1" masked="Masked"/>
|
|
<pin_mask id="10" masked="Masked"/>
|
|
<pin_mask id="11" masked="Masked"/>
|
|
<pin_mask id="12" masked="Masked"/>
|
|
<pin_mask id="13" masked="Masked"/>
|
|
<pin_mask id="14" masked="Masked"/>
|
|
<pin_mask id="15" masked="Masked"/>
|
|
<pin_mask id="16" masked="Masked"/>
|
|
<pin_mask id="17" masked="Masked"/>
|
|
<pin_mask id="18" masked="Masked"/>
|
|
<pin_mask id="19" masked="Masked"/>
|
|
<pin_mask id="2" masked="Masked"/>
|
|
<pin_mask id="20" masked="Masked"/>
|
|
<pin_mask id="21" masked="Masked"/>
|
|
<pin_mask id="22" masked="Masked"/>
|
|
<pin_mask id="23" masked="Masked"/>
|
|
<pin_mask id="24" masked="Masked"/>
|
|
<pin_mask id="25" masked="Masked"/>
|
|
<pin_mask id="26" masked="Masked"/>
|
|
<pin_mask id="27" masked="Masked"/>
|
|
<pin_mask id="28" masked="Masked"/>
|
|
<pin_mask id="29" masked="Masked"/>
|
|
<pin_mask id="3" masked="Masked"/>
|
|
<pin_mask id="30" masked="Masked"/>
|
|
<pin_mask id="31" masked="Masked"/>
|
|
<pin_mask id="4" masked="Masked"/>
|
|
<pin_mask id="5" masked="Masked"/>
|
|
<pin_mask id="6" masked="Masked"/>
|
|
<pin_mask id="7" masked="Masked"/>
|
|
<pin_mask id="8" masked="Masked"/>
|
|
<pin_mask id="9" masked="Masked"/>
|
|
</port>
|
|
<port id="pio1">
|
|
<pin_mask id="0" masked="Masked"/>
|
|
<pin_mask id="1" masked="Masked"/>
|
|
<pin_mask id="10" masked="Masked"/>
|
|
<pin_mask id="11" masked="Masked"/>
|
|
<pin_mask id="12" masked="Masked"/>
|
|
<pin_mask id="13" masked="Masked"/>
|
|
<pin_mask id="14" masked="Masked"/>
|
|
<pin_mask id="15" masked="Masked"/>
|
|
<pin_mask id="16" masked="Masked"/>
|
|
<pin_mask id="17" masked="Masked"/>
|
|
<pin_mask id="18" masked="Masked"/>
|
|
<pin_mask id="19" masked="Masked"/>
|
|
<pin_mask id="2" masked="Masked"/>
|
|
<pin_mask id="20" masked="Masked"/>
|
|
<pin_mask id="21" masked="Masked"/>
|
|
<pin_mask id="22" masked="Masked"/>
|
|
<pin_mask id="23" masked="Masked"/>
|
|
<pin_mask id="24" masked="Masked"/>
|
|
<pin_mask id="25" masked="Masked"/>
|
|
<pin_mask id="26" masked="Masked"/>
|
|
<pin_mask id="27" masked="Masked"/>
|
|
<pin_mask id="28" masked="Masked"/>
|
|
<pin_mask id="29" masked="Masked"/>
|
|
<pin_mask id="3" masked="Masked"/>
|
|
<pin_mask id="30" masked="Masked"/>
|
|
<pin_mask id="31" masked="Masked"/>
|
|
<pin_mask id="4" masked="Masked"/>
|
|
<pin_mask id="5" masked="Masked"/>
|
|
<pin_mask id="6" masked="Masked"/>
|
|
<pin_mask id="7" masked="Masked"/>
|
|
<pin_mask id="8" masked="Masked"/>
|
|
<pin_mask id="9" masked="Masked"/>
|
|
</port>
|
|
</ports>
|
|
<mbcs>
|
|
<mbc checker_id="MBC0" using_global_templates="true">
|
|
<slaves>
|
|
<slave id="PROGRAM_FLASH0_mbc">
|
|
<domain security="s" template="NO_ACCESS"/>
|
|
<base_region start="0" size="1048576"/>
|
|
</slave>
|
|
<slave id="PROGRAM_FLASH1_mbc">
|
|
<domain security="s" template="NO_ACCESS"/>
|
|
<base_region start="0" size="1048576"/>
|
|
</slave>
|
|
<slave id="FlashBank_IFR0_mbc">
|
|
<domain security="s" template="NO_ACCESS"/>
|
|
<base_region start="0" size="65536"/>
|
|
</slave>
|
|
<slave id="FlashBank_IFR1_mbc">
|
|
<domain security="s" template="NO_ACCESS"/>
|
|
<base_region start="0" size="16384"/>
|
|
</slave>
|
|
</slaves>
|
|
</mbc>
|
|
</mbcs>
|
|
</ahbsc_rwx>
|
|
<sau enabled="false" all_non_secure="false" generate_code_for_disabled_regions="false">
|
|
<region start="0" size="32" security="ns" enabled="false" index="0"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="1"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="2"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="3"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="4"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="5"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="6"/>
|
|
<region start="0" size="32" security="ns" enabled="false" index="7"/>
|
|
</sau>
|
|
<global_options>
|
|
<option id="GPIO0_PCNS" value="no"/>
|
|
<option id="GPIO0_ICNS" value="no"/>
|
|
<option id="GPIO0_PCNP" value="no"/>
|
|
<option id="GPIO0_ICNP" value="no"/>
|
|
<option id="GPIO1_PCNS" value="no"/>
|
|
<option id="GPIO1_ICNS" value="no"/>
|
|
<option id="GPIO1_PCNP" value="no"/>
|
|
<option id="GPIO1_ICNP" value="no"/>
|
|
<option id="GPIO2_PCNS" value="no"/>
|
|
<option id="GPIO2_ICNS" value="no"/>
|
|
<option id="GPIO2_PCNP" value="no"/>
|
|
<option id="GPIO2_ICNP" value="no"/>
|
|
<option id="GPIO3_PCNS" value="no"/>
|
|
<option id="GPIO3_ICNS" value="no"/>
|
|
<option id="GPIO3_PCNP" value="no"/>
|
|
<option id="GPIO3_ICNP" value="no"/>
|
|
<option id="GPIO4_PCNS" value="no"/>
|
|
<option id="GPIO4_ICNS" value="no"/>
|
|
<option id="GPIO4_PCNP" value="no"/>
|
|
<option id="GPIO4_ICNP" value="no"/>
|
|
<option id="GPIO5_PCNS" value="no"/>
|
|
<option id="GPIO5_ICNS" value="no"/>
|
|
<option id="GPIO5_PCNP" value="no"/>
|
|
<option id="GPIO5_ICNP" value="no"/>
|
|
<option id="AIRCR_PRIS" value="no"/>
|
|
<option id="AIRCR_BFHFNMINS" value="no"/>
|
|
<option id="AIRCR_SYSRESETREQS" value="no"/>
|
|
<option id="SCR_SLEEPDEEPS" value="no"/>
|
|
<option id="SHCSR_SECUREFAULTENA" value="no"/>
|
|
<option id="CPACR_CP0" value="0"/>
|
|
<option id="CPACR_CP1" value="0"/>
|
|
<option id="CPACR_CP2" value="0"/>
|
|
<option id="CPACR_CP3" value="0"/>
|
|
<option id="CPACR_CP4" value="0"/>
|
|
<option id="CPACR_CP5" value="0"/>
|
|
<option id="CPACR_CP6" value="0"/>
|
|
<option id="CPACR_CP7" value="0"/>
|
|
<option id="CPACR_CP10" value="0"/>
|
|
<option id="CPACR_CP11" value="0"/>
|
|
<option id="NSACR_CP0" value="yes"/>
|
|
<option id="NSACR_CP1" value="yes"/>
|
|
<option id="NSACR_CP2" value="no"/>
|
|
<option id="NSACR_CP3" value="no"/>
|
|
<option id="NSACR_CP4" value="no"/>
|
|
<option id="NSACR_CP5" value="no"/>
|
|
<option id="NSACR_CP6" value="no"/>
|
|
<option id="NSACR_CP7" value="no"/>
|
|
<option id="NSACR_CP10" value="yes"/>
|
|
<option id="NSACR_CP11" value="yes"/>
|
|
<option id="CPPWR_SU0" value="no"/>
|
|
<option id="CPPWR_SUS0" value="no"/>
|
|
<option id="CPPWR_SU1" value="no"/>
|
|
<option id="CPPWR_SUS1" value="no"/>
|
|
<option id="CPPWR_SU2" value="no"/>
|
|
<option id="CPPWR_SUS2" value="no"/>
|
|
<option id="CPPWR_SU3" value="no"/>
|
|
<option id="CPPWR_SUS3" value="no"/>
|
|
<option id="CPPWR_SU4" value="no"/>
|
|
<option id="CPPWR_SUS4" value="no"/>
|
|
<option id="CPPWR_SU5" value="no"/>
|
|
<option id="CPPWR_SUS5" value="no"/>
|
|
<option id="CPPWR_SU6" value="no"/>
|
|
<option id="CPPWR_SUS6" value="no"/>
|
|
<option id="CPPWR_SU7" value="no"/>
|
|
<option id="CPPWR_SUS7" value="no"/>
|
|
<option id="CPPWR_SU10" value="no"/>
|
|
<option id="CPPWR_SUS10" value="no"/>
|
|
<option id="CPPWR_SU11" value="no"/>
|
|
<option id="CPPWR_SUS11" value="no"/>
|
|
<option id="SEC_GPIO_MASK0_LOCK" value="no"/>
|
|
<option id="SEC_GPIO_MASK1_LOCK" value="no"/>
|
|
<option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
|
|
<option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
|
|
<option id="SEC_CPU1_INT_MASK2_LOCK" value="no"/>
|
|
<option id="SEC_CPU1_INT_MASK3_LOCK" value="no"/>
|
|
<option id="SEC_CPU1_INT_MASK4_LOCK" value="no"/>
|
|
<option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
|
|
<option id="CPU0_LOCK_NS_VTOR" value="no"/>
|
|
<option id="CPU0_LOCK_NS_MPU" value="no"/>
|
|
<option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
|
|
<option id="CPU0_LOCK_S_MPU" value="no"/>
|
|
<option id="CPU0_LOCK_SAU" value="no"/>
|
|
<option id="CM33_LOCK_REG_LOCK" value="no"/>
|
|
<option id="CPU1_LOCK_NS_VTOR" value="no"/>
|
|
<option id="CPU1_LOCK_NS_MPU" value="no"/>
|
|
<option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
|
|
<option id="AHB_MISC_CTRL_REG_DISABLE_MASTER_STRICT_MODE" value="yes"/>
|
|
<option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
|
|
<option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="no"/>
|
|
<option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="no"/>
|
|
<option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
|
|
<option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="no"/>
|
|
</global_options>
|
|
<mpus>
|
|
<mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
|
|
<attributes>
|
|
<group index="0" id="0" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="1" id="1" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="2" id="2" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="3" id="3" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="4" id="4" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="5" id="5" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="6" id="6" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="7" id="7" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
</attributes>
|
|
<regions>
|
|
<region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
</regions>
|
|
</mpu>
|
|
<mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
|
|
<attributes>
|
|
<group index="0" id="0" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="1" id="1" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="2" id="2" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="3" id="3" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="4" id="4" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="5" id="5" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="6" id="6" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
<group index="7" id="7" memory_type="device" device="nGnRE">
|
|
<regions_properties>
|
|
<region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
<region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/>
|
|
</regions_properties>
|
|
</group>
|
|
</attributes>
|
|
<regions>
|
|
<region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
<region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/>
|
|
</regions>
|
|
</mpu>
|
|
</mpus>
|
|
<access_templates>
|
|
<template id="NO_ACCESS" name="No access" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="R_s_priv" name="R for S-Priv" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="RW_s_priv" name="RW for S-Priv" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="RW_s_priv__R_s_user" name="RW for S-Priv, R for S-User" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="RW_s" name="RW for S" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="RW_s__R_ns" name="RW for S, R for NS" locked="false">
|
|
<access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="false">
|
|
<access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
<template id="ALL" name="All" locked="false">
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/>
|
|
<access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/>
|
|
</template>
|
|
</access_templates>
|
|
</functional_group>
|
|
</tee>
|
|
</tools>
|
|
</configuration> |