From 9aa97eed3b7591e8ff652b65ab2e511ca9d9826a Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Sun, 17 Sep 2023 23:04:14 +0800 Subject: [PATCH] Enabled Atomic, added LCD driver. Signed-off-by: Yilin Sun --- board/board.c | 58 ++++++++++++++++++++++++++++++++++++++++++++--- board/board.h | 9 ++++++++ board/pinmux.c | 37 ++++++++++++++++++++++++++++++ board/pinmux.h | 1 + riscv32-elf.cmake | 4 ++-- src/main.c | 1 + 6 files changed, 105 insertions(+), 5 deletions(-) diff --git a/board/board.c b/board/board.c index abc4bc2..3306502 100644 --- a/board/board.c +++ b/board/board.c @@ -2,6 +2,7 @@ #include "hpm_clock_drv.h" #include "hpm_femc_drv.h" #include "hpm_i2c_drv.h" +#include "hpm_lcdc_drv.h" #include "hpm_pcfg_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_pmp_drv.h" @@ -32,6 +33,8 @@ void board_init(void) { board_sdram_init(); board_pmp_init(); + + board_lcd_init(); } void board_clock_init(void) { @@ -63,8 +66,8 @@ void board_debug_console_init(void) { board_debug_uart_pins_init(); /* Configure the UART clock to 24MHz */ - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1U); clock_add_to_group(clock_uart0, 0); + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1U); cfg.type = CONSOLE_TYPE_UART; cfg.base = HPM_UART0_BASE; @@ -91,8 +94,8 @@ void board_sdram_init(void) { board_sdram_pins_init(); - clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); clock_add_to_group(clock_femc, 0); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); femc_default_config(HPM_FEMC, &cfg); cfg.dqs = FEMC_DQS_INTERNAL; @@ -131,6 +134,55 @@ void board_sdram_init(void) { femc_config_sdram(HPM_FEMC, clock_get_frequency(clock_femc), &sdram_cfg); } +void board_lcd_init(void) { + lcdc_config_t cfg = {0}; + /* + * Fire 5" LCD Parameters: + * Horizontal Resolution: 800 + * HBP: 46 + * HFP: 210 (16-354) + * Vertical Resolution: 480 + * VBP: 23 + * VFP: 22 (7-147) + * HSync Pulse Width: 1 (1-40) P-CLK + * VSync Pulse Width: 1 (1-20) HSD + * + * Pixel Clock Frequency: 33.264MHz (@60fps, Typ.) + */ + + board_lcd_pins_init(); + + /* Backlight ON */ + gpio_set_pin_output_with_initial(BOARD_LCD_BLK_GPIO_CTRL, BOARD_LCD_BLK_GPIO_INDEX, BOARD_LCD_BLK_GPIO_PIN, 1U); + + clock_add_to_group(clock_display, 0); + clock_set_source_divider(clock_display, clk_src_pll4_clk0, 18U); /* 33.0MHz */ + + /* Bug workaround, seems clock not stable */ + clock_cpu_delay_ms(10); + + lcdc_get_default_config(HPM_LCDC, &cfg); + + cfg.resolution_x = BOARD_LCD_RES_H; + cfg.resolution_y = BOARD_LCD_RES_V; + + cfg.hsync.pulse_width = 10; + cfg.hsync.back_porch_pulse = 46; + cfg.hsync.front_porch_pulse = 210; + + cfg.vsync.pulse_width = 3; + cfg.vsync.back_porch_pulse = 23; + cfg.vsync.front_porch_pulse = 22; + + cfg.control.invert_hsync = false; + cfg.control.invert_vsync = false; + cfg.control.invert_href = false; + cfg.control.invert_pixel_data = false; + cfg.control.invert_pixel_clock = false; + + lcdc_init(HPM_LCDC, &cfg); +} + void board_pmp_init(void) { uint32_t start_addr; uint32_t end_addr; @@ -173,4 +225,4 @@ void board_pmp_init(void) { } pmp_config(&pmp_entry[0], index); -} +} \ No newline at end of file diff --git a/board/board.h b/board/board.h index d2391e3..89742c6 100644 --- a/board/board.h +++ b/board/board.h @@ -48,6 +48,13 @@ #define BOARD_SDRAM_BASE (0x40000000U) #define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_LCD_RES_H (800U) +#define BOARD_LCD_RES_V (480U) + +#define BOARD_LCD_BLK_GPIO_CTRL HPM_GPIO0 +#define BOARD_LCD_BLK_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_LCD_BLK_GPIO_PIN 23 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -62,6 +69,8 @@ void board_led_set(uint8_t led_id, bool state); void board_sdram_init(void); +void board_lcd_init(void); + void board_pmp_init(void); #if defined(__cplusplus) diff --git a/board/pinmux.c b/board/pinmux.c index 24b5db2..bc4c370 100644 --- a/board/pinmux.c +++ b/board/pinmux.c @@ -71,4 +71,41 @@ void board_sdram_pins_init(void) { HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK; HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE; HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; +} + +void board_lcd_pins_init(void) { + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; + + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; + + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; + + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; + + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; + + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; /* Backlight */ } \ No newline at end of file diff --git a/board/pinmux.h b/board/pinmux.h index 11d5fc9..62915d4 100644 --- a/board/pinmux.h +++ b/board/pinmux.h @@ -16,6 +16,7 @@ extern "C" { void board_debug_uart_pins_init(void); void board_led_pins_init(void); void board_sdram_pins_init(void); +void board_lcd_pins_init(void); #ifdef __cplusplus } diff --git a/riscv32-elf.cmake b/riscv32-elf.cmake index 3cdb987..1deab32 100644 --- a/riscv32-elf.cmake +++ b/riscv32-elf.cmake @@ -9,8 +9,8 @@ set(CMAKE_CXX_COMPILER riscv32-elf-g++) # Optionally set size binary name, for elf section size reporting. set(TARGET_TOOLCHAIN_SIZE riscv32-elf-size) -set(CMAKE_C_FLAGS_INIT "-march=rv32imfdcxandes -mabi=ilp32d") -set(CMAKE_CXX_FLAGS_INIT "-march=rv32imfdcxandes -mabi=ilp32d") +set(CMAKE_C_FLAGS_INIT "-march=rv32imafdcxandes -mabi=ilp32d") +set(CMAKE_CXX_FLAGS_INIT "-march=rv32imafdcxandes -mabi=ilp32d") set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nosys.specs -Wl,--print-memory-usage -nostartfiles") # Make CMake happy about those compilers diff --git a/src/main.c b/src/main.c index 29dcd77..ebac4d7 100644 --- a/src/main.c +++ b/src/main.c @@ -1,5 +1,6 @@ #include +/* Board */ #include "board.h" #include "hpm_debug_console.h"