BOARD: Enabled SDRAM.
continuous-integration/drone/push Build is passing
Details
continuous-integration/drone/push Build is passing
Details
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
parent
183c96a1a1
commit
c61e94e3b7
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@ -1,5 +1,6 @@
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/* SDK drivers */
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#include "hpm_clock_drv.h"
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#include "hpm_femc_drv.h"
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#include "hpm_i2c_drv.h"
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#include "hpm_pcfg_drv.h"
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#include "hpm_pllctl_drv.h"
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@ -28,6 +29,8 @@ void board_init(void) {
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board_debug_console_init();
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board_led_init();
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board_sdram_init();
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board_pmp_init();
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}
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@ -44,7 +47,7 @@ void board_clock_init(void) {
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/* Update DCDC voltage */
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pcfg_dcdc_set_voltage(HPM_PCFG, BOARD_CORE_VOLTAGE_MV);
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if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ) != status_success) {
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if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL0, BOARD_CPU_FREQ) != status_success) {
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for (;;) {
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WFI();
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}
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@ -82,6 +85,52 @@ void board_led_set(uint8_t led_id, bool state) {
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}
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}
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void board_sdram_init(void) {
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femc_config_t cfg;
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femc_sdram_config_t sdram_cfg;
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board_sdram_pins_init();
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clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U);
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clock_add_to_group(clock_femc, 0);
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femc_default_config(HPM_FEMC, &cfg);
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cfg.dqs = FEMC_DQS_INTERNAL;
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femc_init(HPM_FEMC, &cfg);
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sdram_cfg.bank_num = FEMC_SDRAM_BANK_NUM_4;
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sdram_cfg.prescaler = 3;
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sdram_cfg.burst_len_in_byte = 8;
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sdram_cfg.auto_refresh_count_in_one_burst = 1;
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sdram_cfg.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
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sdram_cfg.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
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sdram_cfg.precharge_to_act_in_ns = 18;
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sdram_cfg.act_to_rw_in_ns = 18;
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sdram_cfg.refresh_recover_in_ns = 72;
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sdram_cfg.write_recover_in_ns = 12;
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sdram_cfg.cke_off_in_ns = 42;
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sdram_cfg.act_to_precharge_in_ns = 42;
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sdram_cfg.self_refresh_recover_in_ns = 72;
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sdram_cfg.refresh_recover_in_ns = 72;
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sdram_cfg.act_to_act_in_ns = 12;
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sdram_cfg.idle_timeout_in_ns = 6;
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sdram_cfg.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
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sdram_cfg.cs = FEMC_SDRAM_CS0;
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sdram_cfg.base_address = BOARD_SDRAM_BASE;
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sdram_cfg.size_in_byte = BOARD_SDRAM_SIZE;
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sdram_cfg.port_size = FEMC_SDRAM_PORT_SIZE_16_BITS;
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sdram_cfg.refresh_count = 8192;
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sdram_cfg.refresh_in_ms = 64;
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sdram_cfg.data_width_in_byte = 2;
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sdram_cfg.delay_cell_value = 29;
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femc_config_sdram(HPM_FEMC, clock_get_frequency(clock_femc), &sdram_cfg);
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}
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void board_pmp_init(void) {
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uint32_t start_addr;
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uint32_t end_addr;
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@ -45,6 +45,9 @@
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#define BOARD_LED_GPIO_INDEX BOARD_LED0_GPIO_INDEX
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#define BOARD_LED_GPIO_PIN BOARD_LED0_GPIO_PIN
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#define BOARD_SDRAM_BASE (0x40000000U)
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#define BOARD_SDRAM_SIZE (32 * SIZE_1MB)
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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@ -57,6 +60,8 @@ void board_debug_console_init(void);
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void board_led_init(void);
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void board_led_set(uint8_t led_id, bool state);
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void board_sdram_init(void);
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void board_pmp_init(void);
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#if defined(__cplusplus)
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@ -23,4 +23,52 @@ void board_led_pins_init(void) {
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gpio_set_pin_output_with_initial(BOARD_LED0_GPIO_CTRL, BOARD_LED0_GPIO_INDEX, BOARD_LED0_GPIO_PIN, 1U);
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gpio_set_pin_output_with_initial(BOARD_LED1_GPIO_CTRL, BOARD_LED1_GPIO_INDEX, BOARD_LED1_GPIO_PIN, 1U);
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gpio_set_pin_output_with_initial(BOARD_LED2_GPIO_CTRL, BOARD_LED2_GPIO_INDEX, BOARD_LED2_GPIO_PIN, 1U);
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}
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void board_sdram_pins_init(void) {
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HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_A_00;
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HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_A_01;
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HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_A_02;
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HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_A_03;
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HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_A_04;
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HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_A_05;
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HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_A_06;
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HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_A_07;
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HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_A_08;
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HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_A_09;
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HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_A_10;
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HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_11;
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HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_FEMC_A_12;
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HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_DQ_00;
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HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_DQ_01;
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HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_DQ_02;
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HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_DQ_03;
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HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_DQ_04;
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HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_DQ_05;
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HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_DQ_06;
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HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_DQ_07;
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HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_DQ_08;
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HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_DQ_09;
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HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_DQ_10;
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HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_DQ_11;
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HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_DQ_12;
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HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_FEMC_DQ_13;
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HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_DQ_14;
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HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_DQ_15;
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HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_BA0;
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HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_BA1;
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HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_RAS;
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HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_CAS;
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HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_WE;
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HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_CS_0;
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HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_DM_0;
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HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1;
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HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK;
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HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE;
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HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
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}
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@ -15,6 +15,7 @@ extern "C" {
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void board_debug_uart_pins_init(void);
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void board_led_pins_init(void);
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void board_sdram_pins_init(void);
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#ifdef __cplusplus
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}
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