56 lines
2.1 KiB
INI
56 lines
2.1 KiB
INI
adapter speed 5000
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source [find interface/cmsis-dap.cfg]
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transport select jtag
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source [find target/hpmicro/hpm6750-single-core.cfg]
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# openocd flash driver argument:
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# - option0:
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# [31:28] Flash probe type
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# 0 - SFDP SDR / 1 - SFDP DDR
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# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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# 10 - EcoXiP DDR (SPI -> OPI DDR)
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# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [23:20] Command Pads after Configuring FLASH
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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# 0 - Not needed
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# 1 - QE bit is at bit 6 in Status Register 1
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# 2 - QE bit is at bit1 in Status Register 2
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# 3 - QE bit is at bit7 in Status Register 2
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# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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# [15:8] Dummy cycles
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# 0 - Auto-probed / detected / default value
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# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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# [7:4] Misc.
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# 0 - Not used
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# 1 - SPI mode
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# 2 - Internal loopback
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# 3 - External DQS
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# [3:0] Frequency option
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# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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# - option1:
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# [31:20] Reserved
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# [19:16] IO voltage
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# 0 - 3V / 1 - 1.8V
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# [15:12] Pin group
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# 0 - 1st group / 1 - 2nd group
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# [11:8] Connection selection
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# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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# [7:0] Drive Strength
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# 0 - Default value
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# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3040000
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# - base address: 0x80000000
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# - flash size: 0x2000000
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# - flash option0: 0x7
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flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
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