128 lines
4.0 KiB
C
128 lines
4.0 KiB
C
/* SDK drivers */
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#include "hpm_clock_drv.h"
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#include "hpm_i2c_drv.h"
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#include "hpm_pcfg_drv.h"
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#include "hpm_pllctl_drv.h"
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#include "hpm_pmp_drv.h"
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#include "hpm_sysctl_drv.h"
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/* Board */
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#include "board.h"
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#include "pinmux.h"
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typedef struct {
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GPIO_Type *ctl;
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uint8_t index;
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uint8_t pin;
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} board_led_t;
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static const board_led_t s_board_led_table[BOARD_LED_COUNT] = {
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{.ctl = BOARD_LED0_GPIO_CTRL, .index = BOARD_LED0_GPIO_INDEX, .pin = BOARD_LED0_GPIO_PIN},
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{.ctl = BOARD_LED1_GPIO_CTRL, .index = BOARD_LED1_GPIO_INDEX, .pin = BOARD_LED1_GPIO_PIN},
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{.ctl = BOARD_LED2_GPIO_CTRL, .index = BOARD_LED2_GPIO_INDEX, .pin = BOARD_LED2_GPIO_PIN},
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};
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void board_init(void) {
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board_clock_init();
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board_debug_console_init();
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board_led_init();
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board_pmp_init();
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}
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void board_clock_init(void) {
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uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
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if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
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/* Configure the External OSC ramp-up time: ~9ms */
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pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
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/* Select clock setting preset1 */
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sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
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}
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/* Update DCDC voltage */
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pcfg_dcdc_set_voltage(HPM_PCFG, BOARD_CORE_VOLTAGE_MV);
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if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ) != status_success) {
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for (;;) {
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WFI();
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}
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}
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clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
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clock_update_core_clock();
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}
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void board_debug_console_init(void) {
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console_config_t cfg;
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board_debug_uart_pins_init();
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/* Configure the UART clock to 24MHz */
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clock_set_source_divider(clock_uart0, clk_src_osc24m, 1U);
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clock_add_to_group(clock_uart0, 0);
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cfg.type = CONSOLE_TYPE_UART;
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cfg.base = HPM_UART0_BASE;
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cfg.src_freq_in_hz = clock_get_frequency(clock_uart0);
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cfg.baudrate = BOARD_DEBUG_UART_BAUD;
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console_init(&cfg);
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}
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void board_led_init(void) {
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board_led_pins_init();
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}
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void board_led_set(uint8_t led_id, bool state) {
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if (led_id < BOARD_LED_COUNT) {
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const board_led_t *led = &s_board_led_table[led_id];
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gpio_write_pin(led->ctl, led->index, led->pin, !state);
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}
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}
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void board_pmp_init(void) {
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uint32_t start_addr;
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uint32_t end_addr;
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uint32_t length;
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pmp_entry_t pmp_entry[16];
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uint8_t index = 0;
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/* Init noncachable memory */
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extern uint32_t __noncacheable_start__[];
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extern uint32_t __noncacheable_end__[];
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start_addr = (uint32_t)__noncacheable_start__;
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end_addr = (uint32_t)__noncacheable_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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/* Init share memory */
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extern uint32_t __share_mem_start__[];
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extern uint32_t __share_mem_end__[];
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start_addr = (uint32_t)__share_mem_start__;
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end_addr = (uint32_t)__share_mem_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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pmp_config(&pmp_entry[0], index);
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}
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