From eca18b6787a16d979fb2f7f40cd5fc7ba4425b7b Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Fri, 1 Sep 2023 00:30:47 +0800 Subject: [PATCH] Updated to SDK v2.14.0 Signed-off-by: Yilin Sun --- .clang-format | 12 + CMakeLists.txt | 3 +- MIMXRT1021xxxxx.mex | 312 +++++++++++++++++++---- SDK | 2 +- board/clock_config.c | 196 +++++++++----- board/clock_config.h | 103 ++++---- board/dcd.c | 258 ++++++++++++++++++- board/peripherals.c | 4 +- board/pin_mux.c | 22 +- board/pin_mux.h | 2 +- xip/fire_rt1021_evk_flexspi_nor_config.c | 17 +- 11 files changed, 732 insertions(+), 199 deletions(-) create mode 100644 .clang-format diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..214adf0 --- /dev/null +++ b/.clang-format @@ -0,0 +1,12 @@ +BasedOnStyle: Google +IndentWidth: 4 +AlignConsecutiveMacros: Consecutive +AlignConsecutiveDeclarations: Consecutive +AlignConsecutiveAssignments: Consecutive +AllowShortFunctionsOnASingleLine: None +BreakBeforeBraces: Custom +BraceWrapping: + AfterEnum: false + AfterStruct: false + SplitEmptyFunction: false +ColumnLimit: 120 \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index c9a5bed..525a39e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -83,7 +83,6 @@ set(TARGET_SOURCES "SDK/devices/MIMXRT1021/utilities/debug_console/fsl_debug_console.c" "SDK/devices/MIMXRT1021/utilities/fsl_assert.c" "SDK/devices/MIMXRT1021/utilities/fsl_notifier.c" - "SDK/devices/MIMXRT1021/utilities/fsl_sbrk.c" "SDK/devices/MIMXRT1021/utilities/str/fsl_str.c" "SDK/devices/MIMXRT1021/xip/fsl_flexspi_nor_boot.c" "board/board.c" @@ -104,7 +103,9 @@ set(TARGET_C_DEFINES ) set(TARGET_C_DEFINES_XIP + "SKIP_SYSCLK_INIT" "XIP_BOOT_HEADER_ENABLE=1" + "XIP_BOOT_HEADER_DCD_ENABLE=1" "XIP_EXTERNAL_FLASH=1" ) diff --git a/MIMXRT1021xxxxx.mex b/MIMXRT1021xxxxx.mex index 0d227ab..517902f 100644 --- a/MIMXRT1021xxxxx.mex +++ b/MIMXRT1021xxxxx.mex @@ -1,5 +1,5 @@ - + MIMXRT1021xxxxx MIMXRT1021DAG5A @@ -17,17 +17,19 @@ false - + - 12.0.1 - + 14.0.0 + + + - + Configures pin routing and optionally pin electrical features. true @@ -35,96 +37,170 @@ true - + + + true + + + + + true + + + true - + + + + - + - 12.0.1 + 14.0.0 - + - + true - + INPUT - + true - + OUTPUT - + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + true - + true - + + + - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true @@ -135,24 +211,148 @@ - 12.0.1 + 14.0.0 c_array - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - 12.0.1 + 14.0.0 @@ -170,7 +370,7 @@ - + @@ -179,16 +379,16 @@ - + - + - + diff --git a/SDK b/SDK index d983b26..ec9dcda 160000 --- a/SDK +++ b/SDK @@ -1 +1 @@ -Subproject commit d983b267f0e67a8f06c2dad2d7a5e93519a699b0 +Subproject commit ec9dcda9ee2f229b64090ab0ccf11e4015c5770a diff --git a/board/clock_config.c b/board/clock_config.c index 5d07854..967f9ff 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v10.0 +product: Clocks v12.0 processor: MIMXRT1021xxxxx package_id: MIMXRT1021DAG5A mcu_data: ksdk2_0 -processor_version: 12.0.1 +processor_version: 14.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -38,74 +38,122 @@ processor_version: 12.0.1 ******************************************************************************/ void BOARD_InitBootClocks(void) { - BOARD_BootClockRUN(); + BOARD_BootClock500MHz(); } /******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** + ******************** Configuration BOARD_BootClock500MHz ********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration -name: BOARD_BootClockRUN +name: BOARD_BootClock500MHz called_from_default_init: true outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 24 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 4 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 8 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true} +- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* - * Variables for BOARD_BootClockRUN configuration + * Variables for BOARD_BootClock500MHz configuration ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClock500MHz = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 1, /* 30 bit numerator of fractional loop divider */ - .denominator = 60000, /* 30 bit denominator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClock500MHz = { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClock500MHz = + { + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* - * Code for BOARD_BootClockRUN configuration + * Code for BOARD_BootClock500MHz configuration ******************************************************************************/ -void BOARD_BootClockRUN(void) +void BOARD_BootClock500MHz(void) { + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; /* Use free 1MHz clock output. */ @@ -123,6 +171,12 @@ void BOARD_BootClockRUN(void) /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ @@ -131,7 +185,7 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Xbar1); CLOCK_DisableClock(kCLOCK_Xbar2); /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 0); + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); /* Set ARM_PODF. */ CLOCK_SetDiv(kCLOCK_ArmDiv, 0); /* Set PERIPH_CLK2_PODF. */ @@ -143,17 +197,17 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2); /* Set Usdhc1 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); /* Disable USDHC2 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc2); /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2); /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. @@ -163,7 +217,7 @@ void BOARD_BootClockRUN(void) /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 2); + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ @@ -176,9 +230,9 @@ void BOARD_BootClockRUN(void) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiMux, 2); #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); @@ -186,7 +240,7 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Lpspi3); CLOCK_DisableClock(kCLOCK_Lpspi4); /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); /* Set Lpspi clock source. */ CLOCK_SetMux(kCLOCK_LpspiMux, 2); /* Disable TRACE clock gate. */ @@ -194,7 +248,7 @@ void BOARD_BootClockRUN(void) /* Set TRACE_PODF. */ CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -275,28 +329,32 @@ void BOARD_BootClockRUN(void) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." #endif /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClock500MHz); /* Init System pfd0. */ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); /* Init System pfd1. */ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - /* Bypass System PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClock500MHz); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -308,11 +366,9 @@ void BOARD_BootClockRUN(void) /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClock500MHz); /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 2); + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ @@ -359,6 +415,6 @@ void BOARD_BootClockRUN(void) /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + SystemCoreClock = BOARD_BOOTCLOCK500MHZ_CORE_CLOCK; } diff --git a/board/clock_config.h b/board/clock_config.h index 4d34732..77bae5b 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -28,65 +28,68 @@ void BOARD_InitBootClocks(void); #endif /* __cplusplus*/ /******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** + ******************** Configuration BOARD_BootClock500MHz ********************** ******************************************************************************/ /******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration + * Definitions for BOARD_BootClock500MHz configuration ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ +#define BOARD_BOOTCLOCK500MHZ_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 8000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCK500MHZ_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCK500MHZ_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCK500MHZ_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCK500MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCK500MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCK500MHZ_ENET_125M_CLK 0UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_ENET_25M_REF_CLK 0UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCK500MHZ_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCK500MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCK500MHZ_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCK500MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCK500MHZ_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCK500MHZ_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCK500MHZ_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENET, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PWM1, PWM2, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TRNG, USB, USDHC1, USDHC2, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCK500MHZ_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCK500MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCK500MHZ_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCK500MHZ_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCK500MHZ_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCK500MHZ_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCK500MHZ_SEMC_CLK_ROOT 62500000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCK500MHZ_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCK500MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCK500MHZ_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCK500MHZ_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCK500MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ +#define BOARD_BOOTCLOCK500MHZ_USDHC1_CLK_ROOT 176000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCK500MHZ_USDHC2_CLK_ROOT 176000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. +/*! @brief Usb1 PLL set for BOARD_BootClock500MHz configuration. */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClock500MHz; +/*! @brief Sys PLL for BOARD_BootClock500MHz configuration. */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClock500MHz; +/*! @brief Enet PLL set for BOARD_BootClock500MHz configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClock500MHz; /******************************************************************************* - * API for BOARD_BootClockRUN configuration + * API for BOARD_BootClock500MHz configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { @@ -96,7 +99,7 @@ extern "C" { * @brief This function executes configuration of clocks. * */ -void BOARD_BootClockRUN(void); +void BOARD_BootClock500MHz(void); #if defined(__cplusplus) } diff --git a/board/dcd.c b/board/dcd.c index 022cd1b..b38fefe 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -24,7 +24,7 @@ product: DCDx v3.0 processor: MIMXRT1021xxxxx package_id: MIMXRT1021DAG5A mcu_data: ksdk2_0 -processor_version: 12.0.1 +processor_version: 14.0.0 output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ @@ -33,9 +33,261 @@ const uint8_t dcd_data[] = { /* Tag */ 0xD2, /* Image Length */ - 0x00, 0x04, + 0x03, 0xE8, /* Version */ - 0x41 + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-8, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x44, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #2, command: write_clear_bits, address: CCM_ANALOG_PFD_528, value: 0x800000, size: 4 */ + 0xCC, 0x00, 0x0C, 0x0C, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x80, 0x00, 0x00, + /* #3.1-98, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x14, 0x04, + /* #3.1, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40, + /* #3.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #3.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #3.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #3.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #3.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #3.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #3.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #3.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #3.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #3.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #3.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #3.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #3.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #3.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #3.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #3.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #3.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #3.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #3.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #3.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #3.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #3.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #3.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #3.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #3.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #3.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #3.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #3.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #3.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10, + /* #3.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #3.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #3.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #3.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #3.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #3.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #3.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #3.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #3.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #3.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #3.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #3.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1, + /* #3.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1, + /* #3.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1, + /* #3.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1, + /* #3.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1, + /* #3.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1, + /* #3.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1, + /* #3.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1, + /* #3.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1, + /* #3.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1, + /* #3.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1, + /* #3.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1, + /* #3.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1, + /* #3.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1, + /* #3.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1, + /* #3.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1, + /* #3.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1, + /* #3.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1, + /* #3.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1, + /* #3.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1, + /* #3.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1, + /* #3.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1, + /* #3.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1, + /* #3.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1, + /* #3.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1, + /* #3.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1, + /* #3.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1, + /* #3.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1, + /* #3.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1, + /* #3.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1, + /* #3.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1, + /* #3.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1, + /* #3.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1, + /* #3.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1, + /* #3.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1, + /* #3.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1, + /* #3.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1, + /* #3.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1, + /* #3.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1, + /* #3.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1, + /* #3.82, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #3.83, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #3.84, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #3.85, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #3.86, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #3.87, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #3.88, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88, + /* #3.89, command: write_value, address: SEMC_SDRAMCR0, value: 0xF37, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x37, + /* #3.90, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #3.91, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #3.92, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #3.93, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #3.94, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #3.95, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #3.96, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #3.97, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.98, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #9.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #9.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #9.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #10, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #11, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ diff --git a/board/peripherals.c b/board/peripherals.c index 017582a..f2883a2 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -6,11 +6,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Peripherals v11.0 +product: Peripherals v13.0 processor: MIMXRT1021xxxxx package_id: MIMXRT1021DAG5A mcu_data: ksdk2_0 -processor_version: 12.0.1 +processor_version: 14.0.0 functionalGroups: - name: BOARD_InitPeripherals UUID: 8b4c2e98-702d-4536-9c18-c28aae77cb4e diff --git a/board/pin_mux.c b/board/pin_mux.c index 5ec4df0..32cc204 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -6,15 +6,17 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v12.0 +product: Pins v14.0 processor: MIMXRT1021xxxxx package_id: MIMXRT1021DAG5A mcu_data: ksdk2_0 -processor_version: 12.0.1 +processor_version: 14.0.0 +power_domains: {NVCC_GPIO: '3.3'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ #include "fsl_common.h" +#include "fsl_iomuxc.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -24,24 +26,30 @@ processor_version: 12.0.1 * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { - BOARD_InitPins(); + BOARD_InitDbgUARTPins(); } /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: +BOARD_InitDbgUARTPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: [] +- pin_list: + - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07} + - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitPins + * Function Name : BOARD_InitDbgUARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { +void BOARD_InitDbgUARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); } /*********************************************************************************************************************** diff --git a/board/pin_mux.h b/board/pin_mux.h index 736e3be..7829981 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -42,7 +42,7 @@ void BOARD_InitBootPins(void); * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InitPins(void); +void BOARD_InitDbgUARTPins(void); #if defined(__cplusplus) } diff --git a/xip/fire_rt1021_evk_flexspi_nor_config.c b/xip/fire_rt1021_evk_flexspi_nor_config.c index fa278cd..f94fd5f 100644 --- a/xip/fire_rt1021_evk_flexspi_nor_config.c +++ b/xip/fire_rt1021_evk_flexspi_nor_config.c @@ -27,19 +27,20 @@ const flexspi_nor_config_t qspiflash_config = { { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 8u * 1024u * 1024u, + .sflashA1Size = 32u * 1024u * 1024u, .lookupTable = { // Read LUTs - [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20), + [1] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0x00), // Read Status LUTs [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), @@ -48,14 +49,14 @@ const flexspi_nor_config_t qspiflash_config = { [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), // Erase Sector LUTs - [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20), // Erase Block LUTs - [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20), // Pape Program LUTs - [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), - [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x00, STOP, FLEXSPI_1PAD, 0x0), // Erase Chip LUTs [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),