commit efde05796ee08afa35a3ed0507bc35b2130949c9
Author: Embedded_Projects <>
Date: Fri Mar 15 14:46:13 2024 +0000
Initial commit
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..214adf0
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,12 @@
+BasedOnStyle: Google
+IndentWidth: 4
+AlignConsecutiveMacros: Consecutive
+AlignConsecutiveDeclarations: Consecutive
+AlignConsecutiveAssignments: Consecutive
+AllowShortFunctionsOnASingleLine: None
+BreakBeforeBraces: Custom
+BraceWrapping:
+ AfterEnum: false
+ AfterStruct: false
+ SplitEmptyFunction: false
+ColumnLimit: 120
\ No newline at end of file
diff --git a/.drone.yml b/.drone.yml
new file mode 100644
index 0000000..6afe870
--- /dev/null
+++ b/.drone.yml
@@ -0,0 +1,17 @@
+---
+kind: pipeline
+type: docker
+name: Build
+
+steps:
+ - name: Submodules
+ image: alpine/git
+ commands:
+ - git submodule update --init --recursive
+
+ - name: Build
+ image: "git.minori.work/embedded_sdk/embedded-builder-arm:latest"
+ commands:
+ - mkdir build && cd build
+ - cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake ..
+ - make fire_rt1021_evk_template_FLASH.elf
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ee1fbdd
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,6 @@
+/board/*.bak
+/build
+/cmake-build-*
+/.vscode
+/*.jdebug*
+/*.jflash
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..536041c
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "SDK"]
+ path = SDK
+ url = https://git.minori.work/Embedded_SDK/MCUXpresso_MIMXRT1021xxxxx.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 0000000..525a39e
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,204 @@
+cmake_minimum_required(VERSION 3.10)
+
+project(fire_rt1021_evk_template)
+
+enable_language(CXX)
+enable_language(ASM)
+
+# Different linker scripts
+set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1021/gcc/MIMXRT1021xxxxx_flexspi_nor.ld")
+set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1021/gcc/MIMXRT1021xxxxx_ram.ld")
+
+set(TARGET_SOURCES
+ "SDK/components/serial_manager/fsl_component_serial_manager.c"
+ "SDK/components/serial_manager/fsl_component_serial_port_uart.c"
+ "SDK/components/uart/fsl_adapter_lpuart.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_adc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_adc_etc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_aipstz.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_aoi.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_bee.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_cache.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_clock.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_cmp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_common.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_common_arm.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_dcdc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_dcp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_dmamux.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_enc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_enet.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_ewm.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexcan.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_camera.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_camera_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_i2c_master.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_i2s.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_i2s_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_mculcd.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_mculcd_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_spi.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_spi_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_uart.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexio_uart_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexram.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexram_allocate.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexspi.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_flexspi_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_gpc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_gpio.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_gpt.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_kpp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpi2c.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpi2c_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpspi.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpspi_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpuart.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_lpuart_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_ocotp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_pit.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_pmu.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_pwm.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_qtmr.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_romapi.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_rtwdog.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_sai.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_sai_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_semc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_snvs_hp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_snvs_lp.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_spdif.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_spdif_edma.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_src.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_tempmon.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_trng.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_usdhc.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_wdog.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_xbara.c"
+ "SDK/devices/MIMXRT1021/drivers/fsl_xbarb.c"
+ "SDK/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S"
+ "SDK/devices/MIMXRT1021/system_MIMXRT1021.c"
+ "SDK/devices/MIMXRT1021/utilities/debug_console/fsl_debug_console.c"
+ "SDK/devices/MIMXRT1021/utilities/fsl_assert.c"
+ "SDK/devices/MIMXRT1021/utilities/fsl_notifier.c"
+ "SDK/devices/MIMXRT1021/utilities/str/fsl_str.c"
+ "SDK/devices/MIMXRT1021/xip/fsl_flexspi_nor_boot.c"
+ "board/board.c"
+ "board/clock_config.c"
+ "board/dcd.c"
+ "board/peripherals.c"
+ "board/pin_mux.c"
+ "src/main.c"
+ "xip/fire_rt1021_evk_flexspi_nor_config.c"
+)
+
+set(TARGET_C_DEFINES
+ "CPU_MIMXRT1021DAG5A"
+ "MCUXPRESSO_SDK"
+ "SERIAL_PORT_TYPE_UART"
+ "__STARTUP_CLEAR_BSS"
+ "__STARTUP_INITIALIZE_NONCACHEDATA"
+)
+
+set(TARGET_C_DEFINES_XIP
+ "SKIP_SYSCLK_INIT"
+ "XIP_BOOT_HEADER_ENABLE=1"
+ "XIP_BOOT_HEADER_DCD_ENABLE=1"
+ "XIP_EXTERNAL_FLASH=1"
+)
+
+set(TARGET_C_INCLUDES
+ "SDK/CMSIS/Core/Include"
+ "SDK/components/serial_manager"
+ "SDK/components/uart"
+ "SDK/devices/MIMXRT1021"
+ "SDK/devices/MIMXRT1021/drivers"
+ "SDK/devices/MIMXRT1021/utilities"
+ "SDK/devices/MIMXRT1021/utilities/debug_console"
+ "SDK/devices/MIMXRT1021/utilities/str"
+ "board"
+ "include"
+)
+
+# Shared libraries linked with application
+set(TARGET_LIBS
+ "c"
+ "m"
+ "nosys"
+)
+
+# Shared library and linker script search paths
+set(TARGET_LIB_DIRECTORIES
+
+)
+
+# Conditional flags
+# DEBUG
+set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_ASM_FLAGS_DEBUG "-DDEBUG -O0 -g")
+
+# RELEASE
+set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto")
+
+# Final compiler flags
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
+set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections")
+
+# Shared sources, includes and definitions
+add_compile_definitions(${TARGET_C_DEFINES})
+include_directories(${TARGET_C_INCLUDES})
+link_directories(${TARGET_LIB_DIRECTORIES})
+link_libraries(${TARGET_LIBS})
+
+# Main targets are added here
+
+# Create ELF
+add_executable("${CMAKE_PROJECT_NAME}_FLASH.elf" ${TARGET_SOURCES})
+target_compile_definitions("${CMAKE_PROJECT_NAME}_FLASH.elf"
+ PRIVATE ${TARGET_C_DEFINES_XIP}
+)
+target_link_options("${CMAKE_PROJECT_NAME}_FLASH.elf"
+ PRIVATE "-T${TARGET_LDSCRIPT_FLASH}"
+ PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_FLASH.map"
+)
+set_property(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" APPEND
+ PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_FLASH.map"
+)
+add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH.hex"
+ COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLASH.elf" "${CMAKE_PROJECT_NAME}_FLASH.hex"
+ DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.elf"
+)
+add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.hex")
+if(DEFINED TARGET_TOOLCHAIN_SIZE)
+add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD
+ COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH.elf"
+)
+endif()
+
+# Create ELF
+add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${TARGET_SOURCES})
+target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf"
+ PRIVATE "-T${TARGET_LDSCRIPT_RAM}"
+ PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_RAM.map"
+)
+set_property(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" APPEND
+ PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_RAM.map"
+)
+add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex"
+ COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_RAM.elf" "${CMAKE_PROJECT_NAME}_RAM.hex"
+ DEPENDS "${CMAKE_PROJECT_NAME}_RAM.elf"
+)
+add_custom_target("${CMAKE_PROJECT_NAME}_RAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_RAM.hex")
+if(DEFINED TARGET_TOOLCHAIN_SIZE)
+add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" POST_BUILD
+ COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_RAM.elf"
+)
+endif()
diff --git a/MIMXRT1021xxxxx.mex b/MIMXRT1021xxxxx.mex
new file mode 100644
index 0000000..f052075
--- /dev/null
+++ b/MIMXRT1021xxxxx.mex
@@ -0,0 +1,407 @@
+
+
+
+ MIMXRT1021xxxxx
+ MIMXRT1021DAG5A
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 15.0.1
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 15.0.1
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ 15.0.1
+ c_array
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 15.0.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ N/A
+
+
+
+
\ No newline at end of file
diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake
new file mode 100644
index 0000000..a9ef74e
--- /dev/null
+++ b/arm-none-eabi.cmake
@@ -0,0 +1,17 @@
+# Poor old Windows...
+if(WIN32)
+ set(CMAKE_SYSTEM_NAME "Generic")
+endif()
+
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+
+# Optionally set size binary name, for elf section size reporting.
+set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size)
+
+set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16")
+set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16")
+set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments")
+
+# Make CMake happy about those compilers
+set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY")
diff --git a/board/board.c b/board/board.c
new file mode 100644
index 0000000..68f20c7
--- /dev/null
+++ b/board/board.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_lpi2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get debug console frequency. */
+uint32_t BOARD_DebugConsoleSrcFreq(void)
+{
+ uint32_t freq;
+
+ /* To make it simple, we assume default PLL and divider settings, and the only variable
+ from application is use PLL3 source or OSC source */
+ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
+ {
+ freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+ else
+ {
+ freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+
+ return freq;
+}
+
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+/* MPU configuration. */
+void BOARD_ConfigMPU(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$RW_m_ncache$$Base[];
+ /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+ extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+ extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+ uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
+ uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
+ 0 :
+ ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+#elif defined(__MCUXPRESSO)
+ extern uint32_t __base_NCACHE_REGION;
+ extern uint32_t __top_NCACHE_REGION;
+ uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
+ uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
+#elif defined(__ICCARM__) || defined(__GNUC__)
+ extern uint32_t __NCACHE_REGION_START[];
+ extern uint32_t __NCACHE_REGION_SIZE[];
+ uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
+ uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
+#endif
+ volatile uint32_t i = 0;
+
+ /* Disable I cache and D cache */
+ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+ {
+ SCB_DisableICache();
+ }
+ if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+ {
+ SCB_DisableDCache();
+ }
+
+ /* Disable MPU */
+ ARM_MPU_Disable();
+
+ /* MPU configure:
+ * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+ * SubRegionDisable, Size)
+ * API in mpu_armv7.h.
+ * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+ * disabled.
+ * param AccessPermission Data access permissions, allows you to configure read/write access for User and
+ * Privileged mode.
+ * Use MACROS defined in mpu_armv7.h:
+ * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+ * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+ * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
+ * 0 x 0 0 Strongly Ordered shareable
+ * 0 x 0 1 Device shareable
+ * 0 0 1 0 Normal not shareable Outer and inner write
+ * through no write allocate
+ * 0 0 1 1 Normal not shareable Outer and inner write
+ * back no write allocate
+ * 0 1 1 0 Normal shareable Outer and inner write
+ * through no write allocate
+ * 0 1 1 1 Normal shareable Outer and inner write
+ * back no write allocate
+ * 1 0 0 0 Normal not shareable outer and inner
+ * noncache
+ * 1 1 0 0 Normal shareable outer and inner
+ * noncache
+ * 1 0 1 1 Normal not shareable outer and inner write
+ * back write/read acllocate
+ * 1 1 1 1 Normal shareable outer and inner write
+ * back write/read acllocate
+ * 2 x 0 0 Device not shareable
+ * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
+ * policy.
+ * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide
+ * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+ * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+ * mpu_armv7.h.
+ */
+
+ /*
+ * Add default region to deny access to whole address space to workaround speculative prefetch.
+ * Refer to Arm errata 1013783-B for more details.
+ *
+ */
+ /* Region 0 setting: Instruction access disabled, No data access permission. */
+ MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
+
+ /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+ /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+ /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
+ MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+#endif
+
+ /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+ /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
+
+ /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
+
+ /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert(!(nonCacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
+ }
+
+ /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
+
+ /* Enable MPU */
+ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+ /* Enable I cache and D cache */
+ SCB_EnableDCache();
+ SCB_EnableICache();
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
+{
+ lpi2c_master_config_t lpi2cConfig = {0};
+
+ /*
+ * lpi2cConfig.debugEnable = false;
+ * lpi2cConfig.ignoreAck = false;
+ * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
+ * lpi2cConfig.baudRate_Hz = 100000U;
+ * lpi2cConfig.busIdleTimeout_ns = 0;
+ * lpi2cConfig.pinLowTimeout_ns = 0;
+ * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
+ * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
+ */
+ LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
+ LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_LPI2C_Send(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Write;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = txBuff;
+ xfer.dataSize = txBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subAddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ lpi2c_master_transfer_t xfer;
+
+ xfer.flags = kLPI2C_TransferDefaultFlag;
+ xfer.slaveAddress = deviceAddress;
+ xfer.direction = kLPI2C_Read;
+ xfer.subaddress = subAddress;
+ xfer.subaddressSize = subAddressSize;
+ xfer.data = rxBuff;
+ xfer.dataSize = rxBuffSize;
+
+ return LPI2C_MasterTransferBlocking(base, &xfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+
+ return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+ BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/board/board.h b/board/board.h
new file mode 100644
index 0000000..1794b62
--- /dev/null
+++ b/board/board.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "MIMXRT1020-EVK"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_INSTANCE 1U
+
+#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
+
+#define BOARD_UART_IRQ LPUART1_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/* @Brief Board accelerator sensor configuration */
+#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
+
+#define BOARD_CODEC_I2C_BASEADDR LPI2C1
+#define BOARD_CODEC_I2C_INSTANCE 1U
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
+
+/*! @brief The USER_LED used for board */
+#define LOGIC_LED_ON (0U)
+#define LOGIC_LED_OFF (1U)
+#ifndef BOARD_USER_LED_GPIO
+#define BOARD_USER_LED_GPIO GPIO1
+#endif
+#ifndef BOARD_USER_LED_GPIO_PIN
+#define BOARD_USER_LED_GPIO_PIN (5U)
+#endif
+
+#define USER_LED_INIT(output) \
+ GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
+ BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
+#define USER_LED_ON() \
+ GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
+#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClock500MHz);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClock500MHz);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+ /* Disable Usb1 PLL output for USBPHY1. */
+ CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClock500MHz);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCK500MHZ_CORE_CLOCK;
+}
+
diff --git a/board/clock_config.h b/board/clock_config.h
new file mode 100644
index 0000000..77bae5b
--- /dev/null
+++ b/board/clock_config.h
@@ -0,0 +1,109 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClock500MHz **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClock500MHz configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCK500MHZ_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCK500MHZ_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
+#define BOARD_BOOTCLOCK500MHZ_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
+#define BOARD_BOOTCLOCK500MHZ_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
+#define BOARD_BOOTCLOCK500MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
+#define BOARD_BOOTCLOCK500MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
+#define BOARD_BOOTCLOCK500MHZ_ENET_125M_CLK 0UL /* Clock consumers of ENET_125M_CLK output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_ENET_25M_REF_CLK 0UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
+#define BOARD_BOOTCLOCK500MHZ_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
+#define BOARD_BOOTCLOCK500MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
+#define BOARD_BOOTCLOCK500MHZ_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCK500MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
+#define BOARD_BOOTCLOCK500MHZ_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
+#define BOARD_BOOTCLOCK500MHZ_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
+#define BOARD_BOOTCLOCK500MHZ_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENET, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PWM1, PWM2, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TRNG, USB, USDHC1, USDHC2, WDOG1, WDOG2, XBARA, XBARB */
+#define BOARD_BOOTCLOCK500MHZ_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
+#define BOARD_BOOTCLOCK500MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCK500MHZ_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
+#define BOARD_BOOTCLOCK500MHZ_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCK500MHZ_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
+#define BOARD_BOOTCLOCK500MHZ_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCK500MHZ_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCK500MHZ_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCK500MHZ_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCK500MHZ_SEMC_CLK_ROOT 62500000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
+#define BOARD_BOOTCLOCK500MHZ_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCK500MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
+#define BOARD_BOOTCLOCK500MHZ_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCK500MHZ_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
+#define BOARD_BOOTCLOCK500MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */
+#define BOARD_BOOTCLOCK500MHZ_USDHC1_CLK_ROOT 176000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCK500MHZ_USDHC2_CLK_ROOT 176000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+
+/*! @brief Usb1 PLL set for BOARD_BootClock500MHz configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClock500MHz;
+/*! @brief Sys PLL for BOARD_BootClock500MHz configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClock500MHz;
+/*! @brief Enet PLL set for BOARD_BootClock500MHz configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClock500MHz;
+
+/*******************************************************************************
+ * API for BOARD_BootClock500MHz configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClock500MHz(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/board/dcd.c b/board/dcd.c
new file mode 100644
index 0000000..eac5e67
--- /dev/null
+++ b/board/dcd.c
@@ -0,0 +1,297 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "dcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.dcd_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.dcd_data"
+#endif
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx v3.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 15.0.1
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
+const uint8_t dcd_data[] = {
+ /* HEADER */
+ /* Tag */
+ 0xD2,
+ /* Image Length */
+ 0x03, 0xE8,
+ /* Version */
+ 0x41,
+
+ /* COMMANDS */
+
+ /* group: 'Imported Commands' */
+ /* #1.1-8, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x44, 0x04,
+ /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
+ /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
+ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
+ /* #2, command: write_clear_bits, address: CCM_ANALOG_PFD_528, value: 0x800000, size: 4 */
+ 0xCC, 0x00, 0x0C, 0x0C, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x80, 0x00, 0x00,
+ /* #3.1-98, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x03, 0x14, 0x04,
+ /* #3.1, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4 */
+ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40,
+ /* #3.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+ /* #3.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+ /* #3.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+ /* #3.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+ /* #3.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+ /* #3.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+ /* #3.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+ /* #3.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+ /* #3.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+ /* #3.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+ /* #3.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+ /* #3.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+ /* #3.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+ /* #3.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+ /* #3.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+ /* #3.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+ /* #3.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+ /* #3.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+ /* #3.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+ /* #3.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+ /* #3.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+ /* #3.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, size: 4 */
+ 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10,
+ /* #3.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+ /* #3.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+ /* #3.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+ /* #3.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #3.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+ /* #3.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+ /* #3.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+ /* #3.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+ /* #3.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
+ /* #3.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */
+ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00,
+ /* #3.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, size: 4 */
+ 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1,
+ /* #3.82, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
+ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
+ /* #3.83, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
+ /* #3.84, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
+ 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
+ /* #3.85, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
+ /* #3.86, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
+ /* #3.87, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
+ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
+ /* #3.88, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */
+ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88,
+ /* #3.89, command: write_value, address: SEMC_SDRAMCR0, value: 0xF37, size: 4 */
+ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x37,
+ /* #3.90, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
+ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
+ /* #3.91, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
+ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
+ /* #3.92, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
+ 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
+ /* #3.93, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
+ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
+ /* #3.94, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
+ 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
+ /* #3.95, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
+ /* #3.96, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+ 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #3.97, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #3.98, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+ /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #5.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #7.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #7.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #9.1-3, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x1C, 0x04,
+ /* #9.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
+ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
+ /* #9.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #9.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
+ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+ /* #10, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+ /* #11, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
+ 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
+ };
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
+#else
+const uint8_t dcd_data[] = {0x00};
+#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/dcd.h b/board/dcd.h
new file mode 100644
index 0000000..3d8b7cd
--- /dev/null
+++ b/board/dcd.h
@@ -0,0 +1,25 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef __DCD__
+#define __DCD__
+
+#include
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*************************************
+ * DCD Data
+ *************************************/
+#define DCD_TAG_HEADER (0xD2)
+#define DCD_VERSION (0x41)
+#define DCD_TAG_HEADER_SHIFT (24)
+#define DCD_ARRAY_SIZE 1
+
+#endif /* __DCD__ */
diff --git a/board/peripherals.c b/board/peripherals.c
new file mode 100644
index 0000000..36743b5
--- /dev/null
+++ b/board/peripherals.c
@@ -0,0 +1,94 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v14.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 15.0.1
+functionalGroups:
+- name: BOARD_InitPeripherals
+ UUID: 8b4c2e98-702d-4536-9c18-c28aae77cb4e
+ called_from_default_init: true
+ selectedCore: core0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions:
+ - user_definitions: ''
+ - user_includes: ''
+ - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8'
+- global_USART_CMSIS_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6'
+- global_gpio_adapter_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'NVIC'
+- config_sets:
+ - nvic:
+ - interrupt_table: []
+ - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+ /* Initialize components */
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
diff --git a/board/peripherals.h b/board/peripherals.h
new file mode 100644
index 0000000..2a75809
--- /dev/null
+++ b/board/peripherals.h
@@ -0,0 +1,33 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/board/pin_mux.c b/board/pin_mux.c
new file mode 100644
index 0000000..5567e4b
--- /dev/null
+++ b/board/pin_mux.c
@@ -0,0 +1,56 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v15.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 15.0.1
+power_domains: {NVCC_GPIO: '3.3'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitDbgUARTPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDbgUARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
+ - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDbgUARTPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDbgUARTPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/pin_mux.h b/board/pin_mux.h
new file mode 100644
index 0000000..7829981
--- /dev/null
+++ b/board/pin_mux.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type */
+typedef enum _pin_mux_direction
+{
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDbgUARTPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/src/main.c b/src/main.c
new file mode 100644
index 0000000..e42a6d2
--- /dev/null
+++ b/src/main.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ char ch;
+
+ /* Init board hardware. */
+ BOARD_ConfigMPU();
+ BOARD_InitBootPins();
+ BOARD_InitBootClocks();
+ BOARD_InitDebugConsole();
+
+ PRINTF("hello world.\r\n");
+
+ while (1)
+ {
+ ch = GETCHAR();
+ PUTCHAR(ch);
+ }
+}
diff --git a/xip/fire_rt1021_evk_flexspi_nor_config.c b/xip/fire_rt1021_evk_flexspi_nor_config.c
new file mode 100644
index 0000000..f94fd5f
--- /dev/null
+++ b/xip/fire_rt1021_evk_flexspi_nor_config.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fire_rt1021_evk_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+ .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
+ .deviceType = kFlexSpiDeviceType_SerialNOR,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
+ .sflashA1Size = 32u * 1024u * 1024u,
+ .lookupTable =
+ {
+ // Read LUTs
+ [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
+ [1] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04),
+ [2] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0x00),
+
+ // Read Status LUTs
+ [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+
+ // Write Enable LUTs
+ [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
+
+ // Erase Sector LUTs
+ [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
+
+ // Erase Block LUTs
+ [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20),
+
+ // Pape Program LUTs
+ [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20),
+ [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x00, STOP, FLEXSPI_1PAD, 0x0),
+
+ // Erase Chip LUTs
+ [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = 1u,
+ .blockSize = 64u * 1024u,
+ .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/xip/fire_rt1021_evk_flexspi_nor_config.h b/xip/fire_rt1021_evk_flexspi_nor_config.h
new file mode 100644
index 0000000..844aaad
--- /dev/null
+++ b/xip/fire_rt1021_evk_flexspi_nor_config.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
+
+#include
+#include
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_100MHz = 6,
+ kFlexSpiSerialClk_133MHz = 7,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+ kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+ kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
+ kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
+ kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+ kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
+ kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
+ kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+ uint8_t seqId; //!< Sequence Index, valid number: 0-15
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+ kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
+ kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+ kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
+ kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
+ kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
+ kDeviceConfigCmdType_Reset, //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+ uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+ uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
+ uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+ uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
+ uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
+ uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+ //! Serial NAND, need to refer to datasheet
+ uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+ uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+ //! Generic configuration, etc.
+ uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+ //! DPI/QPI/OPI switch or reset command
+ flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+ //! sequence number, [31:16] Reserved
+ uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
+ uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+ uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+ uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
+ uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+ uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
+ uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+ //! details
+ uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
+ uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+ uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+ //! Chapter for more details
+ uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+ //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+ uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+ uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+ uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
+ uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+ uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
+ uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
+ uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+ uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+ uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
+ uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
+ uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
+ uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+ uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+ uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+ //! busy flag is 0 when flash device is busy
+ uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
+ flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+ uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/* */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
+#define NOR_CMD_INDEX_DUMMY 6 //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+ CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+ CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+ CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ * Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+ uint32_t pageSize; //!< Page size of Serial NOR
+ uint32_t sectorSize; //!< Sector size of Serial NOR
+ uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
+ uint8_t isUniformBlockSize; //!< Sector/Block size is the same
+ uint8_t reserved0[2]; //!< Reserved for future use
+ uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
+ uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
+ uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
+ uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
+ uint32_t blockSize; //!< Block size
+ uint32_t reserve2[11]; //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */