diff --git a/.clang-format b/.clang-format index 7ba2003..5da9c43 100644 --- a/.clang-format +++ b/.clang-format @@ -1,7 +1,8 @@ BasedOnStyle: Google IndentWidth: 4 +AllowShortFunctionsOnASingleLine: None AlignConsecutiveMacros: AcrossEmptyLines -AlignConsecutiveDeclarations: AcrossEmptyLines +AlignConsecutiveDeclarations: Consecutive AlignConsecutiveAssignments: AcrossEmptyLinesAndComments BreakBeforeBraces: Custom BraceWrapping: diff --git a/.gitmodules b/.gitmodules index e537b8d..58b3a71 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,9 @@ [submodule "SDK"] path = SDK - url = git@git.minori.work:Embedded_SDK/MCUXpresso_MIMXRT1052xxxxB.git + url = https://git.minori.work/Embedded_SDK/MCUXpresso_MIMXRT1052xxxxB.git +[submodule "lib/lvgl"] + path = lib/lvgl + url = https://github.com/lvgl/lvgl.git +[submodule "lib/freertos"] + path = lib/freertos + url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git diff --git a/CMakeLists.txt b/CMakeLists.txt index d33b5b1..a8e625a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,15 +1,17 @@ cmake_minimum_required(VERSION 3.10) -project(fire_rt1052_pro_template) +project(fire_rt1052_pro_lvgl) enable_language(CXX) enable_language(ASM) # Different linker scripts set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld") +set(TARGET_LDSCRIPT_FLASH_SDRAM "${CMAKE_SOURCE_DIR}/gcc/flexspi_nor_sdram.ld") set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld") set(TARGET_SOURCES + "SDK/components/gt911/fsl_gt911.c" "SDK/components/serial_manager/fsl_component_serial_manager.c" "SDK/components/serial_manager/fsl_component_serial_port_uart.c" "SDK/components/uart/fsl_adapter_lpuart.c" @@ -95,6 +97,7 @@ set(TARGET_SOURCES "board/dcd.c" "board/peripherals.c" "board/pin_mux.c" + "src/app_lvgl.c" "src/main.c" "xip/fire_rt1052_pro_flexspi_nor_config.c" ) @@ -104,6 +107,7 @@ set(TARGET_C_DEFINES "MCUXPRESSO_SDK" "PRINTF_ADVANCED_ENABLE=1" "PRINTF_FLOAT_ENABLE=1" + "SDK_OS_FREE_RTOS" "SERIAL_PORT_TYPE_UART" "__STARTUP_CLEAR_BSS" "__STARTUP_INITIALIZE_NONCACHEDATA" @@ -114,10 +118,12 @@ set(TARGET_C_DEFINES_XIP "XIP_BOOT_HEADER_ENABLE=1" "XIP_BOOT_HEADER_DCD_ENABLE=1" "XIP_EXTERNAL_FLASH=1" + "__STARTUP_INITIALIZE_RAMFUNCTION" ) set(TARGET_C_INCLUDES "SDK/CMSIS/Core/Include" + "SDK/components/gt911" "SDK/components/serial_manager" "SDK/components/uart" "SDK/devices/MIMXRT1052" @@ -131,6 +137,9 @@ set(TARGET_C_INCLUDES # Shared libraries linked with application set(TARGET_LIBS + "lvgl" + "lvgl_demos" + "freertos_kernel" "c" "m" "nosys" @@ -138,9 +147,6 @@ set(TARGET_LIBS # Shared library and linker script search paths set(TARGET_LIB_DIRECTORIES - "c" - "m" - "nosys" ) # Conditional flags @@ -150,10 +156,10 @@ set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0 -g") set(CMAKE_ASM_FLAGS_DEBUG "-DDEBUG -O0 -g") # RELEASE -set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto") -set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto") -set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto") -set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto") +set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2") +set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2") +set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2") +set(CMAKE_EXE_LINKER_FLAGS_RELEASE "") # Final compiler flags set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections") @@ -161,6 +167,15 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp") set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections") +set(LV_CONF_PATH "${CMAKE_CURRENT_SOURCE_DIR}/include/lv_conf.h" CACHE STRING "") +add_subdirectory(lib/lvgl) + +add_library(freertos_config INTERFACE) +target_include_directories(freertos_config SYSTEM INTERFACE include) +set(FREERTOS_PORT "GCC_ARM_CM7" CACHE STRING "") +set(FREERTOS_HEAP "4" CACHE STRING "") +add_subdirectory(lib/freertos) + # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) include_directories(${TARGET_C_INCLUDES}) @@ -192,6 +207,29 @@ add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD ) endif() +# Create ELF +add_executable("${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" ${TARGET_SOURCES}) +target_compile_definitions("${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" + PRIVATE ${TARGET_C_DEFINES_XIP} +) +target_link_options("${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" + PRIVATE "-T${TARGET_LDSCRIPT_FLASH_SDRAM}" + PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_FLASH_SDRAM.map" +) +set_property(TARGET "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" APPEND + PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.map" +) +add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.hex" + COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.hex" + DEPENDS "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" +) +add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_SDRAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.hex") +if(DEFINED TARGET_TOOLCHAIN_SIZE) + add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" POST_BUILD + COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH_SDRAM.elf" + ) +endif() + # Create ELF add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${TARGET_SOURCES}) target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf" diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex index 6d55fc0..bce8caf 100644 --- a/MIMXRT1052xxxxB.mex +++ b/MIMXRT1052xxxxB.mex @@ -1,5 +1,5 @@ - + MIMXRT1052xxxxB MIMXRT1052DVL6B @@ -17,13 +17,13 @@ false - + - 13.0.1 + 14.0.0 @@ -34,6 +34,8 @@ + + @@ -306,6 +308,11 @@ true + + + true + + true @@ -349,6 +356,16 @@ + + + + + + + + + + @@ -628,7 +645,7 @@ Configures pin routing and optionally pin electrical features. - false + true core0 true @@ -650,8 +667,18 @@ - - + + + + + + + + + + + + @@ -714,13 +741,13 @@ - + - 13.0.1 + 14.0.0 @@ -773,8 +800,8 @@ - - + + @@ -800,6 +827,10 @@ + + + + @@ -814,8 +845,13 @@ + + + + + - false + true @@ -899,7 +935,7 @@ - true + false @@ -984,24 +1020,171 @@ - 13.0.1 + 14.0.0 c_array - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + true + + + + + 2.5.0 + + + + + true + + + - 13.0.1 + 14.0.0 @@ -1015,6 +1198,68 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SDK b/SDK new file mode 160000 index 0000000..75f3218 --- /dev/null +++ b/SDK @@ -0,0 +1 @@ +Subproject commit 75f32185d29dbd53f964f34b51e332c04700871d diff --git a/assets/MIMXRT1052.svd b/assets/MIMXRT1052.svd new file mode 100644 index 0000000..53e5618 --- /dev/null +++ b/assets/MIMXRT1052.svd @@ -0,0 +1,219123 @@ + + + nxp.com + MIMXRT1052 + 1.0 + MIMXRT1052DVL6B + +Copyright 2016-2021 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM7 + r0p1 + little + true + true + true + 4 + false + + 8 + 32 + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + AIPSTZ + 0x4007C000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 16 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 20 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 24 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 28 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC6 + Off-platform Peripheral Access Control 6 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC5 + Off-platform Peripheral Access Control 5 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC4 + Off-platform Peripheral Access Control 4 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC3 + Off-platform Peripheral Access Control 3 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC2 + Off-platform Peripheral Access Control 2 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC1 + Off-platform Peripheral Access Control 1 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC0 + Off-platform Peripheral Access Control 0 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC14 + Off-platform Peripheral Access Control 14 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC13 + Off-platform Peripheral Access Control 13 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC12 + Off-platform Peripheral Access Control 12 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC11 + Off-platform Peripheral Access Control 11 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC10 + Off-platform Peripheral Access Control 10 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC9 + Off-platform Peripheral Access Control 9 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC8 + Off-platform Peripheral Access Control 8 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC22 + Off-platform Peripheral Access Control 22 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC21 + Off-platform Peripheral Access Control 21 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC20 + Off-platform Peripheral Access Control 20 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC19 + Off-platform Peripheral Access Control 19 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC18 + Off-platform Peripheral Access Control 18 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC17 + Off-platform Peripheral Access Control 17 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC16 + Off-platform Peripheral Access Control 16 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC30 + Off-platform Peripheral Access Control 30 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC29 + Off-platform Peripheral Access Control 29 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC28 + Off-platform Peripheral Access Control 28 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC27 + Off-platform Peripheral Access Control 27 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC26 + Off-platform Peripheral Access Control 26 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC25 + Off-platform Peripheral Access Control 25 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC24 + Off-platform Peripheral Access Control 24 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC32 + Off-platform Peripheral Access Control 32 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x4017C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x4027C000 + + 0 + 0x54 + registers + + + + AIPSTZ4 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ4_ + 0x4037C000 + + 0 + 0x54 + registers + + + + DCDC + DCDC + DCDC + 0x40080000 + + 0 + 0x10 + registers + + + DCDC + 69 + + + + REG0 + DCDC Register 0 + 0 + 32 + read-write + 0x14030111 + 0xFFFFFFFF + + + PWD_ZCD + Power Down Zero Cross Detection + 0 + 1 + read-write + + + powered_up + Zero cross detetion function powered up + 0 + + + powered_down + Zero cross detetion function powered down + 0x1 + + + + + DISABLE_AUTO_CLK_SWITCH + Disable Auto Clock Switch + 1 + 1 + read-write + + + xtal_clk + If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically + 0 + + + sel_clk + If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses + 0x1 + + + + + SEL_CLK + Select Clock + 2 + 1 + read-write + + + int_rng_osc + DCDC uses internal ring oscillator + 0 + + + xtal_24M + DCDC uses 24M xtal + 0x1 + + + + + PWD_OSC_INT + Power down internal osc + 3 + 1 + read-write + + + powered_up + Internal oscillator powered up + 0 + + + powered_down + Internal oscillator powered down + 0x1 + + + + + PWD_CUR_SNS_CMP + Power down signal of the current detector. + 4 + 1 + read-write + + + powered_up + Current Detector powered up + 0 + + + powered_down + Current Detector powered down + 0x1 + + + + + CUR_SNS_THRSH + Current Sense (detector) Threshold + 5 + 3 + read-write + + + select_zero + 150 mA + 0 + + + select_one + 250 mA + 0x1 + + + select_two + 350 mA + 0x2 + + + select_three + 450 mA + 0x3 + + + select_four + 550 mA + 0x4 + + + select_five + 650 mA + 0x5 + + + + + PWD_OVERCUR_DET + Power down overcurrent detection comparator + 8 + 1 + read-write + + + enabled + Overcurrent detection comparator is enabled + 0 + + + disabled + Overcurrent detection comparator is disabled + 0x1 + + + + + OVERCUR_TRIG_ADJ + Overcurrent Trigger Adjust + 9 + 2 + read-write + + + select_zero + In Run Mode, 1 A. In Power Save Mode, 0.25 A + 0 + + + select_one + In Run Mode, 2 A. In Power Save Mode, 0.25 A + 0x1 + + + select_two + In Run Mode, 1 A. In Power Save Mode, 0.2 A + 0x2 + + + select_three + In Run Mode, 2 A. In Power Save Mode, 0.2 A + 0x3 + + + + + PWD_CMP_BATT_DET + Power Down Battery Detection Comparator + 11 + 1 + read-write + + + enabled + Low voltage detection comparator is enabled + 0 + + + disabled + Low voltage detection comparator is disabled + 0x1 + + + + + EN_LP_OVERLOAD_SNS + Low Power Overload Sense Enable + 16 + 1 + read-write + + + disabled + Overload Detection in power save mode disabled + 0 + + + enabled + Overload Detection in power save mode enabled + 0x1 + + + + + PWD_HIGH_VOLT_DET + Power Down High Voltage Detection + 17 + 1 + read-write + + + enabled + Overvoltage detection comparator is enabled + 0 + + + disabled + Overvoltage detection comparator is disabled + 0x1 + + + + + LP_OVERLOAD_THRSH + Low Power Overload Threshold + 18 + 2 + read-write + + + thrsh_32 + 32 + 0 + + + thrsh_64 + 64 + 0x1 + + + thrsh_16 + 16 + 0x2 + + + thrsh_8 + 8 + 0x3 + + + + + LP_OVERLOAD_FREQ_SEL + Low Power Overload Frequency Select + 20 + 1 + read-write + + + eight_32k_cycle + eight 32k cycle + 0 + + + sixteen_32k_cycle + sixteen 32k cycle + 0x1 + + + + + LP_HIGH_HYS + Low Power High Hysteric Value + 21 + 1 + read-write + + + lp_12p5mV + Adjust hysteretic value in low power to 12.5mV + 0 + + + lp_25mV + Adjust hysteretic value in low power to 25mV + 0x1 + + + + + PWD_CMP_OFFSET + Power down output range comparator + 26 + 1 + read-write + + + powered_up + Output range comparator powered up + 0 + + + powered_down + Output range comparator powered down + 0x1 + + + + + XTALOK_DISABLE + Disable xtalok detection circuit + 27 + 1 + read-write + + + enabled + Enable xtalok detection circuit + 0 + + + disabled + Disable xtalok detection circuit and always outputs OK signal "1" + 0x1 + + + + + CURRENT_ALERT_RESET + Reset Current Alert Signal + 28 + 1 + read-write + + + not_reset + Current Alert Signal not reset + 0 + + + reset + Current Alert Signal reset + 0x1 + + + + + XTAL_24M_OK + 24M XTAL OK + 29 + 1 + read-write + + + int_rng_osc + DCDC uses internal ring OSC + 0 + + + xtal_24M + DCDC uses xtal 24M + 0x1 + + + + + STS_DC_OK + DCDC Output OK + 31 + 1 + read-only + + + not_settled + DCDC is settling + 0 + + + settled + DCDC already settled + 0x1 + + + + + + + REG1 + DCDC Register 1 + 0x4 + 32 + read-write + 0x111BA29C + 0xFFFFFFFF + + + REG_FBK_SEL + Select the feedback point of the internal regulator + 7 + 2 + read-write + + + reg_fbk_sel0 + The regulator outputs 1.0V with 1.2V reference voltage + 0 + + + reg_fbk_sel1 + The regulator outputs 1.1V with 1.2V reference voltage + 0x1 + + + reg_fbk_sel2 + The regulator outputs 1.0V with 1.3V reference voltage + 0x2 + + + reg_fbk_sel3 + The regulator outputs 1.1V with 1.3V reference voltage + 0x3 + + + + + REG_RLOAD_SW + This controls the load resistor of the internal regulator of DCDC + 9 + 1 + read-write + + + loadR_disconnect + Load resistor disconnected + 0 + + + loadR_connect + Load resistor connected + 0x1 + + + + + LP_CMP_ISRC_SEL + Low Power Comparator Current Bias + 12 + 2 + read-write + + + sel0 + 50 nA + 0 + + + sel1 + 100 nA + 0x1 + + + sel2 + 200 nA + 0x2 + + + sel3 + 400 nA + 0x3 + + + + + LOOPCTRL_HST_THRESH + Increase Threshold Detection + 21 + 1 + read-write + + + low_hyst_thresh + Lower hysteresis threshold (about 2.5mV in typical, but this value can vary with PVT corners + 0 + + + high_hyst_thresh + Higher hysteresis threshold (about 5mV in typical) + 0x1 + + + + + LOOPCTRL_EN_HYST + Enable Hysteresis + 23 + 1 + read-write + + + disable + Disable hysteresis in switching converter common mode analog comparators + 0 + + + enable + Enable hysteresis in switching converter common mode analog comparators + 0x1 + + + + + VBG_TRIM + Trim Bandgap Voltage + 24 + 5 + read-write + + + + + REG2 + DCDC Register 2 + 0x8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOOPCTRL_DC_FF + Two's complement feed forward step in duty cycle in the switching DC-DC converter + 6 + 3 + read-write + + + LOOPCTRL_EN_RCSCALE + Enable RC Scale + 9 + 3 + read-write + + + LOOPCTRL_RCSCALE_THRSH + Increase the threshold detection for RC scale circuit. + 12 + 1 + read-write + + + no_increase_thrsh + Do not increase the threshold detection for RC scale circuit. + 0 + + + increase_thrsh + Increase the threshold detection for RC scale circuit. + 0x1 + + + + + LOOPCTRL_HYST_SIGN + Invert the sign of the hysteresis in DC-DC analog comparators. + 13 + 1 + read-write + + + noinvert + Do not invert sign of the hysteresis + 0 + + + invert + Invert sign of the hysteresis + 0x1 + + + + + DISABLE_PULSE_SKIP + Disable Pulse Skip + 27 + 1 + read-write + + + idle + DCDC will be idle to save current dissipation when the duty cycle get to the low limit which is set by NEGLIMIT_IN. + 0 + + + not_idle + DCDC will keep working with the low limited duty cycle NEGLIMIT_IN. + 0x1 + + + + + DCM_SET_CTRL + DCM Set Control + 28 + 1 + read-write + + + + + REG3 + DCDC Register 3 + 0xC + 32 + read-write + 0x10E + 0xFFFFFFFF + + + TRG + Target value of VDD_SOC + 0 + 5 + read-write + + + TARGET_LP + Low Power Target Value + 8 + 3 + read-write + + + sel0 + 0.9 V + 0 + + + sel1 + 0.925 V + 0x1 + + + sel2 + 0.95 V + 0x2 + + + sel3 + 0.975 V + 0x3 + + + sel4 + 1.0 V + 0x4 + + + + + MINPWR_DC_HALFCLK + Set DCDC clock to half frequency for continuous mode + 24 + 1 + read-write + + + fullfreq + DCDC clock remains at full frequency for continuous mode + 0 + + + halffreq + DCDC clock set to half frequency for continuous mode + 0x1 + + + + + DISABLE_STEP + Disable Step + 30 + 1 + read-write + + + enable + Enable stepping for the output of VDD_SOC of DCDC + 0 + + + disable + Disable stepping for the output of VDD_SOC of DCDC + 0x1 + + + + + + + + + PIT + PIT + PIT + 0x40084000 + + 0 + 0x140 + registers + + + PIT + 122 + + + + MCR + PIT Module Control Register + 0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + FRZ + Freeze + 0 + 1 + read-write + + + FRZ_0 + Timers continue to run in Debug mode. + 0 + + + FRZ_1 + Timers are stopped in Debug mode. + 0x1 + + + + + MDIS + Module Disable for PIT + 1 + 1 + read-write + + + MDIS_0 + Clock for standard PIT timers is enabled. + 0 + + + MDIS_1 + Clock for standard PIT timers is disabled. + 0x1 + + + + + + + LTMR64H + PIT Upper Lifetime Timer Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTH + Life Timer value + 0 + 32 + read-only + + + + + LTMR64L + PIT Lower Lifetime Timer Register + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTL + Life Timer value + 0 + 32 + read-only + + + + + 4 + 0x10 + TIMER[%s] + no description available + 0x100 + + LDVAL + Timer Load Value Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 32 + read-write + + + + + CVAL + Current Timer Value Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL + Timer Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + TEN_0 + Timer n is disabled. + 0 + + + TEN_1 + Timer n is enabled. + 0x1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + TIE_0 + Interrupt requests from Timer n are disabled. + 0 + + + TIE_1 + Interrupt is requested whenever TIF is set. + 0x1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + CHN_0 + Timer is not chained. + 0 + + + CHN_1 + Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. + 0x1 + + + + + + + TFLG + Timer Flag Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + oneToClear + + + TIF_0 + Timeout has not yet occurred. + 0 + + + TIF_1 + Timeout has occurred. + 0x1 + + + + + + + + + + CMP1 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP1_ + ACMP + 0x40094000 + + 0 + 0x6 + registers + + + ACMP1 + 123 + + + + CR0 + CMP Control Register 0 + 0 + 8 + read-write + 0 + 0xFF + + + HYSTCTR + Comparator hard block hysteresis control + 0 + 2 + read-write + + + HYSTCTR_0 + Level 0 + 0 + + + HYSTCTR_1 + Level 1 + 0x1 + + + HYSTCTR_2 + Level 2 + 0x2 + + + HYSTCTR_3 + Level 3 + 0x3 + + + + + FILTER_CNT + Filter Sample Count + 4 + 3 + read-write + + + FILTER_CNT_0 + Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + 0 + + + FILTER_CNT_1 + One sample must agree. The comparator output is simply sampled. + 0x1 + + + FILTER_CNT_2 + 2 consecutive samples must agree. + 0x2 + + + FILTER_CNT_3 + 3 consecutive samples must agree. + 0x3 + + + FILTER_CNT_4 + 4 consecutive samples must agree. + 0x4 + + + FILTER_CNT_5 + 5 consecutive samples must agree. + 0x5 + + + FILTER_CNT_6 + 6 consecutive samples must agree. + 0x6 + + + FILTER_CNT_7 + 7 consecutive samples must agree. + 0x7 + + + + + + + CR1 + CMP Control Register 1 + 0x1 + 8 + read-write + 0 + 0xFF + + + EN + Comparator Module Enable + 0 + 1 + read-write + + + EN_0 + Analog Comparator is disabled. + 0 + + + EN_1 + Analog Comparator is enabled. + 0x1 + + + + + OPE + Comparator Output Pin Enable + 1 + 1 + read-write + + + OPE_0 + CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + 0 + + + OPE_1 + CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + 0x1 + + + + + COS + Comparator Output Select + 2 + 1 + read-write + + + COS_0 + Set the filtered comparator output (CMPO) to equal COUT. + 0 + + + COS_1 + Set the unfiltered comparator output (CMPO) to equal COUTA. + 0x1 + + + + + INV + Comparator INVERT + 3 + 1 + read-write + + + INV_0 + Does not invert the comparator output. + 0 + + + INV_1 + Inverts the comparator output. + 0x1 + + + + + PMODE + Power Mode Select + 4 + 1 + read-write + + + PMODE_0 + Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + 0 + + + PMODE_1 + High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + 0x1 + + + + + WE + Windowing Enable + 6 + 1 + read-write + + + WE_0 + Windowing mode is not selected. + 0 + + + WE_1 + Windowing mode is selected. + 0x1 + + + + + SE + Sample Enable + 7 + 1 + read-write + + + SE_0 + Sampling mode is not selected. + 0 + + + SE_1 + Sampling mode is selected. + 0x1 + + + + + + + FPR + CMP Filter Period Register + 0x2 + 8 + read-write + 0 + 0xFF + + + FILT_PER + Filter Sample Period + 0 + 8 + read-write + + + + + SCR + CMP Status and Control Register + 0x3 + 8 + read-write + 0 + 0xFF + + + COUT + Analog Comparator Output + 0 + 1 + read-only + + + CFF + Analog Comparator Flag Falling + 1 + 1 + read-write + oneToClear + + + CFF_0 + Falling-edge on COUT has not been detected. + 0 + + + CFF_1 + Falling-edge on COUT has occurred. + 0x1 + + + + + CFR + Analog Comparator Flag Rising + 2 + 1 + read-write + oneToClear + + + CFR_0 + Rising-edge on COUT has not been detected. + 0 + + + CFR_1 + Rising-edge on COUT has occurred. + 0x1 + + + + + IEF + Comparator Interrupt Enable Falling + 3 + 1 + read-write + + + IEF_0 + Interrupt is disabled. + 0 + + + IEF_1 + Interrupt is enabled. + 0x1 + + + + + IER + Comparator Interrupt Enable Rising + 4 + 1 + read-write + + + IER_0 + Interrupt is disabled. + 0 + + + IER_1 + Interrupt is enabled. + 0x1 + + + + + DMAEN + DMA Enable Control + 6 + 1 + read-write + + + DMAEN_0 + DMA is disabled. + 0 + + + DMAEN_1 + DMA is enabled. + 0x1 + + + + + + + DACCR + DAC Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + VOSEL + DAC Output Voltage Select + 0 + 6 + read-write + + + VRSEL + Supply Voltage Reference Source Select + 6 + 1 + read-write + + + VRSEL_0 + Vin1 is selected as resistor ladder network supply reference. + 0 + + + VRSEL_1 + Vin2 is selected as resistor ladder network supply reference. + 0x1 + + + + + DACEN + DAC Enable + 7 + 1 + read-write + + + DACEN_0 + DAC is disabled. + 0 + + + DACEN_1 + DAC is enabled. + 0x1 + + + + + + + MUXCR + MUX Control Register + 0x5 + 8 + read-write + 0 + 0xFF + + + MSEL + Minus Input Mux Control + 0 + 3 + read-write + + + MSEL_0 + IN0 + 0 + + + MSEL_1 + IN1 + 0x1 + + + MSEL_2 + IN2 + 0x2 + + + MSEL_3 + IN3 + 0x3 + + + MSEL_4 + IN4 + 0x4 + + + MSEL_5 + IN5 + 0x5 + + + MSEL_6 + IN6 + 0x6 + + + MSEL_7 + IN7 + 0x7 + + + + + PSEL + Plus Input Mux Control + 3 + 3 + read-write + + + PSEL_0 + IN0 + 0 + + + PSEL_1 + IN1 + 0x1 + + + PSEL_2 + IN2 + 0x2 + + + PSEL_3 + IN3 + 0x3 + + + PSEL_4 + IN4 + 0x4 + + + PSEL_5 + IN5 + 0x5 + + + PSEL_6 + IN6 + 0x6 + + + PSEL_7 + IN7 + 0x7 + + + + + + + + + CMP2 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP2_ + 0x40094008 + + 0 + 0x6 + registers + + + ACMP2 + 124 + + + + CMP3 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP3_ + 0x40094010 + + 0 + 0x6 + registers + + + ACMP3 + 125 + + + + CMP4 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP4_ + 0x40094018 + + 0 + 0x6 + registers + + + ACMP4 + 126 + + + + IOMUXC_SNVS_GPR + IOMUXC + IOMUXC_SNVS_GPR + IOMUXC_SNVS_GPR_ + 0x400A4000 + + 0 + 0x10 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + LPSR_MODE_ENABLE + Set to enable LPSR mode. + 0 + 1 + read-write + + + LPSR_MODE_ENABLE_0 + SNVS domain will reset when system reset happens + 0 + + + LPSR_MODE_ENABLE_1 + SNVS domain will only reset with SNVS POR + 0x1 + + + + + DCDC_STATUS_CAPT_CLR + DCDC captured status clear + 1 + 1 + read-write + + + POR_PULL_TYPE + POR_B pad control + 2 + 2 + read-write + + + POR_PULL_TYPE_0 + 100 Ohm pull up enabled for POR_B always + 0 + + + POR_PULL_TYPE_1 + Disable pull in SNVS mode, 100 Ohm pull up enabled otherwise + 0x1 + + + POR_PULL_TYPE_2 + Disable pull of POR_B always + 0x2 + + + POR_PULL_TYPE_3 + 100 Ohm pull down enabled in SNVS mode, 100 Ohm pull up enabled otherwise + 0x3 + + + + + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. + 16 + 1 + read-only + + + DCDC_IN_LOW_VOL_0 + DCDC_IN is ok + 0 + + + DCDC_IN_LOW_VOL_1 + DCDC_IN is too low + 0x1 + + + + + DCDC_OVER_CUR + DCDC output over current alert + 17 + 1 + read-only + + + DCDC_OVER_CUR_0 + No over current detected + 0 + + + DCDC_OVER_CUR_1 + Over current detected + 0x1 + + + + + DCDC_OVER_VOL + DCDC output over voltage alert + 18 + 1 + read-only + + + DCDC_OVER_VOL_0 + No over voltage detected + 0 + + + DCDC_OVER_VOL_1 + Over voltage detected + 0x1 + + + + + DCDC_STS_DC_OK + DCDC status OK + 19 + 1 + read-only + + + DCDC_STS_DC_OK_0 + DCDC is ramping up and not ready + 0 + + + DCDC_STS_DC_OK_1 + DCDC is ready + 0x1 + + + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x400A8000 + + 0 + 0x24 + registers + + + + SW_MUX_CTL_PAD_WAKEUP + SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register + 0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: NMI of instance: CM7 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad WAKEUP + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_ON_REQ + SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SNVS_PMIC_ON_REQ of instance: snvs + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_ON_REQ + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_STBY_REQ + SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CCM_PMIC_STBY_REQ of instance: ccm + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_STBY_REQ + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0xC + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x10 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x14 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_WAKEUP + SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register + 0x18 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_ON_REQ + SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register + 0x1C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_STBY_REQ + SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register + 0x20 + 32 + read-write + 0xA0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + Medium + 100MHz + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + + + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR_ + 0x400AC000 + + 0 + 0x68 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SAI1_MCLK1_SEL + SAI1 MCLK1 source select + 0 + 3 + read-write + + + SAI1_MCLK1_SEL_0 + SAI1_CLK_ROOT + 0 + + + SAI1_MCLK1_SEL_1 + SAI2_CLK_ROOT + 0x1 + + + SAI1_MCLK1_SEL_2 + SAI3_CLK_ROOT + 0x2 + + + SAI1_MCLK1_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK1_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK1_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK2_SEL + SAI1 MCLK2 source select + 3 + 3 + read-write + + + SAI1_MCLK2_SEL_0 + SAI1_CLK_ROOT + 0 + + + SAI1_MCLK2_SEL_1 + SAI2_CLK_ROOT + 0x1 + + + SAI1_MCLK2_SEL_2 + SAI3_CLK_ROOT + 0x2 + + + SAI1_MCLK2_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK2_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK2_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK3_SEL + SAI1 MCLK3 source select + 6 + 2 + read-write + + + SAI1_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI1_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI1_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI1_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI2_MCLK3_SEL + SAI2 MCLK3 source select + 8 + 2 + read-write + + + SAI2_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI2_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI2_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI2_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI3_MCLK3_SEL + SAI3 MCLK3 source select + 10 + 2 + read-write + + + SAI3_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI3_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI3_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI3_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + GINT + Global Interrupt + 12 + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted + 0 + + + GINT_1 + Global interrupt request is asserted. Interrupt is issued to Arm M7 IRQ#41 and GPC + 0x1 + + + + + ENET_TX_CLK_SEL + ENET_TX_CLK select + 13 + 1 + read-write + + + ENET_TX_CLK_SEL_0 + Do not use + 0 + + + ENET_TX_CLK_SEL_1 + ENET_TX_CLK is the 25MHz MII clock + 0x1 + + + + + ENET_REF_CLK_DIR + ENET_REF_CLK direction control + 17 + 1 + read-write + + + ENET_REF_CLK_DIR_0 + ENET_REF_CLK is input + 0 + + + ENET_REF_CLK_DIR_1 + ENET_REF_CLK is output driven by ref_enetpll0 + 0x1 + + + + + SAI1_MCLK_DIR + SAI1_MCLK signal direction control. Sets the direction for the SAI1_MCLK pin function. + 19 + 1 + read-write + + + SAI1_MCLK_DIR_0 + SAI1_MCLK is input signal + 0 + + + SAI1_MCLK_DIR_1 + SAI1_MCLK is output signal + 0x1 + + + + + SAI2_MCLK_DIR + SAI2_MCLK signal direction control. Sets the direction for the SAI2_MCLK pin function. + 20 + 1 + read-write + + + SAI2_MCLK_DIR_0 + SAI2_MCLK is input signal + 0 + + + SAI2_MCLK_DIR_1 + SAI2_MCLK is output signal + 0x1 + + + + + SAI3_MCLK_DIR + SAI3_MCLK signal direction control. Sets the direction for the SAI3_MCLK pin function. + 21 + 1 + read-write + + + SAI3_MCLK_DIR_0 + SAI3_MCLK is input signal + 0 + + + SAI3_MCLK_DIR_1 + SAI3_MCLK is output signal + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 22 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response + 0x1 + + + + + CM7_FORCE_HCLK_EN + Arm CM7 platform AHB clock enable + 31 + 1 + read-write + + + CM7_FORCE_HCLK_EN_0 + AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible + 0 + + + CM7_FORCE_HCLK_EN_1 + AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + L2_MEM_EN_POWERSAVING + Enable power saving features on memory + 12 + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + Enters power saving mode only when chip is in SUSPEND mode + 0 + + + L2_MEM_EN_POWERSAVING_1 + Controlled by L2_MEM_DEEPSLEEP bitfield + 0x1 + + + + + L2_MEM_DEEPSLEEP + This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 14 + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode) + 0 + + + L2_MEM_DEEPSLEEP_1 + Force memory into deep sleep mode (OCRAM in power saving mode) + 0x1 + + + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 16 + 8 + read-write + + + DIVIDE_1 + mclk frequency = 1/1 * hmclk frequency + 0 + + + DIVIDE_2 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + DIVIDE_3 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + DIVIDE_4 + mclk frequency = 1/4 * hmclk frequency + 0x3 + + + DIVIDE_5 + mclk frequency = 1/5 * hmclk frequency + 0x4 + + + DIVIDE_6 + mclk frequency = 1/6 * hmclk frequency + 0x5 + + + DIVIDE_7 + mclk frequency = 1/7 * hmclk frequency + 0x6 + + + DIVIDE_8 + mclk frequency = 1/8 * hmclk frequency + 0x7 + + + DIVIDE_9 + mclk frequency = 1/9 * hmclk frequency + 0x8 + + + DIVIDE_10 + mclk frequency = 1/10 * hmclk frequency + 0x9 + + + DIVIDE_11 + mclk frequency = 1/11 * hmclk frequency + 0xA + + + DIVIDE_12 + mclk frequency = 1/12 * hmclk frequency + 0xB + + + DIVIDE_13 + mclk frequency = 1/13 * hmclk frequency + 0xC + + + DIVIDE_14 + mclk frequency = 1/14 * hmclk frequency + 0xD + + + DIVIDE_15 + mclk frequency = 1/15 * hmclk frequency + 0xE + + + DIVIDE_16 + mclk frequency = 1/16 * hmclk frequency + 0xF + + + DIVIDE_17 + mclk frequency = 1/17 * hmclk frequency + 0x10 + + + DIVIDE_18 + mclk frequency = 1/18 * hmclk frequency + 0x11 + + + DIVIDE_19 + mclk frequency = 1/19 * hmclk frequency + 0x12 + + + DIVIDE_20 + mclk frequency = 1/20 * hmclk frequency + 0x13 + + + DIVIDE_21 + mclk frequency = 1/21 * hmclk frequency + 0x14 + + + DIVIDE_22 + mclk frequency = 1/22 * hmclk frequency + 0x15 + + + DIVIDE_23 + mclk frequency = 1/23 * hmclk frequency + 0x16 + + + DIVIDE_24 + mclk frequency = 1/24 * hmclk frequency + 0x17 + + + DIVIDE_25 + mclk frequency = 1/25 * hmclk frequency + 0x18 + + + DIVIDE_26 + mclk frequency = 1/26 * hmclk frequency + 0x19 + + + DIVIDE_27 + mclk frequency = 1/27 * hmclk frequency + 0x1A + + + DIVIDE_28 + mclk frequency = 1/28 * hmclk frequency + 0x1B + + + DIVIDE_29 + mclk frequency = 1/29 * hmclk frequency + 0x1C + + + DIVIDE_30 + mclk frequency = 1/30 * hmclk frequency + 0x1D + + + DIVIDE_31 + mclk frequency = 1/31 * hmclk frequency + 0x1E + + + DIVIDE_32 + mclk frequency = 1/32 * hmclk frequency + 0x1F + + + DIVIDE_33 + mclk frequency = 1/33 * hmclk frequency + 0x20 + + + DIVIDE_34 + mclk frequency = 1/34 * hmclk frequency + 0x21 + + + DIVIDE_35 + mclk frequency = 1/35 * hmclk frequency + 0x22 + + + DIVIDE_36 + mclk frequency = 1/36 * hmclk frequency + 0x23 + + + DIVIDE_37 + mclk frequency = 1/37 * hmclk frequency + 0x24 + + + DIVIDE_38 + mclk frequency = 1/38 * hmclk frequency + 0x25 + + + DIVIDE_39 + mclk frequency = 1/39 * hmclk frequency + 0x26 + + + DIVIDE_40 + mclk frequency = 1/40 * hmclk frequency + 0x27 + + + DIVIDE_41 + mclk frequency = 1/41 * hmclk frequency + 0x28 + + + DIVIDE_42 + mclk frequency = 1/42 * hmclk frequency + 0x29 + + + DIVIDE_43 + mclk frequency = 1/43 * hmclk frequency + 0x2A + + + DIVIDE_44 + mclk frequency = 1/44 * hmclk frequency + 0x2B + + + DIVIDE_45 + mclk frequency = 1/45 * hmclk frequency + 0x2C + + + DIVIDE_46 + mclk frequency = 1/46 * hmclk frequency + 0x2D + + + DIVIDE_47 + mclk frequency = 1/47 * hmclk frequency + 0x2E + + + DIVIDE_48 + mclk frequency = 1/48 * hmclk frequency + 0x2F + + + DIVIDE_49 + mclk frequency = 1/49 * hmclk frequency + 0x30 + + + DIVIDE_50 + mclk frequency = 1/50 * hmclk frequency + 0x31 + + + DIVIDE_51 + mclk frequency = 1/51 * hmclk frequency + 0x32 + + + DIVIDE_52 + mclk frequency = 1/52 * hmclk frequency + 0x33 + + + DIVIDE_53 + mclk frequency = 1/53 * hmclk frequency + 0x34 + + + DIVIDE_54 + mclk frequency = 1/54 * hmclk frequency + 0x35 + + + DIVIDE_55 + mclk frequency = 1/55 * hmclk frequency + 0x36 + + + DIVIDE_56 + mclk frequency = 1/56 * hmclk frequency + 0x37 + + + DIVIDE_57 + mclk frequency = 1/57 * hmclk frequency + 0x38 + + + DIVIDE_58 + mclk frequency = 1/58 * hmclk frequency + 0x39 + + + DIVIDE_59 + mclk frequency = 1/59 * hmclk frequency + 0x3A + + + DIVIDE_60 + mclk frequency = 1/60 * hmclk frequency + 0x3B + + + DIVIDE_61 + mclk frequency = 1/61 * hmclk frequency + 0x3C + + + DIVIDE_62 + mclk frequency = 1/62 * hmclk frequency + 0x3D + + + DIVIDE_63 + mclk frequency = 1/63 * hmclk frequency + 0x3E + + + DIVIDE_64 + mclk frequency = 1/64 * hmclk frequency + 0x3F + + + DIVIDE_65 + mclk frequency = 1/65 * hmclk frequency + 0x40 + + + DIVIDE_66 + mclk frequency = 1/66 * hmclk frequency + 0x41 + + + DIVIDE_67 + mclk frequency = 1/67 * hmclk frequency + 0x42 + + + DIVIDE_68 + mclk frequency = 1/68 * hmclk frequency + 0x43 + + + DIVIDE_69 + mclk frequency = 1/69 * hmclk frequency + 0x44 + + + DIVIDE_70 + mclk frequency = 1/70 * hmclk frequency + 0x45 + + + DIVIDE_71 + mclk frequency = 1/71 * hmclk frequency + 0x46 + + + DIVIDE_72 + mclk frequency = 1/72 * hmclk frequency + 0x47 + + + DIVIDE_73 + mclk frequency = 1/73 * hmclk frequency + 0x48 + + + DIVIDE_74 + mclk frequency = 1/74 * hmclk frequency + 0x49 + + + DIVIDE_75 + mclk frequency = 1/75 * hmclk frequency + 0x4A + + + DIVIDE_76 + mclk frequency = 1/76 * hmclk frequency + 0x4B + + + DIVIDE_77 + mclk frequency = 1/77 * hmclk frequency + 0x4C + + + DIVIDE_78 + mclk frequency = 1/78 * hmclk frequency + 0x4D + + + DIVIDE_79 + mclk frequency = 1/79 * hmclk frequency + 0x4E + + + DIVIDE_80 + mclk frequency = 1/80 * hmclk frequency + 0x4F + + + DIVIDE_81 + mclk frequency = 1/81 * hmclk frequency + 0x50 + + + DIVIDE_82 + mclk frequency = 1/82 * hmclk frequency + 0x51 + + + DIVIDE_83 + mclk frequency = 1/83 * hmclk frequency + 0x52 + + + DIVIDE_84 + mclk frequency = 1/84 * hmclk frequency + 0x53 + + + DIVIDE_85 + mclk frequency = 1/85 * hmclk frequency + 0x54 + + + DIVIDE_86 + mclk frequency = 1/86 * hmclk frequency + 0x55 + + + DIVIDE_87 + mclk frequency = 1/87 * hmclk frequency + 0x56 + + + DIVIDE_88 + mclk frequency = 1/88 * hmclk frequency + 0x57 + + + DIVIDE_89 + mclk frequency = 1/89 * hmclk frequency + 0x58 + + + DIVIDE_90 + mclk frequency = 1/90 * hmclk frequency + 0x59 + + + DIVIDE_91 + mclk frequency = 1/91 * hmclk frequency + 0x5A + + + DIVIDE_92 + mclk frequency = 1/92 * hmclk frequency + 0x5B + + + DIVIDE_93 + mclk frequency = 1/93 * hmclk frequency + 0x5C + + + DIVIDE_94 + mclk frequency = 1/94 * hmclk frequency + 0x5D + + + DIVIDE_95 + mclk frequency = 1/95 * hmclk frequency + 0x5E + + + DIVIDE_96 + mclk frequency = 1/96 * hmclk frequency + 0x5F + + + DIVIDE_97 + mclk frequency = 1/97 * hmclk frequency + 0x60 + + + DIVIDE_98 + mclk frequency = 1/98 * hmclk frequency + 0x61 + + + DIVIDE_99 + mclk frequency = 1/99 * hmclk frequency + 0x62 + + + DIVIDE_100 + mclk frequency = 1/100 * hmclk frequency + 0x63 + + + DIVIDE_101 + mclk frequency = 1/101 * hmclk frequency + 0x64 + + + DIVIDE_102 + mclk frequency = 1/102 * hmclk frequency + 0x65 + + + DIVIDE_103 + mclk frequency = 1/103 * hmclk frequency + 0x66 + + + DIVIDE_104 + mclk frequency = 1/104 * hmclk frequency + 0x67 + + + DIVIDE_105 + mclk frequency = 1/105 * hmclk frequency + 0x68 + + + DIVIDE_106 + mclk frequency = 1/106 * hmclk frequency + 0x69 + + + DIVIDE_107 + mclk frequency = 1/107 * hmclk frequency + 0x6A + + + DIVIDE_108 + mclk frequency = 1/108 * hmclk frequency + 0x6B + + + DIVIDE_109 + mclk frequency = 1/109 * hmclk frequency + 0x6C + + + DIVIDE_110 + mclk frequency = 1/110 * hmclk frequency + 0x6D + + + DIVIDE_111 + mclk frequency = 1/111 * hmclk frequency + 0x6E + + + DIVIDE_112 + mclk frequency = 1/112 * hmclk frequency + 0x6F + + + DIVIDE_113 + mclk frequency = 1/113 * hmclk frequency + 0x70 + + + DIVIDE_114 + mclk frequency = 1/114 * hmclk frequency + 0x71 + + + DIVIDE_115 + mclk frequency = 1/115 * hmclk frequency + 0x72 + + + DIVIDE_116 + mclk frequency = 1/116 * hmclk frequency + 0x73 + + + DIVIDE_117 + mclk frequency = 1/117 * hmclk frequency + 0x74 + + + DIVIDE_118 + mclk frequency = 1/118 * hmclk frequency + 0x75 + + + DIVIDE_119 + mclk frequency = 1/119 * hmclk frequency + 0x76 + + + DIVIDE_120 + mclk frequency = 1/120 * hmclk frequency + 0x77 + + + DIVIDE_121 + mclk frequency = 1/121 * hmclk frequency + 0x78 + + + DIVIDE_122 + mclk frequency = 1/122 * hmclk frequency + 0x79 + + + DIVIDE_123 + mclk frequency = 1/123 * hmclk frequency + 0x7A + + + DIVIDE_124 + mclk frequency = 1/124 * hmclk frequency + 0x7B + + + DIVIDE_125 + mclk frequency = 1/125 * hmclk frequency + 0x7C + + + DIVIDE_126 + mclk frequency = 1/126 * hmclk frequency + 0x7D + + + DIVIDE_127 + mclk frequency = 1/127 * hmclk frequency + 0x7E + + + DIVIDE_128 + mclk frequency = 1/128 * hmclk frequency + 0x7F + + + DIVIDE_129 + mclk frequency = 1/129 * hmclk frequency + 0x80 + + + DIVIDE_130 + mclk frequency = 1/130 * hmclk frequency + 0x81 + + + DIVIDE_131 + mclk frequency = 1/131 * hmclk frequency + 0x82 + + + DIVIDE_132 + mclk frequency = 1/132 * hmclk frequency + 0x83 + + + DIVIDE_133 + mclk frequency = 1/133 * hmclk frequency + 0x84 + + + DIVIDE_134 + mclk frequency = 1/134 * hmclk frequency + 0x85 + + + DIVIDE_135 + mclk frequency = 1/135 * hmclk frequency + 0x86 + + + DIVIDE_136 + mclk frequency = 1/136 * hmclk frequency + 0x87 + + + DIVIDE_137 + mclk frequency = 1/137 * hmclk frequency + 0x88 + + + DIVIDE_138 + mclk frequency = 1/138 * hmclk frequency + 0x89 + + + DIVIDE_139 + mclk frequency = 1/139 * hmclk frequency + 0x8A + + + DIVIDE_140 + mclk frequency = 1/140 * hmclk frequency + 0x8B + + + DIVIDE_141 + mclk frequency = 1/141 * hmclk frequency + 0x8C + + + DIVIDE_142 + mclk frequency = 1/142 * hmclk frequency + 0x8D + + + DIVIDE_143 + mclk frequency = 1/143 * hmclk frequency + 0x8E + + + DIVIDE_144 + mclk frequency = 1/144 * hmclk frequency + 0x8F + + + DIVIDE_145 + mclk frequency = 1/145 * hmclk frequency + 0x90 + + + DIVIDE_146 + mclk frequency = 1/146 * hmclk frequency + 0x91 + + + DIVIDE_147 + mclk frequency = 1/147 * hmclk frequency + 0x92 + + + DIVIDE_148 + mclk frequency = 1/148 * hmclk frequency + 0x93 + + + DIVIDE_149 + mclk frequency = 1/149 * hmclk frequency + 0x94 + + + DIVIDE_150 + mclk frequency = 1/150 * hmclk frequency + 0x95 + + + DIVIDE_151 + mclk frequency = 1/151 * hmclk frequency + 0x96 + + + DIVIDE_152 + mclk frequency = 1/152 * hmclk frequency + 0x97 + + + DIVIDE_153 + mclk frequency = 1/153 * hmclk frequency + 0x98 + + + DIVIDE_154 + mclk frequency = 1/154 * hmclk frequency + 0x99 + + + DIVIDE_155 + mclk frequency = 1/155 * hmclk frequency + 0x9A + + + DIVIDE_156 + mclk frequency = 1/156 * hmclk frequency + 0x9B + + + DIVIDE_157 + mclk frequency = 1/157 * hmclk frequency + 0x9C + + + DIVIDE_158 + mclk frequency = 1/158 * hmclk frequency + 0x9D + + + DIVIDE_159 + mclk frequency = 1/159 * hmclk frequency + 0x9E + + + DIVIDE_160 + mclk frequency = 1/160 * hmclk frequency + 0x9F + + + DIVIDE_161 + mclk frequency = 1/161 * hmclk frequency + 0xA0 + + + DIVIDE_162 + mclk frequency = 1/162 * hmclk frequency + 0xA1 + + + DIVIDE_163 + mclk frequency = 1/163 * hmclk frequency + 0xA2 + + + DIVIDE_164 + mclk frequency = 1/164 * hmclk frequency + 0xA3 + + + DIVIDE_165 + mclk frequency = 1/165 * hmclk frequency + 0xA4 + + + DIVIDE_166 + mclk frequency = 1/166 * hmclk frequency + 0xA5 + + + DIVIDE_167 + mclk frequency = 1/167 * hmclk frequency + 0xA6 + + + DIVIDE_168 + mclk frequency = 1/168 * hmclk frequency + 0xA7 + + + DIVIDE_169 + mclk frequency = 1/169 * hmclk frequency + 0xA8 + + + DIVIDE_170 + mclk frequency = 1/170 * hmclk frequency + 0xA9 + + + DIVIDE_171 + mclk frequency = 1/171 * hmclk frequency + 0xAA + + + DIVIDE_172 + mclk frequency = 1/172 * hmclk frequency + 0xAB + + + DIVIDE_173 + mclk frequency = 1/173 * hmclk frequency + 0xAC + + + DIVIDE_174 + mclk frequency = 1/174 * hmclk frequency + 0xAD + + + DIVIDE_175 + mclk frequency = 1/175 * hmclk frequency + 0xAE + + + DIVIDE_176 + mclk frequency = 1/176 * hmclk frequency + 0xAF + + + DIVIDE_177 + mclk frequency = 1/177 * hmclk frequency + 0xB0 + + + DIVIDE_178 + mclk frequency = 1/178 * hmclk frequency + 0xB1 + + + DIVIDE_179 + mclk frequency = 1/179 * hmclk frequency + 0xB2 + + + DIVIDE_180 + mclk frequency = 1/180 * hmclk frequency + 0xB3 + + + DIVIDE_181 + mclk frequency = 1/181 * hmclk frequency + 0xB4 + + + DIVIDE_182 + mclk frequency = 1/182 * hmclk frequency + 0xB5 + + + DIVIDE_183 + mclk frequency = 1/183 * hmclk frequency + 0xB6 + + + DIVIDE_184 + mclk frequency = 1/184 * hmclk frequency + 0xB7 + + + DIVIDE_185 + mclk frequency = 1/185 * hmclk frequency + 0xB8 + + + DIVIDE_186 + mclk frequency = 1/186 * hmclk frequency + 0xB9 + + + DIVIDE_187 + mclk frequency = 1/187 * hmclk frequency + 0xBA + + + DIVIDE_188 + mclk frequency = 1/188 * hmclk frequency + 0xBB + + + DIVIDE_189 + mclk frequency = 1/189 * hmclk frequency + 0xBC + + + DIVIDE_190 + mclk frequency = 1/190 * hmclk frequency + 0xBD + + + DIVIDE_191 + mclk frequency = 1/191 * hmclk frequency + 0xBE + + + DIVIDE_192 + mclk frequency = 1/192 * hmclk frequency + 0xBF + + + DIVIDE_193 + mclk frequency = 1/193 * hmclk frequency + 0xC0 + + + DIVIDE_194 + mclk frequency = 1/194 * hmclk frequency + 0xC1 + + + DIVIDE_195 + mclk frequency = 1/195 * hmclk frequency + 0xC2 + + + DIVIDE_196 + mclk frequency = 1/196 * hmclk frequency + 0xC3 + + + DIVIDE_197 + mclk frequency = 1/197 * hmclk frequency + 0xC4 + + + DIVIDE_198 + mclk frequency = 1/198 * hmclk frequency + 0xC5 + + + DIVIDE_199 + mclk frequency = 1/199 * hmclk frequency + 0xC6 + + + DIVIDE_200 + mclk frequency = 1/200 * hmclk frequency + 0xC7 + + + DIVIDE_201 + mclk frequency = 1/201 * hmclk frequency + 0xC8 + + + DIVIDE_202 + mclk frequency = 1/202 * hmclk frequency + 0xC9 + + + DIVIDE_203 + mclk frequency = 1/203 * hmclk frequency + 0xCA + + + DIVIDE_204 + mclk frequency = 1/204 * hmclk frequency + 0xCB + + + DIVIDE_205 + mclk frequency = 1/205 * hmclk frequency + 0xCC + + + DIVIDE_206 + mclk frequency = 1/206 * hmclk frequency + 0xCD + + + DIVIDE_207 + mclk frequency = 1/207 * hmclk frequency + 0xCE + + + DIVIDE_208 + mclk frequency = 1/208 * hmclk frequency + 0xCF + + + DIVIDE_209 + mclk frequency = 1/209 * hmclk frequency + 0xD0 + + + DIVIDE_210 + mclk frequency = 1/210 * hmclk frequency + 0xD1 + + + DIVIDE_211 + mclk frequency = 1/211 * hmclk frequency + 0xD2 + + + DIVIDE_212 + mclk frequency = 1/212 * hmclk frequency + 0xD3 + + + DIVIDE_213 + mclk frequency = 1/213 * hmclk frequency + 0xD4 + + + DIVIDE_214 + mclk frequency = 1/214 * hmclk frequency + 0xD5 + + + DIVIDE_215 + mclk frequency = 1/215 * hmclk frequency + 0xD6 + + + DIVIDE_216 + mclk frequency = 1/216 * hmclk frequency + 0xD7 + + + DIVIDE_217 + mclk frequency = 1/217 * hmclk frequency + 0xD8 + + + DIVIDE_218 + mclk frequency = 1/218 * hmclk frequency + 0xD9 + + + DIVIDE_219 + mclk frequency = 1/219 * hmclk frequency + 0xDA + + + DIVIDE_220 + mclk frequency = 1/220 * hmclk frequency + 0xDB + + + DIVIDE_221 + mclk frequency = 1/221 * hmclk frequency + 0xDC + + + DIVIDE_222 + mclk frequency = 1/222 * hmclk frequency + 0xDD + + + DIVIDE_223 + mclk frequency = 1/223 * hmclk frequency + 0xDE + + + DIVIDE_224 + mclk frequency = 1/224 * hmclk frequency + 0xDF + + + DIVIDE_225 + mclk frequency = 1/225 * hmclk frequency + 0xE0 + + + DIVIDE_226 + mclk frequency = 1/226 * hmclk frequency + 0xE1 + + + DIVIDE_227 + mclk frequency = 1/227 * hmclk frequency + 0xE2 + + + DIVIDE_228 + mclk frequency = 1/228 * hmclk frequency + 0xE3 + + + DIVIDE_229 + mclk frequency = 1/229 * hmclk frequency + 0xE4 + + + DIVIDE_230 + mclk frequency = 1/230 * hmclk frequency + 0xE5 + + + DIVIDE_231 + mclk frequency = 1/231 * hmclk frequency + 0xE6 + + + DIVIDE_232 + mclk frequency = 1/232 * hmclk frequency + 0xE7 + + + DIVIDE_233 + mclk frequency = 1/233 * hmclk frequency + 0xE8 + + + DIVIDE_234 + mclk frequency = 1/234 * hmclk frequency + 0xE9 + + + DIVIDE_235 + mclk frequency = 1/235 * hmclk frequency + 0xEA + + + DIVIDE_236 + mclk frequency = 1/236 * hmclk frequency + 0xEB + + + DIVIDE_237 + mclk frequency = 1/237 * hmclk frequency + 0xEC + + + DIVIDE_238 + mclk frequency = 1/238 * hmclk frequency + 0xED + + + DIVIDE_239 + mclk frequency = 1/239 * hmclk frequency + 0xEE + + + DIVIDE_240 + mclk frequency = 1/240 * hmclk frequency + 0xEF + + + DIVIDE_241 + mclk frequency = 1/241 * hmclk frequency + 0xF0 + + + DIVIDE_242 + mclk frequency = 1/242 * hmclk frequency + 0xF1 + + + DIVIDE_243 + mclk frequency = 1/243 * hmclk frequency + 0xF2 + + + DIVIDE_244 + mclk frequency = 1/244 * hmclk frequency + 0xF3 + + + DIVIDE_245 + mclk frequency = 1/245 * hmclk frequency + 0xF4 + + + DIVIDE_246 + mclk frequency = 1/246 * hmclk frequency + 0xF5 + + + DIVIDE_247 + mclk frequency = 1/247 * hmclk frequency + 0xF6 + + + DIVIDE_248 + mclk frequency = 1/248 * hmclk frequency + 0xF7 + + + DIVIDE_249 + mclk frequency = 1/249 * hmclk frequency + 0xF8 + + + DIVIDE_250 + mclk frequency = 1/250 * hmclk frequency + 0xF9 + + + DIVIDE_251 + mclk frequency = 1/251 * hmclk frequency + 0xFA + + + DIVIDE_252 + mclk frequency = 1/252 * hmclk frequency + 0xFB + + + DIVIDE_253 + mclk frequency = 1/253 * hmclk frequency + 0xFC + + + DIVIDE_254 + mclk frequency = 1/254 * hmclk frequency + 0xFD + + + DIVIDE_255 + mclk frequency = 1/255 * hmclk frequency + 0xFE + + + DIVIDE_256 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset + 24 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 25 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Medium Quality Sound (MQS) Oversample + 26 + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + QTIMER1_TMR_CNTS_FREEZE + QTIMER1 timer counter freeze + 28 + 1 + read-write + + + QTIMER1_TMR_CNTS_FREEZE_0 + Timer counter works normally + 0 + + + QTIMER1_TMR_CNTS_FREEZE_1 + Reset counter and ouput flags + 0x1 + + + + + QTIMER2_TMR_CNTS_FREEZE + QTIMER2 timer counter freeze + 29 + 1 + read-write + + + QTIMER2_TMR_CNTS_FREEZE_0 + Timer counter works normally + 0 + + + QTIMER2_TMR_CNTS_FREEZE_1 + Reset counter and ouput flags + 0x1 + + + + + QTIMER3_TMR_CNTS_FREEZE + QTIMER3 timer counter freeze + 30 + 1 + read-write + + + QTIMER3_TMR_CNTS_FREEZE_0 + Timer counter works normally + 0 + + + QTIMER3_TMR_CNTS_FREEZE_1 + Reset counter and ouput flags + 0x1 + + + + + QTIMER4_TMR_CNTS_FREEZE + QTIMER4 timer counter freeze + 31 + 1 + read-write + + + QTIMER4_TMR_CNTS_FREEZE_0 + Timer counter works normally + 0 + + + QTIMER4_TMR_CNTS_FREEZE_1 + Reset counter and ouput flags + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFFF0 + 0xFFFFFFFF + + + DCP_KEY_SEL + Select 128-bit DCP key from 256-bit key from SNVS Master Key + 4 + 1 + read-write + + + DCP_KEY_SEL_0 + Select [127:0] from SNVS Master Key as DCP key + 0 + + + DCP_KEY_SEL_1 + Select [255:128] from SNVS Master Key as DCP key + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDMA_STOP_REQ + EDMA stop request + 0 + 1 + read-write + + + EDMA_STOP_REQ_0 + stop request off + 0 + + + EDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN1_STOP_REQ + CAN1 stop request + 1 + 1 + read-write + + + CAN1_STOP_REQ_0 + stop request off + 0 + + + CAN1_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN2_STOP_REQ + CAN2 stop request + 2 + 1 + read-write + + + CAN2_STOP_REQ_0 + stop request off + 0 + + + CAN2_STOP_REQ_1 + stop request on + 0x1 + + + + + TRNG_STOP_REQ + TRNG stop request + 3 + 1 + read-write + + + TRNG_STOP_REQ_0 + stop request off + 0 + + + TRNG_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET_STOP_REQ + ENET stop request + 4 + 1 + read-write + + + ENET_STOP_REQ_0 + stop request off + 0 + + + ENET_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request + 5 + 1 + read-write + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request + 6 + 1 + read-write + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request + 7 + 1 + read-write + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + SEMC_STOP_REQ + SEMC stop request + 9 + 1 + read-write + + + SEMC_STOP_REQ_0 + stop request off + 0 + + + SEMC_STOP_REQ_1 + stop request on + 0x1 + + + + + PIT_STOP_REQ + PIT stop request + 10 + 1 + read-write + + + PIT_STOP_REQ_0 + stop request off + 0 + + + PIT_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXSPI_STOP_REQ + FlexSPI stop request + 11 + 1 + read-write + + + FLEXSPI_STOP_REQ_0 + stop request off + 0 + + + FLEXSPI_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO1_STOP_REQ + FlexIO1 stop request + 12 + 1 + read-write + + + FLEXIO1_STOP_REQ_0 + stop request off + 0 + + + FLEXIO1_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO2_STOP_REQ + FlexIO2 stop request + 13 + 1 + read-write + + + FLEXIO2_STOP_REQ_0 + stop request off + 0 + + + FLEXIO2_STOP_REQ_1 + stop request on + 0x1 + + + + + EDMA_STOP_ACK + EDMA stop acknowledge + 16 + 1 + read-only + + + EDMA_STOP_ACK_0 + EDMA stop acknowledge is not asserted + 0 + + + EDMA_STOP_ACK_1 + EDMA stop acknowledge is asserted (EDMA is in STOP mode) + 0x1 + + + + + CAN1_STOP_ACK + CAN1 stop acknowledge + 17 + 1 + read-only + + + CAN1_STOP_ACK_0 + CAN1 stop acknowledge is not asserted + 0 + + + CAN1_STOP_ACK_1 + CAN1 stop acknowledge is asserted + 0x1 + + + + + CAN2_STOP_ACK + CAN2 stop acknowledge + 18 + 1 + read-only + + + CAN2_STOP_ACK_0 + CAN2 stop acknowledge is not asserted + 0 + + + CAN2_STOP_ACK_1 + CAN2 stop acknowledge is asserted + 0x1 + + + + + TRNG_STOP_ACK + TRNG stop acknowledge + 19 + 1 + read-only + + + TRNG_STOP_ACK_0 + TRNG stop acknowledge is not asserted + 0 + + + TRNG_STOP_ACK_1 + TRNG stop acknowledge is asserted + 0x1 + + + + + ENET_STOP_ACK + ENET stop acknowledge + 20 + 1 + read-only + + + ENET_STOP_ACK_0 + ENET stop acknowledge is not asserted + 0 + + + ENET_STOP_ACK_1 + ENET stop acknowledge is asserted + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge + 21 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge + 22 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge + 23 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted + 0x1 + + + + + SEMC_STOP_ACK + SEMC stop acknowledge + 25 + 1 + read-only + + + SEMC_STOP_ACK_0 + SEMC stop acknowledge is not asserted + 0 + + + SEMC_STOP_ACK_1 + SEMC stop acknowledge is asserted + 0x1 + + + + + PIT_STOP_ACK + PIT stop acknowledge + 26 + 1 + read-only + + + PIT_STOP_ACK_0 + PIT stop acknowledge is not asserted + 0 + + + PIT_STOP_ACK_1 + PIT stop acknowledge is asserted + 0x1 + + + + + FLEXSPI_STOP_ACK + FLEXSPI stop acknowledge + 27 + 1 + read-only + + + FLEXSPI_STOP_ACK_0 + FLEXSPI stop acknowledge is not asserted + 0 + + + FLEXSPI_STOP_ACK_1 + FLEXSPI stop acknowledge is asserted + 0x1 + + + + + FLEXIO1_STOP_ACK + FLEXIO1 stop acknowledge + 28 + 1 + read-only + + + FLEXIO1_STOP_ACK_0 + FLEXIO1 stop acknowledge is not asserted + 0 + + + FLEXIO1_STOP_ACK_1 + FLEXIO1 stop acknowledge is asserted + 0x1 + + + + + FLEXIO2_STOP_ACK + FLEXIO2 stop acknowledge + 29 + 1 + read-only + + + FLEXIO2_STOP_ACK_0 + FLEXIO2 stop acknowledge is not asserted + 0 + + + FLEXIO2_STOP_ACK_1 + FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 23 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from pad + 0 + + + GPT2_CAPIN1_SEL_1 + source from enet1.ipp_do_mac0_timer[3] + 0x1 + + + + + ENET_EVENT3IN_SEL + ENET input timer event3 source select + 25 + 1 + read-write + + + ENET_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout1 + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 28 + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock. See CCM chapter for more information + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock. It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for more details + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 29 + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock. See CCM chapter for more information + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock. It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for more details + 0x1 + + + + + + + GPR6 + GPR6 General Purpose Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + QTIMER1_TRM0_INPUT_SEL + QTIMER1 TMR0 input select + 0 + 1 + read-write + + + QTIMER1_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM1_INPUT_SEL + QTIMER1 TMR1 input select + 1 + 1 + read-write + + + QTIMER1_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM2_INPUT_SEL + QTIMER1 TMR2 input select + 2 + 1 + read-write + + + QTIMER1_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM3_INPUT_SEL + QTIMER1 TMR3 input select + 3 + 1 + read-write + + + QTIMER1_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM0_INPUT_SEL + QTIMER2 TMR0 input select + 4 + 1 + read-write + + + QTIMER2_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM1_INPUT_SEL + QTIMER2 TMR1 input select + 5 + 1 + read-write + + + QTIMER2_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM2_INPUT_SEL + QTIMER2 TMR2 input select + 6 + 1 + read-write + + + QTIMER2_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM3_INPUT_SEL + QTIMER2 TMR3 input select + 7 + 1 + read-write + + + QTIMER2_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM0_INPUT_SEL + QTIMER3 TMR0 input select + 8 + 1 + read-write + + + QTIMER3_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM1_INPUT_SEL + QTIMER3 TMR1 input select + 9 + 1 + read-write + + + QTIMER3_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM2_INPUT_SEL + QTIMER3 TMR2 input select + 10 + 1 + read-write + + + QTIMER3_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM3_INPUT_SEL + QTIMER3 TMR3 input select + 11 + 1 + read-write + + + QTIMER3_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM0_INPUT_SEL + QTIMER4 TMR0 input select + 12 + 1 + read-write + + + QTIMER4_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM1_INPUT_SEL + QTIMER4 TMR1 input select + 13 + 1 + read-write + + + QTIMER4_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM2_INPUT_SEL + QTIMER4 TMR2 input select + 14 + 1 + read-write + + + QTIMER4_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM3_INPUT_SEL + QTIMER4 TMR3 input select + 15 + 1 + read-write + + + QTIMER4_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_4 + IOMUXC XBAR1_INOUT4 function direction select + 16 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_4_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_4_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_5 + IOMUXC XBAR1_INOUT5 function direction select + 17 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_5_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_5_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_6 + IOMUXC XBAR1_INOUT6 function direction select + 18 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_6_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_6_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_7 + IOMUXC XBAR1_INOUT7 function direction select + 19 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_7_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_7_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_8 + IOMUXC XBAR1_INOUT8 function direction select + 20 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_8_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_8_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_9 + IOMUXC XBAR1_INOUT9 function direction select + 21 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_9_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_9_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_10 + IOMUXC XBAR1_INOUT10 function direction select + 22 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_10_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_10_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_11 + IOMUXC XBAR1_INOUT11 function direction select + 23 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_11_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_11_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_12 + IOMUXC XBAR1_INOUT12 function direction select + 24 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_12_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_12_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_13 + IOMUXC XBAR1_INOUT13 function direction select + 25 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_13_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_13_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_14 + IOMUXC XBAR1_INOUT14 function direction select + 26 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_14_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_14_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_15 + IOMUXC XBAR1_INOUT15 function direction select + 27 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_15_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_15_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_16 + IOMUXC XBAR1_INOUT16 function direction select + 28 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_16_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_16_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_17 + IOMUXC XBAR1_INOUT17 function direction select + 29 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_17_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_17_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_18 + IOMUXC XBAR1_INOUT18 function direction select + 30 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_18_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_18_1 + XBAR1_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_19 + IOMUXC XBAR1_INOUT19 function direction select + 31 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_19_0 + XBAR1_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_19_1 + XBAR1_INOUT as output + 0x1 + + + + + + + GPR7 + GPR7 General Purpose Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_STOP_REQ + LPI2C1 stop request + 0 + 1 + read-write + + + LPI2C1_STOP_REQ_0 + stop request off + 0 + + + LPI2C1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C2_STOP_REQ + LPI2C2 stop request + 1 + 1 + read-write + + + LPI2C2_STOP_REQ_0 + stop request off + 0 + + + LPI2C2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C3_STOP_REQ + LPI2C3 stop request + 2 + 1 + read-write + + + LPI2C3_STOP_REQ_0 + stop request off + 0 + + + LPI2C3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C4_STOP_REQ + LPI2C4 stop request + 3 + 1 + read-write + + + LPI2C4_STOP_REQ_0 + stop request off + 0 + + + LPI2C4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI1_STOP_REQ + LPSPI1 stop request + 4 + 1 + read-write + + + LPSPI1_STOP_REQ_0 + stop request off + 0 + + + LPSPI1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI2_STOP_REQ + LPSPI2 stop request + 5 + 1 + read-write + + + LPSPI2_STOP_REQ_0 + stop request off + 0 + + + LPSPI2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI3_STOP_REQ + LPSPI3 stop request + 6 + 1 + read-write + + + LPSPI3_STOP_REQ_0 + stop request off + 0 + + + LPSPI3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI4_STOP_REQ + LPSPI4 stop request + 7 + 1 + read-write + + + LPSPI4_STOP_REQ_0 + stop request off + 0 + + + LPSPI4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART1_STOP_REQ + LPUART1 stop request + 8 + 1 + read-write + + + LPUART1_STOP_REQ_0 + stop request off + 0 + + + LPUART1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART2_STOP_REQ + LPUART2 stop request + 9 + 1 + read-write + + + LPUART2_STOP_REQ_0 + stop request off + 0 + + + LPUART2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART3_STOP_REQ + LPUART3 stop request + 10 + 1 + read-write + + + LPUART3_STOP_REQ_0 + stop request off + 0 + + + LPUART3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART4_STOP_REQ + LPUART4 stop request + 11 + 1 + read-write + + + LPUART4_STOP_REQ_0 + stop request off + 0 + + + LPUART4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART5_STOP_REQ + LPUART5 stop request + 12 + 1 + read-write + + + LPUART5_STOP_REQ_0 + stop request off + 0 + + + LPUART5_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART6_STOP_REQ + LPUART6 stop request + 13 + 1 + read-write + + + LPUART6_STOP_REQ_0 + stop request off + 0 + + + LPUART6_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART7_STOP_REQ + LPUART7 stop request + 14 + 1 + read-write + + + LPUART7_STOP_REQ_0 + stop request off + 0 + + + LPUART7_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART8_STOP_REQ + LPUART8 stop request + 15 + 1 + read-write + + + LPUART8_STOP_REQ_0 + stop request off + 0 + + + LPUART8_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C1_STOP_ACK + LPI2C1 stop acknowledge + 16 + 1 + read-only + + + LPI2C1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C1_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + LPI2C2_STOP_ACK + LPI2C2 stop acknowledge + 17 + 1 + read-only + + + LPI2C2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C3_STOP_ACK + LPI2C3 stop acknowledge + 18 + 1 + read-only + + + LPI2C3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C4_STOP_ACK + LPI2C4 stop acknowledge + 19 + 1 + read-only + + + LPI2C4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI1_STOP_ACK + LPSPI1 stop acknowledge + 20 + 1 + read-only + + + LPSPI1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI2_STOP_ACK + LPSPI2 stop acknowledge + 21 + 1 + read-only + + + LPSPI2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI3_STOP_ACK + LPSPI3 stop acknowledge + 22 + 1 + read-only + + + LPSPI3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI4_STOP_ACK + LPSPI4 stop acknowledge + 23 + 1 + read-only + + + LPSPI4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART1_STOP_ACK + LPUART1 stop acknowledge + 24 + 1 + read-only + + + LPUART1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART2_STOP_ACK + LPUART2 stop acknowledge + 25 + 1 + read-only + + + LPUART2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART3_STOP_ACK + LPUART3 stop acknowledge + 26 + 1 + read-only + + + LPUART3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART4_STOP_ACK + LPUART4 stop acknowledge + 27 + 1 + read-only + + + LPUART4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART5_STOP_ACK + LPUART5 stop acknowledge + 28 + 1 + read-only + + + LPUART5_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART5_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART6_STOP_ACK + LPUART6 stop acknowledge + 29 + 1 + read-only + + + LPUART6_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART6_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART7_STOP_ACK + LPUART7 stop acknowledge + 30 + 1 + read-only + + + LPUART7_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART7_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART8_STOP_ACK + LPUART8 stop acknowledge + 31 + 1 + read-only + + + LPUART8_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART8_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + + + GPR8 + GPR8 General Purpose Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_IPG_STOP_MODE + LPI2C1 stop mode selection, cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + LPI2C1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C1_IPG_DOZE + LPI2C1 ipg_doze mode + 1 + 1 + read-write + + + LPI2C1_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C2_IPG_STOP_MODE + LPI2C2 stop mode selection, cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + LPI2C2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C2_IPG_DOZE + LPI2C2 ipg_doze mode + 3 + 1 + read-write + + + LPI2C2_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C3_IPG_STOP_MODE + LPI2C3 stop mode selection, cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + LPI2C3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C3_IPG_DOZE + LPI2C3 ipg_doze mode + 5 + 1 + read-write + + + LPI2C3_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C4_IPG_STOP_MODE + LPI2C4 stop mode selection, cannot change when ipg_stop is asserted. + 6 + 1 + read-write + + + LPI2C4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C4_IPG_DOZE + LPI2C4 ipg_doze mode + 7 + 1 + read-write + + + LPI2C4_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI1_IPG_STOP_MODE + LPSPI1 stop mode selection, cannot change when ipg_stop is asserted. + 8 + 1 + read-write + + + LPSPI1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI1_IPG_DOZE + LPSPI1 ipg_doze mode + 9 + 1 + read-write + + + LPSPI1_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI2_IPG_STOP_MODE + LPSPI2 stop mode selection, cannot change when ipg_stop is asserted. + 10 + 1 + read-write + + + LPSPI2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI2_IPG_DOZE + LPSPI2 ipg_doze mode + 11 + 1 + read-write + + + LPSPI2_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI3_IPG_STOP_MODE + LPSPI3 stop mode selection, cannot change when ipg_stop is asserted. + 12 + 1 + read-write + + + LPSPI3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI3_IPG_DOZE + LPSPI3 ipg_doze mode + 13 + 1 + read-write + + + LPSPI3_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI4_IPG_STOP_MODE + LPSPI4 stop mode selection, cannot change when ipg_stop is asserted. + 14 + 1 + read-write + + + LPSPI4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI4_IPG_DOZE + LPSPI4 ipg_doze mode + 15 + 1 + read-write + + + LPSPI4_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART1_IPG_STOP_MODE + LPUART1 stop mode selection, cannot change when ipg_stop is asserted. + 16 + 1 + read-write + + + LPUART1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART1_IPG_DOZE + LPUART1 ipg_doze mode + 17 + 1 + read-write + + + LPUART1_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART2_IPG_STOP_MODE + LPUART2 stop mode selection, cannot change when ipg_stop is asserted. + 18 + 1 + read-write + + + LPUART2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART2_IPG_DOZE + LPUART2 ipg_doze mode + 19 + 1 + read-write + + + LPUART2_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART3_IPG_STOP_MODE + LPUART3 stop mode selection, cannot change when ipg_stop is asserted. + 20 + 1 + read-write + + + LPUART3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART3_IPG_DOZE + LPUART3 ipg_doze mode + 21 + 1 + read-write + + + LPUART3_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART4_IPG_STOP_MODE + LPUART4 stop mode selection, cannot change when ipg_stop is asserted. + 22 + 1 + read-write + + + LPUART4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART4_IPG_DOZE + LPUART4 ipg_doze mode + 23 + 1 + read-write + + + LPUART4_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART5_IPG_STOP_MODE + LPUART5 stop mode selection, cannot change when ipg_stop is asserted. + 24 + 1 + read-write + + + LPUART5_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART5_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART5_IPG_DOZE + LPUART5 ipg_doze mode + 25 + 1 + read-write + + + LPUART5_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART5_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART6_IPG_STOP_MODE + LPUART6 stop mode selection, cannot change when ipg_stop is asserted. + 26 + 1 + read-write + + + LPUART6_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART6_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART6_IPG_DOZE + LPUART6 ipg_doze mode + 27 + 1 + read-write + + + LPUART6_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART6_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART7_IPG_STOP_MODE + LPUART7 stop mode selection, cannot change when ipg_stop is asserted. + 28 + 1 + read-write + + + LPUART7_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART7_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART7_IPG_DOZE + LPUART7 ipg_doze mode + 29 + 1 + read-write + + + LPUART7_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART7_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART8_IPG_STOP_MODE + LPUART8 stop mode selection, cannot change when ipg_stop is asserted. + 30 + 1 + read-write + + + LPUART8_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART8_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART8_IPG_DOZE + LPUART8 ipg_doze mode + 31 + 1 + read-write + + + LPUART8_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART8_IPG_DOZE_1 + in doze mode + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + NIDEN + Arm non-secure (non-invasive) debug enable + 0 + 1 + read-write + + + NIDEN_0 + Debug turned off + 0 + + + NIDEN_1 + Debug enabled (default) + 0x1 + + + + + DBG_EN + Arm invasive debug enable + 1 + 1 + read-write + + + DBG_EN_0 + Debug turned off + 0 + + + DBG_EN_1 + Debug enabled (default) + 0x1 + + + + + SEC_ERR_RESP + Security error response enable + 2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + DCPKEY_OCOTP_OR_KEYMUX + DCP Key selection bit. + 4 + 1 + read-write + + + DCPKEY_OCOTP_OR_KEYMUX_0 + Select key from SNVS Master Key + 0 + + + DCPKEY_OCOTP_OR_KEYMUX_1 + Select key from OCOTP (SW_GP2) + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 8 + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor) + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 9 + 7 + read-write + + + LOCK_NIDEN + Lock NIDEN field for changes + 16 + 1 + read-write + + + LOCK_NIDEN_0 + Field is not locked + 0 + + + LOCK_NIDEN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DBG_EN + Lock DBG_EN field for changes + 17 + 1 + read-write + + + LOCK_DBG_EN_0 + Field is not locked + 0 + + + LOCK_DBG_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_SEC_ERR_RESP + Lock SEC_ERR_RESP field for changes + 18 + 1 + read-write + + + LOCK_SEC_ERR_RESP_0 + Field is not locked + 0 + + + LOCK_SEC_ERR_RESP_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX + Lock DCP Key OCOTP/Key MUX selection bit + 20 + 1 + read-write + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_0 + Field is not locked + 0 + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_EN + Lock OCRAM_TZ_EN field for changes + 24 + 1 + read-write + + + LOCK_OCRAM_TZ_EN_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_ADDR + Lock OCRAM_TZ_ADDR field for changes + 25 + 7 + read-write + + + LOCK_OCRAM_TZ_ADDR_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_ADDR_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR11 + GPR11 General Purpose Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + M7_APC_AC_R0_CTRL + Access control of memory region-0 + 0 + 2 + read-write + + + M7_APC_AC_R0_CTRL_0 + No access protection - All accesses are allowed + 0 + + + M7_APC_AC_R0_CTRL_1 + M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R0_TOP/BOT specified region (IOMUXC_GPR_GPR18 - IOMUXC_GPR_GPR19) + 0x1 + + + + + M7_APC_AC_R1_CTRL + Access control of memory region-1 + 2 + 2 + read-write + + + M7_APC_AC_R1_CTRL_0 + No access protection - All accesses are allowed + 0 + + + M7_APC_AC_R1_CTRL_1 + M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R1_TOP/BOT specified region (IOMUXC_GPR_GPR20 - IOMUXC_GPR_GPR21) + 0x1 + + + + + M7_APC_AC_R2_CTRL + Access control of memory region-2 + 4 + 2 + read-write + + + M7_APC_AC_R2_CTRL_0 + No access protection - All accesses are allowed + 0 + + + M7_APC_AC_R2_CTRL_1 + M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R2_TOP/BOT specified region (IOMUXC_GPR_GPR22 - IOMUXC_GPR_GPR23) + 0x1 + + + + + M7_APC_AC_R3_CTRL + Access control of memory region-3 + 6 + 2 + read-write + + + M7_APC_AC_R3_CTRL_0 + No access protection - All accesses are allowed + 0 + + + M7_APC_AC_R3_CTRL_1 + M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R3_TOP/BOT specified region (IOMUXC_GPR_GPR24 - IOMUXC_GPR_GPR25) + 0x1 + + + + + BEE_DE_RX_EN + BEE data decryption of memory region-n (n = 3 to 0). + 8 + 4 + read-write + + + BEE_DE_RX_EN_0 + FlexSPI data decryption disabled + 0 + + + BEE_DE_RX_EN_1 + FlexSPI data decryption enabled + 0x1 + + + + + LOCK_M7_APC_AC_R0_CTRL + Lock M7_APC_AC_R0_CTRL field for changes + 16 + 2 + read-write + + + LOCK_M7_APC_AC_R0_CTRL_0 + Field is not locked + 0 + + + LOCK_M7_APC_AC_R0_CTRL_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_M7_APC_AC_R1_CTRL + Lock M7_APC_AC_R1_CTRL field for changes + 18 + 2 + read-write + + + LOCK_M7_APC_AC_R1_CTRL_0 + Field is not locked + 0 + + + LOCK_M7_APC_AC_R1_CTRL_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_M7_APC_AC_R2_CTRL + Lock M7_APC_AC_R2_CTRL field for changes + 20 + 2 + read-write + + + LOCK_M7_APC_AC_R2_CTRL_0 + Field is not locked + 0 + + + LOCK_M7_APC_AC_R2_CTRL_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_M7_APC_AC_R3_CTRL + Lock M7_APC_AC_R3_CTRL field for changes + 22 + 2 + read-write + + + LOCK_M7_APC_AC_R3_CTRL_0 + Field is not locked + 0 + + + LOCK_M7_APC_AC_R3_CTRL_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_BEE_DE_RX_EN + Lock BEE_DE_RX_EN[n] (n = 3 to 0) field for changes + 24 + 4 + read-write + + + LOCK_BEE_DE_RX_EN_0 + Field is not locked + 0 + + + LOCK_BEE_DE_RX_EN_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR12 + GPR12 General Purpose Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXIO1_IPG_STOP_MODE + FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + FLEXIO1_IPG_STOP_MODE_0 + FlexIO1 is functional in Stop mode + 0 + + + FLEXIO1_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode + 0x1 + + + + + FLEXIO1_IPG_DOZE + FLEXIO1 ipg_doze mode + 1 + 1 + read-write + + + FLEXIO1_IPG_DOZE_0 + FLEXIO1 is not in doze mode + 0 + + + FLEXIO1_IPG_DOZE_1 + FLEXIO1 is in doze mode + 0x1 + + + + + FLEXIO2_IPG_STOP_MODE + FlexIO2 stop mode selection. Cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + FLEXIO2_IPG_STOP_MODE_0 + FlexIO2 is functional in Stop mode + 0 + + + FLEXIO2_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode + 0x1 + + + + + FLEXIO2_IPG_DOZE + FLEXIO2 ipg_doze mode + 3 + 1 + read-write + + + FLEXIO2_IPG_DOZE_0 + FLEXIO2 is not in doze mode + 0 + + + FLEXIO2_IPG_DOZE_1 + FLEXIO2 is in doze mode + 0x1 + + + + + ACMP_IPG_STOP_MODE + ACMP stop mode selection. Cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + ACMP_IPG_STOP_MODE_0 + ACMP is functional in Stop mode + 0 + + + ACMP_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode + 0x1 + + + + + + + GPR13 + GPR13 General Purpose Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARCACHE_USDHC + uSDHC block cacheable attribute value of AXI read transactions + 0 + 1 + read-write + + + ARCACHE_USDHC_0 + Cacheable attribute is off for read transactions + 0 + + + ARCACHE_USDHC_1 + Cacheable attribute is on for read transactions + 0x1 + + + + + AWCACHE_USDHC + uSDHC block cacheable attribute value of AXI write transactions + 1 + 1 + read-write + + + AWCACHE_USDHC_0 + Cacheable attribute is off for write transactions + 0 + + + AWCACHE_USDHC_1 + Cacheable attribute is on for write transactions + 0x1 + + + + + CACHE_ENET + ENET block cacheable attribute value of AXI transactions + 7 + 1 + read-write + + + CACHE_ENET_0 + Cacheable attribute is off for read/write transactions + 0 + + + CACHE_ENET_1 + Cacheable attribute is on for read/write transactions + 0x1 + + + + + CACHE_USB + USB block cacheable attribute value of AXI transactions + 13 + 1 + read-write + + + CACHE_USB_0 + Cacheable attribute is off for read/write transactions + 0 + + + CACHE_USB_1 + Cacheable attribute is on for read/write transactions + 0x1 + + + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0xAA0000 + 0xFFFFFFFF + + + ACMP1_CMP_IGEN_TRIM_DN + reduces ACMP1 internal bias current by 30% + 0 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP1_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_DN + reduces ACMP2 internal bias current by 30% + 1 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP2_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_DN + reduces ACMP3 internal bias current by 30% + 2 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP3_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_DN + reduces ACMP4 internal bias current by 30% + 3 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP4_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP1_CMP_IGEN_TRIM_UP + increases ACMP1 internal bias current by 30% + 4 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP1_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_UP + increases ACMP2 internal bias current by 30% + 5 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP2_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_UP + increases ACMP3 internal bias current by 30% + 6 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP3_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_UP + increases ACMP4 internal bias current by 30% + 7 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP4_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP1_SAMPLE_SYNC_EN + ACMP1 sample_lv source select + 8 + 1 + read-write + + + ACMP1_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP1_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP2_SAMPLE_SYNC_EN + ACMP2 sample_lv source select + 9 + 1 + read-write + + + ACMP2_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP2_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP3_SAMPLE_SYNC_EN + ACMP3 sample_lv source select + 10 + 1 + read-write + + + ACMP3_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP3_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP4_SAMPLE_SYNC_EN + ACMP4 sample_lv source select + 11 + 1 + read-write + + + ACMP4_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP4_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + + + GPR15 + GPR15 General Purpose Register + 0x3C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + GPR16 + GPR16 General Purpose Register + 0x40 + 32 + read-write + 0x200003 + 0xFFFFFFFF + + + FLEXRAM_BANK_CFG_SEL + FlexRAM bank config source select + 2 + 1 + read-write + + + FLEXRAM_BANK_CFG_SEL_0 + use fuse value to config + 0 + + + FLEXRAM_BANK_CFG_SEL_1 + use FLEXRAM_BANK_CFG to config + 0x1 + + + + + CM7_INIT_VTOR + Vector table offset register out of reset + 7 + 25 + read-write + + + + + GPR17 + GPR17 General Purpose Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXRAM_BANK_CFG + FlexRAM bank config value + 0 + 32 + read-write + + + + + GPR18 + GPR18 General Purpose Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_BOT + lock M7_APC_AC_R0_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_BOT_0 + M7_APC_AC_R0_BOT is not locked + 0 + + + LOCK_M7_APC_AC_R0_BOT_1 + M7_APC_AC_R0_BOT is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_BOT + Access Permission Controller (APC) end address of memory region-0 + 3 + 29 + read-write + + + + + GPR19 + GPR19 General Purpose Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_TOP + lock M7_APC_AC_R0_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_TOP_0 + M7_APC_AC_R0_TOP is not locked + 0 + + + LOCK_M7_APC_AC_R0_TOP_1 + M7_APC_AC_R0_TOP is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_TOP + Access Permission Controller (APC) start address of memory region-0 + 3 + 29 + read-write + + + + + GPR20 + GPR20 General Purpose Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_BOT + lock M7_APC_AC_R1_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_BOT_0 + M7_APC_AC_R1_BOT is not locked + 0 + + + LOCK_M7_APC_AC_R1_BOT_1 + M7_APC_AC_R1_BOT is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_BOT + Access Permission Controller (APC) end address of memory region-1 + 3 + 29 + read-write + + + + + GPR21 + GPR21 General Purpose Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_TOP + lock M7_APC_AC_R1_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_TOP_0 + M7_APC_AC_R1_TOP is not locked + 0 + + + LOCK_M7_APC_AC_R1_TOP_1 + M7_APC_AC_R1_TOP is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_TOP + Access Permission Controller (APC) start address of memory region-1 + 3 + 29 + read-write + + + + + GPR22 + GPR22 General Purpose Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_BOT + lock M7_APC_AC_R2_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_BOT_0 + M7_APC_AC_R2_BOT is not locked + 0 + + + LOCK_M7_APC_AC_R2_BOT_1 + M7_APC_AC_R2_BOT is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_BOT + Access Permission Controller (APC) end address of memory region-2 + 3 + 29 + read-write + + + + + GPR23 + GPR23 General Purpose Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_TOP + lock M7_APC_AC_R2_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_TOP_0 + M7_APC_AC_R2_TOP is not locked + 0 + + + LOCK_M7_APC_AC_R2_TOP_1 + M7_APC_AC_R2_TOP is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_TOP + Access Permission Controller (APC) start address of memory region-2 + 3 + 29 + read-write + + + + + GPR24 + GPR24 General Purpose Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_BOT + lock M7_APC_AC_R3_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_BOT_0 + M7_APC_AC_R3_BOT is not locked + 0 + + + LOCK_M7_APC_AC_R3_BOT_1 + M7_APC_AC_R3_BOT is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_BOT + Access Permission Controller (APC) end address of memory region-3 + 3 + 29 + read-write + + + + + GPR25 + GPR25 General Purpose Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_TOP + lock M7_APC_AC_R3_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_TOP_0 + M7_APC_AC_R3_TOP is not locked + 0 + + + LOCK_M7_APC_AC_R3_TOP_1 + M7_APC_AC_R3_TOP is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_TOP + Access Permission Controller (APC) start address of memory region-3 + 3 + 29 + read-write + + + + + + + FLEXRAM + FLEXRAM + FLEXRAM + 0x400B0000 + + 0 + 0x1C + registers + + + FLEXRAM + 38 + + + + TCM_CTRL + TCM CRTL Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCM_WWAIT_EN + TCM Write Wait Mode Enable + 0 + 1 + read-write + + + TCM_WWAIT_EN_0 + TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_WWAIT_EN_1 + TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + TCM_RWAIT_EN + TCM Read Wait Mode Enable + 1 + 1 + read-write + + + TCM_RWAIT_EN_0 + TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_RWAIT_EN_1 + TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + FORCE_CLK_ON + Force RAM Clock Always On + 2 + 1 + read-write + + + + + INT_STATUS + Interrupt Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STATUS + ITCM Access Error Status + 3 + 1 + read-write + oneToClear + + + ITCM_ERR_STATUS_0 + ITCM access error does not happen + 0 + + + ITCM_ERR_STATUS_1 + ITCM access error happens. + 0x1 + + + + + DTCM_ERR_STATUS + DTCM Access Error Status + 4 + 1 + read-write + oneToClear + + + DTCM_ERR_STATUS_0 + DTCM access error does not happen + 0 + + + DTCM_ERR_STATUS_1 + DTCM access error happens. + 0x1 + + + + + OCRAM_ERR_STATUS + OCRAM Access Error Status + 5 + 1 + read-write + oneToClear + + + OCRAM_ERR_STATUS_0 + OCRAM access error does not happen + 0 + + + OCRAM_ERR_STATUS_1 + OCRAM access error happens. + 0x1 + + + + + + + INT_STAT_EN + Interrupt Status Enable Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STAT_EN + ITCM Access Error Status Enable + 3 + 1 + read-write + + + ITCM_ERR_STAT_EN_0 + Masked + 0 + + + ITCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_STAT_EN + DTCM Access Error Status Enable + 4 + 1 + read-write + + + DTCM_ERR_STAT_EN_0 + Masked + 0 + + + DTCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_STAT_EN + OCRAM Access Error Status Enable + 5 + 1 + read-write + + + OCRAM_ERR_STAT_EN_0 + Masked + 0 + + + OCRAM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + + + INT_SIG_EN + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_SIG_EN + ITCM Access Error Interrupt Enable + 3 + 1 + read-write + + + ITCM_ERR_SIG_EN_0 + Masked + 0 + + + ITCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_SIG_EN + DTCM Access Error Interrupt Enable + 4 + 1 + read-write + + + DTCM_ERR_SIG_EN_0 + Masked + 0 + + + DTCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_SIG_EN + OCRAM Access Error Interrupt Enable + 5 + 1 + read-write + + + OCRAM_ERR_SIG_EN_0 + Masked + 0 + + + OCRAM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + + + + + EWM + EWM + EWM + 0x400B4000 + + 0 + 0x6 + registers + + + EWM + 94 + + + + CTRL + Control Register + 0 + 8 + read-write + 0 + 0xFF + + + EWMEN + EWM enable. + 0 + 1 + read-writeOnce + + + ASSIN + EWM_in's Assertion State Select. + 1 + 1 + read-writeOnce + + + INEN + Input Enable. + 2 + 1 + read-writeOnce + + + INTEN + Interrupt Enable. + 3 + 1 + read-write + + + + + SERV + Service Register + 0x1 + 8 + read-write + 0 + 0xFF + + + SERVICE + SERVICE + 0 + 8 + read-write + + + + + CMPL + Compare Low Register + 0x2 + 8 + read-writeOnce + 0 + 0xFF + + + COMPAREL + COMPAREL + 0 + 8 + read-writeOnce + + + + + CMPH + Compare High Register + 0x3 + 8 + read-writeOnce + 0xFF + 0xFF + + + COMPAREH + COMPAREH + 0 + 8 + read-writeOnce + + + + + CLKCTRL + Clock Control Register + 0x4 + 8 + read-writeOnce + 0 + 0xFF + + + CLKSEL + CLKSEL + 0 + 2 + read-writeOnce + + + + + CLKPRESCALER + Clock Prescaler Register + 0x5 + 8 + read-writeOnce + 0 + 0xFF + + + CLK_DIV + CLK_DIV + 0 + 8 + read-writeOnce + + + + + + + WDOG1 + WDOG + WDOG + WDOG + 0x400B8000 + + 0 + 0xA + registers + + + WDOG1 + 92 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + WDZST + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + WDBG + 1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + WDE + 2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDT + 3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + SRS + 4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDA + 5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + WDW + 7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + WT + 8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + WSR + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + SFTW + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + TOUT + 1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + POR + 4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + WICT + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + WTIS + 14 + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + WIE + 15 + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + PDE + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + 0x400D0000 + + 0 + 0xA + registers + + + WDOG2 + 45 + + + + RTWDOG + WDOG + RTWDOG + 0x400BC000 + + 0 + 0x10 + registers + + + RTWDOG + 93 + + + + CS + Watchdog Control and Status Register + 0 + 32 + read-write + 0x2180 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + STOP_0 + Watchdog disabled in chip stop mode. + 0 + + + STOP_1 + Watchdog enabled in chip stop mode. + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + WAIT_0 + Watchdog disabled in chip wait mode. + 0 + + + WAIT_1 + Watchdog enabled in chip wait mode. + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DBG_0 + Watchdog disabled in chip debug mode. + 0 + + + DBG_1 + Watchdog enabled in chip debug mode. + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + TST_0 + Watchdog test mode disabled. + 0 + + + TST_1 + Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + 0x1 + + + TST_2 + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + TST_3 + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + UPDATE_0 + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + UPDATE_1 + Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + INT_0 + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + INT_1 + Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + EN_0 + Watchdog disabled. + 0 + + + EN_1 + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RCS_0 + Reconfiguring WDOG. + 0 + + + RCS_1 + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + ULK_0 + WDOG is locked. + 0 + + + ULK_1 + WDOG is unlocked. + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + PRES_0 + 256 prescaler disabled. + 0 + + + PRES_1 + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + CMD32EN_0 + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + CMD32EN_1 + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + FLG_0 + No interrupt occurred. + 0 + + + FLG_1 + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + WIN_0 + Window mode disabled. + 0 + + + WIN_1 + Window mode enabled. + 0x1 + + + + + + + CNT + Watchdog Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Watchdog Timeout Value Register + 0x8 + 32 + read-write + 0x7D00 + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Watchdog Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + ADC + 0x400C4000 + + 0 + 0x5C + registers + + + ADC1 + 67 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + COCO1 + Conversion Complete Flag + 1 + 1 + read-only + + + COCO2 + See description for COCO1. + 2 + 1 + read-only + + + COCO3 + See description for COCO1. + 3 + 1 + read-only + + + COCO4 + See description for COCO1. + 4 + 1 + read-only + + + COCO5 + See description for COCO1. + 5 + 1 + read-only + + + COCO6 + See description for COCO1. + 6 + 1 + read-only + + + COCO7 + See description for COCO1. + 7 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + R%s + Data result register for HW triggers + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x44 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the total sample time duration in number of full cycles + 8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 10 + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 11 + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 13 + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 14 + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 16 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 7 + 1 + read-write + + + + + GS + General status register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynchronous wake up interrupt occurred in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 16 + 12 + read-write + + + + + OFS + Offset correction value register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 12 + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + ADC2 + Analog-to-Digital Converter + ADC + ADC2_ + 0x400C8000 + + 0 + 0x5C + registers + + + ADC2 + 68 + + + + TRNG + TRNG + TRNG + 0x400CC000 + + 0 + 0xFF + registers + + + TRNG + 53 + + + + MCTL + Miscellaneous Control Register + 0 + 32 + read-write + 0x12001 + 0xFFFFFFFF + + + SAMP_MODE + Sample Mode + 0 + 2 + read-write + + + SAMP_MODE_0 + use Von Neumann data into both Entropy shifter and Statistical Checker + 0 + + + SAMP_MODE_1 + use raw data into both Entropy shifter and Statistical Checker + 0x1 + + + SAMP_MODE_2 + use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + 0x2 + + + SAMP_MODE_3 + undefined/reserved. + 0x3 + + + + + OSC_DIV + Oscillator Divide + 2 + 2 + read-write + + + OSC_DIV_0 + use ring oscillator with no divide + 0 + + + OSC_DIV_1 + use ring oscillator divided-by-2 + 0x1 + + + OSC_DIV_2 + use ring oscillator divided-by-4 + 0x2 + + + OSC_DIV_3 + use ring oscillator divided-by-8 + 0x3 + + + + + UNUSED4 + This bit is unused. Always reads zero. + 4 + 1 + read-only + + + UNUSED5 + This bit is unused. Always reads zero. + 5 + 1 + read-only + + + RST_DEF + Reset Defaults + 6 + 1 + write-only + + + FOR_SCLK + Force System Clock + 7 + 1 + read-write + + + FCT_FAIL + Read only: Frequency Count Fail + 8 + 1 + read-only + + + FCT_VAL + Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. + 9 + 1 + read-only + + + ENT_VAL + Read only: Entropy Valid + 10 + 1 + read-only + + + TST_OUT + Read only: Test point inside ring oscillator. + 11 + 1 + read-only + + + ERR + Read: Error status + 12 + 1 + read-write + oneToClear + + + TSTOP_OK + TRNG_OK_TO_STOP + 13 + 1 + read-only + + + LRUN_CONT + Long run count continues between entropy generations + 14 + 1 + read-write + + + PRGM + Programming Mode Select + 16 + 1 + read-write + + + + + SCMISC + Statistical Check Miscellaneous Register + 0x4 + 32 + read-write + 0x10022 + 0xFFFFFFFF + + + LRUN_MAX + LONG RUN MAX LIMIT + 0 + 8 + read-write + + + RTY_CT + RETRY COUNT + 16 + 4 + read-write + + + + + PKRRNG + Poker Range Register + 0x8 + 32 + read-write + 0x9A3 + 0xFFFFFFFF + + + PKR_RNG + Poker Range + 0 + 16 + read-write + + + + + PKRMAX + Poker Maximum Limit Register + MAX_SQ + 0xC + 32 + read-write + 0x6920 + 0xFFFFFFFF + + + PKR_MAX + Poker Maximum Limit. + 0 + 24 + read-write + + + + + PKRSQ + Poker Square Calculation Result Register + MAX_SQ + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_SQ + Poker Square Calculation Result. + 0 + 24 + read-only + + + + + SDCTL + Seed Control Register + 0x10 + 32 + read-write + 0xC8009C4 + 0xFFFFFFFF + + + SAMP_SIZE + Sample Size + 0 + 16 + read-write + + + ENT_DLY + Entropy Delay + 16 + 16 + read-write + + + + + SBLIM + Sparse Bit Limit Register + SBLIM_TOTSAM + 0x14 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + SB_LIM + Sparse Bit Limit + 0 + 10 + read-write + + + + + TOTSAM + Total Samples Register + SBLIM_TOTSAM + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOT_SAM + Total Samples + 0 + 20 + read-only + + + + + FRQMIN + Frequency Count Minimum Limit Register + 0x18 + 32 + read-write + 0x640 + 0xFFFFFFFF + + + FRQ_MIN + Frequency Count Minimum Limit + 0 + 22 + read-write + + + + + FRQCNT + Frequency Count Register + MAX_CNT + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FRQ_CT + Frequency Count + 0 + 22 + read-only + + + + + FRQMAX + Frequency Count Maximum Limit Register + MAX_CNT + 0x1C + 32 + read-write + 0x6400 + 0xFFFFFFFF + + + FRQ_MAX + Frequency Counter Maximum Limit + 0 + 22 + read-write + + + + + SCMC + Statistical Check Monobit Count Register + SCML_MC + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + MONO_CT + Monobit Count + 0 + 16 + read-only + + + + + SCML + Statistical Check Monobit Limit Register + SCML_MC + 0x20 + 32 + read-write + 0x10C0568 + 0xFFFFFFFF + + + MONO_MAX + Monobit Maximum Limit + 0 + 16 + read-write + + + MONO_RNG + Monobit Range + 16 + 16 + read-write + + + + + SCR1C + Statistical Check Run Length 1 Count Register + SCR1L_1C + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + R1_0_CT + Runs of Zero, Length 1 Count + 0 + 15 + read-only + + + R1_1_CT + Runs of One, Length 1 Count + 16 + 15 + read-only + + + + + SCR1L + Statistical Check Run Length 1 Limit Register + SCR1L_1C + 0x24 + 32 + read-write + 0xB20195 + 0xFFFFFFFF + + + RUN1_MAX + Run Length 1 Maximum Limit + 0 + 15 + read-write + + + RUN1_RNG + Run Length 1 Range + 16 + 15 + read-write + + + + + SCR2C + Statistical Check Run Length 2 Count Register + SCR2L_2C + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + R2_0_CT + Runs of Zero, Length 2 Count + 0 + 14 + read-only + + + R2_1_CT + Runs of One, Length 2 Count + 16 + 14 + read-only + + + + + SCR2L + Statistical Check Run Length 2 Limit Register + SCR2L_2C + 0x28 + 32 + read-write + 0x7A00DC + 0xFFFFFFFF + + + RUN2_MAX + Run Length 2 Maximum Limit + 0 + 14 + read-write + + + RUN2_RNG + Run Length 2 Range + 16 + 14 + read-write + + + + + SCR3C + Statistical Check Run Length 3 Count Register + SCR3L_3C + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + R3_0_CT + Runs of Zeroes, Length 3 Count + 0 + 13 + read-only + + + R3_1_CT + Runs of Ones, Length 3 Count + 16 + 13 + read-only + + + + + SCR3L + Statistical Check Run Length 3 Limit Register + SCR3L_3C + 0x2C + 32 + read-write + 0x58007D + 0xFFFFFFFF + + + RUN3_MAX + Run Length 3 Maximum Limit + 0 + 13 + read-write + + + RUN3_RNG + Run Length 3 Range + 16 + 13 + read-write + + + + + SCR4C + Statistical Check Run Length 4 Count Register + SCR4L_4C + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + R4_0_CT + Runs of Zero, Length 4 Count + 0 + 12 + read-only + + + R4_1_CT + Runs of One, Length 4 Count + 16 + 12 + read-only + + + + + SCR4L + Statistical Check Run Length 4 Limit Register + SCR4L_4C + 0x30 + 32 + read-write + 0x40004B + 0xFFFFFFFF + + + RUN4_MAX + Run Length 4 Maximum Limit + 0 + 12 + read-write + + + RUN4_RNG + Run Length 4 Range + 16 + 12 + read-write + + + + + SCR5C + Statistical Check Run Length 5 Count Register + SCR5L_5C + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + R5_0_CT + Runs of Zero, Length 5 Count + 0 + 11 + read-only + + + R5_1_CT + Runs of One, Length 5 Count + 16 + 11 + read-only + + + + + SCR5L + Statistical Check Run Length 5 Limit Register + SCR5L_5C + 0x34 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN5_MAX + Run Length 5 Maximum Limit + 0 + 11 + read-write + + + RUN5_RNG + Run Length 5 Range + 16 + 11 + read-write + + + + + SCR6PC + Statistical Check Run Length 6+ Count Register + SCR6PL_PC + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + R6P_0_CT + Runs of Zero, Length 6+ Count + 0 + 11 + read-only + + + R6P_1_CT + Runs of One, Length 6+ Count + 16 + 11 + read-only + + + + + SCR6PL + Statistical Check Run Length 6+ Limit Register + SCR6PL_PC + 0x38 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN6P_MAX + Run Length 6+ Maximum Limit + 0 + 11 + read-write + + + RUN6P_RNG + Run Length 6+ Range + 16 + 11 + read-write + + + + + STATUS + Status Register + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TF1BR0 + Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. + 0 + 1 + read-only + + + TF1BR1 + Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. + 1 + 1 + read-only + + + TF2BR0 + Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. + 2 + 1 + read-only + + + TF2BR1 + Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. + 3 + 1 + read-only + + + TF3BR0 + Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. + 4 + 1 + read-only + + + TF3BR1 + Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. + 5 + 1 + read-only + + + TF4BR0 + Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. + 6 + 1 + read-only + + + TF4BR1 + Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. + 7 + 1 + read-only + + + TF5BR0 + Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. + 8 + 1 + read-only + + + TF5BR1 + Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. + 9 + 1 + read-only + + + TF6PBR0 + Test Fail, 6 Plus Bit Run, Sampling 0s + 10 + 1 + read-only + + + TF6PBR1 + Test Fail, 6 Plus Bit Run, Sampling 1s + 11 + 1 + read-only + + + TFSB + Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. + 12 + 1 + read-only + + + TFLR + Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. + 13 + 1 + read-only + + + TFP + Test Fail, Poker. If TFP=1, the Poker Test has failed. + 14 + 1 + read-only + + + TFMB + Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. + 15 + 1 + read-only + + + RETRY_CT + RETRY COUNT + 16 + 4 + read-only + + + + + 16 + 0x4 + ENT[%s] + Entropy Read Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + PKRCNT10 + Statistical Check Poker Count 1 and 0 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_0_CT + Poker 0h Count + 0 + 16 + read-only + + + PKR_1_CT + Poker 1h Count + 16 + 16 + read-only + + + + + PKRCNT32 + Statistical Check Poker Count 3 and 2 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_2_CT + Poker 2h Count + 0 + 16 + read-only + + + PKR_3_CT + Poker 3h Count + 16 + 16 + read-only + + + + + PKRCNT54 + Statistical Check Poker Count 5 and 4 Register + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_4_CT + Poker 4h Count + 0 + 16 + read-only + + + PKR_5_CT + Poker 5h Count + 16 + 16 + read-only + + + + + PKRCNT76 + Statistical Check Poker Count 7 and 6 Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_6_CT + Poker 6h Count + 0 + 16 + read-only + + + PKR_7_CT + Poker 7h Count + 16 + 16 + read-only + + + + + PKRCNT98 + Statistical Check Poker Count 9 and 8 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_8_CT + Poker 8h Count + 0 + 16 + read-only + + + PKR_9_CT + Poker 9h Count + 16 + 16 + read-only + + + + + PKRCNTBA + Statistical Check Poker Count B and A Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_A_CT + Poker Ah Count + 0 + 16 + read-only + + + PKR_B_CT + Poker Bh Count + 16 + 16 + read-only + + + + + PKRCNTDC + Statistical Check Poker Count D and C Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_C_CT + Poker Ch Count + 0 + 16 + read-only + + + PKR_D_CT + Poker Dh Count + 16 + 16 + read-only + + + + + PKRCNTFE + Statistical Check Poker Count F and E Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_E_CT + Poker Eh Count + 0 + 16 + read-only + + + PKR_F_CT + Poker Fh Count + 16 + 16 + read-only + + + + + SEC_CFG + Security Configuration Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SH0 + Reserved. DRNG specific, not applicable to this version. + 0 + 1 + read-write + + + SH0_0 + See DRNG version. + 0 + + + SH0_1 + See DRNG version. + 0x1 + + + + + NO_PRGM + If set, the TRNG registers cannot be programmed + 1 + 1 + read-write + + + NO_PRGM_0 + Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + 0 + + + NO_PRGM_1 + Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + 0x1 + + + + + SK_VAL + Reserved. DRNG-specific, not applicable to this version. + 2 + 1 + read-write + + + SK_VAL_0 + See DRNG version. + 0 + + + SK_VAL_1 + See DRNG version. + 0x1 + + + + + + + INT_CTRL + Interrupt Control Register + 0xA4 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding bit of INT_STATUS cleared. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 above. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 above. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 above. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 above. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 above. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 above. + 0x1 + + + + + + + INT_MASK + Mask Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding interrupt of INT_STATUS is masked. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS is active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 above. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 above. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 above. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 above. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 above. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 above. + 0x1 + + + + + + + INT_STATUS + Interrupt Status Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_ERR + Read: Error status + 0 + 1 + read-only + + + HW_ERR_0 + no error + 0 + + + HW_ERR_1 + error detected. + 0x1 + + + + + ENT_VAL + Read only: Entropy Valid + 1 + 1 + read-only + + + ENT_VAL_0 + Busy generation entropy. Any value read is invalid. + 0 + + + ENT_VAL_1 + TRNG can be stopped and entropy is valid if read. + 0x1 + + + + + FRQ_CT_FAIL + Read only: Frequency Count Fail + 2 + 1 + read-only + + + FRQ_CT_FAIL_0 + No hardware nor self test frequency errors. + 0 + + + FRQ_CT_FAIL_1 + The frequency counter has detected a failure. + 0x1 + + + + + + + VID1 + Version ID Register (MS) + 0xF0 + 32 + read-only + 0x300301 + 0xFFFFFFFF + + + MIN_REV + Shows the IP's Minor revision of the TRNG. + 0 + 8 + read-only + + + MIN_REV_0 + Minor revision number for TRNG. + 0 + + + + + MAJ_REV + Shows the IP's Major revision of the TRNG. + 8 + 8 + read-only + + + MAJ_REV_1 + Major revision number for TRNG. + 0x1 + + + + + IP_ID + Shows the IP ID. + 16 + 16 + read-only + + + IP_ID_48 + ID for TRNG. + 0x30 + + + + + + + VID2 + Version ID Register (LS) + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + Shows the IP's Configuaration options for the TRNG. + 0 + 8 + read-only + + + CONFIG_OPT_0 + TRNG_CONFIG_OPT for TRNG. + 0 + + + + + ECO_REV + Shows the IP's ECO revision of the TRNG. + 8 + 8 + read-only + + + ECO_REV_0 + TRNG_ECO_REV for TRNG. + 0 + + + + + INTG_OPT + Shows the integration options for the TRNG. + 16 + 8 + read-only + + + INTG_OPT_0 + INTG_OPT for TRNG. + 0 + + + + + ERA + Shows the compile options for the TRNG. + 24 + 8 + read-only + + + ERA_0 + COMPILE_OPT for TRNG. + 0 + + + + + + + + + SNVS + SNVS + SNVS + 0x400D4000 + + 0 + 0x10000 + registers + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WSL + Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + ZMK_RSL + Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + READ_ALLOWED + Read access is allowed (only in software Programming mode) + 0 + + + READ_NOT_ALLOWED + Read access is not allowed + 0x1 + + + + + SRTC_SL + Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + LPCALB_SL + LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + MC_SL + Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + WRITE_ALLOWED + Write access (increment) is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access (increment) is not allowed + 0x1 + + + + + GPR_SL + General Purpose Register Soft Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + WRITE_ALLOWED + Write access is allowed + 0 + + + WRITE_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + LPSVCR_SL + LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + LPSECR_SL + LP Security Events Configuration Register Soft Lock When set, prevents any writes to the LPSECR + 8 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + MKS_SL + Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR + 9 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + HPSVCR_L + HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR + 16 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + HPSICR_L + HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR + 17 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + HAC_L + High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR + 18 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed + 0x1 + + + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSM_ST + SSM State Transition Transition state of the system security monitor + 0 + 1 + write-only + + + SSM_ST_DIS + SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state + 1 + 1 + read-write + + + ENABLED + Secure to Trusted State transition is enabled + 0 + + + DISABLED + Secure to Trusted State transition is disabled + 0x1 + + + + + SSM_SFNS_DIS + SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state + 2 + 1 + read-write + + + ENABLED + Soft Fail to Non-Secure State transition is enabled + 0 + + + DISABLED + Soft Fail to Non-Secure State transition is disabled + 0x1 + + + + + LP_SWR + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Monotonic Counter Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set + 4 + 1 + write-only + + + NO_ACTION + No Action + 0 + + + RESET + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, disables the LP software reset + 5 + 1 + read-write + + + ENABLED + LP software reset is enabled + 0 + + + DISABLED + LP software reset is disabled + 0x1 + + + + + SW_SV + Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation + 8 + 1 + read-write + + + SW_FSV + Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation + 9 + 1 + read-write + + + SW_LPSV + LP Software Security Violation When set, SNVS_LP treats this bit as a security violation + 10 + 1 + read-write + + + PROG_ZMK + Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism + 12 + 1 + write-only + + + NO_ACTION + No Action + 0 + + + PROGRAM_KEY + Activate hardware key programming mechanism + 0x1 + + + + + MKS_EN + Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default + 13 + 1 + read-write + + + SELECT_OTP + OTP master key is selected as an SNVS master key + 0 + + + SELECT_PER_LPMKCR + SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + 0x1 + + + + + HAC_EN + High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state + 16 + 1 + read-write + + + DISABLED + High Assurance Counter is disabled + 0 + + + ENABLED + High Assurance Counter is enabled + 0x1 + + + + + HAC_LOAD + High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register + 17 + 1 + write-only + + + NO_ACTION + No Action + 0 + + + LOAD_HAC + Load the HAC + 0x1 + + + + + HAC_CLEAR + High Assurance Counter Clear When set, it clears the High Assurance Counter Register + 18 + 1 + write-only + + + NO_ACTION + No Action + 0 + + + CLEAR_HAC + Clear the HAC + 0x1 + + + + + HAC_STOP + High Assurance Counter Stop This bit can be set only when SSM is in soft fail state + 19 + 1 + read-write + + + NPSWA_EN + Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real Time Counter Enable + 0 + 1 + read-write + + + DISABLED + RTC is disabled + 0 + + + ENABLED + RTC is enabled + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter + 1 + 1 + read-write + + + DISABLED + HP Time Alarm Interrupt is disabled + 0 + + + ENABLED + HP Time Alarm Interrupt is enabled + 0x1 + + + + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + ENABLED + Periodic interrupt will trigger a functional interrupt + 0 + + + DISABLED + Disable periodic interrupt in the function interrupt + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled + 3 + 1 + read-write + + + DISABLED + HP Periodic Interrupt is disabled + 0 + + + ENABLED + HP Periodic Interrupt is enabled + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines frequency of the periodic interrupt + 4 + 4 + read-write + + + USE_BIT_0 + - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + 0 + + + USE_BIT_1 + - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + 0x1 + + + USE_BIT_2 + - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + 0x2 + + + USE_BIT_3 + - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + 0x3 + + + USE_BIT_4 + - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + 0x4 + + + USE_BIT_5 + - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + 0x5 + + + USE_BIT_6 + - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + 0x6 + + + USE_BIT_7 + - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + 0x7 + + + USE_BIT_8 + - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + 0x8 + + + USE_BIT_9 + - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + 0x9 + + + USE_BIT_10 + - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + 0xA + + + USE_BIT_11 + - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + 0xB + + + USE_BIT_12 + - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + 0xC + + + USE_BIT_13 + - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + 0xD + + + USE_BIT_14 + - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + 0xE + + + USE_BIT_1r5 + - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + 0xF + + + + + HPCALB_EN + HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. + 8 + 1 + read-write + + + DISABLED + HP Timer calibration disabled + 0 + + + ENABLED + HP Timer calibration enabled + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines signed calibration value for the HP Real Time Counter + 10 + 5 + read-write + + + ADD_0_PER_32768_TICKS + +0 counts per each 32768 ticks of the counter + 0 + + + ADD_1_PER_32768_TICKS + +1 counts per each 32768 ticks of the counter + 0x1 + + + ADD_2_PER_32768_TICKS + +2 counts per each 32768 ticks of the counter + 0x2 + + + ADD_15_PER_32768_TICKS + +15 counts per each 32768 ticks of the counter + 0xF + + + SUB_16_PER_32768_TICKS + -16 counts per each 32768 ticks of the counter + 0x10 + + + SUB_15_PER_32768_TICKS + -15 counts per each 32768 ticks of the counter + 0x11 + + + SUB_2_PER_32768_TICKS + -2 counts per each 32768 ticks of the counter + 0x1E + + + SUB_1_PER_32768_TICKS + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + HP_TS + HP Time Synchronize + 16 + 1 + read-write + + + NO_ACTION + No Action + 0 + + + SYNC_TIME + Synchronize the HP Time Counter to the LP Time Counter + 0x1 + + + + + BTN_CONFIG + Button Configuration + 24 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 27 + 1 + read-write + + + + + HPSICR + SNVS_HP Security Interrupt Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation + 0 + 1 + read-write + + + DISABLED + Security Violation 0 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 0 Interrupt is Enabled + 0x1 + + + + + SV1_EN + Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation + 1 + 1 + read-write + + + DISABLED + Security Violation 1 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 1 Interrupt is Enabled + 0x1 + + + + + SV2_EN + Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation + 2 + 1 + read-write + + + DISABLED + Security Violation 2 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 2 Interrupt is Enabled + 0x1 + + + + + SV3_EN + Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation + 3 + 1 + read-write + + + DISABLED + Security Violation 3 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 3 Interrupt is Enabled + 0x1 + + + + + SV4_EN + Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation + 4 + 1 + read-write + + + DISABLED + Security Violation 4 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 4 Interrupt is Enabled + 0x1 + + + + + SV5_EN + Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation + 5 + 1 + read-write + + + DISABLED + Security Violation 5 Interrupt is Disabled + 0 + + + ENABLED + Security Violation 5 Interrupt is Enabled + 0x1 + + + + + LPSVI_EN + LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section + 31 + 1 + read-write + + + DISABLED + LP Security Violation Interrupt is Disabled + 0 + + + ENABLED + LP Security Violation Interrupt is Enabled + 0x1 + + + + + + + HPSVCR + SNVS_HP Security Violation Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_CFG + Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input + 0 + 1 + read-write + + + NON_FATAL + Security Violation 0 is a non-fatal violation + 0 + + + FATAL + Security Violation 0 is a fatal violation + 0x1 + + + + + SV1_CFG + Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input + 1 + 1 + read-write + + + NON_FATAL + Security Violation 1 is a non-fatal violation + 0 + + + FATAL + Security Violation 1 is a fatal violation + 0x1 + + + + + SV2_CFG + Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input + 2 + 1 + read-write + + + NON_FATAL + Security Violation 2 is a non-fatal violation + 0 + + + FATAL + Security Violation 2 is a fatal violation + 0x1 + + + + + SV3_CFG + Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input + 3 + 1 + read-write + + + NON_FATAL + Security Violation 3 is a non-fatal violation + 0 + + + FATAL + Security Violation 3 is a fatal violation + 0x1 + + + + + SV4_CFG + Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input + 4 + 1 + read-write + + + NON_FATAL + Security Violation 4 is a non-fatal violation + 0 + + + FATAL + Security Violation 4 is a fatal violation + 0x1 + + + + + SV5_CFG + Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input + 5 + 2 + read-write + + + DISABLED + Security Violation 5 is disabled + 0 + + + NON_FATAL + Security Violation 5 is a non-fatal violation + 0x1 + + + FATAL + Security Violation 5 is a fatal violation + #1x + + + + + LPSV_CFG + LP Security Violation Configuration This field configures the LP security violation source. + 30 + 2 + read-write + + + DISABLED + LP security violation is disabled + 0 + + + NON_FATAL + LP security violation is a non-fatal violation + 0x1 + + + FATAL + LP security violation is a fatal violation + #1x + + + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x8000B000 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. + 0 + 1 + read-write + oneToClear + + + NOREPORT + No time alarm interrupt occurred. + 0 + + + REPORTED + A time alarm interrupt occurred. + 0x1 + + + + + PI + Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. + 1 + 1 + read-write + oneToClear + + + NOREPORT + No periodic interrupt occurred. + 0 + + + REPORTED + A periodic interrupt occurred. + 0x1 + + + + + LPDIS + Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS + 4 + 1 + read-only + + + BTN + Button Value of the BTN input + 6 + 1 + read-only + + + BI + Button Interrupt Signal ipi_snvs_btn_int_b was asserted. + 7 + 1 + read-write + oneToClear + + + SSM_STATE + System Security Monitor State This field contains the encoded state of the SSM's state machine + 8 + 4 + read-only + + + INIT + Init + 0 + + + HARD_FAIL + Hard Fail + 0x1 + + + SOFT_FAIL + Soft Fail + 0x3 + + + INTERMEDIATE + Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + 0x8 + + + CHECK + Check + 0x9 + + + NON_SECURE + Non-Secure + 0xB + + + TRUSTED + Trusted + 0xD + + + SECURE + Secure + 0xF + + + + + SYS_SECURITY_CFG + System Security Configuration This field reflects the three security configuration inputs to SNVS + 12 + 3 + read-only + + + FAB_CONFIG + Fab Configuration - the default configuration of newly fabricated chips + 0 + + + OPEN_CONFIG + Open Configuration - the configuration after NXP-programmable fuses have been blown + 0x1 + + + CLOSED_CONFIG + Closed Configuration - the configuration after OEM-programmable fuses have been blown + 0x3 + + + FIELD_RETURN_CONFIG + Field Return Configuration - the configuration of chips that are returned to NXP for analysis + 0x7 + + + + + SYS_SECURE_BOOT + System Secure Boot If SYS_SECURE_BOOT is 1, the chip boots from internal ROM + 15 + 1 + read-only + + + OTPMK_SYNDROME + One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location + 16 + 9 + read-only + + + OTPMK_ZERO + One Time Programmable Master Key is Equal to Zero + 27 + 1 + read-only + + + OTPMK_NOT_ZERO + The OTPMK is not zero. + 0 + + + OTPMK_IS_ZERO + The OTPMK is zero. + 0x1 + + + + + ZMK_ZERO + Zeroizable Master Key is Equal to Zero + 31 + 1 + read-only + + + ZMK_NOT_ZERO + The ZMK is not zero. + 0 + + + ZMK_IS_ZERO + The ZMK is zero. + 0x1 + + + + + + + HPSVSR + SNVS_HP Security Violation Status Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + SV0 + Security Violation 0 security violation was detected. + 0 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 0 security violation was detected. + 0 + + + REPORTED + Security Violation 0 security violation was detected. + 0x1 + + + + + SV1 + Security Violation 1 security violation was detected. + 1 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 1 security violation was detected. + 0 + + + REPORTED + Security Violation 1 security violation was detected. + 0x1 + + + + + SV2 + Security Violation 2 security violation was detected. + 2 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 2 security violation was detected. + 0 + + + REPORTED + Security Violation 2 security violation was detected. + 0x1 + + + + + SV3 + Security Violation 3 security violation was detected. + 3 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 3 security violation was detected. + 0 + + + REPORTED + Security Violation 3 security violation was detected. + 0x1 + + + + + SV4 + Security Violation 4 security violation was detected. + 4 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 4 security violation was detected. + 0 + + + REPORTED + Security Violation 4 security violation was detected. + 0x1 + + + + + SV5 + Security Violation 5 security violation was detected. + 5 + 1 + read-write + oneToClear + + + NOREPORT + No Security Violation 5 security violation was detected. + 0 + + + REPORTED + Security Violation 5 security violation was detected. + 0x1 + + + + + SW_SV + Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register + 13 + 1 + read-only + + + SW_FSV + Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register + 14 + 1 + read-only + + + SW_LPSV + LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register + 15 + 1 + read-only + + + ZMK_SYNDROME + Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register + 16 + 9 + read-only + + + ZMK_ECC_FAIL + Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data + 27 + 1 + read-write + oneToClear + + + NOREPORT + ZMK ECC Failure was not detected. + 0 + + + REPORTED + ZMK ECC Failure was detected. + 0x1 + + + + + LP_SEC_VIO + LP Security Violation A security volation was detected in the SNVS low power section + 31 + 1 + read-only + + + + + HPHACIVR + SNVS_HP High Assurance Counter IV Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAC_COUNTER_IV + High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter + 0 + 32 + read-write + + + + + HPHACR + SNVS_HP High Assurance Counter Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + HAC_COUNTER + High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock + 0 + 32 + read-only + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter The most-significant 15 bits of the RTC + 0 + 15 + read-write + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter least-significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_MS + HP Time Alarm, most-significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_LS + HP Time Alarm, 32 least-significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WHL + Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + ZMK_RHL + Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + READ_ACCESS_ALLOWED + Read access is allowed (only in software programming mode). + 0 + + + READ_ACCESS_NOT_ALLOWED + Read access is not allowed. + 0x1 + + + + + SRTC_HL + Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + LPCALB_HL + LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + MC_HL + Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access (increment) is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General Purpose Register Hard Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + LPSVCR_HL + LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + LPSECR_HL + LP Security Events Configuration Register Hard Lock When set, prevents any writes to the LPSECR + 8 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + MKS_HL + Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register + 9 + 1 + read-write + + + WRITE_ACCESS_ALLOWED + Write access is allowed. + 0 + + + WRITE_ACCESS_NOT_ALLOWED + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + SRTC_ENV + Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational + 0 + 1 + read-write + + + DISABLED + SRTC is disabled or invalid. + 0 + + + ENABLED + SRTC is enabled and valid. + 0x1 + + + + + LPTA_EN + LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter + 1 + 1 + read-write + + + DISABLED + LP time alarm interrupt is disabled. + 0 + + + ENABLED + LP time alarm interrupt is enabled. + 0x1 + + + + + MC_ENV + Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) + 2 + 1 + read-write + + + DISABLED + MC is disabled or invalid. + 0 + + + ENABLED + MC is enabled and valid. + 0x1 + + + + + LPWUI_EN + LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (MC rollover, SRTC rollover, or time alarm ) + 3 + 1 + read-write + + + SRTC_INV_EN + If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) + 4 + 1 + read-write + + + KEEP_VALID + SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). + 0 + + + INVALIDATE + SRTC is invalidated in the case of security violation. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, software can control the system power + 5 + 1 + read-write + + + SMART_PMIC_ENABLED + Smart PMIC enabled. + 0 + + + DUMB_PMIC_ENABLED + Dumb PMIC enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power + 6 + 1 + read-write + + + KEEP_ON + Leave system power on. + 0 + + + TURN_OFF + Turn off system power. + 0x1 + + + + + LVD_EN + Digital Low-Voltage Event Enable By default the detection of a low-voltage event does not cause the pmic_en_b signal to be asserted + 7 + 1 + read-write + + + LPCALB_EN + LP Calibration Enable When set, enables the SRTC calibration mechanism + 8 + 1 + read-write + + + DISABLED + SRTC Time calibration is disabled. + 0 + + + ENABLED + SRTC Time calibration is enabled. + 0x1 + + + + + LPCALB_VAL + LP Calibration Value Defines signed calibration value for SRTC + 10 + 5 + read-write + + + ADD_0_PER_32768_TICKS + +0 counts per each 32768 ticks of the counter clock + 0 + + + ADD_1_PER_32768_TICKS + +1 counts per each 32768 ticks of the counter clock + 0x1 + + + ADD_2_PER_32768_TICKS + +2 counts per each 32768 ticks of the counter clock + 0x2 + + + ADD_15_PER_32768_TICKS + +15 counts per each 32768 ticks of the counter clock + 0xF + + + SUB_16_PER_32768_TICKS + -16 counts per each 32768 ticks of the counter clock + 0x10 + + + SUB_15_PER_32768_TICKS + -15 counts per each 32768 ticks of the counter clock + 0x11 + + + SUB_2_PER_32768_TICKS + -2 counts per each 32768 ticks of the counter clock + 0x1E + + + SUB_1_PER_32768_TICKS + -1 counts per each 32768 ticks of the counter clock + 0x1F + + + + + BTN_PRESS_TIME + This field configures the button press time out values for the PMIC Logic + 16 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 18 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power + 20 + 2 + read-write + + + PK_EN + PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en + 22 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override + 23 + 1 + read-write + + + GPR_Z_DIS + General Purpose Registers Zeroization Disable + 24 + 1 + read-write + + + + + LPMKCR + SNVS_LP Master Key Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER_KEY_SEL + Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR + 0 + 2 + read-write + + + SELECT_OTPMK + Select one time programmable master key. + #0x + + + SELECT_ZMK + Select zeroizable master key when MKS_EN bit is set . + 0x2 + + + SELECT_COMBO + Select combined master key when MKS_EN bit is set . + 0x3 + + + + + ZMK_HWP + Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it + 2 + 1 + read-write + + + SW_PROG_MODE + ZMK is in the software programming mode. + 0 + + + HW_PROG_MODE + ZMK is in the hardware programming mode. + 0x1 + + + + + ZMK_VAL + Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules + 3 + 1 + read-write + + + INVALID + ZMK is not valid. + 0 + + + VALID + ZMK is valid. + 0x1 + + + + + ZMK_ECC_EN + Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register + 4 + 1 + read-write + + + DISABLED + ZMK ECC check is disabled. + 0 + + + ENABLED + ZMK ECC check is enabled. + 0x1 + + + + + ZMK_ECC_VALUE + Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register + 7 + 9 + read-only + + + + + LPSVCR + SNVS_LP Security Violation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Enable This bit enables Security Violation 0 Input + 0 + 1 + read-write + + + DISABLED + Security Violation 0 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 0 is enabled in the LP domain. + 0x1 + + + + + SV1_EN + Security Violation 1 Enable This bit enables Security Violation 1 Input + 1 + 1 + read-write + + + DISABLED + Security Violation 1 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 1 is enabled in the LP domain. + 0x1 + + + + + SV2_EN + Security Violation 2 Enable This bit enables Security Violation 2 Input + 2 + 1 + read-write + + + DISABLED + Security Violation 2 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 2 is enabled in the LP domain. + 0x1 + + + + + SV3_EN + Security Violation 3 Enable This bit enables Security Violation 3 Input + 3 + 1 + read-write + + + DISABLED + Security Violation 3 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 3 is enabled in the LP domain. + 0x1 + + + + + SV4_EN + Security Violation 4 Enable This bit enables Security Violation 4 Input + 4 + 1 + read-write + + + DISABLED + Security Violation 4 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 4 is enabled in the LP domain. + 0x1 + + + + + SV5_EN + Security Violation 5 Enable This bit enables Security Violation 5 Input + 5 + 1 + read-write + + + DISABLED + Security Violation 5 is disabled in the LP domain. + 0 + + + ENABLED + Security Violation 5 is enabled in the LP domain. + 0x1 + + + + + + + LPSECR + SNVS_LP Security Events Configuration Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTCR_EN + SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. + 1 + 1 + read-write + + + DISABLED + SRTC rollover is disabled. + 0 + + + ENABLED + SRTC rollover is enabled. + 0x1 + + + + + MCR_EN + MC Rollover Enable When set, an MC Rollover event generates an LP security violation. + 2 + 1 + read-write + + + DISABLED + MC rollover is disabled. + 0 + + + ENABLED + MC rollover is enabled. + 0x1 + + + + + PFD_OBSERV + System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) + 14 + 1 + read-write + + + POR_OBSERV + Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS + 15 + 1 + read-write + + + LTDC + Low Temp Detect Configuration These configuration bits are wired as an output of the module. + 16 + 3 + read-write + + + HTDC + High Temperature Detect Configuration These configuration bits are wired as an output of the module + 20 + 3 + read-write + + + VRC + Voltage Reference Configuration These configuration bits are wired as an output of the module. + 24 + 3 + read-write + + + OSCB + Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted + 28 + 1 + read-write + + + NOT_BYPASSED + Normal SRTC clock oscillator not bypassed. + 0 + + + BYPASSED + Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + 0x1 + + + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + LP Time Alarm + 0 + 1 + read-write + oneToClear + + + NOREPORT + No time alarm interrupt occurred. + 0 + + + REPORTED + A time alarm interrupt occurred. + 0x1 + + + + + SRTCR + Secure Real Time Counter Rollover + 1 + 1 + read-write + oneToClear + + + NOREPORT + SRTC has not reached its maximum value. + 0 + + + REPORTED + SRTC has reached its maximum value. + 0x1 + + + + + MCR + Monotonic Counter Rollover + 2 + 1 + read-write + oneToClear + + + NOREPORT + MC has not reached its maximum value. + 0 + + + REPORTED + MC has reached its maximum value. + 0x1 + + + + + LVD + Digital Low Voltage Event Detected + 3 + 1 + read-write + oneToClear + + + NOLOWVOLT + No low voltage event detected. + 0 + + + LOWVOLTDETECTED + Low voltage event is detected. + 0x1 + + + + + ESVD + External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports + 16 + 1 + read-write + oneToClear + + + NOREPORT + No external security violation. + 0 + + + REPORTED + External security violation is detected. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 17 + 1 + read-write + oneToClear + + + NOREPORT + Emergency off was not detected. + 0 + + + REPORTED + Emergency off was detected. + 0x1 + + + + + SPOF + Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time + 18 + 1 + read-write + oneToClear + + + NOREPORT + Set Power Off was not detected. + 0 + + + REPORTED + Set Power Off was detected. + 0x1 + + + + + SPON + Set Power On The SPON bit is set when the set_pwr_on_irq interrupt is triggered, which happens when the power button is pressed longer than the configured debounce time + 19 + 1 + read-write + oneToClear + + + NOREPORT + Set Power On Interrupt was not detected. + 0 + + + REPORTED + Set Power On Interrupt was detected. + 0x1 + + + + + LPNS + LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state + 30 + 1 + read-only + + + NOT_PRGRMD_IN_NON_SECURE_STATE + LP section was not programmed in the non-secure state. + 0 + + + WAS_PRGRMD_IN_NON_SECURE_STATE + LP section was programmed in the non-secure state. + 0x1 + + + + + LPS + LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state + 31 + 1 + read-only + + + NOT_PRGRMD_IN_SECURE_OR_TRUSTED_STATE + LP section was not programmed in secure or trusted state. + 0 + + + WAS_PRGRMD_IN_SECURE_OR_TRUSTED_STATE + LP section was programmed in secure or trusted state. + 0x1 + + + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter The most-significant 15 bits of the SRTC + 0 + 15 + read-write + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter most-significant 16 Bits Note that writing to this register does not change the value of this field to the value that was written + 0 + 16 + read-write + modify + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses + 16 + 16 + read-only + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits Note that writing to this register does not change the value of this field to the value that was written + 0 + 32 + read-write + modify + + + + + LPLVDR + SNVS_LP Digital Low-Voltage Detector Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVD + Low-Voltage Detector Value + 0 + 32 + read-write + + + + + LPGPR0_legacy_alias + SNVS_LP General Purpose Register 0 (legacy alias) + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPZMKR[%s] + SNVS_LP Zeroizable Master Key Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK + Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR_alias[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPGPR[%s] + SNVS_LP General Purpose Registers 0 .. 7 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0104 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 8 + 8 + read-only + + + IP_ID + SNVS block ID + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Options + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 8 + 8 + read-only + + + INTG_OPT + SNVS Integration Options + 16 + 8 + read-only + + + IP_ERA + IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 06h - Era 6 + 24 + 8 + read-only + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x400D8000 + + 0 + 0x180 + registers + + + + PLL_ARM + Analog ARM PLL control Register + 0 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_SET + Analog ARM PLL control Register + 0x4 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2 + Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + Enable bit + 15 + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 16 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider (signed number) + 0 + 30 + read-write + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + 30 bit denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + Arm supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + Arm supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + Arm supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + Arm supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + PMU + PMU + CCM_ANALOG + PMU + PMU_ + 0x400D8000 + + 0 + 0x180 + registers + + + PMU_EVENT + 61 + + + + REG_1P1 + Regulator 1P1 Register + 0x110 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_SET + Regulator 1P1 Register + 0x114 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_CLR + Regulator 1P1 Register + 0x118 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_TOG + Regulator 1P1 Register + 0x11C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x120 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_SET + Regulator 3P0 Register + 0x124 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_CLR + Regulator 3P0 Register + 0x128 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_TOG + Regulator 3P0 Register + 0x12C + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x130 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_SET + Regulator 2P5 Register + 0x134 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_CLR + Regulator 2P5 Register + 0x138 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_TOG + Regulator 2P5 Register + 0x13C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x140 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the Arm core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_SET + Digital Regulator Core Register + 0x144 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the Arm core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_CLR + Digital Regulator Core Register + 0x148 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the Arm core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_TOG + Digital Regulator Core Register + 0x14C + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the Arm core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_PWDVBGUP + Control bit to power down the VBG-up detection circuitry in the analog bandgap. + 1 + 1 + read-write + + + REFTOP_LOWPOWER + Control bit to enable the low-power mode in the analog bandgap. + 2 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_PWDVBGUP + Control bit to power down the VBG-up detection circuitry in the analog bandgap. + 1 + 1 + read-write + + + REFTOP_LOWPOWER + Control bit to enable the low-power mode in the analog bandgap. + 2 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_PWDVBGUP + Control bit to power down the VBG-up detection circuitry in the analog bandgap. + 1 + 1 + read-write + + + REFTOP_LOWPOWER + Control bit to enable the low-power mode in the analog bandgap. + 2 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_PWDVBGUP + Control bit to power down the VBG-up detection circuitry in the analog bandgap. + 1 + 1 + read-write + + + REFTOP_LOWPOWER + Control bit to enable the low-power mode in the analog bandgap. + 2 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + ARM PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + TEMPMON + Temperature Monitor + CCM_ANALOG + TEMPMON + TEMPMON_ + 0x400D8000 + + 0 + 0x2A0 + registers + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0x180 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x184 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x188 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0x18C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x190 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x194 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x198 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x19C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + CCM_ANALOG + USB_ANALOG + USB_ANALOG_ + 0x400D8000 + + 0 + 0x264 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0x1A0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x1A4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x1A8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x1AC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x1C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x1D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB1_LOOPBACK + USB Loopback Test Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB1_LOOPBACK_SET + USB Loopback Test Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB1_LOOPBACK_CLR + USB Loopback Test Register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB1_LOOPBACK_TOG + USB Loopback Test Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB1_MISC + USB Misc Register + 0x1F0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x1F4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x1F8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x1FC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x200 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x204 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x208 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x20C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB2_LOOPBACK + USB Loopback Test Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB2_LOOPBACK_SET + USB Loopback Test Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB2_LOOPBACK_CLR + USB Loopback Test Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB2_LOOPBACK_TOG + USB Loopback Test Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_TESTSTART + Setting this bit can enable 1 + 0 + 1 + read-write + + + + + USB2_MISC + USB Misc Register + 0x250 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_SET + USB Misc Register + 0x254 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_CLR + USB Misc Register + 0x258 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_TOG + USB Misc Register + 0x25C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0x260 + 32 + read-only + 0x6A0001 + 0xFFFFFFFF + + + SILICON_REVISION + Chip silicon revision + 0 + 32 + read-only + + + SILICON_REVISION_6946817 + Silicon revision 1.1 + 0x6A0001 + + + + + + + + + XTALOSC24M + XTALOSC24M + CCM_ANALOG + XTALOSC24M + XTALOSC24M_ + 0x400D8000 + + 0 + 0x2D0 + registers + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + LOWPWR_CTRL + XTAL OSC (LP) Control Register + 0x270 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_SET + XTAL OSC (LP) Control Register + 0x274 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + XTAL OSC (LP) Control Register + 0x278 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + XTAL OSC (LP) Control Register + 0x27C + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0x2A0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x2A4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x2A8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0x2AC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x2B0 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x2B4 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x2B8 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x2BC + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x2C0 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x2C4 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x2C8 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2CC + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + USBPHY + 0x400D9000 + + 0 + 0x84 + registers + + + USB_PHY1 + 65 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 3 + 1 + read-only + + + RSVD1 + Reserved. + 4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 6 + 1 + read-only + + + RSVD2 + Reserved. + 7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 8 + 1 + read-write + + + RSVD3 + Reserved. + 9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 10 + 1 + read-only + + + RSVD4 + Reserved. + 11 + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 16 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 26 + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4030000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + + + USBPHY2 + USBPHY Register Reference Index + USBPHY + USBPHY2_ + 0x400DA000 + + 0 + 0x84 + registers + + + USB_PHY2 + 66 + + + + CSU + CSU registers + CSU + CSU_ + 0x400DC000 + + 0 + 0x35C + registers + + + CSU + 49 + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + CSL%s + Config security level register + 0 + 32 + read-write + 0x330033 + 0xFFFFFFFF + + + SUR_S2 + Secure user read access control for the second slave + 0 + 1 + read-write + + + SUR_S2_0 + The secure user read access is disabled for the second slave. + 0 + + + SUR_S2_1 + The secure user read access is enabled for the second slave. + 0x1 + + + + + SSR_S2 + Secure supervisor read access control for the second slave + 1 + 1 + read-write + + + SSR_S2_0 + The secure supervisor read access is disabled for the second slave. + 0 + + + SSR_S2_1 + The secure supervisor read access is enabled for the second slave. + 0x1 + + + + + NUR_S2 + Non-secure user read access control for the second slave + 2 + 1 + read-write + + + NUR_S2_0 + The non-secure user read access is disabled for the second slave. + 0 + + + NUR_S2_1 + The non-secure user read access is enabled for the second slave. + 0x1 + + + + + NSR_S2 + Non-secure supervisor read access control for the second slave + 3 + 1 + read-write + + + NSR_S2_0 + The non-secure supervisor read access is disabled for the second slave. + 0 + + + NSR_S2_1 + The non-secure supervisor read access is enabled for the second slave. + 0x1 + + + + + SUW_S2 + Secure user write access control for the second slave + 4 + 1 + read-write + + + SUW_S2_0 + The secure user write access is disabled for the second slave. + 0 + + + SUW_S2_1 + The secure user write access is enabled for the second slave. + 0x1 + + + + + SSW_S2 + Secure supervisor write access control for the second slave + 5 + 1 + read-write + + + SSW_S2_0 + The secure supervisor write access is disabled for the second slave. + 0 + + + SSW_S2_1 + The secure supervisor write access is enabled for the second slave. + 0x1 + + + + + NUW_S2 + Non-secure user write access control for the second slave + 6 + 1 + read-write + + + NUW_S2_0 + The non-secure user write access is disabled for the second slave. + 0 + + + NUW_S2_1 + The non-secure user write access is enabled for the second slave. + 0x1 + + + + + NSW_S2 + Non-secure supervisor write access control for the second slave + 7 + 1 + read-write + + + NSW_S2_0 + The non-secure supervisor write access is disabled for the second slave. + 0 + + + NSW_S2_1 + The non-secure supervisor write access is enabled for the second slave. + 0x1 + + + + + LOCK_S2 + The lock bit corresponding to the second slave. It is written by the secure software. + 8 + 1 + read-write + + + LOCK_S2_0 + Not locked. Bits 7-0 can be written by the software. + 0 + + + LOCK_S2_1 + Bits 7-0 are locked and cannot be written by the software + 0x1 + + + + + SUR_S1 + Secure user read access control for the first slave + 16 + 1 + read-write + + + SUR_S1_0 + The secure user read access is disabled for the first slave. + 0 + + + SUR_S1_1 + The secure user read access is enabled for the first slave. + 0x1 + + + + + SSR_S1 + Secure supervisor read access control for the first slave + 17 + 1 + read-write + + + SSR_S1_0 + The secure supervisor read access is disabled for the first slave. + 0 + + + SSR_S1_1 + The secure supervisor read access is enabled for the first slave. + 0x1 + + + + + NUR_S1 + Non-secure user read access control for the first slave + 18 + 1 + read-write + + + NUR_S1_0 + The non-secure user read access is disabled for the first slave. + 0 + + + NUR_S1_1 + The non-secure user read access is enabled for the first slave. + 0x1 + + + + + NSR_S1 + Non-secure supervisor read access control for the first slave + 19 + 1 + read-write + + + NSR_S1_0 + The non-secure supervisor read access is disabled for the first slave. + 0 + + + NSR_S1_1 + The non-secure supervisor read access is enabled for the first slave. + 0x1 + + + + + SUW_S1 + Secure user write access control for the first slave + 20 + 1 + read-write + + + SUW_S1_0 + The secure user write access is disabled for the first slave. + 0 + + + SUW_S1_1 + The secure user write access is enabled for the first slave. + 0x1 + + + + + SSW_S1 + Secure supervisor write access control for the first slave + 21 + 1 + read-write + + + SSW_S1_0 + The secure supervisor write access is disabled for the first slave. + 0 + + + SSW_S1_1 + The secure supervisor write access is enabled for the first slave. + 0x1 + + + + + NUW_S1 + Non-secure user write access control for the first slave + 22 + 1 + read-write + + + NUW_S1_0 + The non-secure user write access is disabled for the first slave. + 0 + + + NUW_S1_1 + The non-secure user write access is enabled for the first slave. + 0x1 + + + + + NSW_S1 + Non-secure supervisor write access control for the first slave + 23 + 1 + read-write + + + NSW_S1_0 + The non-secure supervisor write access is disabled for the first slave. + 0 + + + NSW_S1_1 + The non-secure supervisor write access is enabled for the first slave + 0x1 + + + + + LOCK_S1 + The lock bit corresponding to the first slave. It is written by the secure software. + 24 + 1 + read-write + + + LOCK_S1_0 + Not locked. The bits 16-23 can be written by the software. + 0 + + + LOCK_S1_1 + The bits 16-23 are locked and can't be written by the software. + 0x1 + + + + + + + HP0 + HP0 register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_DMA + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA + 2 + 1 + read-write + + + HP_DMA_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DMA_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_LCDIF + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF + 4 + 1 + read-write + + + HP_LCDIF_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_LCDIF_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_CSI + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI + 6 + 1 + read-write + + + HP_CSI_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_CSI_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_PXP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP + 8 + 1 + read-write + + + HP_PXP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_PXP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_DCP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP + 10 + 1 + read-write + + + HP_DCP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DCP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit cannot be written by the software. + 0x1 + + + + + HP_ENET + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET + 14 + 1 + read-write + + + HP_ENET_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_ENET_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC1 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1 + 16 + 1 + read-write + + + HP_USDHC1_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC1_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC2 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2 + 18 + 1 + read-write + + + HP_USDHC2_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC2_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_TPSMP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP + 20 + 1 + read-write + + + HP_TPSMP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_TPSMP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USB + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB + 22 + 1 + read-write + + + HP_USB_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USB_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + SA + Secure access register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSA_DMA + Non-secure access policy indicator bit + 2 + 1 + read-write + + + NSA_DMA_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DMA_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_LCDIF + Non-secure access policy indicator bit + 4 + 1 + read-write + + + NSA_LCDIF_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_LCDIF_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_CSI + Non-secure access policy indicator bit + 6 + 1 + read-write + + + NSA_CSI_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_CSI_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_PXP + Non-Secure Access Policy indicator bit + 8 + 1 + read-write + + + NSA_PXP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_PXP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_DCP + Non-secure access policy indicator bit + 10 + 1 + read-write + + + NSA_DCP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DCP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_ENET + Non-secure access policy indicator bit + 14 + 1 + read-write + + + NSA_ENET_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_ENET_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET1 and ENET2 + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC1 + Non-secure access policy indicator bit + 16 + 1 + read-write + + + NSA_USDHC1_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC1_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC2 + Non-secure access policy indicator bit + 18 + 1 + read-write + + + NSA_USDHC2_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC2_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_TPSMP + Non-secure access policy indicator bit + 20 + 1 + read-write + + + NSA_TPSMP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_TPSMP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USB + Non-secure access policy indicator bit + 22 + 1 + read-write + + + NSA_USB_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USB_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + HPCONTROL0 + HPCONTROL0 register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_DMA + Indicates the privilege/user mode for the eDMA + 2 + 1 + read-write + + + HPC_DMA_0 + User mode for the corresponding master + 0 + + + HPC_DMA_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_LCDIF + Indicates the privilege/user mode for the LCDIF + 4 + 1 + read-write + + + HPC_LCDIF_0 + User mode for the corresponding master + 0 + + + HPC_LCDIF_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_CSI + Indicates the privilege/user mode for the CSI + 6 + 1 + read-write + + + HPC_CSI_0 + User mode for the corresponding master + 0 + + + HPC_CSI_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_PXP + Indicates the privilege/user mode for the PXP + 8 + 1 + read-write + + + HPC_PXP_0 + User mode for the corresponding master + 0 + + + HPC_PXP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_DCP + Indicates the privilege/user mode for the DCP + 10 + 1 + read-write + + + HPC_DCP_0 + User mode for the corresponding master + 0 + + + HPC_DCP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_ENET + Indicates the privilege/user mode for the ENET + 14 + 1 + read-write + + + HPC_ENET_0 + User mode for the corresponding master + 0 + + + HPC_ENET_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC1 + Indicates the privilege/user mode for the USDHC1 + 16 + 1 + read-write + + + HPC_USDHC1_0 + User mode for the corresponding master + 0 + + + HPC_USDHC1_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC2 + Indicates the privilege/user mode for the USDHC2 + 18 + 1 + read-write + + + HPC_USDHC2_0 + User mode for the corresponding master + 0 + + + HPC_USDHC2_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2. + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_TPSMP + Indicates the privilege/user mode for the TPSMP + 20 + 1 + read-write + + + HPC_TPSMP_0 + User mode for the corresponding master + 0 + + + HPC_TPSMP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP. + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USB + Indicates the privilege/user mode for the USB + 22 + 1 + read-write + + + HPC_USB_0 + User mode for the corresponding master + 0 + + + HPC_USB_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB. + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + + + TSC + Touch Screen Controller + TSC + TSC_ + 0x400E0000 + + 0 + 0x84 + registers + + + TSC_DIG + 40 + + + + BASIC_SETTING + Basic Setting + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTO_MEASURE + Auto Measure + 0 + 1 + read-write + + + AUTO_MEASURE_0 + Disable Auto Measure + 0 + + + AUTO_MEASURE_1 + Auto Measure + 0x1 + + + + + WIRE_4_5 + 4/5 Wire detection + 4 + 1 + read-write + + + WIRE_4_5_0 + 4-Wire Detection Mode + 0 + + + WIRE_4_5_1 + 5-Wire Detection Mode + 0x1 + + + + + MEASURE_DELAY_TIME + Measure Delay Time + 8 + 24 + read-write + + + + + PRE_CHARGE_TIME + Pre-charge Time + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_CHARGE_TIME + Before detection, the top screen needs some time before being pulled up to a high voltage. + 0 + 32 + read-write + + + + + FLOW_CONTROL + Flow Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + Soft Reset + 0 + 1 + read-write + + + START_MEASURE + Start Measure + 4 + 1 + read-write + + + START_MEASURE_0 + Do not start measure for now + 0 + + + START_MEASURE_1 + Start measure the X/Y coordinate value + 0x1 + + + + + DROP_MEASURE + Drop Measure + 8 + 1 + read-write + + + DROP_MEASURE_0 + Do not drop measure for now + 0 + + + DROP_MEASURE_1 + Drop the measure and controller return to idle status + 0x1 + + + + + START_SENSE + Start Sense + 12 + 1 + read-write + + + START_SENSE_0 + Stay at idle status + 0 + + + START_SENSE_1 + Start sense detection and (if auto_measure set to 1) measure after detect a touch + 0x1 + + + + + DISABLE + This bit is for SW disable registers + 16 + 1 + read-write + + + DISABLE_0 + Leave HW state machine control + 0 + + + DISABLE_1 + SW set to idle status + 0x1 + + + + + + + MEASEURE_VALUE + Measure Value + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + Y_VALUE + Y Value + 0 + 12 + read-only + + + X_VALUE + X Value + 16 + 12 + read-only + + + + + INT_EN + Interrupt Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_INT_EN + Measure Interrupt Enable + 0 + 1 + read-write + + + MEASURE_INT_EN_0 + Disable measure interrupt + 0 + + + MEASURE_INT_EN_1 + Enable measure interrupt + 0x1 + + + + + DETECT_INT_EN + Detect Interrupt Enable + 4 + 1 + read-write + + + DETECT_INT_EN_0 + Disable detect interrupt + 0 + + + DETECT_INT_EN_1 + Enable detect interrupt + 0x1 + + + + + IDLE_SW_INT_EN + Idle Software Interrupt Enable + 12 + 1 + read-write + + + IDLE_SW_INT_EN_0 + Disable idle software interrupt + 0 + + + IDLE_SW_INT_EN_1 + Enable idle software interrupt + 0x1 + + + + + + + INT_SIG_EN + Interrupt Signal Enable + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_SIG_EN + Measure Signal Enable + 0 + 1 + read-write + + + DETECT_SIG_EN + Detect Signal Enable + 4 + 1 + read-write + + + DETECT_SIG_EN_0 + Disable detect signal + 0 + + + DETECT_SIG_EN_1 + Enable detect signal + 0x1 + + + + + VALID_SIG_EN + Valid Signal Enable + 8 + 1 + read-write + + + VALID_SIG_EN_0 + Disable valid signal + 0 + + + VALID_SIG_EN_1 + Enable valid signal + 0x1 + + + + + IDLE_SW_SIG_EN + Idle Software Signal Enable + 12 + 1 + read-write + + + IDLE_SW_SIG_EN_0 + Disable idle software signal + 0 + + + IDLE_SW_SIG_EN_1 + Enable idle software signal + 0x1 + + + + + + + INT_STATUS + Intterrupt Status + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE + Measure Signal + 0 + 1 + read-write + + + MEASURE_0 + Does not exist a measure signal + 0 + + + MEASURE_1 + Exist a measure signal + 0x1 + + + + + DETECT + Detect Signal + 4 + 1 + read-write + + + DETECT_0 + Does not exist a detect signal + 0 + + + DETECT_1 + Exist detect signal + 0x1 + + + + + VALID + Valid Signal + 8 + 1 + read-write + + + VALID_0 + There is no touch detected after measurement, indicates that the measured value is not valid + 0 + + + VALID_1 + There is touch detection after measurement, indicates that the measure is valid + 0x1 + + + + + IDLE_SW + Idle Software + 12 + 1 + read-write + + + IDLE_SW_0 + Haven't return to idle status + 0 + + + IDLE_SW_1 + Already return to idle status + 0x1 + + + + + + + DEBUG_MODE + Debug Mode Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_CONV_VALUE + ADC Conversion Value + 0 + 12 + read-only + + + ADC_COCO + ADC COCO Signal + 12 + 1 + read-only + + + EXT_HWTS + Hardware Trigger Select Signal + 16 + 5 + read-write + + + TRIGGER + Trigger + 24 + 1 + read-write + + + TRIGGER_0 + No hardware trigger signal + 0 + + + TRIGGER_1 + Hardware trigger signal, the signal must last at least 1 ips clock period + 0x1 + + + + + ADC_COCO_CLEAR + ADC Coco Clear + 25 + 1 + read-write + + + ADC_COCO_CLEAR_0 + No ADC COCO clear + 0 + + + ADC_COCO_CLEAR_1 + Set ADC COCO clear + 0x1 + + + + + ADC_COCO_CLEAR_DISABLE + ADC COCO Clear Disable + 26 + 1 + read-write + + + ADC_COCO_CLEAR_DISABLE_0 + Allow TSC hardware generates ADC COCO clear + 0 + + + ADC_COCO_CLEAR_DISABLE_1 + Prevent TSC from generate ADC COCO clear signal + 0x1 + + + + + DEBUG_EN + Debug Enable + 28 + 1 + read-write + + + DEBUG_EN_0 + Enable debug mode + 0 + + + DEBUG_EN_1 + Disable debug mode + 0x1 + + + + + + + DEBUG_MODE2 + Debug Mode Register 2 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + XPUL_PULL_DOWN + XPUL Wire Pull Down Switch + 0 + 1 + read-write + + + XPUL_PULL_DOWN_0 + Close the switch + 0 + + + XPUL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XPUL_PULL_UP + XPUL Wire Pull Up Switch + 1 + 1 + read-write + + + XPUL_PULL_UP_0 + Close the switch + 0 + + + XPUL_PULL_UP_1 + Open up the switch + 0x1 + + + + + XPUL_200K_PULL_UP + XPUL Wire 200K Pull Up Switch + 2 + 1 + read-write + + + XPUL_200K_PULL_UP_0 + Close the switch + 0 + + + XPUL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_DOWN + XNUR Wire Pull Down Switch + 3 + 1 + read-write + + + XNUR_PULL_DOWN_0 + Close the switch + 0 + + + XNUR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_UP + XNUR Wire Pull Up Switch + 4 + 1 + read-write + + + XNUR_PULL_UP_0 + Close the switch + 0 + + + XNUR_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_200K_PULL_UP + XNUR Wire 200K Pull Up Switch + 5 + 1 + read-write + + + XNUR_200K_PULL_UP_0 + Close the switch + 0 + + + XNUR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_DOWN + YPLL Wire Pull Down Switch + 6 + 1 + read-write + + + YPLL_PULL_DOWN_0 + Close the switch + 0 + + + YPLL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_UP + YPLL Wire Pull Up Switch + 7 + 1 + read-write + + + YPLL_PULL_UP_0 + Close the switch + 0 + + + YPLL_PULL_UP_1 + Open the switch + 0x1 + + + + + YPLL_200K_PULL_UP + YPLL Wire 200K Pull Up Switch + 8 + 1 + read-write + + + YPLL_200K_PULL_UP_0 + Close the switch + 0 + + + YPLL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_DOWN + YNLR Wire Pull Down Switch + 9 + 1 + read-write + + + YNLR_PULL_DOWN_0 + Close the switch + 0 + + + YNLR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_UP + YNLR Wire Pull Up Switch + 10 + 1 + read-write + + + YNLR_PULL_UP_0 + Close the switch + 0 + + + YNLR_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_200K_PULL_UP + YNLR Wire 200K Pull Up Switch + 11 + 1 + read-write + + + YNLR_200K_PULL_UP_0 + Close the switch + 0 + + + YNLR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_DOWN + Wiper Wire Pull Down Switch + 12 + 1 + read-write + + + WIPER_PULL_DOWN_0 + Close the switch + 0 + + + WIPER_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_UP + Wiper Wire Pull Up Switch + 13 + 1 + read-write + + + WIPER_PULL_UP_0 + Close the switch + 0 + + + WIPER_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_200K_PULL_UP + Wiper Wire 200K Pull Up Switch + 14 + 1 + read-write + + + WIPER_200K_PULL_UP_0 + Close the switch + 0 + + + WIPER_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + DETECT_FOUR_WIRE + Detect Four Wire + 16 + 1 + read-only + + + DETECT_FOUR_WIRE_0 + No detect signal + 0 + + + DETECT_FOUR_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + DETECT_FIVE_WIRE + Detect Five Wire + 17 + 1 + read-only + + + DETECT_FIVE_WIRE_0 + No detect signal + 0 + + + DETECT_FIVE_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + STATE_MACHINE + State Machine + 20 + 3 + read-only + + + STATE_MACHINE_0 + Idle + 0 + + + STATE_MACHINE_1 + Pre-charge + 0x1 + + + STATE_MACHINE_2 + Detect + 0x2 + + + STATE_MACHINE_3 + X-measure + 0x3 + + + STATE_MACHINE_4 + Y-measure + 0x4 + + + STATE_MACHINE_5 + Pre-charge + 0x5 + + + STATE_MACHINE_6 + Detect + 0x6 + + + + + INTERMEDIATE + Intermediate State + 23 + 1 + read-only + + + INTERMEDIATE_0 + Not in intermedia + 0 + + + INTERMEDIATE_1 + Intermedia + 0x1 + + + + + DETECT_ENABLE_FOUR_WIRE + Detect Enable Four Wire + 24 + 1 + read-write + + + DETECT_ENABLE_FOUR_WIRE_0 + Do not read four wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FOUR_WIRE_1 + Read four wire detect status from analogue + 0x1 + + + + + DETECT_ENABLE_FIVE_WIRE + Detect Enable Five Wire + 28 + 1 + read-write + + + DETECT_ENABLE_FIVE_WIRE_0 + Do not read five wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FIVE_WIRE_1 + Read five wire detect status from analogue + 0x1 + + + + + DE_GLITCH + This field indicates glitch threshold + 29 + 2 + read-only + + + DE_GLITCH_0 + Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + 0 + + + DE_GLITCH_1 + Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + 0x1 + + + DE_GLITCH_2 + Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + 0x2 + + + DE_GLITCH_3 + Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + 0x3 + + + + + + + + + DMA0 + DMA + DMA + 0x400E8000 + + 0 + 0x1400 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + + CR + Control + 0 + 32 + read-write + 0x400 + 0x80FFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + DISABLED + When the chip is in Debug mode, the eDMA continues to operate. + 0 + + + ENABLED + Entry of the chip into Debug mode is effective + 0x1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + DISABLED + Fixed priority arbitration within each group + 0 + + + ENABLED + Round robin arbitration within each group + 0x1 + + + + + ERGA + Enable Round Robin Group Arbitration + 3 + 1 + read-write + + + DISABLED + Fixed priority arbitration + 0 + + + ENABLED + Round robin arbitration + 0x1 + + + + + HOE + Halt On Error + 4 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + HALT_ON_ERROR + Error causes HALT field to be automatically set to 1 + 0x1 + + + + + HALT + Halt eDMA Operations + 5 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + HALT_DMA + eDMA operations halted + 0x1 + + + + + CLM + Continuous Link Mode + 6 + 1 + read-write + + + CLM_OFF + Continuous link mode is off + 0 + + + CLM_ON + Continuous link mode is on + 0x1 + + + + + EMLM + Enable Minor Loop Mapping + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + GRP0PRI + Channel Group 0 Priority + 8 + 1 + read-write + + + GRP1PRI + Channel Group 1 Priority + 10 + 1 + read-write + + + ECX + Error Cancel Transfer + 16 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + CANCEL + Cancel the remaining data transfer + 0x1 + + + + + CX + Cancel Transfer + 17 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + CANCEL + Cancel the remaining data transfer + 0x1 + + + + + VERSION + eDMA version number + 24 + 7 + read-only + + + ACTIVE + eDMA Active Status + 31 + 1 + read-only + + + IDLE + eDMA is idle + 0 + + + ACTIVE + eDMA is executing a channel + 0x1 + + + + + + + ES + Error Status + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + NO_ERROR + No destination bus error. + 0 + + + ERROR + The most-recently recorded error was a bus error on a destination write. + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + NO_ERROR + No source bus error. + 0 + + + ERROR + The most-recently recorded error was a bus error on a source read. + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + NO_ERROR + No scatter/gather configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field. + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NO_ERROR + No NBYTES/CITER configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]. + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + NO_ERROR + No destination offset configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + NO_ERROR + No destination address configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + NO_ERROR + No source offset configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + NO_ERROR + No source address configuration error. + 0 + + + ERROR + The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 8 + 5 + read-only + + + CPE + Channel Priority Error + 14 + 1 + read-only + + + NO_ERROR + No channel priority error. + 0 + + + ERROR + The most-recently recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + 0x1 + + + + + GPE + Group Priority Error + 15 + 1 + read-only + + + NO_ERROR + No group priority error. + 0 + + + ERROR + The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique. + 0x1 + + + + + ECX + Transfer Canceled + 16 + 1 + read-only + + + NO_CANCELS + No canceled transfers + 0 + + + CANCELED + The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field + 0x1 + + + + + VLD + Logical OR of all ERR status fields + 31 + 1 + read-only + + + NO_ERROR + No ERR fields are 1 + 0 + + + ERROR + At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared + 0x1 + + + + + + + ERQ + Enable Request + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ0 + Enable DMA Request 0 + 0 + 1 + read-write + + + DISABLE + The DMA request signal for channel 0 is disabled + 0 + + + ENABLE + The DMA request signal for channel 0 is enabled + 0x1 + + + + + ERQ1 + Enable DMA Request 1 + 1 + 1 + read-write + + + DISABLE + The DMA request signal for channel 1 is disabled + 0 + + + ENABLE + The DMA request signal for channel 1 is enabled + 0x1 + + + + + ERQ2 + Enable DMA Request 2 + 2 + 1 + read-write + + + DISABLE + The DMA request signal for channel 2 is disabled + 0 + + + ENABLE + The DMA request signal for channel 2 is enabled + 0x1 + + + + + ERQ3 + Enable DMA Request 3 + 3 + 1 + read-write + + + DISABLE + The DMA request signal for channel 3 is disabled + 0 + + + ENABLE + The DMA request signal for channel 3 is enabled + 0x1 + + + + + ERQ4 + Enable DMA Request 4 + 4 + 1 + read-write + + + DISABLE + The DMA request signal for channel 4 is disabled + 0 + + + ENABLE + The DMA request signal for channel 4 is enabled + 0x1 + + + + + ERQ5 + Enable DMA Request 5 + 5 + 1 + read-write + + + DISABLE + The DMA request signal for channel 5 is disabled + 0 + + + ENABLE + The DMA request signal for channel 5 is enabled + 0x1 + + + + + ERQ6 + Enable DMA Request 6 + 6 + 1 + read-write + + + DISABLE + The DMA request signal for channel 6 is disabled + 0 + + + ENABLE + The DMA request signal for channel 6 is enabled + 0x1 + + + + + ERQ7 + Enable DMA Request 7 + 7 + 1 + read-write + + + DISABLE + The DMA request signal for channel 7 is disabled + 0 + + + ENABLE + The DMA request signal for channel 7 is enabled + 0x1 + + + + + ERQ8 + Enable DMA Request 8 + 8 + 1 + read-write + + + DISABLE + The DMA request signal for channel 8 is disabled + 0 + + + ENABLE + The DMA request signal for channel 8 is enabled + 0x1 + + + + + ERQ9 + Enable DMA Request 9 + 9 + 1 + read-write + + + DISABLE + The DMA request signal for channel 9 is disabled + 0 + + + ENABLE + The DMA request signal for channel 9 is enabled + 0x1 + + + + + ERQ10 + Enable DMA Request 10 + 10 + 1 + read-write + + + DISABLE + The DMA request signal for channel 10 is disabled + 0 + + + ENABLE + The DMA request signal for channel 10 is enabled + 0x1 + + + + + ERQ11 + Enable DMA Request 11 + 11 + 1 + read-write + + + DISABLE + The DMA request signal for channel 11 is disabled + 0 + + + ENABLE + The DMA request signal for channel 11 is enabled + 0x1 + + + + + ERQ12 + Enable DMA Request 12 + 12 + 1 + read-write + + + DISABLE + The DMA request signal for channel 12 is disabled + 0 + + + ENABLE + The DMA request signal for channel 12 is enabled + 0x1 + + + + + ERQ13 + Enable DMA Request 13 + 13 + 1 + read-write + + + DISABLE + The DMA request signal for channel 13 is disabled + 0 + + + ENABLE + The DMA request signal for channel 13 is enabled + 0x1 + + + + + ERQ14 + Enable DMA Request 14 + 14 + 1 + read-write + + + DISABLE + The DMA request signal for channel 14 is disabled + 0 + + + ENABLE + The DMA request signal for channel 14 is enabled + 0x1 + + + + + ERQ15 + Enable DMA Request 15 + 15 + 1 + read-write + + + DISABLE + The DMA request signal for channel 15 is disabled + 0 + + + ENABLE + The DMA request signal for channel 15 is enabled + 0x1 + + + + + ERQ16 + Enable DMA Request 16 + 16 + 1 + read-write + + + DISABLE + The DMA request signal for channel 16 is disabled + 0 + + + ENABLE + The DMA request signal for channel 16 is enabled + 0x1 + + + + + ERQ17 + Enable DMA Request 17 + 17 + 1 + read-write + + + DISABLE + The DMA request signal for channel 17 is disabled + 0 + + + ENABLE + The DMA request signal for channel 17 is enabled + 0x1 + + + + + ERQ18 + Enable DMA Request 18 + 18 + 1 + read-write + + + DISABLE + The DMA request signal for channel 18 is disabled + 0 + + + ENABLE + The DMA request signal for channel 18 is enabled + 0x1 + + + + + ERQ19 + Enable DMA Request 19 + 19 + 1 + read-write + + + DISABLE + The DMA request signal for channel 19 is disabled + 0 + + + ENABLE + The DMA request signal for channel 19 is enabled + 0x1 + + + + + ERQ20 + Enable DMA Request 20 + 20 + 1 + read-write + + + DISABLE + The DMA request signal for channel 20 is disabled + 0 + + + ENABLE + The DMA request signal for channel 20 is enabled + 0x1 + + + + + ERQ21 + Enable DMA Request 21 + 21 + 1 + read-write + + + DISABLE + The DMA request signal for channel 21 is disabled + 0 + + + ENABLE + The DMA request signal for channel 21 is enabled + 0x1 + + + + + ERQ22 + Enable DMA Request 22 + 22 + 1 + read-write + + + DISABLE + The DMA request signal for channel 22 is disabled + 0 + + + ENABLE + The DMA request signal for channel 22 is enabled + 0x1 + + + + + ERQ23 + Enable DMA Request 23 + 23 + 1 + read-write + + + DISABLE + The DMA request signal for channel 23 is disabled + 0 + + + ENABLE + The DMA request signal for channel 23 is enabled + 0x1 + + + + + ERQ24 + Enable DMA Request 24 + 24 + 1 + read-write + + + DISABLE + The DMA request signal for channel 24 is disabled + 0 + + + ENABLE + The DMA request signal for channel 24 is enabled + 0x1 + + + + + ERQ25 + Enable DMA Request 25 + 25 + 1 + read-write + + + DISABLE + The DMA request signal for channel 25 is disabled + 0 + + + ENABLE + The DMA request signal for channel 25 is enabled + 0x1 + + + + + ERQ26 + Enable DMA Request 26 + 26 + 1 + read-write + + + DISABLE + The DMA request signal for channel 26 is disabled + 0 + + + ENABLE + The DMA request signal for channel 26 is enabled + 0x1 + + + + + ERQ27 + Enable DMA Request 27 + 27 + 1 + read-write + + + DISABLE + The DMA request signal for channel 27 is disabled + 0 + + + ENABLE + The DMA request signal for channel 27 is enabled + 0x1 + + + + + ERQ28 + Enable DMA Request 28 + 28 + 1 + read-write + + + DISABLE + The DMA request signal for channel 28 is disabled + 0 + + + ENABLE + The DMA request signal for channel 28 is enabled + 0x1 + + + + + ERQ29 + Enable DMA Request 29 + 29 + 1 + read-write + + + DISABLE + The DMA request signal for channel 29 is disabled + 0 + + + ENABLE + The DMA request signal for channel 29 is enabled + 0x1 + + + + + ERQ30 + Enable DMA Request 30 + 30 + 1 + read-write + + + DISABLE + The DMA request signal for channel 30 is disabled + 0 + + + ENABLE + The DMA request signal for channel 30 is enabled + 0x1 + + + + + ERQ31 + Enable DMA Request 31 + 31 + 1 + read-write + + + DISABLE + The DMA request signal for channel 31 is disabled + 0 + + + ENABLE + The DMA request signal for channel 31 is enabled + 0x1 + + + + + + + EEI + Enable Error Interrupt + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + EEI0 + Enable Error Interrupt 0 + 0 + 1 + read-write + + + NO_INTERRUPT + An error on channel 0 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 0 generates an error interrupt request + 0x1 + + + + + EEI1 + Enable Error Interrupt 1 + 1 + 1 + read-write + + + NO_INTERRUPT + An error on channel 1 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 1 generates an error interrupt request + 0x1 + + + + + EEI2 + Enable Error Interrupt 2 + 2 + 1 + read-write + + + NO_INTERRUPT + An error on channel 2 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 2 generates an error interrupt request + 0x1 + + + + + EEI3 + Enable Error Interrupt 3 + 3 + 1 + read-write + + + NO_INTERRUPT + An error on channel 3 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 3 generates an error interrupt request + 0x1 + + + + + EEI4 + Enable Error Interrupt 4 + 4 + 1 + read-write + + + NO_INTERRUPT + An error on channel 4 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 4 generates an error interrupt request + 0x1 + + + + + EEI5 + Enable Error Interrupt 5 + 5 + 1 + read-write + + + NO_INTERRUPT + An error on channel 5 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 5 generates an error interrupt request + 0x1 + + + + + EEI6 + Enable Error Interrupt 6 + 6 + 1 + read-write + + + NO_INTERRUPT + An error on channel 6 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 6 generates an error interrupt request + 0x1 + + + + + EEI7 + Enable Error Interrupt 7 + 7 + 1 + read-write + + + NO_INTERRUPT + An error on channel 7 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 7 generates an error interrupt request + 0x1 + + + + + EEI8 + Enable Error Interrupt 8 + 8 + 1 + read-write + + + NO_INTERRUPT + An error on channel 8 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 8 generates an error interrupt request + 0x1 + + + + + EEI9 + Enable Error Interrupt 9 + 9 + 1 + read-write + + + NO_INTERRUPT + An error on channel 9 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 9 generates an error interrupt request + 0x1 + + + + + EEI10 + Enable Error Interrupt 10 + 10 + 1 + read-write + + + NO_INTERRUPT + An error on channel 10 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 10 generates an error interrupt request + 0x1 + + + + + EEI11 + Enable Error Interrupt 11 + 11 + 1 + read-write + + + NO_INTERRUPT + An error on channel 11 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 11 generates an error interrupt request + 0x1 + + + + + EEI12 + Enable Error Interrupt 12 + 12 + 1 + read-write + + + NO_INTERRUPT + An error on channel 12 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 12 generates an error interrupt request + 0x1 + + + + + EEI13 + Enable Error Interrupt 13 + 13 + 1 + read-write + + + NO_INTERRUPT + An error on channel 13 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 13 generates an error interrupt request + 0x1 + + + + + EEI14 + Enable Error Interrupt 14 + 14 + 1 + read-write + + + NO_INTERRUPT + An error on channel 14 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 14 generates an error interrupt request + 0x1 + + + + + EEI15 + Enable Error Interrupt 15 + 15 + 1 + read-write + + + NO_INTERRUPT + An error on channel 15 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 15 generates an error interrupt request + 0x1 + + + + + EEI16 + Enable Error Interrupt 16 + 16 + 1 + read-write + + + NO_INTERRUPT + An error on channel 16 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 16 generates an error interrupt request + 0x1 + + + + + EEI17 + Enable Error Interrupt 17 + 17 + 1 + read-write + + + NO_INTERRUPT + An error on channel 17 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 17 generates an error interrupt request + 0x1 + + + + + EEI18 + Enable Error Interrupt 18 + 18 + 1 + read-write + + + NO_INTERRUPT + An error on channel 18 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 18 generates an error interrupt request + 0x1 + + + + + EEI19 + Enable Error Interrupt 19 + 19 + 1 + read-write + + + NO_INTERRUPT + An error on channel 19 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 19 generates an error interrupt request + 0x1 + + + + + EEI20 + Enable Error Interrupt 20 + 20 + 1 + read-write + + + NO_INTERRUPT + An error on channel 20 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 20 generates an error interrupt request + 0x1 + + + + + EEI21 + Enable Error Interrupt 21 + 21 + 1 + read-write + + + NO_INTERRUPT + An error on channel 21 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 21 generates an error interrupt request + 0x1 + + + + + EEI22 + Enable Error Interrupt 22 + 22 + 1 + read-write + + + NO_INTERRUPT + An error on channel 22 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 22 generates an error interrupt request + 0x1 + + + + + EEI23 + Enable Error Interrupt 23 + 23 + 1 + read-write + + + NO_INTERRUPT + An error on channel 23 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 23 generates an error interrupt request + 0x1 + + + + + EEI24 + Enable Error Interrupt 24 + 24 + 1 + read-write + + + NO_INTERRUPT + An error on channel 24 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 24 generates an error interrupt request + 0x1 + + + + + EEI25 + Enable Error Interrupt 25 + 25 + 1 + read-write + + + NO_INTERRUPT + An error on channel 25 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 25 generates an error interrupt request + 0x1 + + + + + EEI26 + Enable Error Interrupt 26 + 26 + 1 + read-write + + + NO_INTERRUPT + An error on channel 26 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 26 generates an error interrupt request + 0x1 + + + + + EEI27 + Enable Error Interrupt 27 + 27 + 1 + read-write + + + NO_INTERRUPT + An error on channel 27 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 27 generates an error interrupt request + 0x1 + + + + + EEI28 + Enable Error Interrupt 28 + 28 + 1 + read-write + + + NO_INTERRUPT + An error on channel 28 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 28 generates an error interrupt request + 0x1 + + + + + EEI29 + Enable Error Interrupt 29 + 29 + 1 + read-write + + + NO_INTERRUPT + An error on channel 29 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 29 generates an error interrupt request + 0x1 + + + + + EEI30 + Enable Error Interrupt 30 + 30 + 1 + read-write + + + NO_INTERRUPT + An error on channel 30 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 30 generates an error interrupt request + 0x1 + + + + + EEI31 + Enable Error Interrupt 31 + 31 + 1 + read-write + + + NO_INTERRUPT + An error on channel 31 does not generate an error interrupt + 0 + + + INTERRUPT + An error on channel 31 generates an error interrupt request + 0x1 + + + + + + + CEEI + Clear Enable Error Interrupt + 0x18 + 8 + read-write + 0 + 0xFF + + + CEEI + Clear Enable Error Interrupt + 0 + 5 + read-write + + + CAEE + Clear All Enable Error Interrupts + 6 + 1 + read-write + + + CLEAR_EEI + Write 0 only to the EEI field specified in the CEEI field + 0 + + + CLEAR_ALL + Write 0 to all fields in EEI + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation, ignore the other fields in this register + 0x1 + + + + + + + SEEI + Set Enable Error Interrupt + 0x19 + 8 + read-write + 0 + 0xFF + + + SEEI + Set Enable Error Interrupt + 0 + 5 + read-write + + + SAEE + Set All Enable Error Interrupts + 6 + 1 + read-write + + + SET_EEI + Write 1 only to the EEI field specified in the SEEI field + 0 + + + SET_ALL + Writes 1 to all fields in EEI + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation, ignore the other fields in this register + 0x1 + + + + + + + CERQ + Clear Enable Request + 0x1A + 8 + read-write + 0 + 0xFF + + + CERQ + Clear Enable Request + 0 + 5 + read-write + + + CAER + Clear All Enable Requests + 6 + 1 + read-write + + + CLEAR_ERQ + Write 0 to only the ERQ field specified in the CERQ field + 0 + + + CLEAR_ALL + Write 0 to all fields in ERQ + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation, ignore the other fields in this register + 0x1 + + + + + + + SERQ + Set Enable Request + 0x1B + 8 + read-write + 0 + 0xFF + + + SERQ + Set Enable Request + 0 + 5 + read-write + + + SAER + Set All Enable Requests + 6 + 1 + read-write + + + SET_ERQ + Write 1 to only the ERQ field specified in the SERQ field + 0 + + + SET_ALL + Write 1 to all fields in ERQ + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation, ignore the other fields in this register + 0x1 + + + + + + + CDNE + Clear DONE Status Bit + 0x1C + 8 + read-write + 0 + 0xFF + + + CDNE + Clear DONE field + 0 + 5 + read-write + + + CADN + Clears All DONE fields + 6 + 1 + read-write + + + CLEAR_DONE + Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field + 0 + + + CLEAR_ALL + Writes 0 to all bits in TCDn_CSR[DONE] + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation; all other fields in this register are ignored. + 0x1 + + + + + + + SSRT + Set START Bit + 0x1D + 8 + read-write + 0 + 0xFF + + + SSRT + Set START field + 0 + 5 + read-write + + + SAST + Set All START fields (activates all channels) + 6 + 1 + read-write + + + SET_START + Write 1 to only the TCDn_CSR[START] field specified in the SSRT field + 0 + + + SET_ALL + Write 1 to all bits in TCDn_CSR[START] + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation; all other fields in this register are ignored. + 0x1 + + + + + + + CERR + Clear Error + 0x1E + 8 + read-write + 0 + 0xFF + + + CERR + Clear Error Indicator + 0 + 5 + read-write + + + CAEI + Clear All Error Indicators + 6 + 1 + read-write + + + CLEAR_ERR + Write 0 to only the ERR field specified in the CERR field + 0 + + + CLEAR_ALL + Write 0 to all fields in ERR + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation; all other fields in this register are ignored. + 0x1 + + + + + + + CINT + Clear Interrupt Request + 0x1F + 8 + read-write + 0 + 0xFF + + + CINT + Clear Interrupt Request + 0 + 5 + read-write + + + CAIR + Clear All Interrupt Requests + 6 + 1 + read-write + + + CLEAR_INT + Clear only the INT field specified in the CINT field + 0 + + + CLEAR_ALL + Clear all bits in INT + 0x1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + NORMAL_OPS + Normal operation + 0 + + + NO_OPS + No operation; all other fields in this register are ignored. + 0x1 + + + + + + + INT + Interrupt Request + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT0 + Interrupt Request 0 + 0 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 0 is cleared + 0 + + + ACTIVE + The interrupt request for channel 0 is active + 0x1 + + + + + INT1 + Interrupt Request 1 + 1 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 1 is cleared + 0 + + + ACTIVE + The interrupt request for channel 1 is active + 0x1 + + + + + INT2 + Interrupt Request 2 + 2 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 2 is cleared + 0 + + + ACTIVE + The interrupt request for channel 2 is active + 0x1 + + + + + INT3 + Interrupt Request 3 + 3 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 3 is cleared + 0 + + + ACTIVE + The interrupt request for channel 3 is active + 0x1 + + + + + INT4 + Interrupt Request 4 + 4 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 4 is cleared + 0 + + + ACTIVE + The interrupt request for channel 4 is active + 0x1 + + + + + INT5 + Interrupt Request 5 + 5 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 5 is cleared + 0 + + + ACTIVE + The interrupt request for channel 5 is active + 0x1 + + + + + INT6 + Interrupt Request 6 + 6 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 6 is cleared + 0 + + + CTIVE + The interrupt request for channel 6 is active + 0x1 + + + + + INT7 + Interrupt Request 7 + 7 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 7 is cleared + 0 + + + ACTIVE + The interrupt request for channel 7 is active + 0x1 + + + + + INT8 + Interrupt Request 8 + 8 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 8 is cleared + 0 + + + ACTIVE + The interrupt request for channel 8 is active + 0x1 + + + + + INT9 + Interrupt Request 9 + 9 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 9 is cleared + 0 + + + ACTIVE + The interrupt request for channel 9 is active + 0x1 + + + + + INT10 + Interrupt Request 10 + 10 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 10 is cleared + 0 + + + ACTIVE + The interrupt request for channel 10 is active + 0x1 + + + + + INT11 + Interrupt Request 11 + 11 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 11 is cleared + 0 + + + ACTIVE + The interrupt request for channel 11 is active + 0x1 + + + + + INT12 + Interrupt Request 12 + 12 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 12 is cleared + 0 + + + ACTIVE + The interrupt request for channel 12 is active + 0x1 + + + + + INT13 + Interrupt Request 13 + 13 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 13 is cleared + 0 + + + ACTIVE + The interrupt request for channel 13 is active + 0x1 + + + + + INT14 + Interrupt Request 14 + 14 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 14 is cleared + 0 + + + ACTIVE + The interrupt request for channel 14 is active + 0x1 + + + + + INT15 + Interrupt Request 15 + 15 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 15 is cleared + 0 + + + ACTIVE + The interrupt request for channel 15 is active + 0x1 + + + + + INT16 + Interrupt Request 16 + 16 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 16 is cleared + 0 + + + ACTIVE + The interrupt request for channel 16 is active + 0x1 + + + + + INT17 + Interrupt Request 17 + 17 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 17 is cleared + 0 + + + ACTIVE + The interrupt request for channel 17 is active + 0x1 + + + + + INT18 + Interrupt Request 18 + 18 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 18 is cleared + 0 + + + ACTIVE + The interrupt request for channel 18 is active + 0x1 + + + + + INT19 + Interrupt Request 19 + 19 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 19 is cleared + 0 + + + ACTIVE + The interrupt request for channel 19 is active + 0x1 + + + + + INT20 + Interrupt Request 20 + 20 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 20 is cleared + 0 + + + ACTIVE + The interrupt request for channel 20 is active + 0x1 + + + + + INT21 + Interrupt Request 21 + 21 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 21 is cleared + 0 + + + ACTIVE + The interrupt request for channel 21 is active + 0x1 + + + + + INT22 + Interrupt Request 22 + 22 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 22 is cleared + 0 + + + ACTIVE + The interrupt request for channel 22 is active + 0x1 + + + + + INT23 + Interrupt Request 23 + 23 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 23 is cleared + 0 + + + ACTIVE + The interrupt request for channel 23 is active + 0x1 + + + + + INT24 + Interrupt Request 24 + 24 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 24 is cleared + 0 + + + ACTIVE + The interrupt request for channel 24 is active + 0x1 + + + + + INT25 + Interrupt Request 25 + 25 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 25 is cleared + 0 + + + ACTIVE + The interrupt request for channel 25 is active + 0x1 + + + + + INT26 + Interrupt Request 26 + 26 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 26 is cleared + 0 + + + ACTIVE + The interrupt request for channel 26 is active + 0x1 + + + + + INT27 + Interrupt Request 27 + 27 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 27 is cleared + 0 + + + ACTIVE + The interrupt request for channel 27 is active + 0x1 + + + + + INT28 + Interrupt Request 28 + 28 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 28 is cleared + 0 + + + ACTIVE + The interrupt request for channel 28 is active + 0x1 + + + + + INT29 + Interrupt Request 29 + 29 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 29 is cleared + 0 + + + ACTIVE + The interrupt request for channel 29 is active + 0x1 + + + + + INT30 + Interrupt Request 30 + 30 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 30 is cleared + 0 + + + ACTIVE + The interrupt request for channel 30 is active + 0x1 + + + + + INT31 + Interrupt Request 31 + 31 + 1 + read-write + oneToClear + + + NOT_ACTIVE + The interrupt request for channel 31 is cleared + 0 + + + ACTIVE + The interrupt request for channel 31 is active + 0x1 + + + + + + + ERR + Error + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR0 + Error In Channel 0 + 0 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR1 + Error In Channel 1 + 1 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR2 + Error In Channel 2 + 2 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR3 + Error In Channel 3 + 3 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR4 + Error In Channel 4 + 4 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR5 + Error In Channel 5 + 5 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR6 + Error In Channel 6 + 6 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR7 + Error In Channel 7 + 7 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR8 + Error In Channel 8 + 8 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR9 + Error In Channel 9 + 9 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR10 + Error In Channel 10 + 10 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR11 + Error In Channel 11 + 11 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR12 + Error In Channel 12 + 12 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR13 + Error In Channel 13 + 13 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR14 + Error In Channel 14 + 14 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR15 + Error In Channel 15 + 15 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR16 + Error In Channel 16 + 16 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR17 + Error In Channel 17 + 17 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR18 + Error In Channel 18 + 18 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR19 + Error In Channel 19 + 19 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR20 + Error In Channel 20 + 20 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR21 + Error In Channel 21 + 21 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR22 + Error In Channel 22 + 22 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR23 + Error In Channel 23 + 23 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR24 + Error In Channel 24 + 24 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR25 + Error In Channel 25 + 25 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR26 + Error In Channel 26 + 26 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR27 + Error In Channel 27 + 27 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR28 + Error In Channel 28 + 28 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR29 + Error In Channel 29 + 29 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR30 + Error In Channel 30 + 30 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + ERR31 + Error In Channel 31 + 31 + 1 + read-write + oneToClear + + + NO_ERR + No error in this channel has occurred + 0 + + + ERR + An error in this channel has occurred + 0x1 + + + + + + + HRS + Hardware Request Status + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS0 + Hardware Request Status Channel 0 + 0 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 0 is not present + 0 + + + HWRQST + A hardware service request for channel 0 is present + 0x1 + + + + + HRS1 + Hardware Request Status Channel 1 + 1 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 1 is not present + 0 + + + HWRQST + A hardware service request for channel 1 is present + 0x1 + + + + + HRS2 + Hardware Request Status Channel 2 + 2 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 2 is not present + 0 + + + HWRQST + A hardware service request for channel 2 is present + 0x1 + + + + + HRS3 + Hardware Request Status Channel 3 + 3 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 3 is not present + 0 + + + HWRQST + A hardware service request for channel 3 is present + 0x1 + + + + + HRS4 + Hardware Request Status Channel 4 + 4 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 4 is not present + 0 + + + HWRQST + A hardware service request for channel 4 is present + 0x1 + + + + + HRS5 + Hardware Request Status Channel 5 + 5 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 5 is not present + 0 + + + HWRQST + A hardware service request for channel 5 is present + 0x1 + + + + + HRS6 + Hardware Request Status Channel 6 + 6 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 6 is not present + 0 + + + HWRQST + A hardware service request for channel 6 is present + 0x1 + + + + + HRS7 + Hardware Request Status Channel 7 + 7 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 7 is not present + 0 + + + HWRQST + A hardware service request for channel 7 is present + 0x1 + + + + + HRS8 + Hardware Request Status Channel 8 + 8 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 8 is not present + 0 + + + HWRQST + A hardware service request for channel 8 is present + 0x1 + + + + + HRS9 + Hardware Request Status Channel 9 + 9 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 9 is not present + 0 + + + HWRQST + A hardware service request for channel 9 is present + 0x1 + + + + + HRS10 + Hardware Request Status Channel 10 + 10 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 10 is not present + 0 + + + HWRQST + A hardware service request for channel 10 is present + 0x1 + + + + + HRS11 + Hardware Request Status Channel 11 + 11 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 11 is not present + 0 + + + HWRQST + A hardware service request for channel 11 is present + 0x1 + + + + + HRS12 + Hardware Request Status Channel 12 + 12 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 12 is not present + 0 + + + HWRQST + A hardware service request for channel 12 is present + 0x1 + + + + + HRS13 + Hardware Request Status Channel 13 + 13 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 13 is not present + 0 + + + HWRQST + A hardware service request for channel 13 is present + 0x1 + + + + + HRS14 + Hardware Request Status Channel 14 + 14 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 14 is not present + 0 + + + HWRQST + A hardware service request for channel 14 is present + 0x1 + + + + + HRS15 + Hardware Request Status Channel 15 + 15 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 15 is not present + 0 + + + HWRQST + A hardware service request for channel 15 is present + 0x1 + + + + + HRS16 + Hardware Request Status Channel 16 + 16 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 16 is not present + 0 + + + HWRQST + A hardware service request for channel 16 is present + 0x1 + + + + + HRS17 + Hardware Request Status Channel 17 + 17 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 17 is not present + 0 + + + HWRQST + A hardware service request for channel 17 is present + 0x1 + + + + + HRS18 + Hardware Request Status Channel 18 + 18 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 18 is not present + 0 + + + HWRQST + A hardware service request for channel 18 is present + 0x1 + + + + + HRS19 + Hardware Request Status Channel 19 + 19 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 19 is not present + 0 + + + HWRQST + A hardware service request for channel 19 is present + 0x1 + + + + + HRS20 + Hardware Request Status Channel 20 + 20 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 20 is not present + 0 + + + HWRQST + A hardware service request for channel 20 is present + 0x1 + + + + + HRS21 + Hardware Request Status Channel 21 + 21 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 21 is not present + 0 + + + HWRQST + A hardware service request for channel 21 is present + 0x1 + + + + + HRS22 + Hardware Request Status Channel 22 + 22 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 22 is not present + 0 + + + HWRQST + A hardware service request for channel 22 is present + 0x1 + + + + + HRS23 + Hardware Request Status Channel 23 + 23 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 23 is not present + 0 + + + HWRQST + A hardware service request for channel 23 is present + 0x1 + + + + + HRS24 + Hardware Request Status Channel 24 + 24 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 24 is not present + 0 + + + HWRQST + A hardware service request for channel 24 is present + 0x1 + + + + + HRS25 + Hardware Request Status Channel 25 + 25 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 25 is not present + 0 + + + HWRQST + A hardware service request for channel 25 is present + 0x1 + + + + + HRS26 + Hardware Request Status Channel 26 + 26 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 26 is not present + 0 + + + HWRQST + A hardware service request for channel 26 is present + 0x1 + + + + + HRS27 + Hardware Request Status Channel 27 + 27 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 27 is not present + 0 + + + HWRQST + A hardware service request for channel 27 is present + 0x1 + + + + + HRS28 + Hardware Request Status Channel 28 + 28 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 28 is not present + 0 + + + HWRQST + A hardware service request for channel 28 is present + 0x1 + + + + + HRS29 + Hardware Request Status Channel 29 + 29 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 29 is not preset + 0 + + + HWRQST + A hardware service request for channel 29 is present + 0x1 + + + + + HRS30 + Hardware Request Status Channel 30 + 30 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 30 is not present + 0 + + + HWRQST + A hardware service request for channel 30 is present + 0x1 + + + + + HRS31 + Hardware Request Status Channel 31 + 31 + 1 + read-only + + + NO_HWRQST + A hardware service request for channel 31 is not present + 0 + + + HWRQST + A hardware service request for channel 31 is present + 0x1 + + + + + + + EARS + Enable Asynchronous Request in Stop + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDREQ_0 + Enable asynchronous DMA request in stop mode for channel 0. + 0 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 0 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 0 + 0x1 + + + + + EDREQ_1 + Enable asynchronous DMA request in stop mode for channel 1. + 1 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 1 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 1 + 0x1 + + + + + EDREQ_2 + Enable asynchronous DMA request in stop mode for channel 2. + 2 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 2 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 2 + 0x1 + + + + + EDREQ_3 + Enable asynchronous DMA request in stop mode for channel 3. + 3 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 3 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 3 + 0x1 + + + + + EDREQ_4 + Enable asynchronous DMA request in stop mode for channel 4. + 4 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 4 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 4 + 0x1 + + + + + EDREQ_5 + Enable asynchronous DMA request in stop mode for channel 5. + 5 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 5 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 5 + 0x1 + + + + + EDREQ_6 + Enable asynchronous DMA request in stop mode for channel 6. + 6 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 6 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 6 + 0x1 + + + + + EDREQ_7 + Enable asynchronous DMA request in stop mode for channel 7. + 7 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 7 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 7 + 0x1 + + + + + EDREQ_8 + Enable asynchronous DMA request in stop mode for channel 8. + 8 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 8 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 8 + 0x1 + + + + + EDREQ_9 + Enable asynchronous DMA request in stop mode for channel 9. + 9 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 9 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 9 + 0x1 + + + + + EDREQ_10 + Enable asynchronous DMA request in stop mode for channel 10. + 10 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 10 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 10 + 0x1 + + + + + EDREQ_11 + Enable asynchronous DMA request in stop mode for channel 11. + 11 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 11 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 11 + 0x1 + + + + + EDREQ_12 + Enable asynchronous DMA request in stop mode for channel 12. + 12 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 12 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 12 + 0x1 + + + + + EDREQ_13 + Enable asynchronous DMA request in stop mode for channel 13. + 13 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 13 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 13 + 0x1 + + + + + EDREQ_14 + Enable asynchronous DMA request in stop mode for channel 14. + 14 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 14 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 14 + 0x1 + + + + + EDREQ_15 + Enable asynchronous DMA request in stop mode for channel 15. + 15 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 15 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 15 + 0x1 + + + + + EDREQ_16 + Enable asynchronous DMA request in stop mode for channel 16. + 16 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 16 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 16 + 0x1 + + + + + EDREQ_17 + Enable asynchronous DMA request in stop mode for channel 17. + 17 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 17 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 17 + 0x1 + + + + + EDREQ_18 + Enable asynchronous DMA request in stop mode for channel 18. + 18 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 18 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 18 + 0x1 + + + + + EDREQ_19 + Enable asynchronous DMA request in stop mode for channel 19. + 19 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 19 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 19 + 0x1 + + + + + EDREQ_20 + Enable asynchronous DMA request in stop mode for channel 20. + 20 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 20 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 20 + 0x1 + + + + + EDREQ_21 + Enable asynchronous DMA request in stop mode for channel 21. + 21 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 21 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 21 + 0x1 + + + + + EDREQ_22 + Enable asynchronous DMA request in stop mode for channel 22. + 22 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 22 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 22 + 0x1 + + + + + EDREQ_23 + Enable asynchronous DMA request in stop mode for channel 23. + 23 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 23 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 23 + 0x1 + + + + + EDREQ_24 + Enable asynchronous DMA request in stop mode for channel 24. + 24 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 24 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 24 + 0x1 + + + + + EDREQ_25 + Enable asynchronous DMA request in stop mode for channel 25. + 25 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 25 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 25 + 0x1 + + + + + EDREQ_26 + Enable asynchronous DMA request in stop mode for channel 26. + 26 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 26 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 26 + 0x1 + + + + + EDREQ_27 + Enable asynchronous DMA request in stop mode for channel 27. + 27 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 27 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 27 + 0x1 + + + + + EDREQ_28 + Enable asynchronous DMA request in stop mode for channel 28. + 28 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 28 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 28 + 0x1 + + + + + EDREQ_29 + Enable asynchronous DMA request in stop mode for channel 29. + 29 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 29 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 29 + 0x1 + + + + + EDREQ_30 + Enable asynchronous DMA request in stop mode for channel 30. + 30 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 30 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 30 + 0x1 + + + + + EDREQ_31 + Enable asynchronous DMA request in stop mode for channel 31. + 31 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for channel 31 + 0 + + + ENABLE + Enable asynchronous DMA request for channel 31 + 0x1 + + + + + + + DCHPRI3 + Channel Priority + 0x100 + 8 + read-write + 0x3 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI2 + Channel Priority + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI1 + Channel Priority + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI0 + Channel Priority + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI7 + Channel Priority + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI6 + Channel Priority + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI5 + Channel Priority + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI4 + Channel Priority + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI11 + Channel Priority + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI10 + Channel Priority + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI9 + Channel Priority + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI8 + Channel Priority + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI15 + Channel Priority + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI14 + Channel Priority + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI13 + Channel Priority + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI12 + Channel Priority + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI19 + Channel Priority + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI18 + Channel Priority + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI17 + Channel Priority + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI16 + Channel Priority + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI23 + Channel Priority + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI22 + Channel Priority + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI21 + Channel Priority + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI20 + Channel Priority + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI27 + Channel Priority + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI26 + Channel Priority + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI25 + Channel Priority + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI24 + Channel Priority + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI31 + Channel Priority + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI30 + Channel Priority + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI29 + Channel Priority + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + DCHPRI28 + Channel Priority + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + ENABLED + Channel n can suspend a lower priority channel + 0 + + + DISABLED + Channel n cannot suspend any channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + DISABLED + Channel n cannot be suspended by a higher priority channel's service request + 0 + + + ENABLED + Channel n can be temporarily suspended by the service request of a higher priority channel + 0x1 + + + + + + + TCD0_SADDR + TCD Source Address + 0x1000 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD0_SOFF + TCD Signed Source Address Offset + 0x1004 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD0_ATTR + TCD Transfer Attributes + 0x1006 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD0_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD0_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_SLAST + TCD Last Source Address Adjustment + 0x100C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD0_DADDR + TCD Destination Address + 0x1010 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD0_DOFF + TCD Signed Destination Address Offset + 0x1014 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD0_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1018 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD0_CSR + TCD Control and Status + 0x101C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD0_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_SADDR + TCD Source Address + 0x1020 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD1_SOFF + TCD Signed Source Address Offset + 0x1024 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD1_ATTR + TCD Transfer Attributes + 0x1026 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD1_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD1_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_SLAST + TCD Last Source Address Adjustment + 0x102C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD1_DADDR + TCD Destination Address + 0x1030 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD1_DOFF + TCD Signed Destination Address Offset + 0x1034 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD1_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1038 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD1_CSR + TCD Control and Status + 0x103C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD1_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_SADDR + TCD Source Address + 0x1040 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD2_SOFF + TCD Signed Source Address Offset + 0x1044 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD2_ATTR + TCD Transfer Attributes + 0x1046 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD2_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD2_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_SLAST + TCD Last Source Address Adjustment + 0x104C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD2_DADDR + TCD Destination Address + 0x1050 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD2_DOFF + TCD Signed Destination Address Offset + 0x1054 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD2_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1058 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD2_CSR + TCD Control and Status + 0x105C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD2_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_SADDR + TCD Source Address + 0x1060 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD3_SOFF + TCD Signed Source Address Offset + 0x1064 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD3_ATTR + TCD Transfer Attributes + 0x1066 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD3_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD3_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_SLAST + TCD Last Source Address Adjustment + 0x106C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD3_DADDR + TCD Destination Address + 0x1070 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD3_DOFF + TCD Signed Destination Address Offset + 0x1074 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD3_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1078 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD3_CSR + TCD Control and Status + 0x107C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD3_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_SADDR + TCD Source Address + 0x1080 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD4_SOFF + TCD Signed Source Address Offset + 0x1084 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD4_ATTR + TCD Transfer Attributes + 0x1086 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD4_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD4_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_SLAST + TCD Last Source Address Adjustment + 0x108C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD4_DADDR + TCD Destination Address + 0x1090 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD4_DOFF + TCD Signed Destination Address Offset + 0x1094 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD4_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1098 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD4_CSR + TCD Control and Status + 0x109C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD4_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_SADDR + TCD Source Address + 0x10A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD5_SOFF + TCD Signed Source Address Offset + 0x10A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD5_ATTR + TCD Transfer Attributes + 0x10A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD5_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD5_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_SLAST + TCD Last Source Address Adjustment + 0x10AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD5_DADDR + TCD Destination Address + 0x10B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD5_DOFF + TCD Signed Destination Address Offset + 0x10B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD5_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD5_CSR + TCD Control and Status + 0x10BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD5_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_SADDR + TCD Source Address + 0x10C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD6_SOFF + TCD Signed Source Address Offset + 0x10C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD6_ATTR + TCD Transfer Attributes + 0x10C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD6_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD6_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_SLAST + TCD Last Source Address Adjustment + 0x10CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD6_DADDR + TCD Destination Address + 0x10D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD6_DOFF + TCD Signed Destination Address Offset + 0x10D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD6_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD6_CSR + TCD Control and Status + 0x10DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD6_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_SADDR + TCD Source Address + 0x10E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD7_SOFF + TCD Signed Source Address Offset + 0x10E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD7_ATTR + TCD Transfer Attributes + 0x10E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD7_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD7_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_SLAST + TCD Last Source Address Adjustment + 0x10EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD7_DADDR + TCD Destination Address + 0x10F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD7_DOFF + TCD Signed Destination Address Offset + 0x10F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD7_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD7_CSR + TCD Control and Status + 0x10FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD7_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_SADDR + TCD Source Address + 0x1100 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD8_SOFF + TCD Signed Source Address Offset + 0x1104 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD8_ATTR + TCD Transfer Attributes + 0x1106 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD8_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD8_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_SLAST + TCD Last Source Address Adjustment + 0x110C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD8_DADDR + TCD Destination Address + 0x1110 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD8_DOFF + TCD Signed Destination Address Offset + 0x1114 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD8_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1118 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD8_CSR + TCD Control and Status + 0x111C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD8_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_SADDR + TCD Source Address + 0x1120 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD9_SOFF + TCD Signed Source Address Offset + 0x1124 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD9_ATTR + TCD Transfer Attributes + 0x1126 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD9_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD9_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_SLAST + TCD Last Source Address Adjustment + 0x112C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD9_DADDR + TCD Destination Address + 0x1130 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD9_DOFF + TCD Signed Destination Address Offset + 0x1134 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD9_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1138 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD9_CSR + TCD Control and Status + 0x113C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD9_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_SADDR + TCD Source Address + 0x1140 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD10_SOFF + TCD Signed Source Address Offset + 0x1144 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD10_ATTR + TCD Transfer Attributes + 0x1146 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD10_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD10_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_SLAST + TCD Last Source Address Adjustment + 0x114C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD10_DADDR + TCD Destination Address + 0x1150 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD10_DOFF + TCD Signed Destination Address Offset + 0x1154 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD10_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1158 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD10_CSR + TCD Control and Status + 0x115C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD10_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_SADDR + TCD Source Address + 0x1160 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD11_SOFF + TCD Signed Source Address Offset + 0x1164 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD11_ATTR + TCD Transfer Attributes + 0x1166 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD11_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD11_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_SLAST + TCD Last Source Address Adjustment + 0x116C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD11_DADDR + TCD Destination Address + 0x1170 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD11_DOFF + TCD Signed Destination Address Offset + 0x1174 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD11_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1178 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD11_CSR + TCD Control and Status + 0x117C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD11_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_SADDR + TCD Source Address + 0x1180 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD12_SOFF + TCD Signed Source Address Offset + 0x1184 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD12_ATTR + TCD Transfer Attributes + 0x1186 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD12_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD12_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_SLAST + TCD Last Source Address Adjustment + 0x118C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD12_DADDR + TCD Destination Address + 0x1190 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD12_DOFF + TCD Signed Destination Address Offset + 0x1194 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD12_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1198 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD12_CSR + TCD Control and Status + 0x119C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD12_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_SADDR + TCD Source Address + 0x11A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD13_SOFF + TCD Signed Source Address Offset + 0x11A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD13_ATTR + TCD Transfer Attributes + 0x11A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD13_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD13_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_SLAST + TCD Last Source Address Adjustment + 0x11AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD13_DADDR + TCD Destination Address + 0x11B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD13_DOFF + TCD Signed Destination Address Offset + 0x11B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD13_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD13_CSR + TCD Control and Status + 0x11BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD13_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_SADDR + TCD Source Address + 0x11C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD14_SOFF + TCD Signed Source Address Offset + 0x11C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD14_ATTR + TCD Transfer Attributes + 0x11C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD14_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD14_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_SLAST + TCD Last Source Address Adjustment + 0x11CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD14_DADDR + TCD Destination Address + 0x11D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD14_DOFF + TCD Signed Destination Address Offset + 0x11D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD14_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD14_CSR + TCD Control and Status + 0x11DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD14_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_SADDR + TCD Source Address + 0x11E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD15_SOFF + TCD Signed Source Address Offset + 0x11E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD15_ATTR + TCD Transfer Attributes + 0x11E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD15_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD15_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_SLAST + TCD Last Source Address Adjustment + 0x11EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD15_DADDR + TCD Destination Address + 0x11F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD15_DOFF + TCD Signed Destination Address Offset + 0x11F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD15_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD15_CSR + TCD Control and Status + 0x11FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD15_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_SADDR + TCD Source Address + 0x1200 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD16_SOFF + TCD Signed Source Address Offset + 0x1204 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD16_ATTR + TCD Transfer Attributes + 0x1206 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD16_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD16_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_SLAST + TCD Last Source Address Adjustment + 0x120C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD16_DADDR + TCD Destination Address + 0x1210 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD16_DOFF + TCD Signed Destination Address Offset + 0x1214 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD16_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1218 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD16_CSR + TCD Control and Status + 0x121C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD16_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_SADDR + TCD Source Address + 0x1220 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD17_SOFF + TCD Signed Source Address Offset + 0x1224 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD17_ATTR + TCD Transfer Attributes + 0x1226 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD17_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD17_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_SLAST + TCD Last Source Address Adjustment + 0x122C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD17_DADDR + TCD Destination Address + 0x1230 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD17_DOFF + TCD Signed Destination Address Offset + 0x1234 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD17_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1238 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD17_CSR + TCD Control and Status + 0x123C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD17_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_SADDR + TCD Source Address + 0x1240 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD18_SOFF + TCD Signed Source Address Offset + 0x1244 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD18_ATTR + TCD Transfer Attributes + 0x1246 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD18_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD18_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_SLAST + TCD Last Source Address Adjustment + 0x124C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD18_DADDR + TCD Destination Address + 0x1250 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD18_DOFF + TCD Signed Destination Address Offset + 0x1254 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD18_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1258 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD18_CSR + TCD Control and Status + 0x125C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD18_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_SADDR + TCD Source Address + 0x1260 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD19_SOFF + TCD Signed Source Address Offset + 0x1264 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD19_ATTR + TCD Transfer Attributes + 0x1266 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD19_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD19_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_SLAST + TCD Last Source Address Adjustment + 0x126C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD19_DADDR + TCD Destination Address + 0x1270 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD19_DOFF + TCD Signed Destination Address Offset + 0x1274 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD19_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1278 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD19_CSR + TCD Control and Status + 0x127C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD19_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_SADDR + TCD Source Address + 0x1280 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD20_SOFF + TCD Signed Source Address Offset + 0x1284 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD20_ATTR + TCD Transfer Attributes + 0x1286 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD20_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD20_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_SLAST + TCD Last Source Address Adjustment + 0x128C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD20_DADDR + TCD Destination Address + 0x1290 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD20_DOFF + TCD Signed Destination Address Offset + 0x1294 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD20_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1298 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD20_CSR + TCD Control and Status + 0x129C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD20_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_SADDR + TCD Source Address + 0x12A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD21_SOFF + TCD Signed Source Address Offset + 0x12A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD21_ATTR + TCD Transfer Attributes + 0x12A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD21_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD21_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_SLAST + TCD Last Source Address Adjustment + 0x12AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD21_DADDR + TCD Destination Address + 0x12B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD21_DOFF + TCD Signed Destination Address Offset + 0x12B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD21_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD21_CSR + TCD Control and Status + 0x12BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD21_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_SADDR + TCD Source Address + 0x12C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD22_SOFF + TCD Signed Source Address Offset + 0x12C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD22_ATTR + TCD Transfer Attributes + 0x12C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD22_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD22_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_SLAST + TCD Last Source Address Adjustment + 0x12CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD22_DADDR + TCD Destination Address + 0x12D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD22_DOFF + TCD Signed Destination Address Offset + 0x12D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD22_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD22_CSR + TCD Control and Status + 0x12DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD22_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_SADDR + TCD Source Address + 0x12E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD23_SOFF + TCD Signed Source Address Offset + 0x12E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD23_ATTR + TCD Transfer Attributes + 0x12E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD23_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD23_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_SLAST + TCD Last Source Address Adjustment + 0x12EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD23_DADDR + TCD Destination Address + 0x12F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD23_DOFF + TCD Signed Destination Address Offset + 0x12F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD23_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD23_CSR + TCD Control and Status + 0x12FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD23_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_SADDR + TCD Source Address + 0x1300 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD24_SOFF + TCD Signed Source Address Offset + 0x1304 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD24_ATTR + TCD Transfer Attributes + 0x1306 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD24_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD24_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_SLAST + TCD Last Source Address Adjustment + 0x130C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD24_DADDR + TCD Destination Address + 0x1310 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD24_DOFF + TCD Signed Destination Address Offset + 0x1314 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD24_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1318 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD24_CSR + TCD Control and Status + 0x131C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD24_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_SADDR + TCD Source Address + 0x1320 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD25_SOFF + TCD Signed Source Address Offset + 0x1324 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD25_ATTR + TCD Transfer Attributes + 0x1326 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD25_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD25_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_SLAST + TCD Last Source Address Adjustment + 0x132C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD25_DADDR + TCD Destination Address + 0x1330 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD25_DOFF + TCD Signed Destination Address Offset + 0x1334 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD25_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1338 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD25_CSR + TCD Control and Status + 0x133C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD25_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_SADDR + TCD Source Address + 0x1340 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD26_SOFF + TCD Signed Source Address Offset + 0x1344 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD26_ATTR + TCD Transfer Attributes + 0x1346 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD26_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD26_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_SLAST + TCD Last Source Address Adjustment + 0x134C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD26_DADDR + TCD Destination Address + 0x1350 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD26_DOFF + TCD Signed Destination Address Offset + 0x1354 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD26_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1358 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD26_CSR + TCD Control and Status + 0x135C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD26_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_SADDR + TCD Source Address + 0x1360 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD27_SOFF + TCD Signed Source Address Offset + 0x1364 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD27_ATTR + TCD Transfer Attributes + 0x1366 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD27_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD27_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_SLAST + TCD Last Source Address Adjustment + 0x136C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD27_DADDR + TCD Destination Address + 0x1370 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD27_DOFF + TCD Signed Destination Address Offset + 0x1374 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD27_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1378 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD27_CSR + TCD Control and Status + 0x137C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD27_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_SADDR + TCD Source Address + 0x1380 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD28_SOFF + TCD Signed Source Address Offset + 0x1384 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD28_ATTR + TCD Transfer Attributes + 0x1386 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD28_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD28_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_SLAST + TCD Last Source Address Adjustment + 0x138C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD28_DADDR + TCD Destination Address + 0x1390 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD28_DOFF + TCD Signed Destination Address Offset + 0x1394 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD28_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1398 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD28_CSR + TCD Control and Status + 0x139C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD28_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_SADDR + TCD Source Address + 0x13A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD29_SOFF + TCD Signed Source Address Offset + 0x13A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD29_ATTR + TCD Transfer Attributes + 0x13A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD29_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD29_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_SLAST + TCD Last Source Address Adjustment + 0x13AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD29_DADDR + TCD Destination Address + 0x13B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD29_DOFF + TCD Signed Destination Address Offset + 0x13B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD29_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD29_CSR + TCD Control and Status + 0x13BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD29_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_SADDR + TCD Source Address + 0x13C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD30_SOFF + TCD Signed Source Address Offset + 0x13C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD30_ATTR + TCD Transfer Attributes + 0x13C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD30_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD30_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_SLAST + TCD Last Source Address Adjustment + 0x13CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD30_DADDR + TCD Destination Address + 0x13D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD30_DOFF + TCD Signed Destination Address Offset + 0x13D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD30_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD30_CSR + TCD Control and Status + 0x13DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD30_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_SADDR + TCD Source Address + 0x13E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD31_SOFF + TCD Signed Source Address Offset + 0x13E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD31_ATTR + TCD Transfer Attributes + 0x13E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + EIGHT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR + 64-bit + 0x3 + + + THIRTYTWO_BYTE + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLED + Source address modulo feature is disabled + 0 + + + ENABLED + Value defines address range used to set up circular data queue + 0x1 + + + ENABLED + Value defines address range used to set up circular data queue + 0x2 + + + ENABLED + Value defines address range used to set up circular data queue + 0x3 + + + ENABLED + Value defines address range used to set up circular data queue + 0x4 + + + ENABLED + Value defines address range used to set up circular data queue + 0x5 + + + ENABLED + Value defines address range used to set up circular data queue + 0x6 + + + ENABLED + Value defines address range used to set up circular data queue + 0x7 + + + ENABLED + Value defines address range used to set up circular data queue + 0x8 + + + ENABLED + Value defines address range used to set up circular data queue + 0x9 + + + + + + + TCD31_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD31_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the DADDR + 0 + + + ENABLED + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + DISABLED + The minor loop offset is not applied to the SADDR + 0 + + + ENABLED + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_SLAST + TCD Last Source Address Adjustment + 0x13EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD31_DADDR + TCD Destination Address + 0x13F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD31_DOFF + TCD Signed Destination Address Offset + 0x13F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD31_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD31_CSR + TCD Control and Status + 0x13FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + NO_START + Channel is not explicitly started + 0 + + + START + Channel is explicitly started via a software initiated service request + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + DISABLED + End of major loop interrupt is disabled + 0 + + + ENABLED + End of major loop interrupt is enabled + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + DISABLED + Half-point interrupt is disabled + 0 + + + ENABLED + Half-point interrupt is enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + NO_CLEAR + The channel's ERQ field is not affected + 0 + + + CLEAR + The channel's ERQ field value changes to 0 when the major loop is complete + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL + The current channel's TCD is normal format + 0 + + + SCATTER + The current channel's TCD specifies a scatter gather format + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + DISABLED + No eDMA engine stalls + 0 + + + STALL4 + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + STALL8 + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD31_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + DISABLED + Channel-to-channel linking is disabled + 0 + + + ENABLED + Channel-to-channel linking is enabled + 0x1 + + + + + + + + + DMAMUX + DMA_CH_MUX + DMAMUX + 0x400EC000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + CHCFG[%s] + Channel index Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + DMA Channel Source (Slot Number) + 0 + 7 + read-write + + + A_ON + DMA Channel Always Enable + 29 + 1 + read-write + + + A_ON_0 + DMA Channel Always ON function is disabled + 0 + + + A_ON_1 + DMA Channel Always ON function is enabled + 0x1 + + + + + TRIG + DMA Channel Trigger Enable + 30 + 1 + read-write + + + TRIG_0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + 0 + + + TRIG_1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + 0x1 + + + + + ENBL + DMA Mux Channel Enable + 31 + 1 + read-write + + + ENBL_0 + DMA Mux channel is disabled + 0 + + + ENBL_1 + DMA Mux channel is enabled + 0x1 + + + + + + + + + GPC + GPC + GPC + GPC_ + 0x400F4000 + + 0 + 0x3C + registers + + + GPC + 97 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain (FlexRAM PDRAM1) power down request + 2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain (FlexRAM PDRAM1) power up request + 3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + PDRAM0_PGE + FlexRAM PDRAM0 Power Gate Enable + 22 + 1 + read-write + + + PDRAM0_PGE_0 + FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down. + 0 + + + PDRAM0_PGE_1 + FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down.. + 0x1 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[31:0] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + IMR5 + IRQ masking register 5 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR5 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR5 + IRQ status resister 5 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR5 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + PGC + PGC + GPC + PGC + PGC_ + 0x400F4000 + + 0 + 0x2B0 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x224 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) to switch on power + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b) to switch on power, the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x228 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) to switch off power + 8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x2A4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) to switch on power + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b) to switch on power, the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x2A8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) to switch off power + 8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + SRC + SRC + SRC + SRC_ + 0x400F8000 + + 0 + 0x48 + registers + + + SRC + 98 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0xA0480520 + 0xFFFFFFFF + + + mask_wdog_rst + Mask wdog_rst_b source + 7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + core0_rst + Software reset for core0 only + 13 + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 17 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 25 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 28 + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 16 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 24 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + lockup_sysresetreq + Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the Arm core + 1 + 1 + read-write + oneToClear + + + lockup_sysresetreq_0 + Reset is not a result of the mentioned case. + 0 + + + lockup_sysresetreq_1 + Reset is a result of the mentioned case. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input. + 2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of the mentioned case. + 0 + + + jtag_sw_rst_1 + Reset is a result of the mentioned case. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 24 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSIST_REDUNDANT_BOOT + This field identifies which image must be used - 0/1/2/3 + 26 + 2 + read-write + + + PERSIST_SECONDARY_BOOT + This bit identifies which image must be used - primary and secondary + 30 + 1 + read-write + + + + + + + CCM + CCM + CCM + CCM_ + 0x400FC000 + + 0 + 0x8C + registers + + + CCM_1 + 95 + + + CCM_2 + 96 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401107F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened. + 0 + 8 + read-write + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 12 + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 21 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 27 + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + CAMP2_READY + Status indication of CAMP2. + 3 + 1 + read-only + + + CAMP2_READY_0 + CAMP2 is not ready. + 0 + + + CAMP2_READY_1 + CAMP2 is ready. + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ARM_PODF + Divider for Arm clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0xA8300 + 0xFFFFFFFF + + + SEMC_CLK_SEL + SEMC clock source select + 6 + 1 + read-write + + + SEMC_CLK_SEL_0 + Periph_clk output will be used as SEMC clock root + 0 + + + SEMC_CLK_SEL_1 + SEMC alternative clock will be used as SEMC clock root + 0x1 + + + + + SEMC_ALT_CLK_SEL + SEMC alternative clock select + 7 + 1 + read-write + + + SEMC_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for SEMC root clock + 0 + + + SEMC_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for SEMC root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf. + 8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 10 + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + SEMC_PODF + Post divider for SEMC clock + 16 + 3 + read-write + + + SEMC_PODF_0 + divide by 1 + 0 + + + SEMC_PODF_1 + divide by 2 + 0x1 + + + SEMC_PODF_2 + divide by 3 + 0x2 + + + SEMC_PODF_3 + divide by 4 + 0x3 + + + SEMC_PODF_4 + divide by 5 + 0x4 + + + SEMC_PODF_5 + divide by 6 + 0x5 + + + SEMC_PODF_6 + divide by 7 + 0x6 + + + SEMC_PODF_7 + divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock + 25 + 1 + read-write + + + PERIPH_CLK_SEL_0 + derive clock from pre_periph_clk_sel + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk_divided + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 27 + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x2DAE8324 + 0xFFFFFFFF + + + LPSPI_CLK_SEL + Selector for lpspi clock multiplexer + 4 + 2 + read-write + + + LPSPI_CLK_SEL_0 + derive clock from PLL3 PFD1 clk + 0 + + + LPSPI_CLK_SEL_1 + derive clock from PLL3 PFD0 + 0x1 + + + LPSPI_CLK_SEL_2 + derive clock from PLL2 + 0x2 + + + LPSPI_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 12 + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk (pll1_ref_clk) + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + TRACE_CLK_SEL + Selector for Trace clock multiplexer + 14 + 2 + read-write + + + TRACE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + TRACE_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + TRACE_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + TRACE_CLK_SEL_3 + derive clock from PLL2 PFD1 + 0x3 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 18 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided PLL1 + 0x3 + + + + + LCDIF_PODF + Post-divider for LCDIF clock. + 23 + 3 + read-write + + + LCDIF_PODF_0 + divide by 1 + 0 + + + LCDIF_PODF_1 + divide by 2 + 0x1 + + + LCDIF_PODF_2 + divide by 3 + 0x2 + + + LCDIF_PODF_3 + divide by 4 + 0x3 + + + LCDIF_PODF_4 + divide by 5 + 0x4 + + + LCDIF_PODF_5 + divide by 6 + 0x5 + + + LCDIF_PODF_6 + divide by 7 + 0x6 + + + LCDIF_PODF_7 + divide by 8 + 0x7 + + + + + LPSPI_PODF + Divider for LPSPI. Divider should be updated when output clock is gated. + 26 + 3 + read-write + + + LPSPI_PODF_0 + divide by 1 + 0 + + + LPSPI_PODF_1 + divide by 2 + 0x1 + + + LPSPI_PODF_2 + divide by 3 + 0x2 + + + LPSPI_PODF_3 + divide by 4 + 0x3 + + + LPSPI_PODF_4 + divide by 5 + 0x4 + + + LPSPI_PODF_5 + divide by 6 + 0x5 + + + LPSPI_PODF_6 + divide by 7 + 0x6 + + + LPSPI_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900000 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 10 + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 12 + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3 clock multiplexer + 14 + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + USDHC1_CLK_SEL + Selector for usdhc1 clock multiplexer + 16 + 1 + read-write + + + USDHC1_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC1_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + USDHC2_CLK_SEL + Selector for usdhc2 clock multiplexer + 17 + 1 + read-write + + + USDHC2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC2_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + FLEXSPI_PODF + Divider for flexspi clock root. + 23 + 3 + read-write + + + FLEXSPI_PODF_0 + divide by 1 + 0 + + + FLEXSPI_PODF_1 + divide by 2 + 0x1 + + + FLEXSPI_PODF_2 + divide by 3 + 0x2 + + + FLEXSPI_PODF_3 + divide by 4 + 0x3 + + + FLEXSPI_PODF_4 + divide by 5 + 0x4 + + + FLEXSPI_PODF_5 + divide by 6 + 0x5 + + + FLEXSPI_PODF_6 + divide by 7 + 0x6 + + + FLEXSPI_PODF_7 + divide by 8 + 0x7 + + + + + FLEXSPI_CLK_SEL + Selector for flexspi clock multiplexer + 29 + 2 + read-write + + + FLEXSPI_CLK_SEL_0 + derive clock from semc_clk_root_pre + 0 + + + FLEXSPI_CLK_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + FLEXSPI_CLK_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + FLEXSPI_CLK_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x13192F06 + 0xFFFFFFFF + + + CAN_CLK_PODF + Divider for CAN clock podf. + 2 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + CAN_CLK_SEL + Selector for CAN clock multiplexer + 8 + 2 + read-write + + + CAN_CLK_SEL_0 + derive clock from pll3_sw_clk divided clock (60M) + 0 + + + CAN_CLK_SEL_1 + derive clock from osc_clk (24M) + 0x1 + + + CAN_CLK_SEL_2 + derive clock from pll3_sw_clk divided clock (80M) + 0x2 + + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + + + + + FLEXIO2_CLK_SEL + Selector for flexio2 clock multiplexer + 19 + 2 + read-write + + + FLEXIO2_CLK_SEL_0 + derive clock from PLL4 divided clock + 0 + + + FLEXIO2_CLK_SEL_1 + derive clock from PLL3 PFD2 clock + 0x1 + + + FLEXIO2_CLK_SEL_2 + derive clock from PLL5 clock + 0x2 + + + FLEXIO2_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x6490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + USDHC1_PODF + Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + USDHC1_PODF_0 + divide by 1 + 0 + + + USDHC1_PODF_1 + divide by 2 + 0x1 + + + USDHC1_PODF_2 + divide by 3 + 0x2 + + + USDHC1_PODF_3 + divide by 4 + 0x3 + + + USDHC1_PODF_4 + divide by 5 + 0x4 + + + USDHC1_PODF_5 + divide by 6 + 0x5 + + + USDHC1_PODF_6 + divide by 7 + 0x6 + + + USDHC1_PODF_7 + divide by 8 + 0x7 + + + + + USDHC2_PODF + Divider for usdhc2 clock. Divider should be updated when output clock is gated. + 16 + 3 + read-write + + + USDHC2_PODF_0 + divide by 1 + 0 + + + USDHC2_PODF_1 + divide by 2 + 0x1 + + + USDHC2_PODF_2 + divide by 3 + 0x2 + + + USDHC2_PODF_3 + divide by 4 + 0x3 + + + USDHC2_PODF_4 + divide by 5 + 0x4 + + + USDHC2_PODF_5 + divide by 6 + 0x5 + + + USDHC2_PODF_6 + divide by 7 + 0x6 + + + USDHC2_PODF_7 + divide by 8 + 0x7 + + + + + TRACE_PODF + Divider for trace clock. Divider should be updated when output clock is gated. + 25 + 2 + read-write + + + TRACE_PODF_0 + divide by 1 + 0 + + + TRACE_PODF_1 + divide by 2 + 0x1 + + + TRACE_PODF_2 + divide by 3 + 0x2 + + + TRACE_PODF_3 + divide by 4 + 0x3 + + + + + + + CS1CDR + CCM Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PRED + Divider for flexio2 clock. + 9 + 3 + read-write + + + FLEXIO2_CLK_PRED_0 + divide by 1 + 0 + + + FLEXIO2_CLK_PRED_1 + divide by 2 + 0x1 + + + FLEXIO2_CLK_PRED_2 + divide by 3 + 0x2 + + + FLEXIO2_CLK_PRED_3 + divide by 4 + 0x3 + + + FLEXIO2_CLK_PRED_4 + divide by 5 + 0x4 + + + FLEXIO2_CLK_PRED_5 + divide by 6 + 0x5 + + + FLEXIO2_CLK_PRED_6 + divide by 7 + 0x6 + + + FLEXIO2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 16 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3 clock pred. + 22 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PODF + Divider for flexio2 clock. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CS2CDR + CCM Clock Divider Register + 0x2C + 32 + read-write + 0x7336C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + FLEXIO1_CLK_SEL + Selector for flexio1 clock multiplexer + 7 + 2 + read-write + + + FLEXIO1_CLK_SEL_0 + derive clock from PLL4 + 0 + + + FLEXIO1_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + FLEXIO1_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + FLEXIO1_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + FLEXIO1_CLK_PODF + Divider for flexio1 clock podf. Divider should be updated when output clock is gated. + 9 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + FLEXIO1_CLK_PRED + Divider for flexio1 clock pred. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 20 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 22 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29150 + 0xFFFFFFFF + + + LCDIF_PRED + Pre-divider for lcdif clock. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + LCDIF_PRED_0 + divide by 1 + 0 + + + LCDIF_PRED_1 + divide by 2 + 0x1 + + + LCDIF_PRED_2 + divide by 3 + 0x2 + + + LCDIF_PRED_3 + divide by 4 + 0x3 + + + LCDIF_PRED_4 + divide by 5 + 0x4 + + + LCDIF_PRED_5 + divide by 6 + 0x5 + + + LCDIF_PRED_6 + divide by 7 + 0x6 + + + LCDIF_PRED_7 + divide by 8 + 0x7 + + + + + LCDIF_PRE_CLK_SEL + Selector for lcdif root clock pre-multiplexer + 15 + 3 + read-write + + + LCDIF_PRE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + LCDIF_PRE_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + LCDIF_PRE_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + LCDIF_PRE_CLK_SEL_3 + derive clock from PLL2 PFD0 + 0x3 + + + LCDIF_PRE_CLK_SEL_4 + derive clock from PLL2 PFD1 + 0x4 + + + LCDIF_PRE_CLK_SEL_5 + derive clock from PLL3 PFD1 + 0x5 + + + + + LPI2C_CLK_SEL + Selector for the LPI2C clock multiplexor + 18 + 1 + read-write + + + LPI2C_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + LPI2C_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + LPI2C_CLK_PODF + Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 19 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x30841 + 0xFFFFFFFF + + + CSI_CLK_SEL + Selector for csi_mclk multiplexer + 9 + 2 + read-write + + + CSI_CLK_SEL_0 + derive clock from osc_clk (24M) + 0 + + + CSI_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + CSI_CLK_SEL_2 + derive clock from pll3_120M + 0x2 + + + CSI_CLK_SEL_3 + derive clock from PLL3 PFD1 + 0x3 + + + + + CSI_PODF + Post divider for csi_mclk. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + CSI_PODF_0 + divide by 1 + 0 + + + CSI_PODF_1 + divide by 2 + 0x1 + + + CSI_PODF_2 + divide by 3 + 0x2 + + + CSI_PODF_3 + divide by 4 + 0x3 + + + CSI_PODF_4 + divide by 5 + 0x4 + + + CSI_PODF_5 + divide by 6 + 0x5 + + + CSI_PODF_6 + divide by 7 + 0x6 + + + CSI_PODF_7 + divide by 8 + 0x7 + + + + + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEMC_PODF_BUSY + Busy indicator for semc_podf. + 0 + 1 + read-only + + + SEMC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + SEMC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 16 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if Arm clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + Arm clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + Arm clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 11 + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_LPM_HS1 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 19 + 1 + read-write + + + BYPASS_LPM_HS0 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 21 + 1 + read-write + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 22 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 26 + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 27 + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + SEMC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of semc_podf + 17 + 1 + read-write + oneToClear + + + SEMC_PODF_LOADED_0 + interrupt is not generated due to frequency change of semc_podf + 0 + + + SEMC_PODF_LOADED_1 + interrupt generated due to frequency change of semc_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 19 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 20 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 22 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 26 + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_SEMC_PODF_LOADED + mask interrupt generation due to frequency change of semc_podf + 17 + 1 + read-write + + + MASK_SEMC_PODF_LOADED_0 + don't mask interrupt due to frequency change of semc_podf - interrupt will be created + 0 + + + MASK_SEMC_PODF_LOADED_1 + mask interrupt due to frequency change of semc_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 19 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 20 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 22 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 26 + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO1_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO1_SEL_0 + USB1 PLL clock (divided by 2) + 0 + + + CLKO1_SEL_1 + SYS PLL clock (divided by 2) + 0x1 + + + CLKO1_SEL_3 + VIDEO PLL clock (divided by 2) + 0x3 + + + CLKO1_SEL_5 + semc_clk_root + 0x5 + + + CLKO1_SEL_10 + lcdif_pix_clk_root + 0xA + + + CLKO1_SEL_11 + ahb_clk_root + 0xB + + + CLKO1_SEL_12 + ipg_clk_root + 0xC + + + CLKO1_SEL_13 + perclk_root + 0xD + + + CLKO1_SEL_14 + ckil_sync_clk_root + 0xE + + + CLKO1_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 16 + 5 + read-write + + + CLKO2_SEL_3 + usdhc1_clk_root + 0x3 + + + CLKO2_SEL_6 + lpi2c_clk_root + 0x6 + + + CLKO2_SEL_11 + csi_clk_root + 0xB + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_17 + usdhc2_clk_root + 0x11 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root + 0x14 + + + CLKO2_SEL_23 + can_clk_root + 0x17 + + + CLKO2_SEL_27 + flexspi_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 21 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 24 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 14 + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside Arm platform) DS mode when system STOP and PLL are disabled + 0x1 + + + SYS_MEM_DS_CTRL_2 + enable memory (outside Arm platform) DS mode when system is in STOP mode + #1x + + + + + FPL + Fast PLL enable. + 16 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the Arm Platform memories with additional control logic based on the Arm WFI signal + 17 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the Arm platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the Arm platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 2 + 2 + read-write + + + CG2 + mqs clock ( mqs_hmclk_clock_enable) + 4 + 2 + read-write + + + CG3 + Reserved + 6 + 2 + read-write + + + CG4 + sim_m or sim_main register access clock (sim_m_mainclk_r_enable) + 8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 10 + 2 + read-write + + + CG6 + lpuart3 clock (lpuart3_clk_enable) + 12 + 2 + read-write + + + CG7 + can1 clock (can1_clk_enable) + 14 + 2 + read-write + + + CG8 + can1_serial clock (can1_serial_clk_enable) + 16 + 2 + read-write + + + CG9 + can2 clock (can2_clk_enable) + 18 + 2 + read-write + + + CG10 + can2_serial clock (can2_serial_clk_enable) + 20 + 2 + read-write + + + CG11 + trace clock (trace_clk_enable) + 22 + 2 + read-write + + + CG12 + gpt2 bus clocks (gpt2_bus_clk_enable) + 24 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 26 + 2 + read-write + + + CG14 + lpuart2 clock (lpuart2_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 30 + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + lpspi1 clocks (lpspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + lpspi2 clocks (lpspi2_clk_enable) + 2 + 2 + read-write + + + CG2 + lpspi3 clocks (lpspi3_clk_enable) + 4 + 2 + read-write + + + CG3 + lpspi4 clocks (lpspi4_clk_enable) + 6 + 2 + read-write + + + CG4 + adc2 clock (adc2_clk_enable) + 8 + 2 + read-write + + + CG5 + enet clock (enet_clk_enable) + 10 + 2 + read-write + + + CG6 + pit clocks (pit_clk_enable) + 12 + 2 + read-write + + + CG7 + aoi2 clocks (aoi2_clk_enable) + 14 + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 16 + 2 + read-write + + + CG9 + semc_exsc clock (semc_exsc_clk_enable) + 18 + 2 + read-write + + + CG10 + gpt1 bus clock (gpt_clk_enable) + 20 + 2 + read-write + + + CG11 + gpt1 serial clock (gpt_serial_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart4 clock (lpuart4_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 26 + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio5 clock (gpio5_clk_enable) + 30 + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + ocram_exsc clock (ocram_exsc_clk_enable) + 0 + 2 + read-write + + + CG1 + csi clock (csi_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 4 + 2 + read-write + + + CG3 + lpi2c1 clock (lpi2c1_clk_enable) + 6 + 2 + read-write + + + CG4 + lpi2c2 clock (lpi2c2_clk_enable) + 8 + 2 + read-write + + + CG5 + lpi2c3 clock (lpi2c3_clk_enable) + 10 + 2 + read-write + + + CG6 + OCOTP_CTRL clock (ocotp_clk_enable) + 12 + 2 + read-write + + + CG7 + xbar3 clock (xbar3_clk_enable) + 14 + 2 + read-write + + + CG8 + ipmux1 clock (ipmux1_clk_enable) + 16 + 2 + read-write + + + CG9 + ipmux2 clock (ipmux2_clk_enable) + 18 + 2 + read-write + + + CG10 + ipmux3 clock (ipmux3_clk_enable) + 20 + 2 + read-write + + + CG11 + xbar1 clock (xbar1_clk_enable) + 22 + 2 + read-write + + + CG12 + xbar2 clock (xbar2_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 26 + 2 + read-write + + + CG14 + lcd clocks (lcd_clk_enable) + 28 + 2 + read-write + + + CG15 + pxp clocks (pxp_clk_enable) + 30 + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFCF + 0xFFFFFFFF + + + CG0 + flexio2 clocks (flexio2_clk_enable) + 0 + 2 + read-write + + + CG1 + lpuart5 clock (lpuart5_clk_enable) + 2 + 2 + read-write + + + CG2 + semc clocks (semc_clk_enable) + 4 + 2 + read-write + + + CG3 + lpuart6 clock (lpuart6_clk_enable) + 6 + 2 + read-write + + + CG4 + aoi1 clock (aoi1_clk_enable) + 8 + 2 + read-write + + + CG5 + lcdif pix clock (lcdif_pix_clk_enable) + 10 + 2 + read-write + + + CG6 + gpio4 clock (gpio4_clk_enable) + 12 + 2 + read-write + + + CG7 + ewm clocks (ewm_clk_enable) + 14 + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 16 + 2 + read-write + + + CG9 + flexram clock (flexram_clk_enable) + 18 + 2 + read-write + + + CG10 + acmp1 clocks (acmp1_clk_enable) + 20 + 2 + read-write + + + CG11 + acmp2 clocks (acmp2_clk_enable) + 22 + 2 + read-write + + + CG12 + acmp3 clocks (acmp3_clk_enable) + 24 + 2 + read-write + + + CG13 + acmp4 clocks (acmp4_clk_enable) + 26 + 2 + read-write + + + CG14 + The OCRAM clock cannot be turned off when the CM cache is running on this device. + 28 + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 30 + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + sim_m7 register access clock (sim_m7_mainclk_r_enable) + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 4 + 2 + read-write + + + CG3 + bee clock(bee_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m7 clock (sim_m7_clk_enable) + 8 + 2 + read-write + + + CG5 + tsc_dig clock (tsc_clk_enable) + 10 + 2 + read-write + + + CG6 + sim_m clocks (sim_m_clk_enable) + 12 + 2 + read-write + + + CG7 + sim_ems clocks (sim_ems_clk_enable) + 14 + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 16 + 2 + read-write + + + CG9 + pwm2 clocks (pwm2_clk_enable) + 18 + 2 + read-write + + + CG10 + pwm3 clocks (pwm3_clk_enable) + 20 + 2 + read-write + + + CG11 + pwm4 clocks (pwm4_clk_enable) + 22 + 2 + read-write + + + CG12 + enc1 clocks (enc1_clk_enable) + 24 + 2 + read-write + + + CG13 + enc2 clocks (enc2_clk_enable) + 26 + 2 + read-write + + + CG14 + enc3 clocks (enc3_clk_enable) + 28 + 2 + read-write + + + CG15 + enc4 clocks (enc4_clk_enable) + 30 + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + flexio1 clock (flexio1_clk_enable) + 2 + 2 + read-write + + + CG2 + wdog3 clock (wdog3_clk_enable) + 4 + 2 + read-write + + + CG3 + dma clock (dma_clk_enable) + 6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 10 + 2 + read-write + + + CG6 + aipstz4 clocks (aips_tz4_clk_enable) + 12 + 2 + read-write + + + CG7 + spdif clock (spdif_clk_enable) + 14 + 2 + read-write + + + CG8 + sim_main clock (sim_main_clk_enable) + 16 + 2 + read-write + + + CG9 + sai1 clock (sai1_clk_enable) + 18 + 2 + read-write + + + CG10 + sai2 clock (sai2_clk_enable) + 20 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart1 clock (lpuart1_clk_enable) + 24 + 2 + read-write + + + CG13 + lpuart7 clock (lpuart7_clk_enable) + 26 + 2 + read-write + + + CG14 + snvs_hp clock (snvs_hp_clk_enable) + 28 + 2 + read-write + + + CG15 + snvs_lp clock (snvs_lp_clk_enable) + 30 + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + usdhc1 clocks (usdhc1_clk_enable) + 2 + 2 + read-write + + + CG2 + usdhc2 clocks (usdhc2_clk_enable) + 4 + 2 + read-write + + + CG3 + dcdc clocks (dcdc_clk_enable) + 6 + 2 + read-write + + + CG4 + ipmux4 clock (ipmux4_clk_enable) + 8 + 2 + read-write + + + CG5 + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared + 10 + 2 + read-write + + + CG6 + trng clock (trng_clk_enable) + 12 + 2 + read-write + + + CG7 + lpuart8 clocks (lpuart8_clk_enable) + 14 + 2 + read-write + + + CG8 + timer4 clocks (timer4_clk_enable) + 16 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 18 + 2 + read-write + + + CG10 + sim_per clock (sim_per_clk_enable) + 20 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 22 + 2 + read-write + + + CG12 + lpi2c4 serial clock (lpi2c4_serial_clk_enable) + 24 + 2 + read-write + + + CG13 + timer1 clocks (timer1_clk_enable) + 26 + 2 + read-write + + + CG14 + timer2 clocks (timer2_clk_enable) + 28 + 2 + read-write + + + CG15 + timer3 clocks (timer3_clk_enable) + 30 + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_PIT + Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk' + 6 + 1 + read-write + + + MOD_EN_OV_PIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_PIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_USDHC + overide clock enable signal from USDHC. + 7 + 1 + read-write + + + MOD_EN_USDHC_0 + don't override module enable signal + 0 + + + MOD_EN_USDHC_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_TRNG + Overide clock enable signal from TRNG + 9 + 1 + read-write + + + MOD_EN_OV_TRNG_0 + don't override module enable signal + 0 + + + MOD_EN_OV_TRNG_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN2_CPI + Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 28 + 1 + read-write + + + MOD_EN_OV_CAN2_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CAN2_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN1_CPI + Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 30 + 1 + read-write + + + MOD_EN_OV_CAN1_CPI_0 + don't overide module enable signal + 0 + + + MOD_EN_OV_CAN1_CPI_1 + overide module enable signal + 0x1 + + + + + + + + + ROMC + ROMC + ROMC + ROMC_ + 0x40180000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 29 + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch + 0 + 1 + read-write + + + THUMBX_0 + Arm patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 17 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + LPUART1 + LPUART + LPUART + LPUART + 0x40184000 + + 0 + 0x30 + registers + + + LPUART1 + 20 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x4010003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + FEATURE_1 + Standard feature set. + 0x1 + + + FEATURE_3 + Standard feature set with MODEM/IrDA support. + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + GLOBAL + LPUART Global Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset. + 0 + + + RST_1 + Module is reset. + 0x1 + + + + + + + PINCFG + LPUART Pin Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRGSEL + Trigger Select + 0 + 2 + read-write + + + TRGSEL_0 + Input trigger is disabled. + 0 + + + TRGSEL_1 + Input trigger is used instead of RXD pin input. + 0x1 + + + TRGSEL_2 + Input trigger is used instead of CTS_B pin input. + 0x2 + + + TRGSEL_3 + Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + 0x3 + + + + + + + BAUD + LPUART Baud Rate Register + 0x10 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + SBNS_0 + One stop bit. + 0 + + + SBNS_1 + Two stop bits. + 0x1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + RXEDGIE_0 + Hardware interrupts from STAT[RXEDGIF] are disabled. + 0 + + + RXEDGIE_1 + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + 0x1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + LBKDIE_0 + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + 0 + + + LBKDIE_1 + Hardware interrupt requested when STAT[LBKDIF] flag is 1. + 0x1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + RESYNCDIS_0 + Resynchronization during received data word is supported + 0 + + + RESYNCDIS_1 + Resynchronization during received data word is disabled + 0x1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + BOTHEDGE_0 + Receiver samples input data using the rising edge of the baud rate clock. + 0 + + + BOTHEDGE_1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + 0x1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + MATCFG_0 + Address Match Wakeup + 0 + + + MATCFG_1 + Idle Match Wakeup + 0x1 + + + MATCFG_2 + Match On and Match Off + 0x2 + + + MATCFG_3 + Enables RWU on Data Match and Match On/Off for transmitter CTS input + 0x3 + + + + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + RIDMAE_0 + DMA request disabled. + 0 + + + RIDMAE_1 + DMA request enabled. + 0x1 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + RDMAE_0 + DMA request disabled. + 0 + + + RDMAE_1 + DMA request enabled. + 0x1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + TDMAE_0 + DMA request disabled. + 0 + + + TDMAE_1 + DMA request enabled. + 0x1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + OSR_0 + Writing 0 to this field results in an oversampling ratio of 16 + 0 + + + OSR_3 + Oversampling ratio of 4, requires BOTHEDGE to be set. + 0x3 + + + OSR_4 + Oversampling ratio of 5, requires BOTHEDGE to be set. + 0x4 + + + OSR_5 + Oversampling ratio of 6, requires BOTHEDGE to be set. + 0x5 + + + OSR_6 + Oversampling ratio of 7, requires BOTHEDGE to be set. + 0x6 + + + OSR_7 + Oversampling ratio of 8. + 0x7 + + + OSR_8 + Oversampling ratio of 9. + 0x8 + + + OSR_9 + Oversampling ratio of 10. + 0x9 + + + OSR_10 + Oversampling ratio of 11. + 0xA + + + OSR_11 + Oversampling ratio of 12. + 0xB + + + OSR_12 + Oversampling ratio of 13. + 0xC + + + OSR_13 + Oversampling ratio of 14. + 0xD + + + OSR_14 + Oversampling ratio of 15. + 0xE + + + OSR_15 + Oversampling ratio of 16. + 0xF + + + OSR_16 + Oversampling ratio of 17. + 0x10 + + + OSR_17 + Oversampling ratio of 18. + 0x11 + + + OSR_18 + Oversampling ratio of 19. + 0x12 + + + OSR_19 + Oversampling ratio of 20. + 0x13 + + + OSR_20 + Oversampling ratio of 21. + 0x14 + + + OSR_21 + Oversampling ratio of 22. + 0x15 + + + OSR_22 + Oversampling ratio of 23. + 0x16 + + + OSR_23 + Oversampling ratio of 24. + 0x17 + + + OSR_24 + Oversampling ratio of 25. + 0x18 + + + OSR_25 + Oversampling ratio of 26. + 0x19 + + + OSR_26 + Oversampling ratio of 27. + 0x1A + + + OSR_27 + Oversampling ratio of 28. + 0x1B + + + OSR_28 + Oversampling ratio of 29. + 0x1C + + + OSR_29 + Oversampling ratio of 30. + 0x1D + + + OSR_30 + Oversampling ratio of 31. + 0x1E + + + OSR_31 + Oversampling ratio of 32. + 0x1F + + + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + M10_0 + Receiver and transmitter use 7-bit to 9-bit data characters. + 0 + + + M10_1 + Receiver and transmitter use 10-bit data characters. + 0x1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + MAEN2_0 + Normal operation. + 0 + + + MAEN2_1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + 0x1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + MAEN1_0 + Normal operation. + 0 + + + MAEN1_1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + 0x1 + + + + + + + STAT + LPUART Status Register + 0x14 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + oneToClear + + + MA2F_0 + Received data is not equal to MA2 + 0 + + + MA2F_1 + Received data is equal to MA2 + 0x1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + oneToClear + + + MA1F_0 + Received data is not equal to MA1 + 0 + + + MA1F_1 + Received data is equal to MA1 + 0x1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + oneToClear + + + PF_0 + No parity error. + 0 + + + PF_1 + Parity error. + 0x1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + oneToClear + + + FE_0 + No framing error detected. This does not guarantee the framing is correct. + 0 + + + FE_1 + Framing error. + 0x1 + + + + + NF + Noise Flag + 18 + 1 + read-write + oneToClear + + + NF_0 + No noise detected. + 0 + + + NF_1 + Noise detected in the received character in the DATA register. + 0x1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + oneToClear + + + OR_0 + No overrun. + 0 + + + OR_1 + Receive overrun (new LPUART data lost). + 0x1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + oneToClear + + + IDLE_0 + No idle line detected. + 0 + + + IDLE_1 + Idle line was detected. + 0x1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + RDRF_0 + Receive data buffer empty. + 0 + + + RDRF_1 + Receive data buffer full. + 0x1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + TC_0 + Transmitter active (sending data, a preamble, or a break). + 0 + + + TC_1 + Transmitter idle (transmission activity complete). + 0x1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + TDRE_0 + Transmit data buffer full. + 0 + + + TDRE_1 + Transmit data buffer empty. + 0x1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + RAF_0 + LPUART receiver idle waiting for a start bit. + 0 + + + RAF_1 + LPUART receiver active (RXD input not idle). + 0x1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + LBKDE_0 + LIN break detect is disabled, normal break character can be detected. + 0 + + + LBKDE_1 + LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + 0x1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + BRK13_0 + Break character is transmitted with length of 9 to 13 bit times. + 0 + + + BRK13_1 + Break character is transmitted with length of 12 to 15 bit times. + 0x1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + RWUID_0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + 0 + + + RWUID_1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + 0x1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + RXINV_0 + Receive data not inverted. + 0 + + + RXINV_1 + Receive data inverted. + 0x1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + MSBF_0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + 0 + + + MSBF_1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + 0x1 + + + + + RXEDGIF + RXD Pin Active Edge Interrupt Flag + 30 + 1 + read-write + oneToClear + + + RXEDGIF_0 + No active edge on the receive pin has occurred. + 0 + + + RXEDGIF_1 + An active edge on the receive pin has occurred. + 0x1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + oneToClear + + + LBKDIF_0 + No LIN break character has been detected. + 0 + + + LBKDIF_1 + LIN break character has been detected. + 0x1 + + + + + + + CTRL + LPUART Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + PT_0 + Even parity. + 0 + + + PT_1 + Odd parity. + 0x1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + PE_0 + No hardware parity generation or checking. + 0 + + + PE_1 + Parity enabled. + 0x1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + ILT_0 + Idle character bit count starts after start bit. + 0 + + + ILT_1 + Idle character bit count starts after stop bit. + 0x1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + WAKE_0 + Configures RWU for idle-line wakeup. + 0 + + + WAKE_1 + Configures RWU with address-mark wakeup. + 0x1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + M_0 + Receiver and transmitter use 8-bit data characters. + 0 + + + M_1 + Receiver and transmitter use 9-bit data characters. + 0x1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + RSRC_0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + 0 + + + RSRC_1 + Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + 0x1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + DOZEEN_0 + LPUART is enabled in Doze mode. + 0 + + + DOZEEN_1 + LPUART is disabled in Doze mode. + 0x1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + LOOPS_0 + Normal operation - RXD and TXD use separate pins. + 0 + + + LOOPS_1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + 0x1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + IDLECFG_0 + 1 idle character + 0 + + + IDLECFG_1 + 2 idle characters + 0x1 + + + IDLECFG_2 + 4 idle characters + 0x2 + + + IDLECFG_3 + 8 idle characters + 0x3 + + + IDLECFG_4 + 16 idle characters + 0x4 + + + IDLECFG_5 + 32 idle characters + 0x5 + + + IDLECFG_6 + 64 idle characters + 0x6 + + + IDLECFG_7 + 128 idle characters + 0x7 + + + + + M7 + 7-Bit Mode Select + 11 + 1 + read-write + + + M7_0 + Receiver and transmitter use 8-bit to 10-bit data characters. + 0 + + + M7_1 + Receiver and transmitter use 7-bit data characters. + 0x1 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + MA2IE_0 + MA2F interrupt disabled + 0 + + + MA2IE_1 + MA2F interrupt enabled + 0x1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + MA1IE_0 + MA1F interrupt disabled + 0 + + + MA1IE_1 + MA1F interrupt enabled + 0x1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + SBK_0 + Normal transmitter operation. + 0 + + + SBK_1 + Queue break character(s) to be sent. + 0x1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + RWU_0 + Normal receiver operation. + 0 + + + RWU_1 + LPUART receiver in standby waiting for wakeup condition. + 0x1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + RE_0 + Receiver disabled. + 0 + + + RE_1 + Receiver enabled. + 0x1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + TE_0 + Transmitter disabled. + 0 + + + TE_1 + Transmitter enabled. + 0x1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + ILIE_0 + Hardware interrupts from IDLE disabled; use polling. + 0 + + + ILIE_1 + Hardware interrupt requested when IDLE flag is 1. + 0x1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + RIE_0 + Hardware interrupts from RDRF disabled; use polling. + 0 + + + RIE_1 + Hardware interrupt requested when RDRF flag is 1. + 0x1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + TCIE_0 + Hardware interrupts from TC disabled; use polling. + 0 + + + TCIE_1 + Hardware interrupt requested when TC flag is 1. + 0x1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + TIE_0 + Hardware interrupts from TDRE disabled; use polling. + 0 + + + TIE_1 + Hardware interrupt requested when TDRE flag is 1. + 0x1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + PEIE_0 + PF interrupts disabled; use polling). + 0 + + + PEIE_1 + Hardware interrupt requested when PF is set. + 0x1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + FEIE_0 + FE interrupts disabled; use polling. + 0 + + + FEIE_1 + Hardware interrupt requested when FE is set. + 0x1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + NEIE_0 + NF interrupts disabled; use polling. + 0 + + + NEIE_1 + Hardware interrupt requested when NF is set. + 0x1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + ORIE_0 + OR interrupts disabled; use polling. + 0 + + + ORIE_1 + Hardware interrupt requested when OR is set. + 0x1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + TXINV_0 + Transmit data not inverted. + 0 + + + TXINV_1 + Transmit data inverted. + 0x1 + + + + + TXDIR + TXD Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + TXDIR_0 + TXD pin is an input in single-wire mode. + 0 + + + TXDIR_1 + TXD pin is an output in single-wire mode. + 0x1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0x1C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + R0T0 + 0 + 1 + read-write + + + R1T1 + R1T1 + 1 + 1 + read-write + + + R2T2 + R2T2 + 2 + 1 + read-write + + + R3T3 + R3T3 + 3 + 1 + read-write + + + R4T4 + R4T4 + 4 + 1 + read-write + + + R5T5 + R5T5 + 5 + 1 + read-write + + + R6T6 + R6T6 + 6 + 1 + read-write + + + R7T7 + R7T7 + 7 + 1 + read-write + + + R8T8 + R8T8 + 8 + 1 + read-write + + + R9T9 + R9T9 + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + IDLINE_0 + Receiver was not idle before receiving this character. + 0 + + + IDLINE_1 + Receiver was idle before receiving this character. + 0x1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + RXEMPT_0 + Receive buffer contains valid data. + 0 + + + RXEMPT_1 + Receive buffer is empty, data returned on read is not valid. + 0x1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + FRETSC_0 + The dataword was received without a frame error on read, or transmit a normal character on write. + 0 + + + FRETSC_1 + The dataword was received with a frame error, or transmit an idle or break character on transmit. + 0x1 + + + + + PARITYE + PARITYE + 14 + 1 + read-only + + + PARITYE_0 + The dataword was received without a parity error. + 0 + + + PARITYE_1 + The dataword was received with a parity error. + 0x1 + + + + + NOISY + NOISY + 15 + 1 + read-only + + + NOISY_0 + The dataword was received without noise. + 0 + + + NOISY_1 + The data was received with noise. + 0x1 + + + + + + + MATCH + LPUART Match Address Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + TXCTSE_0 + CTS has no effect on the transmitter. + 0 + + + TXCTSE_1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + 0x1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + TXRTSE_0 + The transmitter has no effect on RTS. + 0 + + + TXRTSE_1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + 0x1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + TXRTSPOL_0 + Transmitter RTS is active low. + 0 + + + TXRTSPOL_1 + Transmitter RTS is active high. + 0x1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + RXRTSE_0 + The receiver has no effect on RTS. + 0 + + + RXRTSE_1 + RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + 0x1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + TXCTSC_0 + CTS input is sampled at the start of each character. + 0 + + + TXCTSC_1 + CTS input is sampled when the transmitter is idle. + 0x1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + TXCTSSRC_0 + CTS input is the CTS_B pin. + 0 + + + TXCTSSRC_1 + CTS input is the inverted Receiver Match result. + 0x1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 2 + read-write + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + TNP_0 + 1/OSR. + 0 + + + TNP_1 + 2/OSR. + 0x1 + + + TNP_2 + 3/OSR. + 0x2 + + + TNP_3 + 4/OSR. + 0x3 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + IREN_0 + IR disabled. + 0 + + + IREN_1 + IR enabled. + 0x1 + + + + + + + FIFO + LPUART FIFO Register + 0x28 + 32 + read-write + 0xC00011 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO Buffer Depth + 0 + 3 + read-only + + + RXFIFOSIZE_0 + Receive FIFO/Buffer depth = 1 dataword. + 0 + + + RXFIFOSIZE_1 + Receive FIFO/Buffer depth = 4 datawords. + 0x1 + + + RXFIFOSIZE_2 + Receive FIFO/Buffer depth = 8 datawords. + 0x2 + + + RXFIFOSIZE_3 + Receive FIFO/Buffer depth = 16 datawords. + 0x3 + + + RXFIFOSIZE_4 + Receive FIFO/Buffer depth = 32 datawords. + 0x4 + + + RXFIFOSIZE_5 + Receive FIFO/Buffer depth = 64 datawords. + 0x5 + + + RXFIFOSIZE_6 + Receive FIFO/Buffer depth = 128 datawords. + 0x6 + + + RXFIFOSIZE_7 + Receive FIFO/Buffer depth = 256 datawords. + 0x7 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + RXFE_0 + Receive FIFO is not enabled. Buffer is depth 1. + 0 + + + RXFE_1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + 0x1 + + + + + TXFIFOSIZE + Transmit FIFO Buffer Depth + 4 + 3 + read-only + + + TXFIFOSIZE_0 + Transmit FIFO/Buffer depth = 1 dataword. + 0 + + + TXFIFOSIZE_1 + Transmit FIFO/Buffer depth = 4 datawords. + 0x1 + + + TXFIFOSIZE_2 + Transmit FIFO/Buffer depth = 8 datawords. + 0x2 + + + TXFIFOSIZE_3 + Transmit FIFO/Buffer depth = 16 datawords. + 0x3 + + + TXFIFOSIZE_4 + Transmit FIFO/Buffer depth = 32 datawords. + 0x4 + + + TXFIFOSIZE_5 + Transmit FIFO/Buffer depth = 64 datawords. + 0x5 + + + TXFIFOSIZE_6 + Transmit FIFO/Buffer depth = 128 datawords. + 0x6 + + + TXFIFOSIZE_7 + Transmit FIFO/Buffer depth = 256 datawords + 0x7 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + TXFE_0 + Transmit FIFO is not enabled. Buffer is depth 1. + 0 + + + TXFE_1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + 0x1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + RXUFE_0 + RXUF flag does not generate an interrupt to the host. + 0 + + + RXUFE_1 + RXUF flag generates an interrupt to the host. + 0x1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + TXOFE_0 + TXOF flag does not generate an interrupt to the host. + 0 + + + TXOFE_1 + TXOF flag generates an interrupt to the host. + 0x1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + RXIDEN_0 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + 0 + + + RXIDEN_1 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + 0x1 + + + RXIDEN_2 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + 0x2 + + + RXIDEN_3 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + 0x3 + + + RXIDEN_4 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + 0x4 + + + RXIDEN_5 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + 0x5 + + + RXIDEN_6 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + 0x6 + + + RXIDEN_7 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + 0x7 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + read-write + + + RXFLUSH_0 + No flush operation occurs. + 0 + + + RXFLUSH_1 + All data in the receive FIFO/buffer is cleared out. + 0x1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + read-write + + + TXFLUSH_0 + No flush operation occurs. + 0 + + + TXFLUSH_1 + All data in the transmit FIFO/Buffer is cleared out. + 0x1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + oneToClear + + + RXUF_0 + No receive buffer underflow has occurred since the last time the flag was cleared. + 0 + + + RXUF_1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + oneToClear + + + TXOF_0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + 0 + + + TXOF_1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + RXEMPT_0 + Receive buffer is not empty. + 0 + + + RXEMPT_1 + Receive buffer is empty. + 0x1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + TXEMPT_0 + Transmit buffer is not empty. + 0 + + + TXEMPT_1 + Transmit buffer is empty. + 0x1 + + + + + + + WATER + LPUART Watermark Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 2 + read-write + + + TXCOUNT + Transmit Counter + 8 + 3 + read-only + + + RXWATER + Receive Watermark + 16 + 2 + read-write + + + RXCOUNT + Receive Counter + 24 + 3 + read-only + + + + + + + LPUART2 + LPUART + LPUART + 0x40188000 + + 0 + 0x30 + registers + + + LPUART2 + 21 + + + + LPUART3 + LPUART + LPUART + 0x4018C000 + + 0 + 0x30 + registers + + + LPUART3 + 22 + + + + LPUART4 + LPUART + LPUART + 0x40190000 + + 0 + 0x30 + registers + + + LPUART4 + 23 + + + + LPUART5 + LPUART + LPUART + 0x40194000 + + 0 + 0x30 + registers + + + LPUART5 + 24 + + + + LPUART6 + LPUART + LPUART + 0x40198000 + + 0 + 0x30 + registers + + + LPUART6 + 25 + + + + LPUART7 + LPUART + LPUART + 0x4019C000 + + 0 + 0x30 + registers + + + LPUART7 + 26 + + + + LPUART8 + LPUART + LPUART + 0x401A0000 + + 0 + 0x30 + registers + + + LPUART8 + 27 + + + + FLEXIO1 + FLEXIO + FLEXIO + 0x401AC000 + + 0 + 0x790 + registers + + + FLEXIO1 + 90 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard features implemented. + 0 + + + FEATURE_1 + Supports state, logic and parallel modes. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x2100404 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + FLEXEN_0 + FlexIO module is disabled. + 0 + + + FLEXEN_1 + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + SWRST_0 + Software reset is disabled + 0 + + + SWRST_1 + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + FASTACC_0 + Configures for normal register accesses to FlexIO + 0 + + + FASTACC_1 + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + DBGE_0 + FlexIO is disabled in debug modes. + 0 + + + DBGE_1 + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + DOZEN_0 + FlexIO enabled in Doze modes. + 0 + + + DOZEN_1 + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 16 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSF + Shifter Status Flag + 0 + 4 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEF + Shifter Error Flags + 0 + 4 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSF + Timer Status Flags + 0 + 4 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 4 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 4 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + 4 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + SMOD_0 + Disabled. + 0 + + + SMOD_1 + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + SMOD_2 + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + SMOD_4 + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + SMOD_5 + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + SMOD_6 + State mode. SHIFTBUF contents are used for storing programmable state attributes. + 0x6 + + + SMOD_7 + Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 4 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Shifter pin output disabled + 0 + + + PINCFG_1 + Shifter pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Shifter pin bidirectional output data + 0x2 + + + PINCFG_3 + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + TIMPOL_0 + Shift on posedge of Shift clock + 0 + + + TIMPOL_1 + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 2 + read-write + + + + + 4 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + SSTART_0 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + SSTART_1 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + SSTART_2 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + SSTART_3 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + SSTOP_0 + Stop bit disabled for transmitter/receiver/match store + 0 + + + SSTOP_2 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + 0x2 + + + SSTOP_3 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + INSRC_0 + Pin + 0 + + + INSRC_1 + Shifter N+1 Output + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 4 + read-write + + + + + 4 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 2 + read-write + + + TIMOD_0 + Timer Disabled. + 0 + + + TIMOD_1 + Dual 8-bit counters baud mode. + 0x1 + + + TIMOD_2 + Dual 8-bit counters PWM high mode. + 0x2 + + + TIMOD_3 + Single 16-bit counter mode. + 0x3 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 4 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Timer pin output disabled + 0 + + + PINCFG_1 + Timer pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Timer pin bidirectional output data + 0x2 + + + PINCFG_3 + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + TRGSRC_0 + External trigger selected + 0 + + + TRGSRC_1 + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + TRGPOL_0 + Trigger active high + 0 + + + TRGPOL_1 + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 5 + read-write + + + + + 4 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + TSTART_0 + Start bit disabled + 0 + + + TSTART_1 + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + TSTOP_0 + Stop bit disabled + 0 + + + TSTOP_1 + Stop bit is enabled on timer compare + 0x1 + + + TSTOP_2 + Stop bit is enabled on timer disable + 0x2 + + + TSTOP_3 + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + TIMENA_0 + Timer always enabled + 0 + + + TIMENA_1 + Timer enabled on Timer N-1 enable + 0x1 + + + TIMENA_2 + Timer enabled on Trigger high + 0x2 + + + TIMENA_3 + Timer enabled on Trigger high and Pin high + 0x3 + + + TIMENA_4 + Timer enabled on Pin rising edge + 0x4 + + + TIMENA_5 + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + TIMENA_6 + Timer enabled on Trigger rising edge + 0x6 + + + TIMENA_7 + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + TIMDIS_0 + Timer never disabled + 0 + + + TIMDIS_1 + Timer disabled on Timer N-1 disable + 0x1 + + + TIMDIS_2 + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + TIMDIS_3 + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + TIMDIS_4 + Timer disabled on Pin rising or falling edge + 0x4 + + + TIMDIS_5 + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + TIMDIS_6 + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + TIMRST_0 + Timer never reset + 0 + + + TIMRST_2 + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + TIMRST_3 + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + TIMRST_4 + Timer reset on Timer Pin rising edge + 0x4 + + + TIMRST_6 + Timer reset on Trigger rising edge + 0x6 + + + TIMRST_7 + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 2 + read-write + + + TIMDEC_0 + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + TIMDEC_1 + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + TIMDEC_2 + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + TIMDEC_3 + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + TIMOUT_0 + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + TIMOUT_1 + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + TIMOUT_2 + Timer output is logic one when enabled and on timer reset + 0x2 + + + TIMOUT_3 + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 4 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 4 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + + + FLEXIO2 + FLEXIO + FLEXIO + 0x401B0000 + + 0 + 0x790 + registers + + + FLEXIO2 + 91 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard features implemented. + 0 + + + FEATURE_1 + Supports state, logic and parallel modes. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x2200404 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + FLEXEN_0 + FlexIO module is disabled. + 0 + + + FLEXEN_1 + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + SWRST_0 + Software reset is disabled + 0 + + + SWRST_1 + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + FASTACC_0 + Configures for normal register accesses to FlexIO + 0 + + + FASTACC_1 + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + DBGE_0 + FlexIO is disabled in debug modes. + 0 + + + DBGE_1 + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + DOZEN_0 + FlexIO enabled in Doze modes. + 0 + + + DOZEN_1 + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 32 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSF + Shifter Status Flag + 0 + 4 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEF + Shifter Error Flags + 0 + 4 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSF + Timer Status Flags + 0 + 4 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 4 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 4 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + 4 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + SMOD_0 + Disabled. + 0 + + + SMOD_1 + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + SMOD_2 + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + SMOD_4 + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + SMOD_5 + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + SMOD_6 + State mode. SHIFTBUF contents are used for storing programmable state attributes. + 0x6 + + + SMOD_7 + Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 5 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Shifter pin output disabled + 0 + + + PINCFG_1 + Shifter pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Shifter pin bidirectional output data + 0x2 + + + PINCFG_3 + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + TIMPOL_0 + Shift on posedge of Shift clock + 0 + + + TIMPOL_1 + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 2 + read-write + + + + + 4 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + SSTART_0 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + SSTART_1 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + SSTART_2 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + SSTART_3 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + SSTOP_0 + Stop bit disabled for transmitter/receiver/match store + 0 + + + SSTOP_2 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + 0x2 + + + SSTOP_3 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + INSRC_0 + Pin + 0 + + + INSRC_1 + Shifter N+1 Output + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 5 + read-write + + + + + 4 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 2 + read-write + + + TIMOD_0 + Timer Disabled. + 0 + + + TIMOD_1 + Dual 8-bit counters baud mode. + 0x1 + + + TIMOD_2 + Dual 8-bit counters PWM high mode. + 0x2 + + + TIMOD_3 + Single 16-bit counter mode. + 0x3 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 5 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Timer pin output disabled + 0 + + + PINCFG_1 + Timer pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Timer pin bidirectional output data + 0x2 + + + PINCFG_3 + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + TRGSRC_0 + External trigger selected + 0 + + + TRGSRC_1 + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + TRGPOL_0 + Trigger active high + 0 + + + TRGPOL_1 + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 6 + read-write + + + + + 4 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + TSTART_0 + Start bit disabled + 0 + + + TSTART_1 + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + TSTOP_0 + Stop bit disabled + 0 + + + TSTOP_1 + Stop bit is enabled on timer compare + 0x1 + + + TSTOP_2 + Stop bit is enabled on timer disable + 0x2 + + + TSTOP_3 + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + TIMENA_0 + Timer always enabled + 0 + + + TIMENA_1 + Timer enabled on Timer N-1 enable + 0x1 + + + TIMENA_2 + Timer enabled on Trigger high + 0x2 + + + TIMENA_3 + Timer enabled on Trigger high and Pin high + 0x3 + + + TIMENA_4 + Timer enabled on Pin rising edge + 0x4 + + + TIMENA_5 + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + TIMENA_6 + Timer enabled on Trigger rising edge + 0x6 + + + TIMENA_7 + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + TIMDIS_0 + Timer never disabled + 0 + + + TIMDIS_1 + Timer disabled on Timer N-1 disable + 0x1 + + + TIMDIS_2 + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + TIMDIS_3 + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + TIMDIS_4 + Timer disabled on Pin rising or falling edge + 0x4 + + + TIMDIS_5 + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + TIMDIS_6 + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + TIMRST_0 + Timer never reset + 0 + + + TIMRST_2 + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + TIMRST_3 + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + TIMRST_4 + Timer reset on Timer Pin rising edge + 0x4 + + + TIMRST_6 + Timer reset on Trigger rising edge + 0x6 + + + TIMRST_7 + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 2 + read-write + + + TIMDEC_0 + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + TIMDEC_1 + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + TIMDEC_2 + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + TIMDEC_3 + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + TIMOUT_0 + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + TIMOUT_1 + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + TIMOUT_2 + Timer output is logic one when enabled and on timer reset + 0x2 + + + TIMOUT_3 + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 4 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 4 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + + + GPIO1 + GPIO + GPIO + GPIO + 0x401B8000 + + 0 + 0x90 + registers + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + DR + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GDIR + 0 + 32 + read-write + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + PSR + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + ICR0 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + ICR1 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + ICR2 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + ICR3 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + ICR4 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + ICR5 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + ICR6 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + ICR7 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + ICR8 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + ICR9 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + ICR10 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + ICR11 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + ICR12 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + ICR13 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + ICR14 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + ICR15 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + ICR16 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + ICR17 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + ICR18 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + ICR19 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + ICR20 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + ICR21 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + ICR22 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + ICR23 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + ICR24 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + ICR25 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + ICR26 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + ICR27 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + ICR28 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + ICR29 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + ICR30 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + ICR31 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + IMR + 0 + 32 + read-write + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + ISR + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + GPIO_EDGE_SEL + 0 + 32 + read-write + + + + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + + + + + GPIO5 + GPIO + GPIO + 0x400C0000 + + 0 + 0x90 + registers + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + + GPIO2 + GPIO + GPIO + 0x401BC000 + + 0 + 0x90 + registers + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + + GPIO3 + GPIO + GPIO + 0x401C0000 + + 0 + 0x90 + registers + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + + GPIO4 + GPIO + GPIO + 0x401C4000 + + 0 + 0x90 + registers + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + + CAN1 + FLEXCAN + CAN + FLEXCAN1_ + CAN + 0x401D0000 + + 0 + 0x9E4 + registers + + + CAN1 + 36 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes + 0 + 7 + read-write + + + IDAM + This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below + 8 + 2 + read-write + + + IDAM_0 + Format A One full ID (standard or extended) per ID filter Table element. + 0 + + + IDAM_1 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + 0x1 + + + IDAM_2 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + 0x2 + + + IDAM_3 + Format D All frames rejected. + 0x3 + + + + + AEN + This bit is supplied for backwards compatibility reasons + 12 + 1 + read-write + + + AEN_0 + Abort disabled + 0 + + + AEN_1 + Abort enabled + 0x1 + + + + + LPRIOEN + This bit is provided for backwards compatibility reasons + 13 + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled + 0 + + + LPRIOEN_1 + Local Priority enabled + 0x1 + + + + + IRMQ + This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK + 16 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + This bit defines whether FlexCAN is allowed to receive frames transmitted by itself + 17 + 1 + read-write + + + SRXDIS_0 + Self reception enabled + 0 + + + SRXDIS_1 + Self reception disabled + 0x1 + + + + + WAKSRC + This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up + 19 + 1 + read-write + + + WAKSRC_0 + FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + 0x1 + + + + + LPMACK + This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode + 20 + 1 + read-only + + + LPMACK_0 + FLEXCAN not in any of the low power modes + 0 + + + LPMACK_1 + FLEXCAN is either in Disable Mode, or Stop mode + 0x1 + + + + + WRNEN + When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register + 21 + 1 + read-write + + + WRNEN_0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + 0x1 + + + + + SLFWAK + This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode + 22 + 1 + read-write + + + SLFWAK_0 + FLEXCAN Self Wake Up feature is disabled + 0 + + + SLFWAK_1 + FLEXCAN Self Wake Up feature is enabled + 0x1 + + + + + SUPV + This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode + 23 + 1 + read-write + + + SUPV_0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + 0 + + + SUPV_1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + 0x1 + + + + + FRZACK + This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped + 24 + 1 + read-only + + + FRZACK_0 + FLEXCAN not in Freeze Mode, prescaler running + 0 + + + FRZACK_1 + FLEXCAN in Freeze Mode, prescaler stopped + 0x1 + + + + + SOFTRST + When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers + 25 + 1 + read-write + + + SOFTRST_0 + No reset request + 0 + + + SOFTRST_1 + Reset the registers + 0x1 + + + + + WAKMSK + This bit enables the Wake Up Interrupt generation. + 26 + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled + 0x1 + + + + + NOTRDY + This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode + 27 + 1 + read-only + + + NOTRDY_0 + FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + 0 + + + NOTRDY_1 + FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + 0x1 + + + + + HALT + Assertion of this bit puts the FLEXCAN module into Freeze Mode + 28 + 1 + read-write + + + HALT_0 + No Freeze Mode request. + 0 + + + HALT_1 + Enters Freeze Mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + This bit controls whether the Rx FIFO feature is enabled or not + 29 + 1 + read-write + + + RFEN_0 + FIFO not enabled + 0 + + + RFEN_1 + FIFO enabled + 0x1 + + + + + FRZ + The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level + 30 + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze Mode + 0 + + + FRZ_1 + Enabled to enter Freeze Mode + 0x1 + + + + + MDIS + This bit controls whether FLEXCAN is enabled or not + 31 + 1 + read-write + + + MDIS_0 + Enable the FLEXCAN module + 0 + + + MDIS_1 + Disable the FLEXCAN module + 0x1 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + This 3-bit field defines the length of the Propagation Segment in the bit time + 0 + 3 + read-write + + + LOM + This bit configures FLEXCAN to operate in Listen Only Mode + 3 + 1 + read-write + + + LOM_0 + Listen Only Mode is deactivated + 0 + + + LOM_1 + FLEXCAN module operates in Listen Only Mode + 0x1 + + + + + LBUF + This bit defines the ordering mechanism for Message Buffer transmission + 4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first + 0 + + + LBUF_1 + Lowest number buffer is transmitted first + 0x1 + + + + + TSYN + This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0 + 5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + This bit defines how FLEXCAN recovers from Bus Off state + 6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled + 0x1 + + + + + SMP + This bit defines the sampling mode of CAN bits at the FLEXCAN_RX + 7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + 0x1 + + + + + RWRNMSK + This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register + 10 + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled + 0x1 + + + + + TWRNMSK + This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register + 11 + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled + 0x1 + + + + + LPB + This bit configures FlexCAN to operate in Loop-Back Mode + 12 + 1 + read-write + + + LPB_0 + Loop Back disabled + 0 + + + LPB_1 + Loop Back enabled + 0x1 + + + + + ERRMSK + This bit provides a mask for the Error Interrupt. + 14 + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled + 0 + + + ERRMSK_1 + Error interrupt enabled + 0x1 + + + + + BOFFMSK + This bit provides a mask for the Bus Off Interrupt. + 15 + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled + 0x1 + + + + + PSEG2 + This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time + 16 + 3 + read-write + + + PSEG1 + This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time + 19 + 3 + read-write + + + RJW + This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period + 22 + 2 + read-write + + + PRESDIV + This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency + 24 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + TIMER + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG + These bits mask the Mailbox filter bits as shown in the figure above + 0 + 32 + read-write + + + MG_0 + the corresponding bit in the filter is "don't care" + 0 + + + MG_1 + The corresponding bit in the filter is checked against the one received + 0x1 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M + These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX14M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX14M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M + These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX15M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX15M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ERR_COUNTER + Tx_Err_Counter + 0 + 8 + read-write + + + RX_ERR_COUNTER + Rx_Err_Counter + 8 + 8 + read-write + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm + 0 + 1 + read-write + + + WAKINT_0 + No such occurrence + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + 0x1 + + + + + ERRINT + This bit indicates that at least one of the Error Bits (bits 15-10) is set + 1 + 1 + read-write + + + ERRINT_0 + No such occurrence + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register + 0x1 + + + + + BOFFINT + This bit is set when FLEXCAN enters 'Bus Off' state + 2 + 1 + read-write + + + BOFFINT_0 + No such occurrence + 0 + + + BOFFINT_1 + FLEXCAN module entered 'Bus Off' state + 0x1 + + + + + RX + This bit indicates if FlexCAN is receiving a message. Refer to . + 3 + 1 + read-only + + + RX_0 + FLEXCAN is receiving a message + 0 + + + RX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + FLTCONF + If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive" + 4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + FLTCONF_2 + Bus off + #1x + + + + + TX + This bit indicates if FLEXCAN is transmitting a message.Refer to . + 6 + 1 + read-only + + + TX_0 + FLEXCAN is receiving a message + 0 + + + TX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + IDLE + This bit indicates when CAN bus is in IDLE state.Refer to . + 7 + 1 + read-only + + + IDLE_0 + No such occurrence + 0 + + + IDLE_1 + CAN bus is now IDLE + 0x1 + + + + + RXWRN + This bit indicates when repetitive errors are occurring during message reception. + 8 + 1 + read-only + + + RXWRN_0 + No such occurrence + 0 + + + RXWRN_1 + Rx_Err_Counter >= 96 + 0x1 + + + + + TXWRN + This bit indicates when repetitive errors are occurring during message transmission. + 9 + 1 + read-only + + + TXWRN_0 + No such occurrence + 0 + + + TXWRN_1 + TX_Err_Counter >= 96 + 0x1 + + + + + STFERR + This bit indicates that a Stuffing Error has been detected. + 10 + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + This bit indicates that a Form Error has been detected by the receiver node, i + 11 + 1 + read-only + + + FRMERR_0 + No such occurrence + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register + 0x1 + + + + + CRCERR + This bit indicates that a CRC Error has been detected by the receiver node, i + 12 + 1 + read-only + + + CRCERR_0 + No such occurrence + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + This bit indicates that an Acknowledge Error has been detected by the transmitter node, i + 13 + 1 + read-only + + + ACKERR_0 + No such occurrence + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register + 0x1 + + + + + BIT0ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 14 + 1 + read-only + + + BIT0ERR_0 + No such occurrence + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive + 0x1 + + + + + BIT1ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 15 + 1 + read-only + + + BIT1ERR_0 + No such occurrence + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant + 0x1 + + + + + RWRNINT + If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96 + 16 + 1 + read-write + + + RWRNINT_0 + No such occurrence + 0 + + + RWRNINT_1 + The Rx error counter transition from < 96 to >= 96 + 0x1 + + + + + TWRNINT + If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96 + 17 + 1 + read-write + + + TWRNINT_0 + No such occurrence + 0 + + + TWRNINT_1 + The Tx error counter transition from < 96 to >= 96 + 0x1 + + + + + SYNCH + This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process + 18 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt + 0 + 32 + read-write + + + BUFHM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFHM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFLM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt + 0 + 32 + read-write + + + BUFLM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFLM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHI + Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt. + 0 + 32 + read-write + + + BUFHI_0 + No such occurrence + 0 + + + BUFHI_1 + The corresponding buffer has successfully completed transmission or reception + 0x1 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4TO0I + If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 + 0 + 5 + read-write + + + BUF4TO0I_0 + No such occurrence + 0 + + + BUF4TO0I_1 + Corresponding MB completed transmission/reception + 0x1 + + + + + BUF5I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 + 5 + 1 + read-write + + + BUF5I_0 + No such occurrence + 0 + + + BUF5I_1 + MB5 completed transmission/reception or frames available in the FIFO + 0x1 + + + + + BUF6I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 + 6 + 1 + read-write + + + BUF6I_0 + No such occurrence + 0 + + + BUF6I_1 + MB6 completed transmission/reception or FIFO almost full + 0x1 + + + + + BUF7I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 + 7 + 1 + read-write + + + BUF7I_0 + No such occurrence + 0 + + + BUF7I_1 + MB7 completed transmission/reception or FIFO overflow + 0x1 + + + + + BUF31TO8I + Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt. + 8 + 24 + read-write + + + BUF31TO8I_0 + No such occurrence + 0 + + + BUF31TO8I_1 + The corresponding MB has successfully completed transmission or reception + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + EACEN + This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process + 16 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame + 17 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated + 0 + + + RRS_1 + Remote Request Frame is stored + 0x1 + + + + + MRP + If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO + 18 + 1 + read-write + + + MRP_0 + Matching starts from Rx FIFO and continues on Mailboxes + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Rx FIFO + 0x1 + + + + + TASD + This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus + 19 + 5 + read-write + + + RFFN + This 4-bit field defines the number of Rx FIFO filters according to + 24 + 4 + read-write + + + WRMFRZ + Enable unrestricted write access to FlexCAN memory in Freeze mode + 28 + 1 + read-write + + + WRMFRZ_0 + Keep the write access restricted in some regions of FlexCAN memory + 0 + + + WRMFRZ_1 + Enable unrestricted write access to FlexCAN memory + 0x1 + + + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000) + 13 + 1 + read-only + + + IMB_0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + This bit indicates whether IMB and LPTM contents are currently valid or not + 14 + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid + 0 + + + VPS_1 + Contents of IMB and LPTM are valid + 0x1 + + + + + LPTM + If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description) + 16 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + This field indicates the CRC value of the last message transmitted + 0 + 15 + read-only + + + MBCRC + This field indicates the number of the Mailbox corresponding to the value in TXCRC field. + 16 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM + These bits mask the ID Filter Table elements bits in a perfect alignment + 0 + 32 + read-write + + + FGM_0 + The corresponding bit in the filter is "don't care" + 0 + + + FGM_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO + 0 + 9 + read-only + + + + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + + + CS0 + Message Buffer 0 CS Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID0 + Message Buffer 0 ID Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID1 + Message Buffer 1 ID Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID2 + Message Buffer 2 ID Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID3 + Message Buffer 3 ID Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID4 + Message Buffer 4 ID Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID5 + Message Buffer 5 ID Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID6 + Message Buffer 6 ID Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID7 + Message Buffer 7 ID Register + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID8 + Message Buffer 8 ID Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID9 + Message Buffer 9 ID Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID10 + Message Buffer 10 ID Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID11 + Message Buffer 11 ID Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID12 + Message Buffer 12 ID Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID13 + Message Buffer 13 ID Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID14 + Message Buffer 14 ID Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID15 + Message Buffer 15 ID Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID16 + Message Buffer 16 ID Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID17 + Message Buffer 17 ID Register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID18 + Message Buffer 18 ID Register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID19 + Message Buffer 19 ID Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID20 + Message Buffer 20 ID Register + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID21 + Message Buffer 21 ID Register + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID22 + Message Buffer 22 ID Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID23 + Message Buffer 23 ID Register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID24 + Message Buffer 24 ID Register + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID25 + Message Buffer 25 ID Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID26 + Message Buffer 26 ID Register + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID27 + Message Buffer 27 ID Register + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID28 + Message Buffer 28 ID Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID29 + Message Buffer 29 ID Register + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID30 + Message Buffer 30 ID Register + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID31 + Message Buffer 31 ID Register + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS32 + Message Buffer 32 CS Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID32 + Message Buffer 32 ID Register + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD032 + Message Buffer 32 WORD0 Register + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD132 + Message Buffer 32 WORD1 Register + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS33 + Message Buffer 33 CS Register + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID33 + Message Buffer 33 ID Register + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD033 + Message Buffer 33 WORD0 Register + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD133 + Message Buffer 33 WORD1 Register + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS34 + Message Buffer 34 CS Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID34 + Message Buffer 34 ID Register + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD034 + Message Buffer 34 WORD0 Register + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD134 + Message Buffer 34 WORD1 Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS35 + Message Buffer 35 CS Register + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID35 + Message Buffer 35 ID Register + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD035 + Message Buffer 35 WORD0 Register + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD135 + Message Buffer 35 WORD1 Register + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS36 + Message Buffer 36 CS Register + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID36 + Message Buffer 36 ID Register + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD036 + Message Buffer 36 WORD0 Register + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD136 + Message Buffer 36 WORD1 Register + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS37 + Message Buffer 37 CS Register + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID37 + Message Buffer 37 ID Register + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD037 + Message Buffer 37 WORD0 Register + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD137 + Message Buffer 37 WORD1 Register + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS38 + Message Buffer 38 CS Register + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID38 + Message Buffer 38 ID Register + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD038 + Message Buffer 38 WORD0 Register + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD138 + Message Buffer 38 WORD1 Register + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS39 + Message Buffer 39 CS Register + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID39 + Message Buffer 39 ID Register + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD039 + Message Buffer 39 WORD0 Register + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD139 + Message Buffer 39 WORD1 Register + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS40 + Message Buffer 40 CS Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID40 + Message Buffer 40 ID Register + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD040 + Message Buffer 40 WORD0 Register + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD140 + Message Buffer 40 WORD1 Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS41 + Message Buffer 41 CS Register + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID41 + Message Buffer 41 ID Register + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD041 + Message Buffer 41 WORD0 Register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD141 + Message Buffer 41 WORD1 Register + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS42 + Message Buffer 42 CS Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID42 + Message Buffer 42 ID Register + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD042 + Message Buffer 42 WORD0 Register + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD142 + Message Buffer 42 WORD1 Register + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS43 + Message Buffer 43 CS Register + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID43 + Message Buffer 43 ID Register + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD043 + Message Buffer 43 WORD0 Register + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD143 + Message Buffer 43 WORD1 Register + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS44 + Message Buffer 44 CS Register + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID44 + Message Buffer 44 ID Register + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD044 + Message Buffer 44 WORD0 Register + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD144 + Message Buffer 44 WORD1 Register + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS45 + Message Buffer 45 CS Register + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID45 + Message Buffer 45 ID Register + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD045 + Message Buffer 45 WORD0 Register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD145 + Message Buffer 45 WORD1 Register + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS46 + Message Buffer 46 CS Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID46 + Message Buffer 46 ID Register + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD046 + Message Buffer 46 WORD0 Register + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD146 + Message Buffer 46 WORD1 Register + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS47 + Message Buffer 47 CS Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID47 + Message Buffer 47 ID Register + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD047 + Message Buffer 47 WORD0 Register + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD147 + Message Buffer 47 WORD1 Register + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS48 + Message Buffer 48 CS Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID48 + Message Buffer 48 ID Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD048 + Message Buffer 48 WORD0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD148 + Message Buffer 48 WORD1 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS49 + Message Buffer 49 CS Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID49 + Message Buffer 49 ID Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD049 + Message Buffer 49 WORD0 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD149 + Message Buffer 49 WORD1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS50 + Message Buffer 50 CS Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID50 + Message Buffer 50 ID Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD050 + Message Buffer 50 WORD0 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD150 + Message Buffer 50 WORD1 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS51 + Message Buffer 51 CS Register + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID51 + Message Buffer 51 ID Register + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD051 + Message Buffer 51 WORD0 Register + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD151 + Message Buffer 51 WORD1 Register + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS52 + Message Buffer 52 CS Register + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID52 + Message Buffer 52 ID Register + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD052 + Message Buffer 52 WORD0 Register + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD152 + Message Buffer 52 WORD1 Register + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS53 + Message Buffer 53 CS Register + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID53 + Message Buffer 53 ID Register + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD053 + Message Buffer 53 WORD0 Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD153 + Message Buffer 53 WORD1 Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS54 + Message Buffer 54 CS Register + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID54 + Message Buffer 54 ID Register + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD054 + Message Buffer 54 WORD0 Register + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD154 + Message Buffer 54 WORD1 Register + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS55 + Message Buffer 55 CS Register + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID55 + Message Buffer 55 ID Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD055 + Message Buffer 55 WORD0 Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD155 + Message Buffer 55 WORD1 Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS56 + Message Buffer 56 CS Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID56 + Message Buffer 56 ID Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD056 + Message Buffer 56 WORD0 Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD156 + Message Buffer 56 WORD1 Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS57 + Message Buffer 57 CS Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID57 + Message Buffer 57 ID Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD057 + Message Buffer 57 WORD0 Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD157 + Message Buffer 57 WORD1 Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS58 + Message Buffer 58 CS Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID58 + Message Buffer 58 ID Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD058 + Message Buffer 58 WORD0 Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD158 + Message Buffer 58 WORD1 Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS59 + Message Buffer 59 CS Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID59 + Message Buffer 59 ID Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD059 + Message Buffer 59 WORD0 Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD159 + Message Buffer 59 WORD1 Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS60 + Message Buffer 60 CS Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID60 + Message Buffer 60 ID Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD060 + Message Buffer 60 WORD0 Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD160 + Message Buffer 60 WORD1 Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS61 + Message Buffer 61 CS Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID61 + Message Buffer 61 ID Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD061 + Message Buffer 61 WORD0 Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD161 + Message Buffer 61 WORD1 Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS62 + Message Buffer 62 CS Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID62 + Message Buffer 62 ID Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD062 + Message Buffer 62 WORD0 Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD162 + Message Buffer 62 WORD1 Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS63 + Message Buffer 63 CS Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID63 + Message Buffer 63 ID Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD063 + Message Buffer 63 WORD0 Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD163 + Message Buffer 63 WORD1 Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + 64 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + RXIMR%s + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI + These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways + 0 + 32 + read-write + + + MI_0 + the corresponding bit in the filter is "don't care" + 0 + + + MI_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + It determines the Glitch Filter Width + 0 + 8 + read-write + + + + + + + CAN2 + FLEXCAN + CAN + FLEXCAN2_ + 0x401D4000 + + 0 + 0x9E4 + registers + + + CAN2 + 37 + + + + TMR1 + Quad Timer + TMR + TMR1_ + TMR + 0x401DC000 + + 0 + 0x7A + registers + + + TMR1 + 133 + + + + 4 + 0x20 + 0,1,2,3 + COMP1%s + Timer Channel Compare Register 1 + 0 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_1 + Comparison Value 1 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + COMP2%s + Timer Channel Compare Register 2 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_2 + Comparison Value 2 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CAPT%s + Timer Channel Capture Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CAPTURE + Capture Value + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + LOAD%s + Timer Channel Load Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + LOAD + Timer Load Register + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + HOLD%s + Timer Channel Hold Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + HOLD + This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CNTR%s + Timer Channel Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + COUNTER + This read/write register is the counter for the corresponding channel in a timer module. + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CTRL%s + Timer Channel Control Register + 0xC + 16 + read-write + 0 + 0xFFFF + + + OUTMODE + Output Mode + 0 + 3 + read-write + + + OUTMODE_0 + Asserted while counter is active + 0 + + + OUTMODE_1 + Clear OFLAG output on successful compare + 0x1 + + + OUTMODE_2 + Set OFLAG output on successful compare + 0x2 + + + OUTMODE_3 + Toggle OFLAG output on successful compare + 0x3 + + + OUTMODE_4 + Toggle OFLAG output using alternating compare registers + 0x4 + + + OUTMODE_5 + Set on compare, cleared on secondary source input edge + 0x5 + + + OUTMODE_6 + Set on compare, cleared on counter rollover + 0x6 + + + OUTMODE_7 + Enable gated clock output while counter is active + 0x7 + + + + + COINIT + Co-Channel Initialization + 3 + 1 + read-write + + + COINIT_0 + Co-channel counter/timers cannot force a re-initialization of this counter/timer + 0 + + + COINIT_1 + Co-channel counter/timers may force a re-initialization of this counter/timer + 0x1 + + + + + DIR + Count Direction + 4 + 1 + read-write + + + DIR_0 + Count up. + 0 + + + DIR_1 + Count down. + 0x1 + + + + + LENGTH + Count Length + 5 + 1 + read-write + + + LENGTH_0 + Count until roll over at $FFFF and continue from $0000. + 0 + + + LENGTH_1 + Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + 0x1 + + + + + ONCE + Count Once + 6 + 1 + read-write + + + ONCE_0 + Count repeatedly. + 0 + + + ONCE_1 + Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + 0x1 + + + + + SCS + Secondary Count Source + 7 + 2 + read-write + + + SCS_0 + Counter 0 input pin + 0 + + + SCS_1 + Counter 1 input pin + 0x1 + + + SCS_2 + Counter 2 input pin + 0x2 + + + SCS_3 + Counter 3 input pin + 0x3 + + + + + PCS + Primary Count Source + 9 + 4 + read-write + + + PCS_0 + Counter 0 input pin + 0 + + + PCS_1 + Counter 1 input pin + 0x1 + + + PCS_2 + Counter 2 input pin + 0x2 + + + PCS_3 + Counter 3 input pin + 0x3 + + + PCS_4 + Counter 0 output + 0x4 + + + PCS_5 + Counter 1 output + 0x5 + + + PCS_6 + Counter 2 output + 0x6 + + + PCS_7 + Counter 3 output + 0x7 + + + PCS_8 + IP bus clock divide by 1 prescaler + 0x8 + + + PCS_9 + IP bus clock divide by 2 prescaler + 0x9 + + + PCS_10 + IP bus clock divide by 4 prescaler + 0xA + + + PCS_11 + IP bus clock divide by 8 prescaler + 0xB + + + PCS_12 + IP bus clock divide by 16 prescaler + 0xC + + + PCS_13 + IP bus clock divide by 32 prescaler + 0xD + + + PCS_14 + IP bus clock divide by 64 prescaler + 0xE + + + PCS_15 + IP bus clock divide by 128 prescaler + 0xF + + + + + CM + Count Mode + 13 + 3 + read-write + + + CM_0 + No operation + 0 + + + CM_1 + Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + 0x1 + + + CM_2 + Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + 0x2 + + + CM_3 + Count rising edges of primary source while secondary input high active + 0x3 + + + CM_4 + Quadrature count mode, uses primary and secondary sources + 0x4 + + + CM_5 + Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + 0x5 + + + CM_6 + Edge of secondary source triggers primary count until compare + 0x6 + + + CM_7 + Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + 0x7 + + + + + + + 4 + 0x20 + 0,1,2,3 + SCTRL%s + Timer Channel Status and Control Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + OEN + Output Enable + 0 + 1 + read-write + + + OEN_0 + The external pin is configured as an input. + 0 + + + OEN_1 + The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + 0x1 + + + + + OPS + Output Polarity Select + 1 + 1 + read-write + + + OPS_0 + True polarity. + 0 + + + OPS_1 + Inverted polarity. + 0x1 + + + + + FORCE + Force OFLAG Output + 2 + 1 + read-write + + + VAL + Forced OFLAG Value + 3 + 1 + read-write + + + EEOF + Enable External OFLAG Force + 4 + 1 + read-write + + + MSTR + Master Mode + 5 + 1 + read-write + + + CAPTURE_MODE + Input Capture Mode + 6 + 2 + read-write + + + CAPTURE_MODE_0 + Capture function is disabled + 0 + + + CAPTURE_MODE_1 + Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + 0x1 + + + CAPTURE_MODE_2 + Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + 0x2 + + + CAPTURE_MODE_3 + Load capture register on both edges of input + 0x3 + + + + + INPUT + External Input Signal + 8 + 1 + read-only + + + IPS + Input Polarity Select + 9 + 1 + read-write + + + IEFIE + Input Edge Flag Interrupt Enable + 10 + 1 + read-write + + + IEF + Input Edge Flag + 11 + 1 + read-write + + + TOFIE + Timer Overflow Flag Interrupt Enable + 12 + 1 + read-write + + + TOF + Timer Overflow Flag + 13 + 1 + read-write + + + TCFIE + Timer Compare Flag Interrupt Enable + 14 + 1 + read-write + + + TCF + Timer Compare Flag + 15 + 1 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD1%s + Timer Channel Comparator Load Register 1 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_1 + This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD2%s + Timer Channel Comparator Load Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_2 + This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CSCTRL%s + Timer Channel Comparator Status and Control Register + 0x14 + 16 + read-write + 0 + 0xFFFF + + + CL1 + Compare Load Control 1 + 0 + 2 + read-write + + + CL1_0 + Never preload + 0 + + + CL1_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL1_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + CL2 + Compare Load Control 2 + 2 + 2 + read-write + + + CL2_0 + Never preload + 0 + + + CL2_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL2_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + TCF1 + Timer Compare 1 Interrupt Flag + 4 + 1 + read-write + + + TCF2 + Timer Compare 2 Interrupt Flag + 5 + 1 + read-write + + + TCF1EN + Timer Compare 1 Interrupt Enable + 6 + 1 + read-write + + + TCF2EN + Timer Compare 2 Interrupt Enable + 7 + 1 + read-write + + + UP + Counting Direction Indicator + 9 + 1 + read-only + + + UP_0 + The last count was in the DOWN direction. + 0 + + + UP_1 + The last count was in the UP direction. + 0x1 + + + + + TCI + Triggered Count Initialization Control + 10 + 1 + read-write + + + TCI_0 + Stop counter upon receiving a second trigger event while still counting from the first trigger event. + 0 + + + TCI_1 + Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + 0x1 + + + + + ROC + Reload on Capture + 11 + 1 + read-write + + + ROC_0 + Do not reload the counter on a capture event. + 0 + + + ROC_1 + Reload the counter on a capture event. + 0x1 + + + + + ALT_LOAD + Alternative Load Enable + 12 + 1 + read-write + + + ALT_LOAD_0 + Counter can be re-initialized only with the LOAD register. + 0 + + + ALT_LOAD_1 + Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + 0x1 + + + + + FAULT + Fault Enable + 13 + 1 + read-write + + + FAULT_0 + Fault function disabled. + 0 + + + FAULT_1 + Fault function enabled. + 0x1 + + + + + DBG_EN + Debug Actions Enable + 14 + 2 + read-write + + + DBG_EN_0 + Continue with normal operation during debug mode. (default) + 0 + + + DBG_EN_1 + Halt TMR counter during debug mode. + 0x1 + + + DBG_EN_2 + Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + 0x2 + + + DBG_EN_3 + Both halt counter and force output to 0 during debug mode. + 0x3 + + + + + + + 4 + 0x20 + 0,1,2,3 + FILT%s + Timer Channel Input Filter Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + DMA%s + Timer Channel DMA Enable Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + IEFDE + Input Edge Flag DMA Enable + 0 + 1 + read-write + + + CMPLD1DE + Comparator Preload Register 1 DMA Enable + 1 + 1 + read-write + + + CMPLD2DE + Comparator Preload Register 2 DMA Enable + 2 + 1 + read-write + + + + + ENBL + Timer Channel Enable Register + 0x1E + 16 + read-write + 0xF + 0xFFFF + + + ENBL + Timer Channel Enable + 0 + 4 + read-write + + + ENBL_0 + Timer channel is disabled. + 0 + + + ENBL_1 + Timer channel is enabled. (default) + 0x1 + + + + + + + + + TMR2 + Quad Timer + TMR + TMR2_ + 0x401E0000 + + 0 + 0x7A + registers + + + TMR2 + 134 + + + + TMR3 + Quad Timer + TMR + TMR3_ + 0x401E4000 + + 0 + 0x7A + registers + + + TMR3 + 135 + + + + TMR4 + Quad Timer + TMR + TMR4_ + 0x401E8000 + + 0 + 0x7A + registers + + + TMR4 + 136 + + + + GPT1 + GPT + GPT + GPT1_ + GPT + 0x401EC000 + + 0 + 0x28 + registers + + + GPT1 + 100 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 10 + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 15 + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 16 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 18 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 20 + 3 + read-write + + + OM2 + See OM3 + 23 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 26 + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + OM3_4 + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + See F03 + 29 + 1 + read-write + + + FO2 + See F03 + 30 + 1 + read-write + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 31 + 1 + read-write + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 12 + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x401F0000 + + 0 + 0x28 + registers + + + GPT2 + 101 + + + + OCOTP + no description available + OCOTP + 0x401F4000 + + 0 + 0x6F4 + registers + + + + HW_OCOTP_CTRL + OTP Controller Control and Status Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + not_busy + No write or read access to OTP started. + 0 + + + busy + Write or read access to OTP started. + 0x1 + + + + + ERROR + Locked Region Access Error + 9 + 1 + read-write + + + no_error + No error. + 0 + + + error + Error - access to a locked region requested. + 0x1 + + + + + RELOAD_SHADOWS + Reload Shadow Registers + 10 + 1 + read-write + + + shadow_noforce_reload + Do not force shadow register re-load. + 0 + + + shadow_force_reload + Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded. + 0x1 + + + + + WR_UNLOCK + Write Unlock + 16 + 16 + read-write + + + otp_w_locked + OTP write access is locked. + 0 + + + otp_w_unlocked + OTP write access is unlocked. + 0x3E77 + + + + + + + HW_OCOTP_CTRL_SET + OTP Controller Control and Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToSet + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToSet + + + ERROR + Locked Region Access Error + 9 + 1 + read-write + oneToSet + + + RELOAD_SHADOWS + Reload Shadow Registers + 10 + 1 + read-write + oneToSet + + + WR_UNLOCK + Write Unlock + 16 + 16 + read-write + oneToSet + + + + + HW_OCOTP_CTRL_CLR + OTP Controller Control and Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToClear + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToClear + + + ERROR + Locked Region Access Error + 9 + 1 + read-write + oneToClear + + + RELOAD_SHADOWS + Reload Shadow Registers + 10 + 1 + read-write + oneToClear + + + WR_UNLOCK + Write Unlock + 16 + 16 + read-write + oneToClear + + + + + HW_OCOTP_CTRL_TOG + OTP Controller Control and Status Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToToggle + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToToggle + + + ERROR + Locked Region Access Error + 9 + 1 + read-write + oneToToggle + + + RELOAD_SHADOWS + Reload Shadow Registers + 10 + 1 + read-write + oneToToggle + + + WR_UNLOCK + Write Unlock + 16 + 16 + read-write + oneToToggle + + + + + HW_OCOTP_TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x60D9755 + 0xFFFFFFFF + + + STROBE_PROG + Write Strobe Period + 0 + 12 + read-write + + + RELAX + Relax Count Value + 12 + 4 + read-write + + + STROBE_READ + Read Strobe Period + 16 + 6 + read-write + + + WAIT + Wait Interval + 22 + 6 + read-write + + + + + HW_OCOTP_DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data + 0 + 32 + read-write + + + + + HW_OCOTP_READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Read Fuse + 0 + 1 + read-write + + + + + HW_OCOTP_READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data + 0 + 32 + read-write + + + + + HW_OCOTP_SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRK_REVOKE_LOCK + SRK Revoke Lock + 1 + 1 + read-write + + + notblocked + The writing of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + The writing of this region's shadow register and OTP fuse word are blocked. Once this bit is set, it is always high unless a POR is issued. + 0x1 + + + + + FIELD_RETURN_LOCK + Field Return Lock + 2 + 1 + read-write + + + notblocked + Writing to this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + Writing to this region's shadow register and OTP fuse word are blocked. Once this bit is set, it is always high unless a POR is issued. + 0x1 + + + + + + + HW_OCOTP_SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + jtag_dbg_dis + JTAG debugging is not enabled by the HAB (it may still be enabled by other mechanisms). + 0 + + + jtag_dbg_en + JTAG debugging is enabled by the HAB (though this signal may be gated off). + 0x1 + + + + + SPARE + Spare + 1 + 30 + read-write + + + LOCK + Lock + 31 + 1 + read-write + + + unlocked + Bits in this register are unlocked. + 0 + + + locked + Bits in this register are locked. When set, all of the bits in this register are locked and can not be changed through SW programming. After this bit is set, it can only be cleared by a POR. + 0x1 + + + + + + + HW_OCOTP_SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToSet + + + SPARE + Spare + 1 + 30 + read-write + oneToSet + + + LOCK + Lock + 31 + 1 + read-write + oneToSet + + + + + HW_OCOTP_SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToClear + + + SPARE + Spare + 1 + 30 + read-write + oneToClear + + + LOCK + Lock + 31 + 1 + read-write + oneToClear + + + + + HW_OCOTP_SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToToggle + + + SPARE + Spare + 1 + 30 + read-write + oneToToggle + + + LOCK + Lock + 31 + 1 + read-write + oneToToggle + + + + + HW_OCOTP_VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + STEP + RTL Version Steping + 0 + 16 + read-only + + + MINOR + Minor RTL Version + 16 + 8 + read-only + + + MAJOR + Major RTL Version + 24 + 8 + read-only + + + + + HW_OCOTP_TIMING2 + OTP Controller Timing Register 2 + 0x100 + 32 + read-write + 0x30092 + 0xFFFFFFFF + + + RELAX_PROG + Relax Prog. count value + 0 + 12 + read-write + + + RELAX_READ + Relax Read count value + 16 + 6 + read-write + + + + + HW_OCOTP_LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0x40128003 + 0xFFFFFFFF + + + BOOT_CFG + BOOT_CFG Write Lock Status + 2 + 2 + read-only + + + SJC_RESP + SJC_RESP Lock Status + 6 + 1 + read-only + + + notblocked + The writing or reading of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + When set, the writing of this region's shadow register and OTP fuse word are blocked. The read of this region's shadow register and OTP fuse word are also blocked + 0x1 + + + + + MAC_ADDR + MAC_ADDR Write Lock Status + 8 + 2 + read-only + + + GP1 + GP1 Write Lock Status + 10 + 2 + read-only + + + GP2 + GP2 Write Lock Status + 12 + 2 + read-only + + + SW_GP1 + SW_GP1 Write Lock Status + 16 + 1 + read-only + + + notblocked + Writing of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + When set, the writing of this region's shadow register and OTP fuse word are blocked. + 0x1 + + + + + ANALOG + ANALOG Write Lock Status + 18 + 2 + read-only + + + SW_GP2_LOCK + SW_GP2 Write Lock Status + 21 + 1 + read-only + + + notblocked + Writing of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + When set, the writing of this region's shadow register and OTP fuse word are blocked. + 0x1 + + + + + MISC_CONF + MISC_CONF Write Lock Status + 22 + 1 + read-only + + + notblocked + Writing of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + When set, the writing of this region's shadow register and OTP fuse word are blocked. + 0x1 + + + + + SW_GP2_RLOCK + SW_GP2 Read Lock Status + 23 + 1 + read-only + + + notblocked + The reading of this region's shadow register and OTP fuse word are not blocked. + 0 + + + blocked + When set, the reading of this region's shadow register and OTP fuse word are blocked. + 0x1 + + + + + GP3 + GP3 Write Lock Status + 26 + 2 + read-only + + + FIELD_RETURN + FIELD RETURN Status + 31 + 1 + read-write + + + functional + The device is a functional part. + 0 + + + field_returned + The device is a field returned part. + 0x1 + + + + + + + HW_OCOTP_CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MEM4 + Value of OTP Bank 1 Word 4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_ANA0 + Value of OTP Bank 1 Word 5 (Analog Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_ANA1 + Value of OTP Bank 1 Word 6 (Analog Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_ANA2 + Value of OTP Bank 1 Word 7 (Analog Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_GP3 + Value of OTP Bank4 Word4 (MAC Address) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP1 + Value of OTP Bank5 Word0 (SW GP1) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP20 + Value of OTP Bank5 Word1 (SW GP2) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP21 + Value of OTP Bank5 Word2 (SW GP2) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP22 + Value of OTP Bank5 Word3 (SW GP2) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP23 + Value of OTP Bank5 Word4 (SW GP2) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF0 + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF1 + Value of OTP Bank5 Word6 (Misc Conf) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + HW_OCOTP_SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x401F8000 + + 0 + 0x65C + registers + + + + SW_MUX_CTL_PAD_GPIO_EMC_00 + SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register + 0x14 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D00 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_01 + SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register + 0x18 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_B of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D01 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_02 + SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register + 0x1C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDO of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D02 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_03 + SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register + 0x20 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_B of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDI of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D03 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_04 + SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register + 0x24 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D04 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_05 + SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register + 0x28 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_B of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D05 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_06 + SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register + 0x2C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_A of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D06 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_07 + SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register + 0x30 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_B of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D07 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_08 + SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register + 0x34 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_A of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D08 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_09 + SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register + 0x38 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_B of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D09 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_10 + SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register + 0x3C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_A of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D10 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_11 + SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register + 0x40 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_B of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SDA of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D11 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_12 + SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register + 0x44 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SCL of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC1_WP of instance: usdhc1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM3_A of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_13 + SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register + 0x48 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TXD of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_RIGHT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM3_B of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_14 + SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register + 0x4C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RXD of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_LEFT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS1 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_15 + SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register + 0x50 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN20 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR3_TIMER0 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_16 + SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register + 0x54 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN21 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR3_TIMER1 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_17 + SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register + 0x58 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR3_TIMER2 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_18 + SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_B of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR3_TIMER3 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_19 + SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_A of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TXD of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR2_TIMER0 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_20 + SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_B of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RXD of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR2_TIMER1 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_21 + SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_A of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR2_TIMER2 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_22 + SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA1 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_B of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: TMR2_TIMER3 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_23 + SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_TXD of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_24 + SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RXD of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_24 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_25 + SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TXD of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_25 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_26 + SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CLK of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RXD of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D12 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_26 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_27 + SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CKE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SCK of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D13 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_27 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_28 + SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_WE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_CTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDO of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D14 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_28 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_29 + SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CS0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_A of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDI of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_D15 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO29 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_29 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_30 + SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_B of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_CTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA23 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO30 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_30 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_31 + SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_A of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TXD of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS1 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA22 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO31 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_31 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_32 + SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_B of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RXD of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA21 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_32 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_33 + SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_A of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA20 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_33 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_34 + SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_B of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA19 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_34 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_35 + SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA13 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA18 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_35 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_36 + SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA14 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN22 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA17 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_36 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_37 + SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DA15 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN23 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA16 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_37 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_38 + SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_FIELD of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_38 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_39 + SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DQS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_39 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_40 + SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RDY of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDC of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_40 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_41 + SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_41 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_00 + SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWM3_A of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_32K of instance: xtalosc + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_ID of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SCLS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SCK of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_01 + SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWM3_B of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_24M of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_ID of instance: anatop + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SDAS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: EWM_OUT_B of instance: ewm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDO of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_02 + SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_TX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TXD of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM0_X of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: lpi2c1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDI of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_03 + SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RXD of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM1_X of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_04 + SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_05 + SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_06 + SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_CLK of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS3 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_07 + SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_ER of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_OUT of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_08 + SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN20 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_IN of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_09 + SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_A of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN21 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: GPT2_CLK of instance: gpt2 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_10 + SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_CRS of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_MCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN22 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_11 + SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_COL of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG1_B of instance: wdog1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN23 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_12 + SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_TXD of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG2_B of instance: wdog2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM2_X of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: NMI of instance: CM7 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_13 + SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RXD of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWM3_X of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_14 + SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_15 + SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_00 + SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_01 + SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_02 + SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TXD of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_OUT of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_03 + SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RXD of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_IN of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_04 + SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_B_DATA3 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDC of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_SR_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_PIXCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_05 + SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_B_DATA2 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDIO of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_MCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_06 + SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_B_DATA1 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TXD of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_LOCK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_07 + SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_B_DATA0 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RXD of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_EXT_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_08 + SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_SS1_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CMD of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW03 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_09 + SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_10 + SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_DATA3 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_B of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW02 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_11 + SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_DATA2 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: EWM_OUT_B of instance: ewm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL02 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_12 + SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_DATA1 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP1_OUT of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW01 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_13 + SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_DATA00 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP2_OUT of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDI of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL01 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_14 + SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_SCLK of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP3_OUT of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDO of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW00 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_15 + SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI_A_SS0_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP4_OUT of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SCK of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL00 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_00 + SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_CLK of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR1_TIMER0 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_RIGHT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D00 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX1 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_01 + SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_ENABLE of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR1_TIMER1 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDI of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D01 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX2 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_02 + SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_HSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR1_TIMER2 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDO of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D02 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX3 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_03 + SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_VSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR2_TIMER0 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SCK of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D03 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: WDOG2_RESET_B_DEB of instance: wdog2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_04 + SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA00 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR2_TIMER1 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE00 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D04 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_05 + SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA01 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR2_TIMER2 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE01 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D05 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_06 + SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA02 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM0_A of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE02 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D06 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_07 + SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA03 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM0_B of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE03 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D07 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_08 + SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA04 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM1_A of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_TXD of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D08 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_09 + SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA05 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR4_TIMER0 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM1_B of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_RXD of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D09 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_10 + SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA06 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR4_TIMER1 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM2_A of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D10 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_11 + SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA07 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR4_TIMER2 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM2_B of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D11 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_12 + SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA08 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_TRACE_CLK of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D12 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_13 + SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA09 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_TRACE_SWO of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D13 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_14 + SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA10 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D14 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG10 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_15 + SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA11 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D15 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG11 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_00 + SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA12 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TXD of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D16 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWM3_A of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_01 + SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA13 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RXD of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D17 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWM3_B of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_02 + SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA14 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS2 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D18 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWM3_A of instance: flexpwm2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_03 + SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA15 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS1 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D19 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWM3_B of instance: flexpwm2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_04 + SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA16 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA15 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D20 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_05 + SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA17 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDI of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA14 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D21 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_06 + SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA18 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDO of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA13 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D22 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_07 + SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA19 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SCK of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA12 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D23 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_08 + SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA20 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR1_TIMER3 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA11 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D24 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO24 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_09 + SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA21 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR2_TIMER3 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA10 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D25 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO25 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_10 + SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA22 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA00 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D26 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO26 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_REF_CLK of instance: enet + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_11 + SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA23 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: TMR4_TIMER3 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA01 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D27 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO27 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPSPI4_PCS3 of instance: lpspi4 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_12 + SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_TXD of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_PIXCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D28 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO28 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_13 + SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: WDOG1_B of instance: wdog1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_RXD of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_VSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D29 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO29 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_14 + SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDC of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_HSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D30 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO30 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_15 + SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDIO of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_A of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_MCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_D31 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO31 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_00 + SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SCK of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPI_A_SS1_B of instance: flexspi + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_01 + SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPI_B_SS1_B of instance: flexspi + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_02 + SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_CTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_03 + SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDI of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_04 + SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_A of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPI_B_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_05 + SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_B of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RXD of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPI_B_DQS of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_00 + SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA3 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_TXD of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_01 + SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA2 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_RXD of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_02 + SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA1 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM3_A of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_03 + SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA0 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWM3_B of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_READY of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_04 + SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPI_A_SS1_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_05 + SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DQS of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPI_B_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_06 + SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_CTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_07 + SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX1 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_REF_EN_B of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_08 + SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA00 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TXD of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SD0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX2 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_09 + SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA1 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RXD of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_10 + SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA2 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RXD of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_11 + SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA3 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TXD of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_11 + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_00 + SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register + 0x204 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_01 + SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register + 0x208 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_02 + SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register + 0x20C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_03 + SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register + 0x210 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_04 + SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register + 0x214 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_05 + SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register + 0x218 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_06 + SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register + 0x21C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_07 + SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register + 0x220 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_08 + SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register + 0x224 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_09 + SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register + 0x228 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_10 + SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register + 0x22C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_11 + SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register + 0x230 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_12 + SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register + 0x234 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_13 + SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register + 0x238 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_14 + SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register + 0x23C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_15 + SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register + 0x240 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_16 + SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register + 0x244 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_17 + SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register + 0x248 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_18 + SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register + 0x24C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_19 + SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register + 0x250 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_20 + SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register + 0x254 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_21 + SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register + 0x258 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_22 + SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register + 0x25C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_23 + SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register + 0x260 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_24 + SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register + 0x264 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_25 + SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register + 0x268 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_26 + SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register + 0x26C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_27 + SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register + 0x270 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_28 + SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register + 0x274 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_29 + SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register + 0x278 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_30 + SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register + 0x27C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_31 + SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register + 0x280 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_32 + SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register + 0x284 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_33 + SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register + 0x288 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_34 + SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register + 0x28C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_35 + SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register + 0x290 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_36 + SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register + 0x294 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_37 + SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register + 0x298 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_38 + SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register + 0x29C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_39 + SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register + 0x2A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_40 + SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register + 0x2A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_41 + SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register + 0x2A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_00 + SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register + 0x2AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_01 + SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register + 0x2B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_02 + SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register + 0x2B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_03 + SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register + 0x2B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_04 + SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register + 0x2BC + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_05 + SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register + 0x2C0 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_06 + SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register + 0x2C4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_07 + SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register + 0x2C8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_08 + SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register + 0x2CC + 32 + read-write + 0xB0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_09 + SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register + 0x2D0 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_10 + SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register + 0x2D4 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_11 + SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register + 0x2D8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_12 + SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register + 0x2DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_13 + SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register + 0x2E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_14 + SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register + 0x2E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_15 + SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_00 + SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_01 + SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_02 + SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_03 + SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_04 + SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register + 0x2FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_05 + SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register + 0x300 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_06 + SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register + 0x304 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_07 + SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register + 0x308 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_08 + SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register + 0x30C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_09 + SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register + 0x310 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_10 + SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register + 0x314 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_11 + SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register + 0x318 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_12 + SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register + 0x31C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_13 + SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register + 0x320 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_14 + SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register + 0x324 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_15 + SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register + 0x328 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_00 + SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register + 0x32C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_01 + SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register + 0x330 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_02 + SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register + 0x334 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_03 + SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register + 0x338 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_04 + SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register + 0x33C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_05 + SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register + 0x340 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_06 + SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register + 0x344 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_07 + SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register + 0x348 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_08 + SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register + 0x34C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_09 + SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register + 0x350 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_10 + SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register + 0x354 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_11 + SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register + 0x358 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_12 + SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register + 0x35C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_13 + SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register + 0x360 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_14 + SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register + 0x364 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_15 + SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register + 0x368 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_00 + SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register + 0x36C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_01 + SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register + 0x370 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_02 + SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register + 0x374 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_03 + SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register + 0x378 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_04 + SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register + 0x37C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_05 + SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register + 0x380 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_06 + SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register + 0x384 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_07 + SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register + 0x388 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_08 + SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register + 0x38C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_09 + SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register + 0x390 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_10 + SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register + 0x394 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_11 + SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register + 0x398 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_12 + SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register + 0x39C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_13 + SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register + 0x3A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_14 + SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register + 0x3A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_15 + SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register + 0x3A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_00 + SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register + 0x3AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_01 + SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register + 0x3B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_02 + SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_03 + SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_04 + SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register + 0x3BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_05 + SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register + 0x3C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_00 + SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register + 0x3C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_01 + SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register + 0x3C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_02 + SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register + 0x3CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_03 + SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_04 + SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_05 + SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_06 + SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register + 0x3DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_07 + SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_08 + SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_09 + SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_10 + SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register + 0x3EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_11 + SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register + 0x3F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0 + HI-Z + 0 + + + DSE_1 + Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V + 0x1 + + + DSE_2 + Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V + 0x2 + + + DSE_3 + Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V + 0x3 + + + DSE_4 + Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V + 0x4 + + + DSE_5 + Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V + 0x5 + + + DSE_6 + Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V + 0x6 + + + DSE_7 + Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_Low + 50MHz + 0 + + + SPEED_1_Medium + 100MHz - 150MHz + 0x1 + + + SPEED_2_Medium + 100MHz - 150MHz + 0x2 + + + SPEED_3_Maximum + 150MHz - 200MHz + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled (Output is CMOS) + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled (Output is Open Drain) + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. + 13 + 1 + read-write + + + PUE_0_Keeper + Keep the previous output value when the output driver is disabled. + 0 + + + PUE_1_Pull + Pull-up or pull-down (determined by PUS field). + 0x1 + + + + + PUS + Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled (CMOS input) + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled (Schmitt Trigger input) + 0x1 + + + + + + + ANATOP_USB_OTG1_ID_SELECT_INPUT + ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT3 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 + 0 + + + GPIO_AD_B1_02_ALT0 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + 0x1 + + + + + + + ANATOP_USB_OTG2_ID_SELECT_INPUT + ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT3 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT3 + 0 + + + GPIO_AD_B1_00_ALT0 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT0 + 0x1 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_03_ALT6 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + 0 + + + GPIO_AD_B0_12_ALT1 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + 0x1 + + + GPIO_AD_B1_01_ALT4 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + 0x2 + + + GPIO_AD_B1_08_ALT3 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + 0x3 + + + GPIO_EMC_32_ALT3 + Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + 0x4 + + + + + + + CSI_DATA02_SELECT_INPUT + CSI_DATA02_SELECT_INPUT DAISY Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_15_ALT4 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT4 + 0 + + + GPIO_AD_B0_11_ALT4 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA03_SELECT_INPUT + CSI_DATA03_SELECT_INPUT DAISY Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_14_ALT4 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT4 + 0 + + + GPIO_AD_B0_10_ALT4 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA04_SELECT_INPUT + CSI_DATA04_SELECT_INPUT DAISY Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_13_ALT4 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT4 + 0 + + + GPIO_AD_B0_09_ALT4 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA05_SELECT_INPUT + CSI_DATA05_SELECT_INPUT DAISY Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_12_ALT4 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT4 + 0 + + + GPIO_AD_B0_08_ALT4 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA06_SELECT_INPUT + CSI_DATA06_SELECT_INPUT DAISY Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_11_ALT4 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT4 + 0 + + + GPIO_AD_B0_07_ALT4 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA07_SELECT_INPUT + CSI_DATA07_SELECT_INPUT DAISY Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_10_ALT4 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT4 + 0 + + + GPIO_AD_B0_06_ALT4 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA08_SELECT_INPUT + CSI_DATA08_SELECT_INPUT DAISY Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_09_ALT4 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT4 + 0 + + + GPIO_AD_B0_05_ALT4 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA09_SELECT_INPUT + CSI_DATA09_SELECT_INPUT DAISY Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_08_ALT4 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT4 + 0 + + + GPIO_AD_B0_04_ALT4 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT4 + 0x1 + + + + + + + CSI_HSYNC_SELECT_INPUT + CSI_HSYNC_SELECT_INPUT DAISY Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT4 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_07_ALT4 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT4 + 0x1 + + + GPIO_B1_14_ALT2 + Selecting Pad: GPIO_B1_14 for Mode: ALT2 + 0x2 + + + + + + + CSI_PIXCLK_SELECT_INPUT + CSI_PIXCLK_SELECT_INPUT DAISY Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_04_ALT4 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT4 + 0 + + + GPIO_B1_12_ALT2 + Selecting Pad: GPIO_B1_12 for Mode: ALT2 + 0x1 + + + + + + + CSI_VSYNC_SELECT_INPUT + CSI_VSYNC_SELECT_INPUT DAISY Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_14_ALT4 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT4 + 0 + + + GPIO_AD_B1_06_ALT4 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT4 + 0x1 + + + GPIO_B1_13_ALT2 + Selecting Pad: GPIO_B1_13 for Mode: ALT2 + 0x2 + + + + + + + ENET_IPG_CLK_RMII_SELECT_INPUT + ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT4 + Selecting Pad: GPIO_EMC_25 for Mode: ALT4 + 0 + + + GPIO_B1_10_ALT6 + Selecting Pad: GPIO_B1_10 for Mode: ALT6 + 0x1 + + + + + + + ENET_MDIO_SELECT_INPUT + ENET_MDIO_SELECT_INPUT DAISY Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_05_ALT1 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT1 + 0 + + + GPIO_EMC_41_ALT4 + Selecting Pad: GPIO_EMC_41 for Mode: ALT4 + 0x1 + + + GPIO_B1_15_ALT0 + Selecting Pad: GPIO_B1_15 for Mode: ALT0 + 0x2 + + + + + + + ENET0_RXDATA_SELECT_INPUT + ENET0_RXDATA_SELECT_INPUT DAISY Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT3 + Selecting Pad: GPIO_EMC_20 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT3 + Selecting Pad: GPIO_B1_04 for Mode: ALT3 + 0x1 + + + + + + + ENET1_RXDATA_SELECT_INPUT + ENET1_RXDATA_SELECT_INPUT DAISY Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT3 + Selecting Pad: GPIO_EMC_19 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT3 + Selecting Pad: GPIO_B1_05 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXEN_SELECT_INPUT + ENET_RXEN_SELECT_INPUT DAISY Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT3 + Selecting Pad: GPIO_EMC_23 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT3 + Selecting Pad: GPIO_B1_06 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXERR_SELECT_INPUT + ENET_RXERR_SELECT_INPUT DAISY Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT3 + Selecting Pad: GPIO_EMC_26 for Mode: ALT3 + 0 + + + GPIO_B1_11_ALT3 + Selecting Pad: GPIO_B1_11 for Mode: ALT3 + 0x1 + + + + + + + ENET0_TIMER_SELECT_INPUT + ENET0_TIMER_SELECT_INPUT DAISY Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT3 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT3 + 0 + + + GPIO_AD_B0_11_ALT7 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT7 + 0x1 + + + GPIO_B1_12_ALT3 + Selecting Pad: GPIO_B1_12 for Mode: ALT3 + 0x2 + + + + + + + ENET_TXCLK_SELECT_INPUT + ENET_TXCLK_SELECT_INPUT DAISY Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT3 + Selecting Pad: GPIO_EMC_25 for Mode: ALT3 + 0 + + + GPIO_B1_10_ALT3 + Selecting Pad: GPIO_B1_10 for Mode: ALT3 + 0x1 + + + + + + + FLEXCAN1_RX_SELECT_INPUT + FLEXCAN1_RX_SELECT_INPUT DAISY Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT4 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT4 + 0 + + + GPIO_EMC_18_ALT3 + Selecting Pad: GPIO_EMC_18 for Mode: ALT3 + 0x1 + + + GPIO_AD_B1_09_ALT2 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT2 + 0x2 + + + GPIO_B0_03_ALT2 + Selecting Pad: GPIO_B0_03 for Mode: ALT2 + 0x3 + + + + + + + FLEXCAN2_RX_SELECT_INPUT + FLEXCAN2_RX_SELECT_INPUT DAISY Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_10_ALT3 + Selecting Pad: GPIO_EMC_10 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT0 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT0 + 0x1 + + + GPIO_AD_B0_15_ALT6 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT6 + 0x2 + + + GPIO_B1_09_ALT6 + Selecting Pad: GPIO_B1_09 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM1_PWMA3_SELECT_INPUT + FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_00_ALT2 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2 + 0 + + + GPIO_EMC_12_ALT4 + Selecting Pad: GPIO_EMC_12 for Mode: ALT4 + 0x1 + + + GPIO_EMC_38_ALT1 + Selecting Pad: GPIO_EMC_38 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_10_ALT1 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT1 + 0x3 + + + GPIO_B1_00_ALT6 + Selecting Pad: GPIO_B1_00 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMA0_SELECT_INPUT + FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT1 + Selecting Pad: GPIO_EMC_23 for Mode: ALT1 + 0 + + + GPIO_SD_B0_00_ALT1 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA1_SELECT_INPUT + FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT1 + Selecting Pad: GPIO_EMC_25 for Mode: ALT1 + 0 + + + GPIO_SD_B0_02_ALT1 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA2_SELECT_INPUT + FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT1 + Selecting Pad: GPIO_EMC_27 for Mode: ALT1 + 0 + + + GPIO_SD_B0_04_ALT1 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB3_SELECT_INPUT + FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_01_ALT2 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT4 + Selecting Pad: GPIO_EMC_13 for Mode: ALT4 + 0x1 + + + GPIO_EMC_39_ALT1 + Selecting Pad: GPIO_EMC_39 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_11_ALT1 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT1 + 0x3 + + + GPIO_B1_01_ALT6 + Selecting Pad: GPIO_B1_01 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMB0_SELECT_INPUT + FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT1 + Selecting Pad: GPIO_EMC_24 for Mode: ALT1 + 0 + + + GPIO_SD_B0_01_ALT1 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB1_SELECT_INPUT + FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT1 + Selecting Pad: GPIO_EMC_26 for Mode: ALT1 + 0 + + + GPIO_SD_B0_03_ALT1 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB2_SELECT_INPUT + FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT1 + Selecting Pad: GPIO_EMC_28 for Mode: ALT1 + 0 + + + GPIO_SD_B0_05_ALT1 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM2_PWMA3_SELECT_INPUT + FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_02_ALT2 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2 + 0 + + + GPIO_EMC_19_ALT1 + Selecting Pad: GPIO_EMC_19 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_00_ALT0 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT0 + 0x2 + + + GPIO_AD_B0_09_ALT1 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT1 + 0x3 + + + GPIO_B1_02_ALT6 + Selecting Pad: GPIO_B1_02 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM2_PWMA0_SELECT_INPUT + FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT1 + Selecting Pad: GPIO_EMC_06 for Mode: ALT1 + 0 + + + GPIO_B0_06_ALT2 + Selecting Pad: GPIO_B0_06 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA1_SELECT_INPUT + FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT1 + Selecting Pad: GPIO_EMC_08 for Mode: ALT1 + 0 + + + GPIO_B0_08_ALT2 + Selecting Pad: GPIO_B0_08 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA2_SELECT_INPUT + FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT1 + Selecting Pad: GPIO_EMC_10 for Mode: ALT1 + 0 + + + GPIO_B0_10_ALT2 + Selecting Pad: GPIO_B0_10 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB3_SELECT_INPUT + FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register + 0x484 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT2 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2 + 0 + + + GPIO_EMC_20_ALT1 + Selecting Pad: GPIO_EMC_20 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_01_ALT0 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT0 + 0x2 + + + GPIO_B1_03_ALT6 + Selecting Pad: GPIO_B1_03 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM2_PWMB0_SELECT_INPUT + FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT1 + Selecting Pad: GPIO_EMC_07 for Mode: ALT1 + 0 + + + GPIO_B0_07_ALT2 + Selecting Pad: GPIO_B0_07 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB1_SELECT_INPUT + FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register + 0x48C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT1 + Selecting Pad: GPIO_EMC_09 for Mode: ALT1 + 0 + + + GPIO_B0_09_ALT2 + Selecting Pad: GPIO_B0_09 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB2_SELECT_INPUT + FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT1 + Selecting Pad: GPIO_EMC_11 for Mode: ALT1 + 0 + + + GPIO_B0_11_ALT2 + Selecting Pad: GPIO_B0_11 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM4_PWMA0_SELECT_INPUT + FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT1 + Selecting Pad: GPIO_EMC_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_08_ALT1 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA1_SELECT_INPUT + FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register + 0x498 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT1 + Selecting Pad: GPIO_EMC_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT1 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA2_SELECT_INPUT + FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register + 0x49C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT1 + Selecting Pad: GPIO_EMC_04 for Mode: ALT1 + 0 + + + GPIO_B1_14_ALT1 + Selecting Pad: GPIO_B1_14 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA3_SELECT_INPUT + FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_17_ALT1 + Selecting Pad: GPIO_EMC_17 for Mode: ALT1 + 0 + + + GPIO_B1_15_ALT1 + Selecting Pad: GPIO_B1_15 for Mode: ALT1 + 0x1 + + + + + + + FLEXSPI_A_DQS_SELECT_INPUT + FLEXSPI_A_DQS_SELECT_INPUT DAISY Register + 0x4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT1 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT0 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_A_DATA0_SELECT_INPUT + FLEXSPI_A_DATA0_SELECT_INPUT DAISY Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT1 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT1 + 0 + + + GPIO_AD_B1_13_ALT0 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_A_DATA1_SELECT_INPUT + FLEXSPI_A_DATA1_SELECT_INPUT DAISY Register + 0x4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT1 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT1 + 0 + + + GPIO_AD_B1_12_ALT0 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_A_DATA2_SELECT_INPUT + FLEXSPI_A_DATA2_SELECT_INPUT DAISY Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT1 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT1 + 0 + + + GPIO_AD_B1_11_ALT0 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_A_DATA3_SELECT_INPUT + FLEXSPI_A_DATA3_SELECT_INPUT DAISY Register + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT1 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT1 + 0 + + + GPIO_AD_B1_10_ALT0 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_B_DATA0_SELECT_INPUT + FLEXSPI_B_DATA0_SELECT_INPUT DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT1 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT1 + 0 + + + GPIO_AD_B1_07_ALT0 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_B_DATA1_SELECT_INPUT + FLEXSPI_B_DATA1_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT1 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_06_ALT0 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_B_DATA2_SELECT_INPUT + FLEXSPI_B_DATA2_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT1 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT1 + 0 + + + GPIO_AD_B1_05_ALT0 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_B_DATA3_SELECT_INPUT + FLEXSPI_B_DATA3_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT1 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_04_ALT0 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI_A_SCK_SELECT_INPUT + FLEXSPI_A_SCK_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT1 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT1 + 0 + + + GPIO_AD_B1_14_ALT0 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT0 + 0x1 + + + + + + + LPI2C1_SCL_SELECT_INPUT + LPI2C1_SCL_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT2 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_00_ALT3 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT3 + 0x1 + + + + + + + LPI2C1_SDA_SELECT_INPUT + LPI2C1_SDA_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT2 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_01_ALT3 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT3 + 0x1 + + + + + + + LPI2C2_SCL_SELECT_INPUT + LPI2C2_SCL_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT3 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT3 + 0 + + + GPIO_B0_04_ALT2 + Selecting Pad: GPIO_B0_04 for Mode: ALT2 + 0x1 + + + + + + + LPI2C2_SDA_SELECT_INPUT + LPI2C2_SDA_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT3 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT3 + 0 + + + GPIO_B0_05_ALT2 + Selecting Pad: GPIO_B0_05 for Mode: ALT2 + 0x1 + + + + + + + LPI2C3_SCL_SELECT_INPUT + LPI2C3_SCL_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_22_ALT2 + Selecting Pad: GPIO_EMC_22 for Mode: ALT2 + 0 + + + GPIO_SD_B0_00_ALT2 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_07_ALT1 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT1 + 0x2 + + + + + + + LPI2C3_SDA_SELECT_INPUT + LPI2C3_SDA_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_21_ALT2 + Selecting Pad: GPIO_EMC_21 for Mode: ALT2 + 0 + + + GPIO_SD_B0_01_ALT2 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_06_ALT1 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT1 + 0x2 + + + + + + + LPI2C4_SCL_SELECT_INPUT + LPI2C4_SCL_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT2 + Selecting Pad: GPIO_EMC_12 for Mode: ALT2 + 0 + + + GPIO_AD_B0_12_ALT0 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT0 + 0x1 + + + + + + + LPI2C4_SDA_SELECT_INPUT + LPI2C4_SDA_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT2 + Selecting Pad: GPIO_EMC_11 for Mode: ALT2 + 0 + + + GPIO_AD_B0_13_ALT0 + Selecting Pad: GPIO_AD_B0_13 for Mode: ALT0 + 0x1 + + + + + + + LPSPI1_PCS0_SELECT_INPUT + LPSPI1_PCS0_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B0_01_ALT4 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT4 + 0 + + + GPIO_EMC_30_ALT3 + Selecting Pad: GPIO_EMC_30 for Mode: ALT3 + 0x1 + + + + + + + LPSPI1_SCK_SELECT_INPUT + LPSPI1_SCK_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT3 + Selecting Pad: GPIO_EMC_27 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT4 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDI_SELECT_INPUT + LPSPI1_SDI_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_29_ALT3 + Selecting Pad: GPIO_EMC_29 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT4 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDO_SELECT_INPUT + LPSPI1_SDO_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT3 + Selecting Pad: GPIO_EMC_28 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT4 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT4 + 0x1 + + + + + + + LPSPI2_PCS0_SELECT_INPUT + LPSPI2_PCS0_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_06_ALT4 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT4 + 0 + + + GPIO_EMC_01_ALT2 + Selecting Pad: GPIO_EMC_01 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SCK_SELECT_INPUT + LPSPI2_SCK_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT4 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT4 + 0 + + + GPIO_EMC_00_ALT2 + Selecting Pad: GPIO_EMC_00 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDI_SELECT_INPUT + LPSPI2_SDI_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT4 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT4 + 0 + + + GPIO_EMC_03_ALT2 + Selecting Pad: GPIO_EMC_03 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDO_SELECT_INPUT + LPSPI2_SDO_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT4 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT4 + 0 + + + GPIO_EMC_02_ALT2 + Selecting Pad: GPIO_EMC_02 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_PCS0_SELECT_INPUT + LPSPI3_PCS0_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT7 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT7 + 0 + + + GPIO_AD_B1_12_ALT2 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SCK_SELECT_INPUT + LPSPI3_SCK_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT7 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT7 + 0 + + + GPIO_AD_B1_15 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDI_SELECT_INPUT + LPSPI3_SDI_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT7 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT7 + 0 + + + GPIO_AD_B1_13_ALT2 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDO_SELECT_INPUT + LPSPI3_SDO_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT7 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT7 + 0 + + + GPIO_AD_B1_14_ALT2 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT2 + 0x1 + + + + + + + LPSPI4_PCS0_SELECT_INPUT + LPSPI4_PCS0_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_00_ALT3 + Selecting Pad: GPIO_B0_00 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT1 + Selecting Pad:GPIO_B1_04 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SCK_SELECT_INPUT + LPSPI4_SCK_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_03_ALT3 + Selecting Pad: GPIO_B0_03 for Mode: ALT3 + 0 + + + GPIO_B1_07_ALT1 + Selecting Pad: GPIO_B1_07 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDI_SELECT_INPUT + LPSPI4_SDI_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_01_ALT3 + Selecting Pad: GPIO_B0_01 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT1 + Selecting Pad: GPIO_B1_05 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDO_SELECT_INPUT + LPSPI4_SDO_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_02_ALT3 + Selecting Pad: GPIO_B0_02 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT1 + Selecting Pad: GPIO_B1_06 for Mode: ALT1 + 0x1 + + + + + + + LPUART2_RX_SELECT_INPUT + LPUART2_RX_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT2 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT2 + 0 + + + GPIO_AD_B1_03_ALT2 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART2_TX_SELECT_INPUT + LPUART2_TX_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT2 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT2 + 0 + + + GPIO_AD_B1_02_ALT2 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_CTS_B_SELECT_INPUT + LPUART3_CTS_B_SELECT_INPUT DAISY Register + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT2 + Selecting Pad: GPIO_EMC_15 for Mode: ALT2 + 0 + + + GPIO_AD_B1_04_ALT2 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_RX_SELECT_INPUT + LPUART3_RX_SELECT_INPUT DAISY Register + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_07_ALT2 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT2 + 0 + + + GPIO_EMC_14_ALT2 + Selecting Pad: GPIO_EMC_14 for Mode: ALT2 + 0x1 + + + GPIO_B0_09_ALT3 + Selecting Pad: GPIO_B0_09 for Mode: ALT3 + 0x2 + + + + + + + LPUART3_TX_SELECT_INPUT + LPUART3_TX_SELECT_INPUT DAISY Register + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_06_ALT2 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT2 + Selecting Pad: GPIO_EMC_13 for Mode: ALT2 + 0x1 + + + GPIO_B0_08_ALT3 + Selecting Pad: GPIO_B0_08 for Mode: ALT3 + 0x2 + + + + + + + LPUART4_RX_SELECT_INPUT + LPUART4_RX_SELECT_INPUT DAISY Register + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_01_ALT4 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT4 + 0 + + + GPIO_EMC_20_ALT2 + Selecting Pad: GPIO_EMC_20 for Mode: ALT2 + 0x1 + + + GPIO_B1_01_ALT2 + Selecting Pad: GPIO_B1_01 for Mode: ALT2 + 0x2 + + + + + + + LPUART4_TX_SELECT_INPUT + LPUART4_TX_SELECT_INPUT DAISY Register + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_00_ALT4 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT4 + 0 + + + GPIO_EMC_19_ALT2 + Selecting Pad: GPIO_EMC_19 for Mode: ALT2 + 0x1 + + + GPIO_B1_00_ALT2 + Selecting Pad: GPIO_B1_00 for Mode: ALT2 + 0x2 + + + + + + + LPUART5_RX_SELECT_INPUT + LPUART5_RX_SELECT_INPUT DAISY Register + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT2 + Selecting Pad: GPIO_EMC_24 for Mode: ALT2 + 0 + + + GPIO_B1_13_ALT1 + Selecting Pad: GPIO_B1_13 for Mode: ALT1 + 0x1 + + + + + + + LPUART5_TX_SELECT_INPUT + LPUART5_TX_SELECT_INPUT DAISY Register + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT2 + Selecting Pad: GPIO_EMC_23 for Mode: ALT2 + 0 + + + GPIO_B1_12_ALT1 + Selecting Pad: GPIO_B1_12 for Mode: ALT1 + 0x1 + + + + + + + LPUART6_RX_SELECT_INPUT + LPUART6_RX_SELECT_INPUT DAISY Register + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT2 + Selecting Pad: GPIO_EMC_26 for Mode: ALT2 + 0 + + + GPIO_AD_B0_03_ALT2 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART6_TX_SELECT_INPUT + LPUART6_TX_SELECT_INPUT DAISY Register + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT2 + Selecting Pad: GPIO_EMC_25 for Mode: ALT2 + 0 + + + GPIO_AD_B0_02_ALT2 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_RX_SELECT_INPUT + LPUART7_RX_SELECT_INPUT DAISY Register + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT2 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT2 + 0 + + + GPIO_EMC_32_ALT2 + Selecting Pad: GPIO_EMC_32 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_TX_SELECT_INPUT + LPUART7_TX_SELECT_INPUT DAISY Register + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT2 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT2 + 0 + + + GPIO_EMC_31_ALT2 + Selecting Pad:GPIO_EMC_31 for Mode: ALT2 + 0x1 + + + + + + + LPUART8_RX_SELECT_INPUT + LPUART8_RX_SELECT_INPUT DAISY Register + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_05_ALT2 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_11_ALT2 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT2 + 0x1 + + + GPIO_EMC_39_ALT2 + Selecting Pad: GPIO_EMC_39 for Mode: ALT2 + 0x2 + + + + + + + LPUART8_TX_SELECT_INPUT + LPUART8_TX_SELECT_INPUT DAISY Register + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_04_ALT2 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_10_ALT2 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT2 + 0x1 + + + GPIO_EMC_38_ALT2 + Selecting Pad: GPIO_EMC_38 for Mode: ALT2 + 0x2 + + + + + + + NMI_SELECT_INPUT + NMI_SELECT_INPUT DAISY Register + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_12_ALT7 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7 + 0 + + + WAKEUP_ALT7 + Selecting Pad: WAKEUP for Mode: ALT7 + 0x1 + + + + + + + QTIMER2_TIMER0_SELECT_INPUT + QTIMER2_TIMER0_SELECT_INPUT DAISY Register + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT4 + Selecting Pad: GPIO_EMC_19 for Mode: ALT4 + 0 + + + GPIO_B0_03_ALT1 + Selecting Pad: GPIO_B0_03 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER1_SELECT_INPUT + QTIMER2_TIMER1_SELECT_INPUT DAISY Register + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT4 + Selecting Pad: GPIO_EMC_20 for Mode: ALT4 + 0 + + + GPIO_B0_04_ALT1 + Selecting Pad: GPIO_B0_04 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER2_SELECT_INPUT + QTIMER2_TIMER2_SELECT_INPUT DAISY Register + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_21_ALT4 + Selecting Pad: GPIO_EMC_21 for Mode: ALT4 + 0 + + + GPIO_B0_05_ALT1 + Selecting Pad: GPIO_B0_05 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER3_SELECT_INPUT + QTIMER2_TIMER3_SELECT_INPUT DAISY Register + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_22_ALT4 + Selecting Pad: GPIO_EMC_22 for Mode: ALT4 + 0 + + + GPIO_B1_09_ALT1 + Selecting Pad: GPIO_B1_09 for Mode: ALT1 + 0x1 + + + + + + + QTIMER3_TIMER0_SELECT_INPUT + QTIMER3_TIMER0_SELECT_INPUT DAISY Register + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_15_ALT4 + Selecting Pad: GPIO_EMC_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_00_ALT1 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT1 + 0x1 + + + GPIO_B0_06_ALT1 + Selecting Pad: GPIO_B0_06 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER1_SELECT_INPUT + QTIMER3_TIMER1_SELECT_INPUT DAISY Register + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_01_ALT1 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT1 + 0 + + + GPIO_EMC_16_ALT4 + Selecting Pad: GPIO_EMC_16 for Mode: ALT4 + 0x1 + + + GPIO_B0_07_ALT1 + Selecting Pad: GPIO_B0_07 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER2_SELECT_INPUT + QTIMER3_TIMER2_SELECT_INPUT DAISY Register + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_17_ALT4 + Selecting Pad: GPIO_EMC_17 for Mode: ALT4 + 0 + + + GPIO_AD_B1_02_ALT1 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT1 + 0x1 + + + GPIO_B0_08_ALT1 + Selecting Pad: GPIO_B0_08 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER3_SELECT_INPUT + QTIMER3_TIMER3_SELECT_INPUT DAISY Register + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_18_ALT4 + Selecting Pad: GPIO_EMC_18 for Mode: ALT4 + 0 + + + GPIO_AD_B1_03_ALT1 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT1 + 0x1 + + + GPIO_B1_10_ALT1 + Selecting Pad: GPIO_B1_10 for Mode: ALT1 + 0x2 + + + + + + + SAI1_MCLK2_SELECT_INPUT + SAI1_MCLK2_SELECT_INPUT DAISY Register + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT3 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_09_ALT3 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT3 + 0x1 + + + GPIO_B0_13_ALT3 + Selecting Pad: GPIO_B0_13 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_BCLK_SELECT_INPUT + SAI1_RX_BCLK_SELECT_INPUT DAISY Register + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_05_ALT3 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT3 + 0 + + + GPIO_AD_B1_11_ALT3 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT3 + 0x1 + + + GPIO_B0_15_ALT3 + Selecting Pad: GPIO_B0_15 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA0_SELECT_INPUT + SAI1_RX_DATA0_SELECT_INPUT DAISY Register + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_06_ALT3 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT3 + 0 + + + GPIO_AD_B1_12_ALT3 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT3 + 0x1 + + + GPIO_B1_00_ALT3 + Selecting Pad: GPIO_B1_00 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA1_SELECT_INPUT + SAI1_RX_DATA1_SELECT_INPUT DAISY Register + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT3 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT3 + 0 + + + GPIO_B0_10_ALT3 + Selecting Pad: GPIO_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA2_SELECT_INPUT + SAI1_RX_DATA2_SELECT_INPUT DAISY Register + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT3 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT3 + 0 + + + GPIO_B0_11_ALT3 + Selecting Pad: GPIO_B0_11 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA3_SELECT_INPUT + SAI1_RX_DATA3_SELECT_INPUT DAISY Register + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT3 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT3 + 0 + + + GPIO_B0_12_ALT3 + Selecting Pad: GPIO_B0_12 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_SYNC_SELECT_INPUT + SAI1_RX_SYNC_SELECT_INPUT DAISY Register + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_04_ALT3 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT3 + 0 + + + GPIO_AD_B1_10_ALT3 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT3 + 0x1 + + + GPIO_B0_14_ALT3 + Selecting Pad: GPIO_B0_14 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_08_ALT3 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT3 + 0 + + + GPIO_AD_B1_14_ALT3 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT3 + 0x1 + + + GPIO_B1_02_ALT3 + Selecting Pad: GPIO_B1_02 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_09_ALT3 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT3 + 0 + + + GPIO_AD_B1_15_ALT3 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT3 + 0x1 + + + GPIO_B1_03_ALT3 + Selecting Pad: GPIO_B1_03 for Mode: ALT3 + 0x2 + + + + + + + SAI2_MCLK2_SELECT_INPUT + SAI2_MCLK2_SELECT_INPUT DAISY Register + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT2 + Selecting Pad: GPIO_EMC_07 for Mode: ALT2 + 0 + + + GPIO_AD_B0_10_ALT3 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_BCLK_SELECT_INPUT + SAI2_RX_BCLK_SELECT_INPUT DAISY Register + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT2 + Selecting Pad: GPIO_EMC_10 for Mode: ALT2 + 0 + + + GPIO_AD_B0_06_ALT3 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_DATA0_SELECT_INPUT + SAI2_RX_DATA0_SELECT_INPUT DAISY Register + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT2 + Selecting Pad: GPIO_EMC_08 for Mode: ALT2 + 0 + + + GPIO_AD_B0_08_ALT3 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_SYNC_SELECT_INPUT + SAI2_RX_SYNC_SELECT_INPUT DAISY Register + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT2 + Selecting Pad: GPIO_EMC_09 for Mode: ALT2 + 0 + + + GPIO_AD_B0_07_ALT3 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_BCLK_SELECT_INPUT + SAI2_TX_BCLK_SELECT_INPUT DAISY Register + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT2 + Selecting Pad: GPIO_EMC_06 for Mode: ALT2 + 0 + + + GPIO_AD_B0_05_ALT3 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_SYNC_SELECT_INPUT + SAI2_TX_SYNC_SELECT_INPUT DAISY Register + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT2 + Selecting Pad: GPIO_EMC_05 for Mode: ALT2 + 0 + + + GPIO_AD_B0_04_ALT3 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + SPDIF_IN_SELECT_INPUT + SPDIF_IN_SELECT_INPUT DAISY Register + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT3 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT3 + 0 + + + GPIO_EMC_16_ALT3 + Selecting Pad: GPIO_EMC_16 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG2_OC_SELECT_INPUT + USB_OTG2_OC_SELECT_INPUT DAISY Register + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_14_ALT0 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT0 + 0 + + + GPIO_EMC_40_ALT3 + Selecting Pad: GPIO_EMC_40 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG1_OC_SELECT_INPUT + USB_OTG1_OC_SELECT_INPUT DAISY Register + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT3 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_03_ALT0 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT0 + 0x1 + + + + + + + USDHC1_CD_B_SELECT_INPUT + USDHC1_CD_B_SELECT_INPUT DAISY Register + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_35_ALT6 + Selecting Pad: GPIO_EMC_35 for Mode: ALT6 + 0 + + + GPIO_AD_B1_02_ALT6 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT6 + 0x1 + + + GPIO_B1_12_ALT6 + Selecting Pad: GPIO_B1_12 for Mode: ALT6 + 0x2 + + + + + + + USDHC1_WP_SELECT_INPUT + USDHC1_WP_SELECT_INPUT DAISY Register + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_12_ALT3 + Selecting Pad: GPIO_EMC_12 for Mode: ALT3 + 0 + + + GPIO_EMC_36_ALT6 + Selecting Pad: GPIO_EMC_36for Mode: ALT6 + 0x1 + + + GPIO_AD_B1_00_ALT6 + Selecting Pad:GPIO_AD_B1_00 for Mode: ALT6 + 0x2 + + + GPIO_B1_13_ALT6 + Selecting Pad: GPIO_B1_13 for Mode: ALT6 + 0x3 + + + + + + + USDHC2_CLK_SELECT_INPUT + USDHC2_CLK_SELECT_INPUT DAISY Register + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT0 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT0 + 0 + + + GPIO_AD_B1_09_ALT6 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CD_B_SELECT_INPUT + USDHC2_CD_B_SELECT_INPUT DAISY Register + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT6 + Selecting Pad:GPIO_AD_B1_03 for Mode: ALT6 + 0 + + + GPIO_EMC_39_ALT6 + Selecting Pad: GPIO_EMC_39 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CMD_SELECT_INPUT + USDHC2_CMD_SELECT_INPUT DAISY Register + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT0 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT0 + 0 + + + GPIO_AD_B1_08_ALT6 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA0_SELECT_INPUT + USDHC2_DATA0_SELECT_INPUT DAISY Register + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT0 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT0 + 0 + + + GPIO_AD_B1_04_ALT6 + Selecting Pad:GPIO_AD_B1_04 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA1_SELECT_INPUT + USDHC2_DATA1_SELECT_INPUT DAISY Register + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT0 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT0 + 0 + + + GPIO_AD_B1_05_ALT6 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA2_SELECT_INPUT + USDHC2_DATA2_SELECT_INPUT DAISY Register + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT0 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT0 + 0 + + + GPIO_AD_B1_06_ALT6 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA3_SELECT_INPUT + USDHC2_DATA3_SELECT_INPUT DAISY Register + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT0 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT0 + 0 + + + GPIO_AD_B1_07_ALT6 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA4_SELECT_INPUT + USDHC2_DATA4_SELECT_INPUT DAISY Register + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT0 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT0 + 0 + + + GPIO_AD_B1_12_ALT6 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA5_SELECT_INPUT + USDHC2_DATA5_SELECT_INPUT DAISY Register + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT0 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT0 + 0 + + + GPIO_AD_B1_13_ALT6 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA6_SELECT_INPUT + USDHC2_DATA6_SELECT_INPUT DAISY Register + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT0 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT0 + 0 + + + GPIO_AD_B1_14_ALT6 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA7_SELECT_INPUT + USDHC2_DATA7_SELECT_INPUT DAISY Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT0 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT0 + 0 + + + GPIO_AD_B1_15_ALT6 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_WP_SELECT_INPUT + USDHC2_WP_SELECT_INPUT DAISY Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT6 + Selecting Pad: GPIO_EMC_37 for Mode: ALT6 + 0 + + + GPIO_AD_B1_10_ALT6 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT02_SELECT_INPUT + XBAR_INOUT02_SELECT_INPUT DAISY Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT3 + Selecting Pad: GPIO_EMC_00 for Mode: ALT3 + 0 + + + GPIO_B1_14_ALT3 + Selecting Pad: GPIO_B1_14 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT03_SELECT_INPUT + XBAR_INOUT03_SELECT_INPUT DAISY Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_01_ALT3 + Selecting Pad: GPIO_EMC_01 for Mode: ALT3 + 0 + + + GPIO_B1_15_ALT3 + Selecting Pad: GPIO_B1_15 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT04_SELECT_INPUT + XBAR_INOUT04_SELECT_INPUT DAISY Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT3 + Selecting Pad: GPIO_EMC_02 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT3 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT05_SELECT_INPUT + XBAR_INOUT05_SELECT_INPUT DAISY Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_03_ALT3 + Selecting Pad: GPIO_EMC_03 for Mode: ALT3 + 0 + + + GPIO_SD_B0_01_ALT3 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT06_SELECT_INPUT + XBAR_INOUT06_SELECT_INPUT DAISY Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT3 + Selecting Pad: GPIO_EMC_04 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT3 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT07_SELECT_INPUT + XBAR_INOUT07_SELECT_INPUT DAISY Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT3 + Selecting Pad: GPIO_EMC_05 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT3 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT08_SELECT_INPUT + XBAR_INOUT08_SELECT_INPUT DAISY Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT3 + Selecting Pad: GPIO_EMC_06 for Mode: ALT3 + 0 + + + GPIO_SD_B0_04_ALT3 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT09_SELECT_INPUT + XBAR_INOUT09_SELECT_INPUT DAISY Register + 0x628 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT3 + Selecting Pad: GPIO_EMC_07 for Mode: ALT3 + 0 + + + GPIO_SD_B0_05_ALT3 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + XBAR_INOUT17_SELECT_INPUT + XBAR_INOUT17_SELECT_INPUT DAISY Register + 0x62C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_08_ALT3 + Selecting Pad: GPIO_EMC_08 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT1 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_05_ALT6 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6 + 0x2 + + + GPIO_B1_03_ALT1 + Selecting Pad: GPIO_B1_03 for Mode: ALT1 + 0x3 + + + + + + + XBAR_INOUT18_SELECT_INPUT + XBAR_INOUT18_SELECT_INPUT DAISY Register + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_35_ALT1 + Selecting Pad: GPIO_EMC_35 for Mode: ALT1 + 0 + + + GPIO_AD_B0_06_ALT6 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT20_SELECT_INPUT + XBAR_INOUT20_SELECT_INPUT DAISY Register + 0x634 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT1 + Selecting Pad: GPIO_EMC_15 for Mode: ALT1 + 0 + + + GPIO_AD_B0_08_ALT6 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT22_SELECT_INPUT + XBAR_INOUT22_SELECT_INPUT DAISY Register + 0x638 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_36_ALT1 + Selecting Pad: GPIO_EMC_36 for Mode: ALT1 + 0 + + + GPIO_AD_B0_10_ALT6 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT23_SELECT_INPUT + XBAR_INOUT23_SELECT_INPUT DAISY Register + 0x63C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT1 + Selecting Pad: GPIO_EMC_37 for Mode: ALT1 + 0 + + + GPIO_AD_B0_11_ALT6 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT24_SELECT_INPUT + XBAR_INOUT24_SELECT_INPUT DAISY Register + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT1 + Selecting Pad: GPIO_EMC_12 for Mode: ALT1 + 0 + + + GPIO_AD_B0_14_ALT1 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT1 + 0x1 + + + + + + + XBAR_INOUT14_SELECT_INPUT + XBAR_INOUT14_SELECT_INPUT DAISY Register + 0x644 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT1 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT1 + 0 + + + GPIO_B1_00_ALT1 + Selecting Pad:GPIO_B1_00 for Mode: ALT1 + 0x1 + + + + + + + XBAR_INOUT15_SELECT_INPUT + XBAR_INOUT15_SELECT_INPUT DAISY Register + 0x648 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT1 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT1 + 0 + + + GPIO_B1_01_ALT1 + Selecting Pad: GPIO_B1_01 for Mode: ALT1 + 0x1 + + + + + + + XBAR_INOUT16_SELECT_INPUT + XBAR_INOUT16_SELECT_INPUT DAISY Register + 0x64C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT1 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT1 + 0 + + + GPIO_B1_02_ALT1 + Selecting Pad: GPIO_B1_02 for Mode: ALT1 + 0x1 + + + + + + + XBAR_INOUT25_SELECT_INPUT + XBAR_INOUT25_SELECT_INPUT DAISY Register + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_15_ALT1 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT1 + 0 + + + GPIO_EMC_13_ALT1 + Selecting Pad: GPIO_EMC_13 for Mode: ALT1 + 0x1 + + + + + + + XBAR_INOUT19_SELECT_INPUT + XBAR_INOUT19_SELECT_INPUT DAISY Register + 0x654 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_14_ALT1 + Selecting Pad: GPIO_EMC_14 for Mode: ALT1 + 0 + + + GPIO_AD_B0_07_ALT6 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT6 + 0x1 + + + + + + + XBAR_INOUT21_SELECT_INPUT + XBAR_INOUT23_SELECT_INPUT DAISY Register + 0x658 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_16_ALT1 + Selecting Pad: GPIO_EMC_16 for Mode: ALT1 + 0 + + + GPIO_AD_B0_09_ALT6 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT6 + 0x1 + + + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x401FC000 + + 0 + 0x8 + registers + + + KPP + 39 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 2 + 1 + read-write + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 3 + 1 + read-write + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 8 + 8 + read-write + + + + + + + FLEXSPI + FlexSPI + FLEXSPI + 0x402A8000 + + 0 + 0x300 + registers + + + FLEXSPI + 108 + + + + MCR0 + Module Control Register 0 + 0 + 32 + read-write + 0xFFFF80C2 + 0xFFFFFFFF + + + SWRESET + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + RXCLKSRC + Sample Clock source selection for Flash Reading + 4 + 2 + read-write + + + RXCLKSRC_0 + Dummy Read strobe generated by FlexSPI Controller and loopback internally. + 0 + + + RXCLKSRC_1 + Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + 0x1 + + + RXCLKSRC_3 + Flash provided Read strobe and input from DQS pad + 0x3 + + + + + ARDFEN + Enable AHB bus Read Access to IP RX FIFO. + 6 + 1 + read-write + + + ARDFEN_0 + IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + 0 + + + ARDFEN_1 + IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + 0x1 + + + + + ATDFEN + Enable AHB bus Write Access to IP TX FIFO. + 7 + 1 + read-write + + + ATDFEN_0 + IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + 0 + + + ATDFEN_1 + IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + 0x1 + + + + + SERCLKDIV + The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. + 8 + 3 + read-write + + + SERCLKDIV_0 + Divided by 1 + 0 + + + SERCLKDIV_1 + Divided by 2 + 0x1 + + + SERCLKDIV_2 + Divided by 3 + 0x2 + + + SERCLKDIV_3 + Divided by 4 + 0x3 + + + SERCLKDIV_4 + Divided by 5 + 0x4 + + + SERCLKDIV_5 + Divided by 6 + 0x5 + + + SERCLKDIV_6 + Divided by 7 + 0x6 + + + SERCLKDIV_7 + Divided by 8 + 0x7 + + + + + HSEN + Half Speed Serial Flash access Enable. + 11 + 1 + read-write + + + HSEN_0 + Disable divide by 2 of serial flash clock for half speed commands. + 0 + + + HSEN_1 + Enable divide by 2 of serial flash clock for half speed commands. + 0x1 + + + + + DOZEEN + Doze mode enable bit + 12 + 1 + read-write + + + DOZEEN_0 + Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + 0 + + + DOZEEN_1 + Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + 0x1 + + + + + COMBINATIONEN + This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). + 13 + 1 + read-write + + + COMBINATIONEN_0 + Disable. + 0 + + + COMBINATIONEN_1 + Enable. + 0x1 + + + + + SCKFREERUNEN + This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). + 14 + 1 + read-write + + + SCKFREERUNEN_0 + Disable. + 0 + + + SCKFREERUNEN_1 + Enable. + 0x1 + + + + + IPGRANTWAIT + Time out wait cycle for IP command grant. + 16 + 8 + read-write + + + AHBGRANTWAIT + Timeout wait cycle for AHB command grant. + 24 + 8 + read-write + + + + + MCR1 + Module Control Register 1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + AHBBUSWAIT + AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response + 0 + 16 + read-write + + + SEQWAIT + Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles + 16 + 16 + read-write + + + + + MCR2 + Module Control Register 2 + 0x8 + 32 + read-write + 0x200081F7 + 0xFFFFFFFF + + + CLRAHBBUFOPT + This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + 11 + 1 + read-write + + + CLRAHBBUFOPT_0 + AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + 0 + + + CLRAHBBUFOPT_1 + AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + 0x1 + + + + + CLRLEARNPHASE + The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. + 14 + 1 + read-write + + + SAMEDEVICEEN + All external devices are same devices (both in types and size) for A1/A2/B1/B2. + 15 + 1 + read-write + + + SAMEDEVICEEN_0 + In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + 0 + + + SAMEDEVICEEN_1 + FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + 0x1 + + + + + SCKBDIFFOPT + B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. + 19 + 1 + read-write + + + SCKBDIFFOPT_0 + B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. + 0 + + + SCKBDIFFOPT_1 + B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. + 0x1 + + + + + RESUMEWAIT + Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + 24 + 8 + read-write + + + + + AHBCR + AHB Bus Control Register + 0xC + 32 + read-write + 0x18 + 0xFFFFFFFF + + + APAREN + Parallel mode enabled for AHB triggered Command (both read and write) . + 0 + 1 + read-write + + + APAREN_0 + Flash will be accessed in Individual mode. + 0 + + + APAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + CACHABLEEN + Enable AHB bus cachable read access support. + 3 + 1 + read-write + + + CACHABLEEN_0 + Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + 0 + + + CACHABLEEN_1 + Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + 0x1 + + + + + BUFFERABLEEN + Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + 4 + 1 + read-write + + + BUFFERABLEEN_0 + Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + 0 + + + BUFFERABLEEN_1 + Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + 0x1 + + + + + PREFETCHEN + AHB Read Prefetch Enable. + 5 + 1 + read-write + + + READADDROPT + AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + 6 + 1 + read-write + + + READADDROPT_0 + There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + 0 + + + READADDROPT_1 + There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. + 0x1 + + + + + + + INTEN + Interrupt Enable Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP triggered Command Sequences Execution finished interrupt enable. + 0 + 1 + read-write + + + IPCMDGEEN + IP triggered Command Sequences Grant Timeout interrupt enable. + 1 + 1 + read-write + + + AHBCMDGEEN + AHB triggered Command Sequences Grant Timeout interrupt enable. + 2 + 1 + read-write + + + IPCMDERREN + IP triggered Command Sequences Error Detected interrupt enable. + 3 + 1 + read-write + + + AHBCMDERREN + AHB triggered Command Sequences Error Detected interrupt enable. + 4 + 1 + read-write + + + IPRXWAEN + IP RX FIFO WaterMark available interrupt enable. + 5 + 1 + read-write + + + IPTXWEEN + IP TX FIFO WaterMark empty interrupt enable. + 6 + 1 + read-write + + + SCKSTOPBYRDEN + SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. + 8 + 1 + read-write + + + SCKSTOPBYWREN + SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. + 9 + 1 + read-write + + + AHBBUSTIMEOUTEN + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + + + SEQTIMEOUTEN + Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. + 11 + 1 + read-write + + + + + INTR + Interrupt Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONE + IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. + 0 + 1 + read-write + oneToClear + + + IPCMDGE + IP triggered Command Sequences Grant Timeout interrupt. + 1 + 1 + read-write + oneToClear + + + AHBCMDGE + AHB triggered Command Sequences Grant Timeout interrupt. + 2 + 1 + read-write + oneToClear + + + IPCMDERR + IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. + 3 + 1 + read-write + oneToClear + + + AHBCMDERR + AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. + 4 + 1 + read-write + oneToClear + + + IPRXWA + IP RX FIFO watermark available interrupt. + 5 + 1 + read-write + oneToClear + + + IPTXWE + IP TX FIFO watermark empty interrupt. + 6 + 1 + read-write + oneToClear + + + SCKSTOPBYRD + SCLK is stopped during command sequence because Async RX FIFO full interrupt. + 8 + 1 + read-write + oneToClear + + + SCKSTOPBYWR + SCLK is stopped during command sequence because Async TX FIFO empty interrupt. + 9 + 1 + read-write + oneToClear + + + AHBBUSTIMEOUT + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + oneToClear + + + SEQTIMEOUT + Sequence execution timeout interrupt. + 11 + 1 + read-write + oneToClear + + + + + LUTKEY + LUT Key Register + 0x18 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The Key to lock or unlock LUT. + 0 + 32 + read-write + + + + + LUTCR + LUT Control Register + 0x1C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Lock LUT + 0 + 1 + read-write + + + UNLOCK + Unlock LUT + 1 + 1 + read-write + + + + + AHBRXBUF0CR0 + AHB RX Buffer 0 Control Register 0 + 0x20 + 32 + read-write + 0x80000020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 + Flash Control Register 0 + 0x60 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHA2CR0 + Flash Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR1%s + Flash Control Register 1 + 0x70 + 32 + read-write + 0x63 + 0xFFFFFFFF + + + TCSS + Serial Flash CS setup time. + 0 + 5 + read-write + + + TCSH + Serial Flash CS Hold time. + 5 + 5 + read-write + + + WA + Word Addressable. + 10 + 1 + read-write + + + CAS + Column Address Size. + 11 + 4 + read-write + + + CSINTERVALUNIT + CS interval unit + 15 + 1 + read-write + + + CSINTERVALUNIT_0 + The CS interval unit is 1 serial clock cycle + 0 + + + CSINTERVALUNIT_1 + The CS interval unit is 256 serial clock cycle + 0x1 + + + + + CSINTERVAL + This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. + 16 + 16 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR2%s + Flash Control Register 2 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARDSEQID + Sequence Index for AHB Read triggered Command in LUT. + 0 + 4 + read-write + + + ARDSEQNUM + Sequence Number for AHB Read triggered Command in LUT. + 5 + 3 + read-write + + + AWRSEQID + Sequence Index for AHB Write triggered Command. + 8 + 4 + read-write + + + AWRSEQNUM + Sequence Number for AHB Write triggered Command. + 13 + 3 + read-write + + + AWRWAIT + For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface + 16 + 12 + read-write + + + AWRWAITUNIT + AWRWAIT unit + 28 + 3 + read-write + + + AWRWAITUNIT_0 + The AWRWAIT unit is 2 ahb clock cycle + 0 + + + AWRWAITUNIT_1 + The AWRWAIT unit is 8 ahb clock cycle + 0x1 + + + AWRWAITUNIT_2 + The AWRWAIT unit is 32 ahb clock cycle + 0x2 + + + AWRWAITUNIT_3 + The AWRWAIT unit is 128 ahb clock cycle + 0x3 + + + AWRWAITUNIT_4 + The AWRWAIT unit is 512 ahb clock cycle + 0x4 + + + AWRWAITUNIT_5 + The AWRWAIT unit is 2048 ahb clock cycle + 0x5 + + + AWRWAITUNIT_6 + The AWRWAIT unit is 8192 ahb clock cycle + 0x6 + + + AWRWAITUNIT_7 + The AWRWAIT unit is 32768 ahb clock cycle + 0x7 + + + + + CLRINSTRPTR + Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. + 31 + 1 + read-write + + + + + FLSHCR4 + Flash Control Register 4 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMOPT1 + Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + 0 + 1 + read-write + + + WMOPT1_0 + DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0 + + + WMOPT1_1 + DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0x1 + + + + + WMENA + Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + 2 + 1 + read-write + + + WMENA_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENA_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + WMENB + Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + 3 + 1 + read-write + + + WMENB_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENB_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + + + IPCR0 + IP Control Register 0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFAR + Serial Flash Address for IP command. + 0 + 32 + read-write + + + + + IPCR1 + IP Control Register 1 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + Flash Read/Program Data Size (in Bytes) for IP command. + 0 + 16 + read-write + + + ISEQID + Sequence Index in LUT for IP command. + 16 + 4 + read-write + + + ISEQNUM + Sequence Number for IP command: ISEQNUM+1. + 24 + 3 + read-write + + + IPAREN + Parallel mode Enabled for IP command. + 31 + 1 + read-write + + + IPAREN_0 + Flash will be accessed in Individual mode. + 0 + + + IPAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + + + IPCMD + IP Command Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRG + Setting this bit will trigger an IP Command. + 0 + 1 + read-write + + + + + IPRXFCR + IP RX FIFO Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPRXF + Clear all valid data entries in IP RX FIFO. + 0 + 1 + read-write + + + RXDMAEN + IP RX FIFO reading by DMA enabled. + 1 + 1 + read-write + + + RXDMAEN_0 + IP RX FIFO would be read by processor. + 0 + + + RXDMAEN_1 + IP RX FIFO would be read by DMA. + 0x1 + + + + + RXWMRK + Watermark level is (RXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + IPTXFCR + IP TX FIFO Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPTXF + Clear all valid data entries in IP TX FIFO. + 0 + 1 + read-write + + + TXDMAEN + IP TX FIFO filling by DMA enabled. + 1 + 1 + read-write + + + TXDMAEN_0 + IP TX FIFO would be filled by processor. + 0 + + + TXDMAEN_1 + IP TX FIFO would be filled by DMA. + 0x1 + + + + + TXWMRK + Watermark level is (TXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + 2 + 0x4 + A,B + DLLCR%s + DLL Control Register 0 + 0xC0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DLLEN + DLL calibration enable. + 0 + 1 + read-write + + + DLLRESET + Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). + 1 + 1 + read-write + + + SLVDLYTARGET + The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). + 3 + 4 + read-write + + + OVRDEN + Slave clock delay line delay cell number selection override enable. + 8 + 1 + read-write + + + OVRDVAL + Slave clock delay line delay cell number selection override value. + 9 + 6 + read-write + + + + + STS0 + Status Register 0 + 0xE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SEQIDLE + This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. + 0 + 1 + read-only + + + ARBIDLE + This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + 1 + 1 + read-only + + + ARBCMDSRC + This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + 2 + 2 + read-only + + + ARBCMDSRC_0 + Triggered by AHB read command (triggered by AHB read). + 0 + + + ARBCMDSRC_1 + Triggered by AHB write command (triggered by AHB Write). + 0x1 + + + ARBCMDSRC_2 + Triggered by IP command (triggered by setting register bit IPCMD.TRG). + 0x2 + + + ARBCMDSRC_3 + Triggered by suspended command (resumed). + 0x3 + + + + + + + STS1 + Status Register 1 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHBCMDERRID + Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 0 + 4 + read-only + + + AHBCMDERRCODE + Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 8 + 4 + read-only + + + AHBCMDERRCODE_0 + No error. + 0 + + + AHBCMDERRCODE_2 + AHB Write command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + AHBCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + AHBCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + AHBCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + AHBCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + + + IPCMDERRID + Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 16 + 4 + read-only + + + IPCMDERRCODE + Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 24 + 4 + read-only + + + IPCMDERRCODE_0 + No error. + 0 + + + IPCMDERRCODE_2 + IP command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + IPCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + IPCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + IPCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + IPCMDERRCODE_6 + Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + 0x6 + + + IPCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + IPCMDERRCODE_15 + Flash boundary crossed. + 0xF + + + + + + + STS2 + Status Register 2 + 0xE8 + 32 + read-only + 0x1000100 + 0xFFFFFFFF + + + ASLVLOCK + Flash A sample clock slave delay line locked. + 0 + 1 + read-only + + + AREFLOCK + Flash A sample clock reference delay line locked. + 1 + 1 + read-only + + + ASLVSEL + Flash A sample clock slave delay line delay cell number selection . + 2 + 6 + read-only + + + AREFSEL + Flash A sample clock reference delay line delay cell number selection. + 8 + 6 + read-only + + + BSLVLOCK + Flash B sample clock slave delay line locked. + 16 + 1 + read-only + + + BREFLOCK + Flash B sample clock reference delay line locked. + 17 + 1 + read-only + + + BSLVSEL + Flash B sample clock slave delay line delay cell number selection. + 18 + 6 + read-only + + + BREFSEL + Flash B sample clock reference delay line delay cell number selection. + 24 + 6 + read-only + + + + + AHBSPNDSTS + AHB Suspend Status Register + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + ACTIVE + Indicates if an AHB read prefetch command sequence has been suspended. + 0 + 1 + read-only + + + BUFID + AHB RX BUF ID for suspended command sequence. + 1 + 3 + read-only + + + DATLFT + Left Data size for suspended command sequence (in byte). + 16 + 16 + read-only + + + + + IPRXFSTS + IP RX FIFO Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP RX FIFO. + 0 + 8 + read-only + + + RDCNTR + Total Read Data Counter: RDCNTR * 64 Bits. + 16 + 16 + read-only + + + + + IPTXFSTS + IP TX FIFO Status Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP TX FIFO. + 0 + 8 + read-only + + + WRCNTR + Total Write Data Counter: WRCNTR * 64 Bits. + 16 + 16 + read-only + + + + + 32 + 0x4 + RFDR[%s] + IP RX FIFO Data Register x + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-only + + + + + 32 + 0x4 + TFDR[%s] + IP TX FIFO Data Register x + 0x180 + 32 + write-only + 0 + 0xFFFFFFFF + + + TXDATA + TX Data + 0 + 32 + write-only + + + + + 64 + 0x4 + LUT[%s] + LUT x + 0x200 + 32 + read-write + 0 + 0 + + + OPERAND0 + OPERAND0 + 0 + 8 + read-write + + + NUM_PADS0 + NUM_PADS0 + 8 + 2 + read-write + + + OPCODE0 + OPCODE + 10 + 6 + read-write + + + OPERAND1 + OPERAND1 + 16 + 8 + read-write + + + NUM_PADS1 + NUM_PADS1 + 24 + 2 + read-write + + + OPCODE1 + OPCODE1 + 26 + 6 + read-write + + + + + + + PXP + PXP v2.0 Register Reference Index + PXP + PXP_ + 0x402B4000 + + 0 + 0x444 + registers + + + PXP + 44 + + + + CTRL + Control Register 0 + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + Disabled + PXP is disabled + 0 + + + Enabled + PXP is enabled + 0x1 + + + + + IRQ_ENABLE + Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally + 1 + 1 + read-write + + + Disabled + PXP interrupt is disabled + 0 + + + Enabled + PXP interrupt is enabled + 0x1 + + + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + Disabled + Horizontal Flip is disabled + 0 + + + Enabled + Horizontal Flip is enabled + 0x1 + + + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + Disabled + Vertical Flip is disabled + 0 + + + Enabled + Vertical Flip is enabled + 0x1 + + + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + Complete + PXP will complete the process and enter the idle state ready to accept the next frame to be processed + 0 + + + Repeat + PXP will repeat based on the current configuration register settings + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + Normal + Normal operation + 0 + + + Gated + All clocks to PXP is gated-off + 0x1 + + + + + SFTRST + This bit can be turned on and then off to reset the PXP block to its default state. + 31 + 1 + read-write + + + Enabled + Normal PXP operation is enabled + 0 + + + Disabled + Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + 0x1 + + + + + + + CTRL_SET + Control Register 0 + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + Disabled + PXP is disabled + 0 + + + Enabled + PXP is enabled + 0x1 + + + + + IRQ_ENABLE + Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally + 1 + 1 + read-write + + + Disabled + PXP interrupt is disabled + 0 + + + Enabled + PXP interrupt is enabled + 0x1 + + + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + Disabled + Horizontal Flip is disabled + 0 + + + Enabled + Horizontal Flip is enabled + 0x1 + + + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + Disabled + Vertical Flip is disabled + 0 + + + Enabled + Vertical Flip is enabled + 0x1 + + + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + Complete + PXP will complete the process and enter the idle state ready to accept the next frame to be processed + 0 + + + Repeat + PXP will repeat based on the current configuration register settings + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + Normal + Normal operation + 0 + + + Gated + All clocks to PXP is gated-off + 0x1 + + + + + SFTRST + This bit can be turned on and then off to reset the PXP block to its default state. + 31 + 1 + read-write + + + Enabled + Normal PXP operation is enabled + 0 + + + Disabled + Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + 0x1 + + + + + + + CTRL_CLR + Control Register 0 + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + Disabled + PXP is disabled + 0 + + + Enabled + PXP is enabled + 0x1 + + + + + IRQ_ENABLE + Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally + 1 + 1 + read-write + + + Disabled + PXP interrupt is disabled + 0 + + + Enabled + PXP interrupt is enabled + 0x1 + + + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + Disabled + Horizontal Flip is disabled + 0 + + + Enabled + Horizontal Flip is enabled + 0x1 + + + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + Disabled + Vertical Flip is disabled + 0 + + + Enabled + Vertical Flip is enabled + 0x1 + + + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + Complete + PXP will complete the process and enter the idle state ready to accept the next frame to be processed + 0 + + + Repeat + PXP will repeat based on the current configuration register settings + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + Normal + Normal operation + 0 + + + Gated + All clocks to PXP is gated-off + 0x1 + + + + + SFTRST + This bit can be turned on and then off to reset the PXP block to its default state. + 31 + 1 + read-write + + + Enabled + Normal PXP operation is enabled + 0 + + + Disabled + Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + 0x1 + + + + + + + CTRL_TOG + Control Register 0 + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + Disabled + PXP is disabled + 0 + + + Enabled + PXP is enabled + 0x1 + + + + + IRQ_ENABLE + Interrupt enable When using the PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally + 1 + 1 + read-write + + + Disabled + PXP interrupt is disabled + 0 + + + Enabled + PXP interrupt is enabled + 0x1 + + + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + Disabled + Horizontal Flip is disabled + 0 + + + Enabled + Horizontal Flip is enabled + 0x1 + + + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + Disabled + Vertical Flip is disabled + 0 + + + Enabled + Vertical Flip is enabled + 0x1 + + + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + Complete + PXP will complete the process and enter the idle state ready to accept the next frame to be processed + 0 + + + Repeat + PXP will repeat based on the current configuration register settings + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + Normal + Normal operation + 0 + + + Gated + All clocks to PXP is gated-off + 0x1 + + + + + SFTRST + This bit can be turned on and then off to reset the PXP block to its default state. + 31 + 1 + read-write + + + Enabled + Normal PXP operation is enabled + 0 + + + Disabled + Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + 0x1 + + + + + + + STAT + Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + IRQ_0 + No interrupt + 0 + + + IRQ_1 + Interrupt generated + 0x1 + + + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + Normal + AXI write is normal + 0 + + + Error + AXI write error has occurred + 0x1 + + + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + Normal + AXI read is normal + 0 + + + Error + AXI read error has occurred + 0x1 + + + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + Active + LUT DMA LOAD transfer is active + 0 + + + Complete + LUT DMA LOAD transfer is complete + 0x1 + + + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_SET + Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + IRQ_0 + No interrupt + 0 + + + IRQ_1 + Interrupt generated + 0x1 + + + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + Normal + AXI write is normal + 0 + + + Error + AXI write error has occurred + 0x1 + + + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + Normal + AXI read is normal + 0 + + + Error + AXI read error has occurred + 0x1 + + + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + Active + LUT DMA LOAD transfer is active + 0 + + + Complete + LUT DMA LOAD transfer is complete + 0x1 + + + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_CLR + Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + IRQ_0 + No interrupt + 0 + + + IRQ_1 + Interrupt generated + 0x1 + + + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + Normal + AXI write is normal + 0 + + + Error + AXI write error has occurred + 0x1 + + + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + Normal + AXI read is normal + 0 + + + Error + AXI read error has occurred + 0x1 + + + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + Active + LUT DMA LOAD transfer is active + 0 + + + Complete + LUT DMA LOAD transfer is complete + 0x1 + + + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_TOG + Status Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + IRQ_0 + No interrupt + 0 + + + IRQ_1 + Interrupt generated + 0x1 + + + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + Normal + AXI write is normal + 0 + + + Error + AXI write error has occurred + 0x1 + + + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + Normal + AXI read is normal + 0 + + + Error + AXI read error has occurred + 0x1 + + + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + Active + LUT DMA LOAD transfer is active + 0 + + + Complete + LUT DMA LOAD transfer is complete + 0x1 + + + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + OUT_CTRL + Output Buffer Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + Retain + Retain + 0 + + + Overwritten + Overwritten + 0x1 + + + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_SET + Output Buffer Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + Retain + Retain + 0 + + + Overwritten + Overwritten + 0x1 + + + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_CLR + Output Buffer Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + Retain + Retain + 0 + + + Overwritten + Overwritten + 0x1 + + + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_TOG + Output Buffer Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + Retain + Retain + 0 + + + Overwritten + Overwritten + 0x1 + + + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_BUF + Output Frame Buffer Pointer + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + OUT_BUF2 + Output Frame Buffer Pointer #2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + OUT_PITCH + Output Buffer Pitch + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + OUT_LRC + Output Surface Lower Right Coordinate + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + Indicates the number of vertical PIXELS in the output surface (non-rotated) + 0 + 14 + read-write + + + X + Indicates number of horizontal PIXELS in the output surface (non-rotated) + 16 + 14 + read-write + + + + + OUT_PS_ULC + Processed Surface Upper Left Coordinate + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer + 0 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer + 16 + 14 + read-write + + + + + OUT_PS_LRC + Processed Surface Lower Right Coordinate + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer + 0 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer + 16 + 14 + read-write + + + + + OUT_AS_ULC + Alpha Surface Upper Left Coordinate + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 16 + 14 + read-write + + + + + OUT_AS_LRC + Alpha Surface Lower Right Coordinate + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 16 + 14 + read-write + + + + + PS_CTRL + Processed Surface (PS) Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888_ARGB8888 + 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) + 0x4 + + + RGB555_ARGB1555 + 16-bit pixels with/without alpha at high 1bit + 0xC + + + RGB444_ARGB4444 + 16-bit pixels with/without alpha at high 4 bits + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + RGBA8888 + 2-bit pixels with alpha at the low 8 bits + 0x24 + + + RGBA5551 + 16-bit pixels with alpha at the low 1bits + 0x2C + + + RGBA4444 + 16-bit pixels with alpha at the low 4 bits + 0x2D + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 6 + 1 + read-write + + + Disabled + Byte swap is disabled + 0 + + + Enabled + Byte swap is enabled + 0x1 + + + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + + + PS_CTRL_SET + Processed Surface (PS) Control Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888_ARGB8888 + 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) + 0x4 + + + RGB555_ARGB1555 + 16-bit pixels with/without alpha at high 1bit + 0xC + + + RGB444_ARGB4444 + 16-bit pixels with/without alpha at high 4 bits + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + RGBA8888 + 2-bit pixels with alpha at the low 8 bits + 0x24 + + + RGBA5551 + 16-bit pixels with alpha at the low 1bits + 0x2C + + + RGBA4444 + 16-bit pixels with alpha at the low 4 bits + 0x2D + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 6 + 1 + read-write + + + Disabled + Byte swap is disabled + 0 + + + Enabled + Byte swap is enabled + 0x1 + + + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + + + PS_CTRL_CLR + Processed Surface (PS) Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888_ARGB8888 + 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) + 0x4 + + + RGB555_ARGB1555 + 16-bit pixels with/without alpha at high 1bit + 0xC + + + RGB444_ARGB4444 + 16-bit pixels with/without alpha at high 4 bits + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + RGBA8888 + 2-bit pixels with alpha at the low 8 bits + 0x24 + + + RGBA5551 + 16-bit pixels with alpha at the low 1bits + 0x2C + + + RGBA4444 + 16-bit pixels with alpha at the low 4 bits + 0x2D + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 6 + 1 + read-write + + + Disabled + Byte swap is disabled + 0 + + + Enabled + Byte swap is enabled + 0x1 + + + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + + + PS_CTRL_TOG + Processed Surface (PS) Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888_ARGB8888 + 32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) + 0x4 + + + RGB555_ARGB1555 + 16-bit pixels with/without alpha at high 1bit + 0xC + + + RGB444_ARGB4444 + 16-bit pixels with/without alpha at high 4 bits + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + RGBA8888 + 2-bit pixels with alpha at the low 8 bits + 0x24 + + + RGBA5551 + 16-bit pixels with alpha at the low 1bits + 0x2C + + + RGBA4444 + 16-bit pixels with alpha at the low 4 bits + 0x2D + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 6 + 1 + read-write + + + Disabled + Byte swap is disabled + 0 + + + Enabled + Byte swap is enabled + 0x1 + + + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + + + PS_BUF + PS Input Buffer Address + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PS_UBUF + PS U/Cb or 2 Plane UV Input Buffer Address + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer. + 0 + 32 + read-write + + + + + PS_VBUF + PS V/Cr Input Buffer Address + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS V/Cr Chroma input buffer. + 0 + 32 + read-write + + + + + PS_PITCH + Processed Surface Pitch + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + PS_BACKGROUND + PS Background Color + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + + + PS_SCALE + PS Scale Factor Register + 0x110 + 32 + read-write + 0x10001000 + 0xFFFFFFFF + + + XSCALE + This is a two bit integer and 12 bit fractional representation (## + 0 + 15 + read-write + + + YSCALE + This is a two bit integer and 12 bit fractional representation (## + 16 + 15 + read-write + + + + + PS_OFFSET + PS Scale Offset Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOFFSET + This is a 12 bit fractional representation (0 + 0 + 12 + read-write + + + YOFFSET + This is a 12 bit fractional representation (0 + 16 + 12 + read-write + + + + + PS_CLRKEYLOW + PS Color Key Low + 0x130 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + + + PS_CLRKEYHIGH + PS Color Key High + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + + + AS_CTRL + Alpha Surface Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 1 + 2 + read-write + + + Embedded + Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + 0 + + + Override + Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + 0x1 + + + Multiply + Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + 0x2 + + + ROPs + Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + 0x3 + + + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 3 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + FORMAT + Indicates the input buffer format for AS. + 4 + 4 + read-write + + + ARGB8888 + 32-bit pixels with alpha + 0 + + + RGBA888 + 2-bit pixel with alpha at low 8 bits + 0x1 + + + RGB888 + 32-bit pixels without alpha (unpacked 24-bit format) + 0x4 + + + ARGB1555 + 16-bit pixels with alpha + 0x8 + + + ARGB4444 + 16-bit pixels with alpha + 0x9 + + + RGBA5551 + 16-bit pixel with alpha at low 1 bit + 0xA + + + RGBA4444 + 16-bit pixel with alpha at low 4 bits + 0xB + + + RGB555 + 16-bit pixels without alpha + 0xC + + + RGB444 + 16-bit pixels without alpha + 0xD + + + RGB565 + 16-bit pixels without alpha + 0xE + + + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in PXP_AS_CTRL[ALPHA_CTRL] + 8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 16 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + ALPHA_INVERT + Setting this bit to logic 0 will not alter the alpha value + 20 + 1 + read-write + + + ALPHA_INVERT_0 + Not inverted + 0 + + + Inverted + Inverted + 0x1 + + + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + AS_PITCH + Alpha Surface Pitch + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + AS_CLRKEYLOW + Overlay Color Key Low + 0x180 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + + + AS_CLRKEYHIGH + Overlay Color Key High + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + + + CSC1_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1A0 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data + 0 + 9 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data + 9 + 9 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + BYPASS + Bypass the CSC unit in the scaling engine + 30 + 1 + read-write + + + YCBCR_MODE + Set to 1 when performing YCbCr conversion to RGB + 31 + 1 + read-write + + + YCBCR_MODE_0 + YUV to RGB + 0 + + + YCBCR_MODE_1 + YCbCr to RGB + 0x1 + + + + + + + CSC1_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1B0 + 32 + read-write + 0x1230208 + 0xFFFFFFFF + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) + 0 + 11 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) + 16 + 11 + read-write + + + + + CSC1_COEF2 + Color Space Conversion Coefficient Register 2 + 0x1C0 + 32 + read-write + 0x79B076C + 0xFFFFFFFF + + + C3 + Two's complement Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) + 0 + 11 + read-write + + + C2 + Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) + 16 + 11 + read-write + + + + + POWER + PXP Power Control Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROT_MEM_LP_STATE + Select the low power state of the Rotation (ROT) memory. + 9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + CTRL + Power control for the PXP. + 12 + 20 + read-write + + + + + NEXT + Next Frame Pointer + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLED + Indicates that the "next frame" functionality has been enabled + 0 + 1 + read-only + + + POINTER + A pointer to a data structure containing register values to be used when processing the next frame + 2 + 30 + read-write + + + + + PORTER_DUFF_CTRL + PXP Alpha Engine A Control Register. + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORTER_DUFF_ENABLE + Porter-Duff Enable + 0 + 1 + read-write + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 0x1 + + + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 1 + 2 + read-write + + + S0_S1_FACTOR_MODE_0 + 1 + 0 + + + S0_S1_FACTOR_MODE_1 + 0 + 0x1 + + + S0_S1_FACTOR_MODE_2 + Straight alpha + 0x2 + + + S0_S1_FACTOR_MODE_3 + Inverse alpha + 0x3 + + + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 3 + 2 + read-write + + + S0_GLOBAL_ALPHA_MODE_0 + Global alpha + 0 + + + S0_GLOBAL_ALPHA_MODE_1 + Local alpha + 0x1 + + + S0_GLOBAL_ALPHA_MODE_2 + Scaled alpha + 0x2 + + + S0_GLOBAL_ALPHA_MODE_3 + Scaled alpha + 0x3 + + + + + S0_ALPHA_MODE + s0 alpha mode (Porter-Duff alpha mode) + 5 + 1 + read-write + + + S0_ALPHA_MODE_0 + Straight mode + 0 + + + S0_ALPHA_MODE_1 + Inverted mode + 0x1 + + + + + S0_COLOR_MODE + s0 color mode (Porter-Duff color mode) + 6 + 1 + read-write + + + S0_COLOR_MODE_0 + Original pixel + 0 + + + S0_COLOR_MODE_1 + Scaled pixel + 0x1 + + + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode (Porter-Duff factor mode) + 8 + 2 + read-write + + + S1_S0_FACTOR_MODE_0 + 1 + 0 + + + S1_S0_FACTOR_MODE_1 + 0 + 0x1 + + + S1_S0_FACTOR_MODE_2 + Straight alpha + 0x2 + + + S1_S0_FACTOR_MODE_3 + Inverse alpha + 0x3 + + + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode (Porter-Duff Global Alpha mode) + 10 + 2 + read-write + + + S1_GLOBAL_ALPHA_MODE_0 + Global alpha + 0 + + + S1_GLOBAL_ALPHA_MODE_1 + Local alpha + 0x1 + + + S1_GLOBAL_ALPHA_MODE_2 + Scaled alpha + 0x2 + + + S1_GLOBAL_ALPHA_MODE_3 + Scaled alpha + 0x3 + + + + + S1_ALPHA_MODE + s1 alpha mode (Porter-Duff Alpha mode) + 12 + 1 + read-write + + + S1_ALPHA_MODE_0 + Straight mode + 0 + + + S1_ALPHA_MODE_1 + Inverted mode + 0x1 + + + + + S1_COLOR_MODE + s1 color mode + 13 + 1 + read-write + + + S1_COLOR_MODE_0 + Original pixel + 0 + + + S1_COLOR_MODE_1 + Scaled pixel + 0x1 + + + + + S0_GLOBAL_ALPHA + s0 global alpha + 16 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 24 + 8 + read-write + + + + + + + LCDIF + LCDIF Register Reference Index + LCDIF + LCDIF_ + 0x402B8000 + + 0 + 0xB44 + registers + + + LCDIF + 42 + + + + CTRL + LCDIF General Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_SET + LCDIF General Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_CLR + LCDIF General Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_TOG + LCDIF General Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master. + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. When LUT enabled, this field should be set to 0x01. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL1 + LCDIF General Control1 Register + 0x10 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_SET + LCDIF General Control1 Register + 0x14 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_CLR + LCDIF General Control1 Register + 0x18 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_TOG + LCDIF General Control1 Register + 0x1C + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL2 + LCDIF General Control2 Register + 0x20 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_SET + LCDIF General Control2 Register + 0x24 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_CLR + LCDIF General Control2 Register + 0x28 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_TOG + LCDIF General Control2 Register + 0x2C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + TRANSFER_COUNT + LCDIF Horizontal and Vertical Valid Data Count Register + 0x30 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + H_COUNT + Total valid data (pixels) in each horizontal line + 0 + 16 + read-write + + + V_COUNT + Number of horizontal lines per frame which contain valid data + 16 + 16 + read-write + + + + + CUR_BUF + LCD Interface Current Buffer Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the current frame being transmitted by LCDIF. + 0 + 32 + read-write + + + + + NEXT_BUF + LCD Interface Next Buffer Address Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by LCDIF. + 0 + 32 + read-write + + + + + VDCTRL0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_SET + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_CLR + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_TOG + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL1 + LCDIF VSYNC Mode and Dotclk Mode Control Register1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PERIOD + Total number of units between two positive or two negative edges of the VSYNC signal + 0 + 32 + read-write + + + + + VDCTRL2 + LCDIF VSYNC Mode and Dotclk Mode Control Register2 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSYNC_PERIOD + Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal + 0 + 18 + read-write + + + HSYNC_PULSE_WIDTH + Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. + 18 + 14 + read-write + + + + + VDCTRL3 + LCDIF VSYNC Mode and Dotclk Mode Control Register3 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + VERTICAL_WAIT_CNT + In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set + 0 + 16 + read-write + + + HORIZONTAL_WAIT_CNT + In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins + 16 + 12 + read-write + + + VSYNC_ONLY + This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. + 28 + 1 + read-write + + + MUX_SYNC_SIGNALS + When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + 29 + 1 + read-write + + + + + VDCTRL4 + LCDIF VSYNC Mode and Dotclk Mode Control Register4 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOTCLK_H_VALID_DATA_CNT + Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode + 0 + 18 + read-write + + + SYNC_SIGNALS_ON + Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end + 18 + 1 + read-write + + + DOTCLK_DLY_SEL + This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin + 29 + 3 + read-write + + + + + BM_ERROR_STAT + Bus Master Error Status Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Virtual address at which bus master error occurred. + 0 + 32 + read-write + + + + + CRC_STAT + CRC Status Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_VALUE + Calculated CRC value + 0 + 32 + read-write + + + + + STAT + LCD Interface Status Register + 0x1B0 + 32 + read-only + 0x95000000 + 0xFFFFFFFF + + + LFIFO_COUNT + Read only view of the current count in Latency buffer (LFIFO). + 0 + 9 + read-only + + + TXFIFO_EMPTY + Read only view of the signals that indicates LCD TXFIFO is empty. + 26 + 1 + read-only + + + TXFIFO_FULL + Read only view of the signals that indicates LCD TXFIFO is full. + 27 + 1 + read-only + + + LFIFO_EMPTY + Read only view of the signals that indicates LCD LFIFO is empty. + 28 + 1 + read-only + + + LFIFO_FULL + Read only view of the signals that indicates LCD LFIFO is full. + 29 + 1 + read-only + + + PRESENT + 0: LCDIF not present on this product 1: LCDIF is present. + 31 + 1 + read-only + + + + + RGB_ADJUST + RGB Color Range Adjust + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + Adjust value of RGB color for display. + 0 + 24 + read-write + + + RGB_ADJ_MODE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 30 + 2 + read-write + + + NO_ADJ + No Adjust + 0 + + + INC_MODE + Increment RGB + 0x1 + + + DEC_MODE + Decrement RGB + 0x2 + + + MUT_MODE + Multiply RGB + 0x3 + + + + + + + RGB_ADJUST_SET + RGB Color Range Adjust + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + Adjust value of RGB color for display. + 0 + 24 + read-write + + + RGB_ADJ_MODE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 30 + 2 + read-write + + + NO_ADJ + No Adjust + 0 + + + INC_MODE + Increment RGB + 0x1 + + + DEC_MODE + Decrement RGB + 0x2 + + + MUT_MODE + Multiply RGB + 0x3 + + + + + + + RGB_ADJUST_CLR + RGB Color Range Adjust + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + Adjust value of RGB color for display. + 0 + 24 + read-write + + + RGB_ADJ_MODE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 30 + 2 + read-write + + + NO_ADJ + No Adjust + 0 + + + INC_MODE + Increment RGB + 0x1 + + + DEC_MODE + Decrement RGB + 0x2 + + + MUT_MODE + Multiply RGB + 0x3 + + + + + + + RGB_ADJUST_TOG + RGB Color Range Adjust + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + Adjust value of RGB color for display. + 0 + 24 + read-write + + + RGB_ADJ_MODE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 30 + 2 + read-write + + + NO_ADJ + No Adjust + 0 + + + INC_MODE + Increment RGB + 0x1 + + + DEC_MODE + Decrement RGB + 0x2 + + + MUT_MODE + Multiply RGB + 0x3 + + + + + + + PIGEONCTRL0 + LCDIF Pigeon Mode Control0 Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_SET + LCDIF Pigeon Mode Control0 Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_CLR + LCDIF Pigeon Mode Control0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_TOG + LCDIF Pigeon Mode Control0 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL1 + LCDIF Pigeon Mode Control1 Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_SET + LCDIF Pigeon Mode Control1 Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_CLR + LCDIF Pigeon Mode Control1 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_TOG + LCDIF Pigeon Mode Control1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL2 + LCDIF Pigeon Mode Control2 Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_SET + LCDIF Pigeon Mode Control2 Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_CLR + LCDIF Pigeon Mode Control2 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_TOG + LCDIF Pigeon Mode Control2 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEON_0_0 + Panel Interface Signal Generator Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_0_1 + Panel Interface Signal Generator Register + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_0_2 + Panel Interface Signal Generator Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_1_0 + Panel Interface Signal Generator Register + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_1_1 + Panel Interface Signal Generator Register + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_1_2 + Panel Interface Signal Generator Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_2_0 + Panel Interface Signal Generator Register + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_2_1 + Panel Interface Signal Generator Register + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_2_2 + Panel Interface Signal Generator Register + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_3_0 + Panel Interface Signal Generator Register + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_3_1 + Panel Interface Signal Generator Register + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_3_2 + Panel Interface Signal Generator Register + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_4_0 + Panel Interface Signal Generator Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_4_1 + Panel Interface Signal Generator Register + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_4_2 + Panel Interface Signal Generator Register + 0x920 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_5_0 + Panel Interface Signal Generator Register + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_5_1 + Panel Interface Signal Generator Register + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_5_2 + Panel Interface Signal Generator Register + 0x960 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_6_0 + Panel Interface Signal Generator Register + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_6_1 + Panel Interface Signal Generator Register + 0x990 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_6_2 + Panel Interface Signal Generator Register + 0x9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_7_0 + Panel Interface Signal Generator Register + 0x9C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_7_1 + Panel Interface Signal Generator Register + 0x9D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_7_2 + Panel Interface Signal Generator Register + 0x9E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_8_0 + Panel Interface Signal Generator Register + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_8_1 + Panel Interface Signal Generator Register + 0xA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_8_2 + Panel Interface Signal Generator Register + 0xA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_9_0 + Panel Interface Signal Generator Register + 0xA40 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_9_1 + Panel Interface Signal Generator Register + 0xA50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_9_2 + Panel Interface Signal Generator Register + 0xA60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_10_0 + Panel Interface Signal Generator Register + 0xA80 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_10_1 + Panel Interface Signal Generator Register + 0xA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_10_2 + Panel Interface Signal Generator Register + 0xAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_11_0 + Panel Interface Signal Generator Register + 0xAC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_11_1 + Panel Interface Signal Generator Register + 0xAD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_11_2 + Panel Interface Signal Generator Register + 0xAE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + LUT_CTRL + Look Up Table Control Register + 0xB00 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + LUT_BYPASS + Setting this bit will bypass the LUT memory resource completely + 0 + 1 + read-write + + + + + LUT0_ADDR + Lookup Table 0 Index Register + 0xB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 8 + read-write + + + + + LUT0_DATA + Lookup Table 0 Data Register + 0xB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + LUT1_ADDR + Lookup Table 1 Index Register + 0xB30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 8 + read-write + + + + + LUT1_DATA + Lookup Table 1 Data Register + 0xB40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + + + CSI + CSI + CSI + CSI_ + 0x402BC000 + + 0 + 0x50 + registers + + + CSI + 43 + + + + CR1 + CSI Control Register 1 + 0 + 32 + read-write + 0x40000800 + 0xFFFFFFFF + + + PIXEL_BIT + Pixel Bit + 0 + 1 + read-write + + + PIXEL_BIT_0 + 8-bit data for each pixel + 0 + + + PIXEL_BIT_1 + 10-bit data for each pixel + 0x1 + + + + + REDGE + Valid Pixel Clock Edge Select + 1 + 1 + read-write + + + REDGE_0 + Pixel data is latched at the falling edge of CSI_PIXCLK + 0 + + + REDGE_1 + Pixel data is latched at the rising edge of CSI_PIXCLK + 0x1 + + + + + INV_PCLK + Invert Pixel Clock Input + 2 + 1 + read-write + + + INV_PCLK_0 + CSI_PIXCLK is directly applied to internal circuitry + 0 + + + INV_PCLK_1 + CSI_PIXCLK is inverted before applied to internal circuitry + 0x1 + + + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. + 3 + 1 + read-write + + + INV_DATA_0 + CSI_D[7:0] data lines are directly applied to internal circuitry + 0 + + + INV_DATA_1 + CSI_D[7:0] data lines are inverted before applied to internal circuitry + 0x1 + + + + + GCLK_MODE + Gated Clock Mode Enable + 4 + 1 + read-write + + + GCLK_MODE_0 + Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + 0 + + + GCLK_MODE_1 + Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + 0x1 + + + + + CLR_RXFIFO + Asynchronous RXFIFO Clear + 5 + 1 + read-write + + + CLR_STATFIFO + Asynchronous STATFIFO Clear + 6 + 1 + read-write + + + PACK_DIR + Data Packing Direction + 7 + 1 + read-write + + + PACK_DIR_0 + Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + 0 + + + PACK_DIR_1 + Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + 0x1 + + + + + FCC + FIFO Clear Control + 8 + 1 + read-write + + + FCC_0 + Asynchronous FIFO clear is selected. + 0 + + + FCC_1 + Synchronous FIFO clear is selected. + 0x1 + + + + + CCIR_EN + BT.656 Interface Enable. This bit selects the type of interface used. + 10 + 1 + read-write + + + CCIR_EN_0 + Traditional interface is selected. + 0 + + + CCIR_EN_1 + BT.656 interface is selected. + 0x1 + + + + + HSYNC_POL + HSYNC Polarity Select + 11 + 1 + read-write + + + HSYNC_POL_0 + HSYNC is active low + 0 + + + HSYNC_POL_1 + HSYNC is active high + 0x1 + + + + + SOF_INTEN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. + 16 + 1 + read-write + + + SOF_INTEN_0 + SOF interrupt disable + 0 + + + SOF_INTEN_1 + SOF interrupt enable + 0x1 + + + + + SOF_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. + 17 + 1 + read-write + + + SOF_POL_0 + SOF interrupt is generated on SOF falling edge + 0 + + + SOF_POL_1 + SOF interrupt is generated on SOF rising edge + 0x1 + + + + + RXFF_INTEN + RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. + 18 + 1 + read-write + + + RXFF_INTEN_0 + RxFIFO full interrupt disable + 0 + + + RXFF_INTEN_1 + RxFIFO full interrupt enable + 0x1 + + + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable + 19 + 1 + read-write + + + FB1_DMA_DONE_INTEN_0 + Frame Buffer1 DMA Transfer Done interrupt disable + 0 + + + FB1_DMA_DONE_INTEN_1 + Frame Buffer1 DMA Transfer Done interrupt enable + 0x1 + + + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable + 20 + 1 + read-write + + + FB2_DMA_DONE_INTEN_0 + Frame Buffer2 DMA Transfer Done interrupt disable + 0 + + + FB2_DMA_DONE_INTEN_1 + Frame Buffer2 DMA Transfer Done interrupt enable + 0x1 + + + + + STATFF_INTEN + STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. + 21 + 1 + read-write + + + STATFF_INTEN_0 + STATFIFO full interrupt disable + 0 + + + STATFF_INTEN_1 + STATFIFO full interrupt enable + 0x1 + + + + + SFF_DMA_DONE_INTEN + STATFIFO DMA Transfer Done Interrupt Enable + 22 + 1 + read-write + + + SFF_DMA_DONE_INTEN_0 + STATFIFO DMA Transfer Done interrupt disable + 0 + + + SFF_DMA_DONE_INTEN_1 + STATFIFO DMA Transfer Done interrupt enable + 0x1 + + + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. + 24 + 1 + read-write + + + RF_OR_INTEN_0 + RxFIFO overrun interrupt is disabled + 0 + + + RF_OR_INTEN_1 + RxFIFO overrun interrupt is enabled + 0x1 + + + + + SF_OR_INTEN + STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. + 25 + 1 + read-write + + + SF_OR_INTEN_0 + STATFIFO overrun interrupt is disabled + 0 + + + SF_OR_INTEN_1 + STATFIFO overrun interrupt is enabled + 0x1 + + + + + COF_INT_EN + Change Of Image Field (COF) Interrupt Enable + 26 + 1 + read-write + + + COF_INT_EN_0 + COF interrupt is disabled + 0 + + + COF_INT_EN_1 + COF interrupt is enabled + 0x1 + + + + + CCIR_MODE + BT + 27 + 1 + read-write + + + CCIR_MODE_0 + Progressive mode is selected + 0 + + + CCIR_MODE_1 + Interlace mode is selected + 0x1 + + + + + PrP_IF_EN + CSI-PrP Interface Enable + 28 + 1 + read-write + + + PrP_IF_EN_0 + CSI to PrP bus is disabled + 0 + + + PrP_IF_EN_1 + CSI to PrP bus is enabled + 0x1 + + + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. + 29 + 1 + read-write + + + EOF_INT_EN_0 + EOF interrupt is disabled. + 0 + + + EOF_INT_EN_1 + EOF interrupt is generated when RX count value is reached. + 0x1 + + + + + EXT_VSYNC + External VSYNC Enable + 30 + 1 + read-write + + + EXT_VSYNC_0 + Internal VSYNC mode + 0 + + + EXT_VSYNC_1 + External VSYNC mode + 0x1 + + + + + SWAP16_EN + SWAP 16-Bit Enable + 31 + 1 + read-write + + + SWAP16_EN_0 + Disable swapping + 0 + + + SWAP16_EN_1 + Enable swapping + 0x1 + + + + + + + CR2 + CSI Control Register 2 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSC + Horizontal Skip Count + 0 + 8 + read-write + + + VSC + Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. + 8 + 8 + read-write + + + LVRM + Live View Resolution Mode. Selects the grid size used for live view resolution. + 16 + 3 + read-write + + + LVRM_0 + 512 x 384 + 0 + + + LVRM_1 + 448 x 336 + 0x1 + + + LVRM_2 + 384 x 288 + 0x2 + + + LVRM_3 + 384 x 256 + 0x3 + + + LVRM_4 + 320 x 240 + 0x4 + + + LVRM_5 + 288 x 216 + 0x5 + + + LVRM_6 + 400 x 300 + 0x6 + + + + + BTS + Bayer Tile Start. Controls the Bayer pattern starting point. + 19 + 2 + read-write + + + BTS_0 + GR + 0 + + + BTS_1 + RG + 0x1 + + + BTS_2 + BG + 0x2 + + + BTS_3 + GB + 0x3 + + + + + SCE + Skip Count Enable + 23 + 1 + read-write + + + SCE_0 + Skip count disable + 0 + + + SCE_1 + Skip count enable + 0x1 + + + + + AFS + Auto Focus Spread. Selects which green pixels are used for auto-focus. + 24 + 2 + read-write + + + AFS_0 + Abs Diff on consecutive green pixels + 0 + + + AFS_1 + Abs Diff on every third green pixels + 0x1 + + + AFS_2 + Abs Diff on every four green pixels + #1x + + + + + DRM + Double Resolution Mode. Controls size of statistics grid. + 26 + 1 + read-write + + + DRM_0 + Stats grid of 8 x 6 + 0 + + + DRM_1 + Stats grid of 8 x 12 + 0x1 + + + + + DMA_BURST_TYPE_SFF + Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO. + 28 + 2 + read-write + + + DMA_BURST_TYPE_SFF_0 + INCR8 + #x0 + + + DMA_BURST_TYPE_SFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_SFF_3 + INCR16 + 0x3 + + + + + DMA_BURST_TYPE_RFF + Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO. + 30 + 2 + read-write + + + DMA_BURST_TYPE_RFF_0 + INCR8 + #x0 + + + DMA_BURST_TYPE_RFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_RFF_3 + INCR16 + 0x3 + + + + + + + CR3 + CSI Control Register 3 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ECC_AUTO_EN + Automatic Error Correction Enable + 0 + 1 + read-write + + + ECC_AUTO_EN_0 + Auto Error correction is disabled. + 0 + + + ECC_AUTO_EN_1 + Auto Error correction is enabled. + 0x1 + + + + + ECC_INT_EN + Error Detection Interrupt Enable + 1 + 1 + read-write + + + ECC_INT_EN_0 + No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + 0 + + + ECC_INT_EN_1 + Interrupt is generated when error is detected. + 0x1 + + + + + ZERO_PACK_EN + Dummy Zero Packing Enable + 2 + 1 + read-write + + + ZERO_PACK_EN_0 + Zero packing disabled + 0 + + + ZERO_PACK_EN_1 + Zero packing enabled + 0x1 + + + + + SENSOR_16BITS + 16-bit Sensor Mode + 3 + 1 + read-write + + + SENSOR_16BITS_0 + Only one 8-bit sensor is connected. + 0 + + + SENSOR_16BITS_1 + One 16-bit sensor is connected. + 0x1 + + + + + RxFF_LEVEL + RxFIFO Full Level + 4 + 3 + read-write + + + RxFF_LEVEL_0 + 4 Double words + 0 + + + RxFF_LEVEL_1 + 8 Double words + 0x1 + + + RxFF_LEVEL_2 + 16 Double words + 0x2 + + + RxFF_LEVEL_3 + 24 Double words + 0x3 + + + RxFF_LEVEL_4 + 32 Double words + 0x4 + + + RxFF_LEVEL_5 + 48 Double words + 0x5 + + + RxFF_LEVEL_6 + 64 Double words + 0x6 + + + RxFF_LEVEL_7 + 96 Double words + 0x7 + + + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse (AHB protocol standard) error interrupt. + 7 + 1 + read-write + + + HRESP_ERR_EN_0 + Disable hresponse error interrupt + 0 + + + HRESP_ERR_EN_1 + Enable hresponse error interrupt + 0x1 + + + + + STATFF_LEVEL + STATFIFO Full Level + 8 + 3 + read-write + + + STATFF_LEVEL_0 + 4 Double words + 0 + + + STATFF_LEVEL_1 + 8 Double words + 0x1 + + + STATFF_LEVEL_2 + 12 Double words + 0x2 + + + STATFF_LEVEL_3 + 16 Double words + 0x3 + + + STATFF_LEVEL_4 + 24 Double words + 0x4 + + + STATFF_LEVEL_5 + 32 Double words + 0x5 + + + STATFF_LEVEL_6 + 48 Double words + 0x6 + + + STATFF_LEVEL_7 + 64 Double words + 0x7 + + + + + DMA_REQ_EN_SFF + DMA Request Enable for STATFIFO + 11 + 1 + read-write + + + DMA_REQ_EN_SFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_SFF_1 + Enable the dma request + 0x1 + + + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO + 12 + 1 + read-write + + + DMA_REQ_EN_RFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_RFF_1 + Enable the dma request + 0x1 + + + + + DMA_REFLASH_SFF + Reflash DMA Controller for STATFIFO + 13 + 1 + read-write + + + DMA_REFLASH_SFF_0 + No reflashing + 0 + + + DMA_REFLASH_SFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + DMA_REFLASH_RFF + Reflash DMA Controller for RxFIFO + 14 + 1 + read-write + + + DMA_REFLASH_RFF_0 + No reflashing + 0 + + + DMA_REFLASH_RFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done) + 15 + 1 + read-write + + + FRMCNT_RST_0 + Do not reset + 0 + + + FRMCNT_RST_1 + Reset frame counter immediately + 0x1 + + + + + FRMCNT + Frame Counter + 16 + 16 + read-write + + + + + STATFIFO + CSI Statistic FIFO Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT + Static data from sensor + 0 + 32 + read-only + + + + + RFIFO + CSI RX FIFO Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMAGE + Received image data + 0 + 32 + read-only + + + + + RXCNT + CSI RX Count Register + 0x14 + 32 + read-write + 0x9600 + 0xFFFFFFFF + + + RXCNT + RxFIFO Count + 0 + 22 + read-write + + + + + SR + CSI Status Register + 0x18 + 32 + read-write + 0x80004000 + 0xFFFFFFFF + + + DRDY + RXFIFO Data Ready + 0 + 1 + read-write + + + DRDY_0 + No data (word) is ready + 0 + + + DRDY_1 + At least 1 datum (word) is ready in RXFIFO. + 0x1 + + + + + ECC_INT + BT + 1 + 1 + read-write + + + ECC_INT_0 + No error detected + 0 + + + ECC_INT_1 + Error is detected in BT.656 coding + 0x1 + + + + + HRESP_ERR_INT + Hresponse Error Interrupt Status + 7 + 1 + read-write + + + HRESP_ERR_INT_0 + No hresponse error. + 0 + + + HRESP_ERR_INT_1 + Hresponse error is detected. + 0x1 + + + + + COF_INT + Change Of Field Interrupt Status + 13 + 1 + read-write + + + COF_INT_0 + Video field has no change. + 0 + + + COF_INT_1 + Change of video field is detected. + 0x1 + + + + + F1_INT + BT + 14 + 1 + read-write + + + F1_INT_0 + Field 1 of video is not detected. + 0 + + + F1_INT_1 + Field 1 of video is about to start. + 0x1 + + + + + F2_INT + BT + 15 + 1 + read-write + + + F2_INT_0 + Field 2 of video is not detected + 0 + + + F2_INT_1 + Field 2 of video is about to start + 0x1 + + + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) + 16 + 1 + read-write + + + SOF_INT_0 + SOF is not detected. + 0 + + + SOF_INT_1 + SOF is detected. + 0x1 + + + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) + 17 + 1 + read-write + + + EOF_INT_0 + EOF is not detected. + 0 + + + EOF_INT_1 + EOF is detected. + 0x1 + + + + + RxFF_INT + RXFIFO Full Interrupt Status + 18 + 1 + read-write + + + RxFF_INT_0 + RxFIFO is not full. + 0 + + + RxFF_INT_1 + RxFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1 + 19 + 1 + read-write + + + DMA_TSF_DONE_FB1_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB1_1 + DMA transfer is completed. + 0x1 + + + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2 + 20 + 1 + read-write + + + DMA_TSF_DONE_FB2_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB2_1 + DMA transfer is completed. + 0x1 + + + + + STATFF_INT + STATFIFO Full Interrupt Status + 21 + 1 + read-write + + + STATFF_INT_0 + STATFIFO is not full. + 0 + + + STATFF_INT_1 + STATFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_SFF + DMA Transfer Done from StatFIFO + 22 + 1 + read-write + + + DMA_TSF_DONE_SFF_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_SFF_1 + DMA transfer is completed. + 0x1 + + + + + RF_OR_INT + RxFIFO Overrun Interrupt Status + 24 + 1 + read-write + + + RF_OR_INT_0 + RXFIFO has not overflowed. + 0 + + + RF_OR_INT_1 + RXFIFO has overflowed. + 0x1 + + + + + SF_OR_INT + STATFIFO Overrun Interrupt Status + 25 + 1 + read-write + + + SF_OR_INT_0 + STATFIFO has not overflowed. + 0 + + + SF_OR_INT_1 + STATFIFO has overflowed. + 0x1 + + + + + DMA_FIELD1_DONE + When DMA field 1 is complete, this bit will be set to 1(clear by writing 1). + 26 + 1 + read-write + + + DMA_FIELD0_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 27 + 1 + read-write + + + BASEADDR_CHHANGE_ERROR + When using base address switching enable, this bit will be 1 when switching occur before DMA complete + 28 + 1 + read-write + + + + + DMASA_STATFIFO + CSI DMA Start Address Register - for STATFIFO + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_SFF + DMA Start Address for STATFIFO + 2 + 30 + read-write + + + + + DMATS_STATFIFO + CSI DMA Transfer Size Register - for STATFIFO + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_TSF_SIZE_SFF + DMA Transfer Size for STATFIFO + 0 + 32 + read-write + + + + + DMASA_FB1 + CSI DMA Start Address Register - for Frame Buffer1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB1 + DMA Start Address in Frame Buffer1 + 2 + 30 + read-write + + + + + DMASA_FB2 + CSI DMA Transfer Size Register - for Frame Buffer2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB2 + DMA Start Address in Frame Buffer2 + 2 + 30 + read-write + + + + + FBUF_PARA + CSI Frame Buffer Parameter Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBUF_STRIDE + Frame Buffer Parameter + 0 + 16 + read-write + + + DEINTERLACE_STRIDE + DEINTERLACE_STRIDE is only used in the deinterlace mode + 16 + 16 + read-write + + + + + IMAG_PARA + CSI Image Parameter Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_HEIGHT + Image Height. Indicates how many pixels in a column of the image from the sensor. + 0 + 16 + read-write + + + IMAGE_WIDTH + This field indicates the number of active pixel cycles per line + 16 + 16 + read-write + + + + + CR18 + CSI Control Register 18 + 0x48 + 32 + read-write + 0x2D000 + 0xFFFFFFFF + + + DEINTERLACE_EN + This bit is used to select the output method When input is standard BT.656 video. + 2 + 1 + read-write + + + DEINTERLACE_EN_0 + Deinterlace disabled + 0 + + + DEINTERLACE_EN_1 + Deinterlace enabled + 0x1 + + + + + PARALLEL24_EN + Enable bit for Parallel RGB888/YUV444 24bit input + 3 + 1 + read-write + + + PARALLEL24_EN_0 + Input is disabled + 0 + + + PARALLEL24_EN_1 + Input is enabled + 0x1 + + + + + BASEADDR_SWITCH_EN + When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than automatically by DMA completed + 4 + 1 + read-write + + + BASEADDR_SWITCH_SEL + CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. + 5 + 1 + read-write + + + BASEADDR_SWITCH_SEL_0 + Switching base address at the edge of the vsync + 0 + + + BASEADDR_SWITCH_SEL_1 + Switching base address at the edge of the first data of each frame + 0x1 + + + + + FIELD0_DONE_IE + In interlace mode, field 0 means interrupt enabled. + 6 + 1 + read-write + + + FIELD0_DONE_IE_0 + Interrupt disabled + 0 + + + FIELD0_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + DMA_FIELD1_DONE_IE + When in interlace mode, field 1 done interrupt enable. + 7 + 1 + read-write + + + DMA_FIELD1_DONE_IE_0 + Interrupt disabled + 0 + + + DMA_FIELD1_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + LAST_DMA_REQ_SEL + Choosing the last DMA request condition + 8 + 1 + read-write + + + LAST_DMA_REQ_SEL_0 + fifo_full_level + 0 + + + LAST_DMA_REQ_SEL_1 + hburst_length + 0x1 + + + + + BASEADDR_CHANGE_ERROR_IE + Base address change error interrupt enable signal. + 9 + 1 + read-write + + + BASEADDR_CHANGE_ERROR_IE_0 + Interrupt disabled + 0 + + + BASEADDR_CHANGE_ERROR_IE_1 + Interrupt enabled + 0x1 + + + + + RGB888A_FORMAT_SEL + Output is 32-bit format. + 10 + 1 + read-write + + + RGB888A_FORMAT_SEL_0 + {8'h0, data[23:0]} + 0 + + + RGB888A_FORMAT_SEL_1 + {data[23:0], 8'h0} + 0x1 + + + + + AHB_HPROT + Hprot value in AHB bus protocol. + 12 + 4 + read-write + + + MASK_OPTION + These bits used to choose the method to mask the CSI input. + 18 + 2 + read-write + + + MASK_OPTION_0 + Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. + 0 + + + MASK_OPTION_1 + Writing to memory when CSI_ENABLE is 1. + 0x1 + + + MASK_OPTION_2 + Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + 0x2 + + + MASK_OPTION_3 + Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + 0x3 + + + + + CSI_ENABLE + CSI global enable signal + 31 + 1 + read-write + + + + + CR19 + CSI Control Register 19 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_RFIFO_HIGHEST_FIFO_LEVEL + This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it + 0 + 8 + read-write + + + + + + + USDHC1 + uSDHC + USDHC + USDHC + 0x402C0000 + + 0 + 0xD0 + registers + + + USDHC1 + 110 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + System address + 0 + 32 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + BLKSIZE + Transfer block size + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 byte + 0x1 + + + BLKSIZE_2 + 2 bytes + 0x2 + + + BLKSIZE_3 + 3 bytes + 0x3 + + + BLKSIZE_4 + 4 bytes + 0x4 + + + BLKSIZE_511 + 511 bytes + 0x1FF + + + BLKSIZE_512 + 512 bytes + 0x200 + + + BLKSIZE_2048 + 2048 bytes + 0x800 + + + BLKSIZE_4096 + 4096 bytes + 0x1000 + + + + + BLKCNT + Blocks count for current transfer + 16 + 16 + read-write + + + BLKCNT_0 + Stop count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + BLKCNT_65535 + 65535 blocks + 0xFFFF + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response type select + 16 + 2 + read-write + + + RSPTYP_0 + No response + 0 + + + RSPTYP_1 + Response length 136 + 0x1 + + + RSPTYP_2 + Response length 48 + 0x2 + + + RSPTYP_3 + Response length 48, check busy after response + 0x3 + + + + + CCCEN + Command CRC check enable + 19 + 1 + read-write + + + CCCEN_0 + Disables command CRC check + 0 + + + CCCEN_1 + Enables command CRC check + 0x1 + + + + + CICEN + Command index check enable + 20 + 1 + read-write + + + CICEN_0 + Disable command index check + 0 + + + CICEN_1 + Enables command index check + 0x1 + + + + + DPSEL + Data present select + 21 + 1 + read-write + + + DPSEL_0 + No data present + 0 + + + DPSEL_1 + Data present + 0x1 + + + + + CMDTYP + Command type + 22 + 2 + read-write + + + CMDTYP_0 + Normal other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing bus suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing function select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command index + 24 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0x72FFFF + + + CIHB + Command inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command inhibit (DATA) + 1 + 1 + read-only + + + CDIHB_0 + Can issue command that uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command that uses the DATA line + 0x1 + + + + + DLA + Data line active + 2 + 1 + read-only + + + DLA_0 + DATA line inactive + 0 + + + DLA_1 + DATA line active + 0x1 + + + + + SDSTB + SD clock stable + 3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + Peripheral clock gated off internally + 4 + 1 + read-only + + + IPGOFF_0 + Peripheral clock is active. + 0 + + + IPGOFF_1 + Peripheral clock is gated off. + 0x1 + + + + + HCKOFF + HCLK gated off internally + 5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK gated off internally + 6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD clock gated off internally + 7 + 1 + read-only + + + SDOFF_0 + SD clock is active. + 0 + + + SDOFF_1 + SD clock is gated off. + 0x1 + + + + + WTA + Write transfer active + 8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read transfer active + 9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer write enable + 10 + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer read enable + 11 + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape select change done + 15 + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card inserted + 16 + 1 + read-only + + + CINST_0 + Power on reset or no card + 0 + + + CINST_1 + Card inserted + 0x1 + + + + + CDPL + Card detect pin level + 18 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write protect switch pin level + 19 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD line signal level + 23 + 1 + read-only + + + DLSL + DATA[7:0] line signal level + 24 + 8 + read-only + + + DATA0 + Data 0 line signal level + 0 + + + DATA1 + Data 1 line signal level + 0x1 + + + DATA2 + Data 2 line signal level + 0x2 + + + DATA3 + Data 3 line signal level + 0x3 + + + DATA4 + Data 4 line signal level + 0x4 + + + DATA5 + Data 5 line signal level + 0x5 + + + DATA6 + Data 6 line signal level + 0x6 + + + DATA7 + Data 7 line signal level + 0x7 + + + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data transfer width + 1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as card detection pin + 3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor card insertion + 0 + + + D3CD_1 + DATA3 as card detection pin + 0x1 + + + + + EMODE + Endian mode + 4 + 2 + read-write + + + EMODE_0 + Big endian mode + 0 + + + EMODE_1 + Half word big endian mode + 0x1 + + + EMODE_2 + Little endian mode + 0x2 + + + + + CDTL + Card detect test level + 6 + 1 + read-write + + + CDTL_0 + Card detect test level is 0, no card inserted + 0 + + + CDTL_1 + Card detect test level is 1, card inserted + 0x1 + + + + + CDSS + Card detect signal selection + 7 + 1 + read-write + + + CDSS_0 + Card detection level is selected (for normal purpose). + 0 + + + CDSS_1 + Card detection test level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA select + 8 + 2 + read-write + + + DMASEL_0 + No DMA or simple DMA is selected. + 0 + + + DMASEL_1 + ADMA1 is selected. + 0x1 + + + DMASEL_2 + ADMA2 is selected. + 0x2 + + + + + SABGREQ + Stop at block gap request + 16 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue request + 17 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read wait control + 18 + 1 + read-write + + + RWCTL_0 + Disables read wait control and stop SD clock at block gap when SABGREQ field is set + 0 + + + RWCTL_1 + Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set + 0x1 + + + + + IABG + Interrupt at block gap + 19 + 1 + read-write + + + IABG_0 + Disables interrupt at block gap + 0 + + + IABG_1 + Enables interrupt at block gap + 0x1 + + + + + RD_DONE_NO_8CLK + Read performed number 8 clock + 20 + 1 + read-write + + + WECINT + Wakeup event enable on card interrupt + 24 + 1 + read-write + + + WECINT_0 + Disables wakeup event enable on card interrupt + 0 + + + WECINT_1 + Enables wakeup event enable on card interrupt + 0x1 + + + + + WECINS + Wakeup event enable on SD card insertion + 25 + 1 + read-write + + + WECINS_0 + Disable wakeup event enable on SD card insertion + 0 + + + WECINS_1 + Enable wakeup event enable on SD card insertion + 0x1 + + + + + WECRM + Wakeup event enable on SD card removal + 26 + 1 + read-write + + + WECRM_0 + Disables wakeup event enable on SD card removal + 0 + + + WECRM_1 + Enables wakeup event enable on SD card removal + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 27 + 3 + read-write + + + BURST_LEN_EN_1 + Burst length is enabled for INCR. + #xx1 + + + + + NON_EXACT_BLK_RD + Non-exact block read + 30 + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + DVS + Divisor + 4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK frequency select + 8 + 8 + read-write + + + DTOCV + Data timeout counter value + 16 + 4 + read-write + + + DTOCV_0 + SDCLK x 2 32 + 0 + + + DTOCV_1 + SDCLK x 2 33 + 0x1 + + + DTOCV_2 + SDCLK x 2 18 + 0x2 + + + DTOCV_3 + SDCLK x 2 19 + 0x3 + + + DTOCV_13 + SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode + 0xD + + + DTOCV_14 + SDCLK x 2 30 recommend to use for HS200/SDR104 mode + 0xE + + + DTOCV_15 + SDCLK x 2 31 recommend to use for HS400 mode + 0xF + + + + + IPP_RST_N + Hardware reset + 23 + 1 + read-write + + + RSTA + Software reset for all + 24 + 1 + read-write + + + RSTA_0 + No reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software reset for CMD line + 25 + 1 + read-write + + + RSTC_0 + No reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software reset for data line + 26 + 1 + read-write + + + RSTD_0 + No reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization active + 27 + 1 + read-write + + + RSTT + Reset tuning + 28 + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer complete + 1 + 1 + read-write + oneToClear + + + TC_0 + Transfer does not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block gap event + 2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA interrupt + 3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA interrupt + 0 + + + DINT_1 + DMA interrupt is generated. + 0x1 + + + + + BWR + Buffer write ready + 4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer + 0x1 + + + + + BRR + Buffer read ready + 5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card insertion + 6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card removal + 7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card interrupt + 8 + 1 + read-write + oneToClear + + + CINT_0 + No card interrupt + 0 + + + CINT_1 + Generate card interrupt + 0x1 + + + + + RTE + Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-write + oneToClear + + + RTE_0 + Re-tuning is not required. + 0 + + + RTE_1 + Re-tuning should be performed. + 0x1 + + + + + TP + Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) + 14 + 1 + read-write + oneToClear + + + CTOE + Command timeout error + 16 + 1 + read-write + oneToClear + + + CTOE_0 + No error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC error + 17 + 1 + read-write + oneToClear + + + CCE_0 + No error + 0 + + + CCE_1 + CRC error generated + 0x1 + + + + + CEBE + Command end bit error + 18 + 1 + read-write + oneToClear + + + CEBE_0 + No error + 0 + + + CEBE_1 + End bit error generated + 0x1 + + + + + CIE + Command index error + 19 + 1 + read-write + oneToClear + + + CIE_0 + No error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data timeout error + 20 + 1 + read-write + oneToClear + + + DTOE_0 + No error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC error + 21 + 1 + read-write + oneToClear + + + DCE_0 + No error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data end bit error + 22 + 1 + read-write + oneToClear + + + DEBE_0 + No error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 error + 24 + 1 + read-write + oneToClear + + + AC12E_0 + No error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 26 + 1 + read-write + oneToClear + + + DMAE + DMA error + 28 + 1 + read-write + oneToClear + + + DMAE_0 + No error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command complete status enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer complete status enable + 1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block gap event status enable + 2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA interrupt status enable + 3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer write ready status enable + 4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer read ready status enable + 5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card insertion status enable + 6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card removal status enable + 7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card interrupt status enable + 8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-tuning event status enable + 12 + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning pass status enable + 14 + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command timeout error status enable + 16 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC error status enable + 17 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command end bit error status enable + 18 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command index error status enable + 19 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data timeout error status enable + 20 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC error status enable + 21 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data end bit error status enable + 22 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 error status enable + 24 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning error status enable + 26 + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA error status enable + 28 + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command complete interrupt enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer complete interrupt enable + 1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block gap event interrupt enable + 2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA interrupt enable + 3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer write ready interrupt enable + 4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer read ready interrupt enable + 5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card insertion interrupt enable + 6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card removal interrupt enable + 7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card interrupt enable + 8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-tuning event interrupt enable + 12 + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass interrupt enable + 14 + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command timeout error interrupt enable + 16 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC error interrupt enable + 17 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command end bit error interrupt enable + 18 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command index error interrupt enable + 19 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data timeout error interrupt enable + 20 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC error interrupt enable + 21 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data end bit error interrupt enable + 22 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 error interrupt enable + 24 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning error interrupt enable + 26 + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA error interrupt enable + 28 + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 not executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 timeout error + 1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 end bit error + 2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End bit error generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC error + 3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC error met in Auto CMD12/23 response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 index error + 4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command not issued by Auto CMD12 error + 7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not issued + 0x1 + + + + + EXECUTE_TUNING + Execute tuning + 22 + 1 + read-write + + + SMP_CLK_SEL + Sample clock select + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time counter for retuning + 8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning. + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning. + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 14 + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max block length + 16 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA support + 20 + 1 + read-only + + + ADMAS_0 + Advanced DMA not supported + 0 + + + ADMAS_1 + Advanced DMA supported + 0x1 + + + + + HSS + High speed support + 21 + 1 + read-only + + + HSS_0 + High speed not supported + 0 + + + HSS_1 + High speed supported + 0x1 + + + + + DMAS + DMA support + 22 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA supported + 0x1 + + + + + SRS + Suspend / resume support + 23 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage support 3.3 V + 24 + 1 + read-only + + + VS33_0 + 3.3 V not supported + 0 + + + VS33_1 + 3.3 V supported + 0x1 + + + + + VS30 + Voltage support 3.0 V + 25 + 1 + read-only + + + VS30_0 + 3.0 V not supported + 0 + + + VS30_1 + 3.0 V supported + 0x1 + + + + + VS18 + Voltage support 1.8 V + 26 + 1 + read-only + + + VS18_0 + 1.8 V not supported + 0 + + + VS18_1 + 1.8 V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read watermark level + 0 + 8 + read-write + + + RD_BRST_LEN + Read burst length due to system restriction, the actual burst length might not exceed 16 + 8 + 5 + read-write + + + WR_WML + Write watermark level + 16 + 8 + read-write + + + WR_BRST_LEN + Write burst length due to system restriction, the actual burst length might not exceed 16 + 24 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block count enable + 1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 enable + 2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual data rate mode selection + 3 + 1 + read-write + + + DTDSEL + Data transfer direction select + 4 + 1 + read-write + + + DTDSEL_0 + Write (Host to card) + 0 + + + DTDSEL_1 + Read (Card to host) + 0x1 + + + + + MSBSEL + Multi / Single block select + 5 + 1 + read-write + + + MSBSEL_0 + Single block + 0 + + + MSBSEL_1 + Multiple blocks + 0x1 + + + + + NIBBLE_POS + Nibble position indication + 6 + 1 + read-write + + + AC23EN + Auto CMD23 enable + 7 + 1 + read-write + + + EXE_TUNE + Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 22 + 1 + read-write + + + EXE_TUNE_0 + Not tuned or tuning completed + 0 + + + EXE_TUNE_1 + Execute tuning + 0x1 + + + + + SMP_CLK_SEL + Clock selection + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + 24 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 25 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force event auto command 12 not executed + 0 + 1 + read-write + + + FEVTAC12TOE + Force event auto command 12 time out error + 1 + 1 + read-write + + + FEVTAC12CE + Force event auto command 12 CRC error + 2 + 1 + read-write + + + FEVTAC12EBE + Force event Auto Command 12 end bit error + 3 + 1 + read-write + + + FEVTAC12IE + Force event Auto Command 12 index error + 4 + 1 + read-write + + + FEVTCNIBAC12E + Force event command not executed by Auto Command 12 error + 7 + 1 + read-write + + + FEVTCTOE + Force event command time out error + 16 + 1 + read-write + + + FEVTCCE + Force event command CRC error + 17 + 1 + read-write + + + FEVTCEBE + Force event command end bit error + 18 + 1 + read-write + + + FEVTCIE + Force event command index error + 19 + 1 + read-write + + + FEVTDTOE + Force event data time out error + 20 + 1 + read-write + + + FEVTDCE + Force event data CRC error + 21 + 1 + read-write + + + FEVTDEBE + Force event data end bit error + 22 + 1 + read-write + + + FEVTAC12E + Force event Auto Command 12 error + 24 + 1 + read-write + + + FEVTTNE + Force tuning error + 26 + 1 + read-write + + + FEVTDMAE + Force event DMA error + 28 + 1 + read-write + + + FEVTCINT + Force event card interrupt + 31 + 1 + read-write + + + + + ADMA_ERR_STATUS + ADMA Error Status + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA error state (when ADMA error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA length mismatch error + 2 + 1 + read-only + + + ADMALME_0 + No error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA descriptor error + 3 + 1 + read-only + + + ADMADCE_0 + No error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA system address + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + DLL and delay chain + 0 + 1 + read-write + + + DLL_CTRL_RESET + DLL reset + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + DLL slave delay line + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + DLL slave delay target0 + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + DLL gate update + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + DLL slave override + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + DLL slave override val + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + DLL slave delay target1 + 16 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + Slave delay line update interval + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL control loop update interval + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0x200 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + Reference DLL lock status + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + Slave delay line select status + 2 + 7 + read-only + + + DLL_STS_REF_SEL + Reference delay line select taps + 9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + Delay cells on the feedback clock between CLK_OUT and CLK_POST + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + Delay cells on the feedback clock between CLK_PRE and CLK_OUT + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + delay cells on the feedback clock between the feedback clock and CLK_PRE + 8 + 7 + read-write + + + NXT_ERR + NXT error + 15 + 1 + read-only + + + TAP_SEL_POST + Delay cells added on the feedback clock between CLK_OUT and CLK_POST + 16 + 4 + read-only + + + TAP_SEL_OUT + Delay cells added on the feedback clock between CLK_PRE and CLK_OUT + 20 + 4 + read-only + + + TAP_SEL_PRE + TAP_SEL_PRE + 24 + 7 + read-only + + + PRE_ERR + PRE error + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + VSELECT + Voltage selection + 1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable + 2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + Check busy enable + 3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + FRC_SDCLK_ON + Force CLK + 8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 15 + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC fields for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet + 0x1 + + + + + CMD_BYTE_EN + Byte access + 31 + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + Boot ACK time out + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^14 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^15 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^16 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^17 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^18 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^19 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^20 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^21 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^28 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^29 + 0xF + + + + + BOOT_ACK + BOOT ACK + 4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + Boot mode + 5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + Boot enable + 6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + Auto stop at block gap + 7 + 1 + read-write + + + DISABLE_TIME_OUT + Time out + 8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + Stop At Block Gap value of automatic mode + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x1006 + 0xFFFFFFFF + + + CARD_INT_D3_TEST + Card interrupt detection test + 3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + Tuning 8bit enable + 4 + 1 + read-write + + + TUNING_1bit_EN + Tuning 1bit enable + 5 + 1 + read-write + + + TUNING_CMD_EN + Tuning command enable + 6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + ACMD23_ARGU2_EN + Argument2 register enable for ACMD23 + 12 + 1 + read-write + + + ACMD23_ARGU2_EN_0 + Disable + 0 + + + ACMD23_ARGU2_EN_1 + Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. + 0x1 + + + + + + + TUNING_CTRL + Tuning Control + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + Tuning start + 0 + 8 + read-write + + + TUNING_COUNTER + Tuning counter + 8 + 8 + read-write + + + TUNING_STEP + TUNING_STEP + 16 + 3 + read-write + + + TUNING_WINDOW + Data window + 20 + 3 + read-write + + + STD_TUNING_EN + Standard tuning circuit and procedure enable + 24 + 1 + read-write + + + + + + + USDHC2 + uSDHC + USDHC + 0x402C4000 + + 0 + 0xD0 + registers + + + USDHC2 + 111 + + + + ENET + ENET + ENET + 0x402D8000 + + 0 + 0x628 + registers + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + Timestamp Timer + 15 + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 16 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 17 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 18 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 19 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 20 + 1 + read-write + oneToClear + + + LC + Late Collision + 21 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 22 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 23 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 24 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 25 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 26 + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 27 + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 28 + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 29 + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 30 + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + TS_TIMER Interrupt Mask + 15 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 16 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + WAKEUP + WAKEUP Interrupt Mask + 17 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + PLR + PLR Interrupt Mask + 18 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + UN + UN Interrupt Mask + 19 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + RL + RL Interrupt Mask + 20 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + LC + LC Interrupt Mask + 21 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + EBERR + EBERR Interrupt Mask + 22 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + MII + MII Interrupt Mask + 23 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + RXB + RXB Interrupt Mask + 24 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + RXF + RXF Interrupt Mask + 25 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + TXB + TXB Interrupt Mask + 26 + 1 + read-write + + + MASKED + The corresponding interrupt source is masked. + 0 + + + UNMASKED + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 27 + 1 + read-write + + + MASKED + The corresponding interrupt source is masked. + 0 + + + UNMASKED + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 28 + 1 + read-write + + + MASKED + The corresponding interrupt source is masked. + 0 + + + UMASKED + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 29 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 30 + 1 + read-write + + + ZERO + The corresponding interrupt source is masked. + 0 + + + ONE + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register - Ring 0 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register - Ring 0 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 1 + 1 + read-write + + + ZERO + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ONE + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 2 + 1 + read-write + + + ZERO + Magic detection logic disabled. + 0 + + + ONE + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 3 + 1 + read-write + + + ZERO + Normal operating mode. + 0 + + + ONE + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 4 + 1 + read-write + + + ZERO + Legacy FEC buffer descriptors and functions enabled. + 0 + + + ONE + Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. + 0x1 + + + + + DBGEN + Debug Enable + 6 + 1 + read-write + + + ZERO + MAC continues operation in debug mode. + 0 + + + ONE + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 8 + 1 + read-write + + + ZERO + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + ONE + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 16 + 2 + read-write + + + RA + Register Address + 18 + 5 + read-write + + + PA + PHY Address + 23 + 5 + read-write + + + OP + Operation Code + 28 + 2 + read-write + + + ST + Start Of Frame Delimiter + 30 + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 7 + 1 + read-write + + + ZERO + Preamble enabled. + 0 + + + ONE + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 8 + 3 + read-write + + + VAL_1 + 1 internal module clock cycle + 0 + + + VAL2 + 2 internal module clock cycles + 0x1 + + + VAL3 + 3 internal module clock cycles + 0x2 + + + VAL8 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 29 + 1 + read-write + + + ZERO + See note above. + 0 + + + ONE + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 30 + 1 + read-only + + + ZERO + The MIB block is updating MIB counters. + 0 + + + ONE + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 31 + 1 + read-write + + + ZERO + MIB logic is enabled. + 0 + + + ONE + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + ZERO + Loopback disabled. + 0 + + + ONE + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 1 + 1 + read-write + + + ZERO + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + ONE + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 2 + 1 + read-write + + + ONE + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 3 + 1 + read-write + + + ZERO + Disabled. + 0 + + + ONE + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 4 + 1 + read-write + + + ZERO + Will not reject frames as described above + 0 + + + ONE + Will reject frames as described above + 0x1 + + + + + FCE + Flow Control Enable + 5 + 1 + read-write + + + ZERO + Disable flow control + 0 + + + ONE + Enable flow control + 0x1 + + + + + RMII_MODE + RMII Mode Enable + 8 + 1 + read-write + + + ZERO + MAC configured for MII mode. + 0 + + + ONE + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII . + 9 + 1 + read-write + + + ZERO + 100-Mbit/s operation. + 0 + + + ONE + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 12 + 1 + read-write + + + ZERO + No padding is removed on receive by the MAC. + 0 + + + ONE + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 13 + 1 + read-write + + + ZERO + Pause frames are terminated and discarded in the MAC. + 0 + + + ONE + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 14 + 1 + read-write + + + ZERO + The CRC field of received frames is transmitted to the user application. + 0 + + + ONE + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 15 + 1 + read-write + + + ZERO + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + ONE + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 16 + 14 + read-write + + + NLC + Payload Length Check Disable + 30 + 1 + read-write + + + ZERO + The payload length check is disabled. + 0 + + + ONE + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 31 + 1 + read-only + + + ZERO + Receive not stopped + 0 + + + ONE + Receive stopped + 0x1 + + + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + ZERO + Disable graceful transmit stop + 0 + + + ONE + Enable graceful transmit stop + 0x1 + + + + + FDEN + Full-Duplex Enable + 2 + 1 + read-write + + + ZERO + Disable full-duplex + 0 + + + ONE + Enable full-duplex + 0x1 + + + + + TFC_PAUSE + Transmit Frame Control Pause + 3 + 1 + read-write + + + ZERO + No PAUSE frame transmitted. + 0 + + + ONE + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 5 + 3 + read-write + + + VAL_MAC + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 8 + 1 + read-write + + + ZERO + The source MAC address is not modified by the MAC. + 0 + + + ONE + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 9 + 1 + read-write + + + ZERO + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + ONE + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 16 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 16 + 16 + read-only + + + + + TXIC0 + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ZERO + Use MII/GMII TX clocks. + 0 + + + ONE + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ZERO + Disable Interrupt coalescing. + 0 + + + ONE + Enable Interrupt coalescing. + 0x1 + + + + + + + RXIC0 + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ZERO + Use MII/GMII TX clocks. + 0 + + + ONE + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ZERO + Disable Interrupt coalescing. + 0 + + + ONE + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + VAL64_0 + 64 bytes written. + 0 + + + VAL64_1 + 64 bytes written. + 0x1 + + + VAL128 + 128 bytes written. + 0x2 + + + VAL192 + 192 bytes written. + 0x3 + + + VAL1984 + 1984 bytes written. + 0x1F + + + + + STRFWD + Store And Forward Enable + 8 + 1 + read-write + + + ZERO + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + ONE + Enabled. + 0x1 + + + + + + + RDSR + Receive Descriptor Ring 0 Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. + 3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring 0 Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register - Ring 0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 10 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 8 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 8 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 16 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 8 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + ZERO + Disabled. + 0 + + + ONE + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 3 + 1 + read-write + + + ZERO + Checksum is not inserted. + 0 + + + ONE + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 4 + 1 + read-write + + + ZERO + Checksum not inserted. + 0 + + + ONE + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + ZERO + Padding not removed. + 0 + + + ONE + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 1 + 1 + read-write + + + ZERO + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + ONE + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 2 + 1 + read-write + + + ZERO + Frames with wrong checksum are not discarded. + 0 + + + ONE + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 6 + 1 + read-write + + + ZERO + Frames with errors are not discarded. + 0 + + + ONE + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 7 + 1 + read-write + + + ZERO + Disabled. + 0 + + + ONE + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + ZERO + The timer stops at the current value. + 0 + + + ONE + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 2 + 1 + read-write + + + ZERO + Disable. + 0 + + + ONE + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 3 + 1 + read-write + + + ZERO + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + ONE + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 4 + 1 + read-write + + + ZERO + Disable. + 0 + + + ONE + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output external pin frc_evt_period assertion on period event + 7 + 1 + read-write + + + ZERO + Disable. + 0 + + + ONE + Enable. + 0x1 + + + + + RESTART + Reset Timer + 9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 11 + 1 + read-write + + + ZERO + No effect. + 0 + + + ONE + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 13 + 1 + read-write + + + ZERO + The timer is active and all configuration fields in this register are relevant. + 0 + + + ONE + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + ZERO + Timer Flag for Channel 0 is clear + 0 + + + ONE + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 1 + 1 + read-write + oneToClear + + + ZERO + Timer Flag for Channel 1 is clear + 0 + + + ONE + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 2 + 1 + read-write + oneToClear + + + ZERO + Timer Flag for Channel 2 is clear + 0 + + + ONE + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 3 + 1 + read-write + oneToClear + + + ZERO + Timer Flag for Channel 3 is clear + 0 + + + ONE + Timer Flag for Channel 3 is set + 0x1 + + + + + + + TCSR0 + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + ZERO + DMA request is disabled + 0 + + + ONE + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMR_DIS + Timer Channel is disabled. + 0 + + + TMR_RE + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMR_FE + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMR_BE + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMR_OUT + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMR_TOGGLE + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMR_CLR + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMR_SET_OUT + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMR_CLR_SET1 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMR_CLR_SET + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMR_OUT_CMP_LOW + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMR_OUT_CMP_HIGH + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + ZERO + Interrupt is disabled + 0 + + + ONE + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + ZERO + Input Capture or Output Compare has not occurred. + 0 + + + ONE + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + VALW1 + Pulse width is one 1588-clock cycle. + 0 + + + VALW2 + Pulse width is two 1588-clock cycles. + 0x1 + + + VALW3 + Pulse width is three 1588-clock cycles. + 0x2 + + + VALW4 + Pulse width is four 1588-clock cycles. + 0x3 + + + VALW32 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + TCCR0 + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + TCSR1 + Timer Control Status Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + ZERO + DMA request is disabled + 0 + + + ONE + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMR_DIS + Timer Channel is disabled. + 0 + + + TMR_RE + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMR_FE + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMR_BE + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMR_OUT + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMR_TOGGLE + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMR_CLR + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMR_SET_OUT + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMR_CLR_SET1 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMR_CLR_SET + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMR_OUT_CMP_LOW + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMR_OUT_CMP_HIGH + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + ZERO + Interrupt is disabled + 0 + + + ONE + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + ZERO + Input Capture or Output Compare has not occurred. + 0 + + + ONE + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + VALW1 + Pulse width is one 1588-clock cycle. + 0 + + + VALW2 + Pulse width is two 1588-clock cycles. + 0x1 + + + VALW3 + Pulse width is three 1588-clock cycles. + 0x2 + + + VALW4 + Pulse width is four 1588-clock cycles. + 0x3 + + + VALW32 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + TCCR1 + Timer Compare Capture Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + TCSR2 + Timer Control Status Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + ZERO + DMA request is disabled + 0 + + + ONE + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMR_DIS + Timer Channel is disabled. + 0 + + + TMR_RE + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMR_FE + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMR_BE + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMR_OUT + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMR_TOGGLE + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMR_CLR + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMR_SET_OUT + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMR_CLR_SET1 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMR_CLR_SET + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMR_OUT_CMP_LOW + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMR_OUT_CMP_HIGH + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + ZERO + Interrupt is disabled + 0 + + + ONE + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + ZERO + Input Capture or Output Compare has not occurred. + 0 + + + ONE + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + VALW1 + Pulse width is one 1588-clock cycle. + 0 + + + VALW2 + Pulse width is two 1588-clock cycles. + 0x1 + + + VALW3 + Pulse width is three 1588-clock cycles. + 0x2 + + + VALW4 + Pulse width is four 1588-clock cycles. + 0x3 + + + VALW32 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + TCCR2 + Timer Compare Capture Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + TCSR3 + Timer Control Status Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + ZERO + DMA request is disabled + 0 + + + ONE + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMR_DIS + Timer Channel is disabled. + 0 + + + TMR_RE + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMR_FE + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMR_BE + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMR_OUT + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMR_TOGGLE + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMR_CLR + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMR_SET_OUT + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMR_CLR_SET1 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMR_CLR_SET + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMR_OUT_CMP_LOW + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMR_OUT_CMP_HIGH + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + ZERO + Interrupt is disabled + 0 + + + ONE + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + ZERO + Input Capture or Output Compare has not occurred. + 0 + + + ONE + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + VALW1 + Pulse width is one 1588-clock cycle. + 0 + + + VALW2 + Pulse width is two 1588-clock cycles. + 0x1 + + + VALW3 + Pulse width is three 1588-clock cycles. + 0x2 + + + VALW4 + Pulse width is four 1588-clock cycles. + 0x3 + + + VALW32 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + TCCR3 + Timer Compare Capture Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + USB1 + USB + USB + USB_ + USB + 0x402E0000 + + 0 + 0x1E0 + registers + + + USB_OTG1 + 113 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 16 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 16 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 12 + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 16 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 20 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 24 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 1 + 1 + read-write + + + FS_1 + See description at bit 15 + 2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 11 + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 13 + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 14 + 1 + read-write + + + FS_2 + Frame List Size - (Read/Write or Read Only) + 15 + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 16 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 3 + 1 + read-write + + + SEI + System Error- R/WC + 4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 6 + 1 + read-write + + + SRI + SOF Received - R/WC + 7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 10 + 1 + read-write + + + HCH + HCHaIted - Read Only + 12 + 1 + read-write + + + RCL + Reclamation - Read Only + 13 + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 14 + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 15 + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 16 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 24 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 25 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 10 + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 16 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 18 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 19 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 24 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 25 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 24 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 25 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 16 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 16 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 16 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 9 + 1 + read-only + + + LS + Line Status-Read Only + 10 + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 12 + 1 + read-write + + + PO + Port Owner-Read/Write + 13 + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 14 + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 16 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 20 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 21 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 22 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 23 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 24 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 25 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 26 + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 28 + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 29 + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 30 + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 11 + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 12 + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 13 + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 14 + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 16 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 17 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 18 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 19 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 20 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 21 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 22 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 26 + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 27 + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 28 + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 29 + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 30 + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 16 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 16 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 16 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 18 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 23 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + + + USB2 + USB + USB + USB_ + 0x402E0200 + + 0 + 0x1E0 + registers + + + USB_OTG2 + 112 + + + + USBNC1 + USB + USB1 + USBNC + USBNC_ + 0x402E0000 + + 0 + 0x81C + registers + + + + USB_OTG1_CTRL + USB OTG1 Control Register + 0x800 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTG1 Overcurrent Detection + 7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event + 8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity. + 9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt + 10 + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTG1 Software Wake-up Enable + 14 + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTG1 Software Wake-up + 15 + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTG1 Wake-up on ID change enable + 16 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTG1 wake-up on VBUS change enable + 17 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WKUP_DPDM_EN + Wake-up on DPDM change enable + 29 + 1 + read-write + + + WKUP_DPDM_EN_0 + DPDM changes wake-up to be disabled only when VBUS is 0. + 0 + + + WKUP_DPDM_EN_1 + (Default) DPDM changes wake-up to be enabled, it is for device only. + 0x1 + + + + + WIR + OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port + 31 + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTG1_PHY_CTRL_0 + OTG1 UTMI PHY Control 0 Register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTG1 UTMI PHY clock is valid + 31 + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + USBNC2 + USB + USBNC + USBNC_ + 0x402E0004 + + 0 + 0x81C + registers + + + + USB_OTG2_CTRL + USB OTG2 Control Register + 0x800 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTG2 Overcurrent Detection + 7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTG2 Polarity of Overcurrent The polarity of OTG2 port overcurrent event + 8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTG2 Power Polarity This bit should be set according to PMIC Power Pin polarity. + 9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTG2 Wake-up Interrupt Enable This bit enables or disables the OTG2 wake-up interrupt + 10 + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTG2 Software Wake-up Enable + 14 + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTG2 Software Wake-up + 15 + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTG2 Wake-up on ID change enable + 16 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTG2 wake-up on VBUS change enable + 17 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WKUP_DPDM_EN + Wake-up on DPDM change enable + 29 + 1 + read-write + + + WKUP_DPDM_EN_0 + DPDM changes wake-up to be disabled only when VBUS is 0. + 0 + + + WKUP_DPDM_EN_1 + (Default) DPDM changes wake-up to be enabled, it is for device only. + 0x1 + + + + + WIR + OTG2 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG port + 31 + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTG2_PHY_CTRL_0 + OTG2 UTMI PHY Control 0 Register + 0x818 + 32 + read-write + 0x98 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTG2 UTMI PHY clock is valid + 31 + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + SEMC + SEMC + SEMC + 0x402F0000 + + 0 + 0x100 + registers + + + SEMC + 109 + + + + MCR + Module Control Register + 0 + 32 + read-write + 0x10000002 + 0xFFFFFFFF + + + SWRST + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + MDIS_0 + Module enabled + 0 + + + MDIS_1 + Module disabled + 0x1 + + + + + DQSMD + DQS (read strobe) mode + 2 + 1 + read-write + + + DQSMD_0 + Dummy read strobe loopbacked internally + 0 + + + DQSMD_1 + Dummy read strobe loopbacked from DQS pad + 0x1 + + + + + WPOL0 + WAIT/RDY# polarity for NOR/PSRAM + 6 + 1 + read-write + + + WPOL0_0 + Active low + 0 + + + WPOL0_1 + Active high + 0x1 + + + + + WPOL1 + WAIT/RDY# polarity for NAND + 7 + 1 + read-write + + + WPOL1_0 + Active low + 0 + + + WPOL1_1 + Active high + 0x1 + + + + + CTO + Command Execution timeout cycles + 16 + 8 + read-write + + + BTO + Bus timeout cycles + 24 + 5 + read-write + + + BTO_0 + 255*1 + 0 + + + BTO_1 + 255*2 - 255*2^30 + 0x1 + + + BTO_2 + 255*2 - 255*2^30 + 0x2 + + + BTO_3 + 255*2 - 255*2^30 + 0x3 + + + BTO_4 + 255*2 - 255*2^30 + 0x4 + + + BTO_5 + 255*2 - 255*2^30 + 0x5 + + + BTO_6 + 255*2 - 255*2^30 + 0x6 + + + BTO_7 + 255*2 - 255*2^30 + 0x7 + + + BTO_8 + 255*2 - 255*2^30 + 0x8 + + + BTO_9 + 255*2 - 255*2^30 + 0x9 + + + BTO_31 + 255*2^31 + 0x1F + + + + + + + IOCR + IO Mux Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_A8 + SEMC_A8 output selection + 0 + 3 + read-write + + + MUX_A8_0 + SDRAM Address bit (A8) + 0 + + + MUX_A8_1 + NAND CE# + 0x1 + + + MUX_A8_2 + NOR CE# + 0x2 + + + MUX_A8_3 + PSRAM CE# + 0x3 + + + MUX_A8_4 + DBI CSX + 0x4 + + + MUX_A8_5 + SDRAM Address bit (A8) + 0x5 + + + MUX_A8_6 + SDRAM Address bit (A8) + 0x6 + + + MUX_A8_7 + SDRAM Address bit (A8) + 0x7 + + + + + MUX_CSX0 + SEMC_CSX0 output selection + 3 + 3 + read-write + + + MUX_CSX0_0 + NOR/PSRAM Address bit 24 (A24) + 0 + + + MUX_CSX0_1 + SDRAM CS1 + 0x1 + + + MUX_CSX0_2 + SDRAM CS2 + 0x2 + + + MUX_CSX0_3 + SDRAM CS3 + 0x3 + + + MUX_CSX0_4 + NAND CE# + 0x4 + + + MUX_CSX0_5 + NOR CE# + 0x5 + + + MUX_CSX0_6 + PSRAM CE# + 0x6 + + + MUX_CSX0_7 + DBI CSX + 0x7 + + + + + MUX_CSX1 + SEMC_CSX1 output selection + 6 + 3 + read-write + + + MUX_CSX1_0 + NOR/PSRAM Address bit 25 (A25) + 0 + + + MUX_CSX1_1 + SDRAM CS1 + 0x1 + + + MUX_CSX1_2 + SDRAM CS2 + 0x2 + + + MUX_CSX1_3 + SDRAM CS3 + 0x3 + + + MUX_CSX1_4 + NAND CE# + 0x4 + + + MUX_CSX1_5 + NOR CE# + 0x5 + + + MUX_CSX1_6 + PSRAM CE# + 0x6 + + + MUX_CSX1_7 + DBI CSX + 0x7 + + + + + MUX_CSX2 + SEMC_CSX2 output selection + 9 + 3 + read-write + + + MUX_CSX2_0 + NOR/PSRAM Address bit 26 (A26) + 0 + + + MUX_CSX2_1 + SDRAM CS1 + 0x1 + + + MUX_CSX2_2 + SDRAM CS2 + 0x2 + + + MUX_CSX2_3 + SDRAM CS3 + 0x3 + + + MUX_CSX2_4 + NAND CE# + 0x4 + + + MUX_CSX2_5 + NOR CE# + 0x5 + + + MUX_CSX2_6 + PSRAM CE# + 0x6 + + + MUX_CSX2_7 + DBI CSX + 0x7 + + + + + MUX_CSX3 + SEMC_CSX3 output selection + 12 + 3 + read-write + + + MUX_CSX3_0 + NOR/PSRAM Address bit 27 (A27) + 0 + + + MUX_CSX3_1 + SDRAM CS1 + 0x1 + + + MUX_CSX3_2 + SDRAM CS2 + 0x2 + + + MUX_CSX3_3 + SDRAM CS3 + 0x3 + + + MUX_CSX3_4 + NAND CE# + 0x4 + + + MUX_CSX3_5 + NOR CE# + 0x5 + + + MUX_CSX3_6 + PSRAM CE# + 0x6 + + + MUX_CSX3_7 + DBI CSX + 0x7 + + + + + MUX_RDY + SEMC_RDY function selection + 15 + 3 + read-write + + + MUX_RDY_0 + NAND Ready/Wait# input + 0 + + + MUX_RDY_1 + SDRAM CS1 + 0x1 + + + MUX_RDY_2 + SDRAM CS2 + 0x2 + + + MUX_RDY_3 + SDRAM CS3 + 0x3 + + + MUX_RDY_4 + NOR CE# + 0x4 + + + MUX_RDY_5 + PSRAM CE# + 0x5 + + + MUX_RDY_6 + DBI CSX + 0x6 + + + MUX_RDY_7 + NOR/PSRAM Address bit 27 + 0x7 + + + + + + + BMCR0 + Bus (AXI) Master Control Register 0 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + WAGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + WSH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + WRWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + + + BMCR1 + Bus (AXI) Master Control Register 1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + WAGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + WPH + Weight of Page Hit. This weight score is valid when queue command's page hits current executing command. + 8 + 8 + read-write + + + WRWS + Weight of slave hit without Read/Write Switch. This weight score is valid when queue command's read/write operation is same as current executing command. + 16 + 8 + read-write + + + WBR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current executing command. + 24 + 8 + read-write + + + + + BR0 + Base Register 0 (For SDRAM CS0 device) + 0x10 + 32 + read-write + 0x8000001D + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR1 + Base Register 1 (For SDRAM CS1 device) + 0x14 + 32 + read-write + 0x8400001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR2 + Base Register 2 (For SDRAM CS2 device) + 0x18 + 32 + read-write + 0x8800001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR3 + Base Register 3 (For SDRAM CS3 device) + 0x1C + 32 + read-write + 0x8C00001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR4 + Base Register 4 (For NAND device) + 0x20 + 32 + read-write + 0x9E00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR5 + Base Register 5 (For NOR device) + 0x24 + 32 + read-write + 0x90000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR6 + Base Register 6 (For PSRAM device 0) + 0x28 + 32 + read-write + 0x98000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR7 + Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device) + 0x2C + 32 + read-write + 0x9C00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR8 + Base Register 8 (For NAND device) + 0x30 + 32 + read-write + 0x26 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP command done interrupt enable + 0 + 1 + read-write + + + IPCMDDONEEN_0 + Interrupt is disabled + 0 + + + IPCMDDONEEN_1 + Interrupt is enabled + 0x1 + + + + + IPCMDERREN + IP command error interrupt enable + 1 + 1 + read-write + + + IPCMDERREN_0 + Interrupt is disabled + 0 + + + IPCMDERREN_1 + Interrupt is enabled + 0x1 + + + + + AXICMDERREN + AXI command error interrupt enable + 2 + 1 + read-write + + + AXICMDERREN_0 + Interrupt is disabled + 0 + + + AXICMDERREN_1 + Interrupt is enabled + 0x1 + + + + + AXIBUSERREN + AXI bus error interrupt enable + 3 + 1 + read-write + + + AXIBUSERREN_0 + Interrupt is disabled + 0 + + + AXIBUSERREN_1 + Interrupt is enabled + 0x1 + + + + + NDPAGEENDEN + NAND page end interrupt enable + 4 + 1 + read-write + + + NDPAGEENDEN_0 + Interrupt is disabled + 0 + + + NDPAGEENDEN_1 + Interrupt is enabled + 0x1 + + + + + NDNOPENDEN + NAND no pending AXI access interrupt enable + 5 + 1 + read-write + + + NDNOPENDEN_0 + Interrupt is disabled + 0 + + + NDNOPENDEN_1 + Interrupt is enabled + 0x1 + + + + + + + INTR + Interrupt Enable Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + read-write + oneToClear + + + IPCMDERR + IP command error done interrupt + 1 + 1 + read-write + oneToClear + + + AXICMDERR + AXI command error interrupt + 2 + 1 + read-write + oneToClear + + + AXIBUSERR + AXI bus error interrupt + 3 + 1 + read-write + oneToClear + + + NDPAGEEND + NAND page end interrupt + 4 + 1 + read-write + oneToClear + + + NDNOPEND + NAND no pending AXI access interrupt + 5 + 1 + read-write + oneToClear + + + + + SDRAMCR0 + SDRAM control register 0 + 0x40 + 32 + read-write + 0xC26 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 8 + 0x4 + + + BL_5 + 8 + 0x5 + + + BL_6 + 8 + 0x6 + + + BL_7 + 8 + 0x7 + + + + + COL + Column address bit number + 8 + 2 + read-write + + + COL_0 + 12 bit + 0 + + + COL_1 + 11 bit + 0x1 + + + COL_2 + 10 bit + 0x2 + + + COL_3 + 9 bit + 0x3 + + + + + CL + CAS Latency + 10 + 2 + read-write + + + CL_0 + 1 + 0 + + + CL_1 + 1 + 0x1 + + + CL_2 + 2 + 0x2 + + + CL_3 + 3 + 0x3 + + + + + + + SDRAMCR1 + SDRAM control register 1 + 0x44 + 32 + read-write + 0x994934 + 0xFFFFFFFF + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time + 0 + 4 + read-write + + + ACT2RW + ACT to Read/Write wait time + 4 + 4 + read-write + + + RFRC + Refresh recovery time + 8 + 5 + read-write + + + WRC + Write recovery time + 13 + 3 + read-write + + + CKEOFF + CKE OFF minimum time + 16 + 4 + read-write + + + ACT2PRE + ACT to Precharge minimum time + 20 + 4 + read-write + + + + + SDRAMCR2 + SDRAM control register 2 + 0x48 + 32 + read-write + 0x80000EEE + 0xFFFFFFFF + + + SRRC + Self Refresh Recovery time + 0 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time + 8 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time + 16 + 8 + read-write + + + ITO + SDRAM Idle timeout + 24 + 8 + read-write + + + ITO_0 + IDLE timeout period is 256*Prescale period. + 0 + + + ITO_1 + IDLE timeout period is ITO*Prescale period. + 0x1 + + + ITO_2 + IDLE timeout period is ITO*Prescale period. + 0x2 + + + ITO_3 + IDLE timeout period is ITO*Prescale period. + 0x3 + + + ITO_4 + IDLE timeout period is ITO*Prescale period. + 0x4 + + + ITO_5 + IDLE timeout period is ITO*Prescale period. + 0x5 + + + ITO_6 + IDLE timeout period is ITO*Prescale period. + 0x6 + + + ITO_7 + IDLE timeout period is ITO*Prescale period. + 0x7 + + + ITO_8 + IDLE timeout period is ITO*Prescale period. + 0x8 + + + ITO_9 + IDLE timeout period is ITO*Prescale period. + 0x9 + + + + + + + SDRAMCR3 + SDRAM control register 3 + 0x4C + 32 + read-write + 0x40808000 + 0xFFFFFFFF + + + REN + Refresh enable + 0 + 1 + read-write + + + REBL + Refresh burst length + 1 + 3 + read-write + + + REBL_0 + 1 + 0 + + + REBL_1 + 2 + 0x1 + + + REBL_2 + 3 + 0x2 + + + REBL_3 + 4 + 0x3 + + + REBL_4 + 5 + 0x4 + + + REBL_5 + 6 + 0x5 + + + REBL_6 + 7 + 0x6 + + + REBL_7 + 8 + 0x7 + + + + + PRESCALE + Prescaler timer period + 8 + 8 + read-write + + + PRESCALE_0 + 256*16 clock cycles + 0 + + + PRESCALE_1 + PRESCALE*16 clock cycles + 0x1 + + + PRESCALE_2 + PRESCALE*16 clock cycles + 0x2 + + + PRESCALE_3 + PRESCALE*16 clock cycles + 0x3 + + + PRESCALE_4 + PRESCALE*16 clock cycles + 0x4 + + + PRESCALE_5 + PRESCALE*16 clock cycles + 0x5 + + + PRESCALE_6 + PRESCALE*16 clock cycles + 0x6 + + + PRESCALE_7 + PRESCALE*16 clock cycles + 0x7 + + + PRESCALE_8 + PRESCALE*16 clock cycles + 0x8 + + + PRESCALE_9 + PRESCALE*16 clock cycles + 0x9 + + + + + RT + Refresh timer period + 16 + 8 + read-write + + + RT_0 + 256*Prescaler period + 0 + + + RT_1 + RT*Prescaler period + 0x1 + + + RT_2 + RT*Prescaler period + 0x2 + + + RT_3 + RT*Prescaler period + 0x3 + + + RT_4 + RT*Prescaler period + 0x4 + + + RT_5 + RT*Prescaler period + 0x5 + + + RT_6 + RT*Prescaler period + 0x6 + + + RT_7 + RT*Prescaler period + 0x7 + + + RT_8 + RT*Prescaler period + 0x8 + + + RT_9 + RT*Prescaler period + 0x9 + + + + + UT + Refresh urgent threshold + 24 + 8 + read-write + + + UT_0 + 256*Prescaler period + 0 + + + UT_1 + UT*Prescaler period + 0x1 + + + UT_2 + UT*Prescaler period + 0x2 + + + UT_3 + UT*Prescaler period + 0x3 + + + UT_4 + UT*Prescaler period + 0x4 + + + UT_5 + UT*Prescaler period + 0x5 + + + UT_6 + UT*Prescaler period + 0x6 + + + UT_7 + UT*Prescaler period + 0x7 + + + UT_8 + UT*Prescaler period + 0x8 + + + UT_9 + UT*Prescaler period + 0x9 + + + + + + + NANDCR0 + NAND control register 0 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + EDO + EDO mode enabled + 7 + 1 + read-write + + + EDO_0 + EDO mode disabled + 0 + + + EDO_1 + EDO mode enabled + 0x1 + + + + + COL + Column address bit number + 8 + 3 + read-write + + + COL_0 + 16 + 0 + + + COL_1 + 15 + 0x1 + + + COL_2 + 14 + 0x2 + + + COL_3 + 13 + 0x3 + + + COL_4 + 12 + 0x4 + + + COL_5 + 11 + 0x5 + + + COL_6 + 10 + 0x6 + + + COL_7 + 9 + 0x7 + + + + + + + NANDCR1 + NAND control register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time + 0 + 4 + read-write + + + CEH + CE hold time + 4 + 4 + read-write + + + WEL + WE# low time + 8 + 4 + read-write + + + WEH + WE# high time + 12 + 4 + read-write + + + REL + RE# low time + 16 + 4 + read-write + + + REH + RE# high time + 20 + 4 + read-write + + + TA + Turnaround time + 24 + 4 + read-write + + + CEITV + CE# interval time + 28 + 4 + read-write + + + + + NANDCR2 + NAND control register 2 + 0x58 + 32 + read-write + 0x10410 + 0xFFFFFFFF + + + TWHR + WE# high to RE# low wait time + 0 + 6 + read-write + + + TRHW + RE# high to WE# low wait time + 6 + 6 + read-write + + + TADL + ALE to write data start wait time + 12 + 6 + read-write + + + TRR + Ready to RE# low wait time + 18 + 6 + read-write + + + TWB + WE# high to busy wait time + 24 + 6 + read-write + + + + + NANDCR3 + NAND control register 3 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + NDOPT1 + NAND option bit 1 + 0 + 1 + read-write + + + NDOPT2 + NAND option bit 2 + 1 + 1 + read-write + + + NDOPT3 + NAND option bit 3 + 2 + 1 + read-write + + + + + NORCR0 + NOR control register 0 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode (ADMUX) + 0 + + + AM_1 + Advanced Address/Data MUX mode (AADM) + 0x1 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is active low. + 0 + + + ADVP_1 + ADV# is active high. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + NORCR1 + NOR control register 1 + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time + 0 + 4 + read-write + + + CEH + CE hold time + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE low time + 16 + 4 + read-write + + + WEH + WE high time + 20 + 4 + read-write + + + REL + RE low time + 24 + 4 + read-write + + + REH + RE high time + 28 + 4 + read-write + + + + + NORCR2 + NOR control register 2 + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + TA + Turnaround time + 8 + 4 + read-write + + + AWDH + Address to write data hold time + 12 + 4 + read-write + + + CEITV + CE# interval time + 24 + 4 + read-write + + + + + NORCR3 + NOR control register 3 + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAMCR0 + SRAM control register 0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode (ADMUX) + 0 + + + AM_1 + Advanced Address/Data MUX mode (AADM) + 0x1 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is active low. + 0 + + + ADVP_1 + ADV# is active high. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + SRAMCR1 + SRAM control register 1 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time + 0 + 4 + read-write + + + CEH + CE hold time + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE low time + 16 + 4 + read-write + + + WEH + WE high time + 20 + 4 + read-write + + + REL + RE low time + 24 + 4 + read-write + + + REH + RE high time + 28 + 4 + read-write + + + + + SRAMCR2 + SRAM control register 2 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + TA + Turnaround time + 8 + 4 + read-write + + + AWDH + Address to write data hold time + 12 + 4 + read-write + + + CEITV + CE# interval time + 24 + 4 + read-write + + + + + SRAMCR3 + SRAM control register 3 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBICR0 + DBI-B control register 0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + DBICR1 + DBI-B control register 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CSX Setup Time + 0 + 4 + read-write + + + CEH + CSX Hold Time + 4 + 4 + read-write + + + WEL + WRX Low Time + 8 + 4 + read-write + + + WEH + WRX High Time + 12 + 4 + read-write + + + REL + RDX Low Time bit [3:0] + 16 + 4 + read-write + + + REH + RDX High Time bit [3:0] + 20 + 4 + read-write + + + CEITV + CSX interval time + 24 + 4 + read-write + + + REL2 + RDX Low Time bit [5:4] + 28 + 2 + read-write + + + REH2 + RDX High Time bit [5:4] + 30 + 2 + read-write + + + + + IPCR0 + IP Command control register 0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + IPCR1 + IP Command control register 1 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATSZ + Data Size in Byte + 0 + 3 + read-write + + + DATSZ_0 + 4 + 0 + + + DATSZ_1 + 1 + 0x1 + + + DATSZ_2 + 2 + 0x2 + + + DATSZ_3 + 3 + 0x3 + + + DATSZ_4 + 4 + 0x4 + + + DATSZ_5 + 4 + 0x5 + + + DATSZ_6 + 4 + 0x6 + + + DATSZ_7 + 4 + 0x7 + + + + + + + IPCR2 + IP Command control register 2 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) + 0 + 1 + read-write + + + BM0_0 + Byte Unmasked + 0 + + + BM0_1 + Byte Masked + 0x1 + + + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) + 1 + 1 + read-write + + + BM1_0 + Byte Unmasked + 0 + + + BM1_1 + Byte Masked + 0x1 + + + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) + 2 + 1 + read-write + + + BM2_0 + Byte Unmasked + 0 + + + BM2_1 + Byte Masked + 0x1 + + + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) + 3 + 1 + read-write + + + BM3_0 + Byte Unmasked + 0 + + + BM3_1 + Byte Masked + 0x1 + + + + + + + IPCMD + IP Command register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH is sent to all SDRAM devices because they shared same SEMC_CLK pin + 0 + 16 + read-write + + + KEY + This field should be written with 0xA55A when trigging an IP command. + 16 + 16 + write-only + + + + + IPTXDAT + TX DATA register (for IP Command) + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAT + data + 0 + 32 + read-write + + + + + IPRXDAT + RX DATA register (for IP Command) + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DAT + data + 0 + 32 + read-only + + + + + STS0 + Status register 0 + 0xC0 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + IDLE + Indicating whether SEMC is in IDLE state. + 0 + 1 + read-only + + + NARDY + Indicating NAND device Ready/WAIT# pin level. + 1 + 1 + read-only + + + NARDY_0 + NAND device is not ready + 0 + + + NARDY_1 + NAND device is ready + 0x1 + + + + + + + STS1 + Status register 1 + 0xC4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS2 + Status register 2 + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDWRPEND + This field indicating whether there is pending AXI command (write) to NAND device. + 3 + 1 + read-only + + + NDWRPEND_0 + No pending + 0 + + + NDWRPEND_1 + Pending + 0x1 + + + + + + + STS3 + Status register 3 + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS4 + Status register 4 + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS5 + Status register 5 + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS6 + Status register 6 + 0xD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS7 + Status register 7 + 0xDC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS8 + Status register 8 + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS9 + Status register 9 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS10 + Status register 10 + 0xE8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS11 + Status register 11 + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS12 + Status register 12 + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDADDR + This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). + 0 + 32 + read-only + + + + + STS13 + Status register 13 + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS14 + Status register 14 + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS15 + Status register 15 + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x402FC000 + + 0 + 0x434 + registers + + + DCP + 50 + + + DCP_VMI + 51 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_SET + DCP control register 0 + 0x4 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_CLR + DCP control register 0 + 0x8 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_TOG + DCP control register 0 + 0xC + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_SET + DCP status register + 0x14 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_CLR + DCP status register + 0x18 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_TOG + DCP status register + 0x1C + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_SET + DCP channel control register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_CLR + DCP channel control register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_TOG + DCP channel control register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 29 + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 31 + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + AES128 + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 16 + 16 + read-only + + + SHA1 + SHA1 + 0x1 + + + CRC32 + CRC32 + 0x2 + + + SHA256 + SHA256 + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected memory-copy (memcopy) function should be enabled for this operation. + 4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 8 + 1 + read-only + + + DECRYPT + DECRYPT + 0 + + + ENCRYPT + ENCRYPT + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 10 + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 11 + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 12 + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 13 + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 14 + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 15 + 1 + read-only + + + INPUT + INPUT + 0 + + + OUTPUT + OUTPUT + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 16 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 17 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 18 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 19 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 20 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 21 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 22 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 23 + 1 + read-only + + + TAG + Packet Tag + 24 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + AES128 + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 4 + 4 + read-only + + + ECB + ECB + 0 + + + CBC + CBC + 0x1 + + + + + KEY_SELECT + Key selection field + 8 + 8 + read-only + + + KEY0 + KEY0 + 0 + + + KEY1 + KEY1 + 0x1 + + + KEY2 + KEY2 + 0x2 + + + KEY3 + KEY3 + 0x3 + + + UNIQUE_KEY + UNIQUE_KEY + 0xFE + + + OTP_KEY + OTP_KEY + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 16 + 4 + read-only + + + SHA1 + SHA1 + 0 + + + CRC32 + CRC32 + 0x1 + + + SHA256 + SHA256 + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 24 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_SET + DCP channel 0 status register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_CLR + DCP channel 0 status register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_TOG + DCP channel 0 status register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_SET + DCP channel 0 options register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_CLR + DCP channel 0 options register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_TOG + DCP channel 0 options register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_SET + DCP channel 1 status register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_CLR + DCP channel 1 status register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_TOG + DCP channel 1 status register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_SET + DCP channel 1 options register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_CLR + DCP channel 1 options register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_TOG + DCP channel 1 options register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_SET + DCP channel 2 status register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_CLR + DCP channel 2 status register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_TOG + DCP channel 2 status register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_SET + DCP channel 2 options register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_CLR + DCP channel 2 options register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_TOG + DCP channel 2 options register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_SET + DCP channel 3 status register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_CLR + DCP channel 3 status register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_TOG + DCP channel 3 status register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_SET + DCP channel 3 options register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_CLR + DCP channel 3 options register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_TOG + DCP channel 3 options register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + CONTROL + 0x1 + + + OTPKEY0 + OTPKEY0 + 0x10 + + + OTPKEY1 + OTPKEY1 + 0x11 + + + OTPKEY2 + OTPKEY2 + 0x12 + + + OTPKEY3 + OTPKEY3 + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 1 + 1 + read-write + + + BASE + Page table base address + 2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 24 + 8 + read-only + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x40380000 + + 0 + 0x54 + registers + + + SPDIF + 60 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 12 + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 13 + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + write-only + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. + 7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + TxClk_Source_0 + XTALOSC input (XTALOSC clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_2 + tx_clk1 (from SAI1) + 0x2 + + + TxClk_Source_3 + tx_clk2 SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_4 + tx_clk3 (from SAI2) + 0x4 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + TxClk_Source_6 + tx_clk4 (from SAI3) + 0x6 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 11 + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + SAI1 + I2S + SAI + 0x40384000 + + 0 + 0xE4 + registers + + + SAI1 + 56 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50504 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 1 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO reads (from transmit shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO writes (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + TDR[%s] + SAI Transmit Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + read-write + + + + + 4 + 0x4 + TFR[%s] + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + WCP + Write Channel Pointer + 31 + 1 + read-only + + + WCP_0 + No effect. + 0 + + + WCP_1 + FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + 0x1 + + + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 1 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO writes (from receive shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO reads (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + RDR[%s] + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + 4 + 0x4 + RFR[%s] + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + RCP + Receive Channel Pointer + 15 + 1 + read-only + + + RCP_0 + No effect. + 0 + + + RCP_1 + FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + 0x1 + + + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + SAI2 + I2S + SAI + SAI + 0x40388000 + + 0 + 0xE4 + registers + + + SAI2 + 57 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50501 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 1 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 1 + read-write + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + TDR0 + SAI Transmit Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + read-write + + + + + TFR0 + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 1 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 1 + read-write + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + RDR0 + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + RFR0 + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + SAI3 + I2S + SAI + 0x4038C000 + + 0 + 0xE4 + registers + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + + LPSPI1 + LPSPI + LPSPI + LPSPI + 0x40394000 + + 0 + 0x78 + registers + + + LPSPI1 + 32 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010004 + 0xFFFFFFFF + + + FEATURE + Module Identification Number + 0 + 16 + read-only + + + STANDARD + Standard feature set supporting a 32-bit shift register. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x404 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + CR + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Module Enable + 0 + 1 + read-write + + + DISABLED + Module is disabled + 0 + + + ENABLED + Module is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Module is not reset + 0 + + + RESET + Module is reset + 0x1 + + + + + DOZEN + Doze Mode Enable + 2 + 1 + read-write + + + ENABLED + LPSPI module is enabled in Doze mode + 0 + + + DISABLED + LPSPI module is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DISABLED + LPSPI module is disabled in debug mode + 0 + + + ENABLED + LPSPI module is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + NO_EFFECT + No effect + 0 + + + TXFIFO_RST + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + NO_EFFECT + No effect + 0 + + + RXFIFO_RST + Receive FIFO is reset + 0x1 + + + + + + + SR + Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TXDATA_NOT_REQST + Transmit data not requested + 0 + + + TXDATA_REQST + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + NOTREADY + Receive Data is not ready + 0 + + + READY + Receive data is ready + 0x1 + + + + + WCF + Word Complete Flag + 8 + 1 + read-write + oneToClear + + + NOT_COMPLETED + Transfer of a received word has not yet completed + 0 + + + COMPLETED + Transfer of a received word has completed + 0x1 + + + + + FCF + Frame Complete Flag + 9 + 1 + read-write + oneToClear + + + NOT_COMPLETED + Frame transfer has not completed + 0 + + + COMPLETED + Frame transfer has completed + 0x1 + + + + + TCF + Transfer Complete Flag + 10 + 1 + read-write + oneToClear + + + NOT_COMPLETED + All transfers have not completed + 0 + + + COMPLETED + All transfers have completed + 0x1 + + + + + TEF + Transmit Error Flag + 11 + 1 + read-write + oneToClear + + + NO_UNDERRUN + Transmit FIFO underrun has not occurred + 0 + + + UNDERRUN + Transmit FIFO underrun has occurred + 0x1 + + + + + REF + Receive Error Flag + 12 + 1 + read-write + oneToClear + + + NOT_OVERFLOWED + Receive FIFO has not overflowed + 0 + + + OVERFLOWED + Receive FIFO has overflowed + 0x1 + + + + + DMF + Data Match Flag + 13 + 1 + read-write + oneToClear + + + NO_MATCH + Have not received matching data + 0 + + + MATCH + Have received matching data + 0x1 + + + + + MBF + Module Busy Flag + 24 + 1 + read-only + + + IDLE + LPSPI is idle + 0 + + + BUSY + LPSPI is busy + 0x1 + + + + + + + IER + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + WCIE + Word Complete Interrupt Enable + 8 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FCIE + Frame Complete Interrupt Enable + 9 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TCIE + Transfer Complete Interrupt Enable + 10 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TEIE + Transmit Error Interrupt Enable + 11 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + REIE + Receive Error Interrupt Enable + 12 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 13 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + + + DER + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + + + CFGR0 + Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + DISABLED + Host request is disabled + 0 + + + ENABLED + Host request is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + DISABLED + LPSPI_HREQ pin is active low + 0 + + + ENABLED + LPSPI_HREQ pin is active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HREQPIN + Host request input is the LPSPI_HREQ pin + 0 + + + INPUT_TRIGGER + Host request input is the input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + DISABLED + Circular FIFO is disabled + 0 + + + ENABLED + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + STORED + Received data is stored in the receive FIFO as in normal operations + 0 + + + DISCARDED + Received data is discarded unless the Data Match Flag (DMF) is set + 0x1 + + + + + + + CFGR1 + Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER + Master Mode + 0 + 1 + read-write + + + SLAVE_MODE + Slave mode + 0 + + + MASTER_MODE + Master mode + 0x1 + + + + + SAMPLE + Sample Point + 1 + 1 + read-write + + + ON_SCK_EDGE + Input data is sampled on SCK edge + 0 + + + ON_DELAYED_SCK_EDGE + Input data is sampled on delayed SCK edge + 0x1 + + + + + AUTOPCS + Automatic PCS + 2 + 1 + read-write + + + DISABLED + Automatic PCS generation is disabled + 0 + + + ENABLED + Automatic PCS generation is enabled + 0x1 + + + + + NOSTALL + No Stall + 3 + 1 + read-write + + + DISABLED + Transfers will stall when the transmit FIFO is empty + 0 + + + ENABLED + Transfers will not stall, allowing transmit FIFO underruns to occur + 0x1 + + + + + PCSPOL + Peripheral Chip Select Polarity + 8 + 4 + read-write + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + DISABLED + Match is disabled + 0 + + + ENABLED_FIRSTDATAMATCH + 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + 0x2 + + + ENABLED_ANYDATAMATCH + 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + 0x3 + + + ENABLED_DATAMATCH_100 + 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + 0x4 + + + ENABLED_DATAMATCH_101 + 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + 0x5 + + + ENABLED_DATAMATCH_110 + 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + 0x6 + + + ENABLED_DATAMATCH_111 + 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 2 + read-write + + + SIN_IN_SOUT_OUT + SIN is used for input data and SOUT is used for output data + 0 + + + SIN_BOTH_IN_OUT + SIN is used for both input and output data, only half-duplex serial transfers are supported + 0x1 + + + SOUT_BOTH_IN_OUT + SOUT is used for both input and output data, only half-duplex serial transfers are supported + 0x2 + + + SOUT_IN_SIN_OUT + SOUT is used for input data and SIN is used for output data + 0x3 + + + + + OUTCFG + Output Configuration + 26 + 1 + read-write + + + RETAIN_LASTVALUE + Output data retains last value when chip select is negated + 0 + + + TRISTATED + Output data is tristated when chip select is negated + 0x1 + + + + + PCSCFG + Peripheral Chip Select Configuration + 27 + 1 + read-write + + + CHIP_SELECT + PCS[3:2] are configured for chip select function + 0 + + + HALFDUPLEX4BIT + PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + 0x1 + + + + + + + DMR0 + Data Match Register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 32 + read-write + + + + + DMR1 + Data Match Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH1 + Match 1 Value + 0 + 32 + read-write + + + + + CCR + Clock Configuration Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKDIV + SCK Divider + 0 + 8 + read-write + + + DBT + Delay Between Transfers + 8 + 8 + read-write + + + PCSSCK + PCS-to-SCK Delay + 16 + 8 + read-write + + + SCKPCS + SCK-to-PCS Delay + 24 + 8 + read-write + + + + + FCR + The FIFO Control register contains the RXWATER and TXWATER control fields. + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 4 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 4 + read-write + + + + + FSR + FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 5 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 5 + read-only + + + + + TCR + Transmit Command Register + 0x60 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + FRAMESZ + Frame Size + 0 + 12 + read-write + + + WIDTH + Transfer Width + 16 + 2 + read-write + + + ONEBIT + 1 bit transfer + 0 + + + TWOBIT + 2 bit transfer + 0x1 + + + FOURBIT + 4 bit transfer + 0x2 + + + + + TXMSK + Transmit Data Mask + 18 + 1 + read-write + + + NORMAL + Normal transfer + 0 + + + MASK + Mask transmit data + 0x1 + + + + + RXMSK + Receive Data Mask + 19 + 1 + read-write + + + NORMAL + Normal transfer + 0 + + + MASK + Receive data is masked + 0x1 + + + + + CONTC + Continuing Command + 20 + 1 + read-write + + + START + Command word for start of new transfer + 0 + + + CONTINUE + Command word for continuing transfer + 0x1 + + + + + CONT + Continuous Transfer + 21 + 1 + read-write + + + DISABLED + Continuous transfer is disabled + 0 + + + ENABLED + Continuous transfer is enabled + 0x1 + + + + + BYSW + Byte Swap + 22 + 1 + read-write + + + DISABLED + Byte swap is disabled + 0 + + + ENABLED + Byte swap is enabled + 0x1 + + + + + LSBF + LSB First + 23 + 1 + read-write + + + MSB_FIRST + Data is transferred MSB first + 0 + + + LSB_FIRST + Data is transferred LSB first + 0x1 + + + + + PCS + Peripheral Chip Select + 24 + 2 + read-write + + + TX_PCS0 + Transfer using LPSPI_PCS[0] + 0 + + + TX_PCS1 + Transfer using LPSPI_PCS[1] + 0x1 + + + TX_PCS2 + Transfer using LPSPI_PCS[2] + 0x2 + + + TX_PCS3 + Transfer using LPSPI_PCS[3] + 0x3 + + + + + PRESCALE + Prescaler Value + 27 + 3 + read-write + + + DIVIDEBY1 + Divide by 1 + 0 + + + DIVIDEBY2 + Divide by 2 + 0x1 + + + DIVIDEBY4 + Divide by 4 + 0x2 + + + DIVIDEBY8 + Divide by 8 + 0x3 + + + DIVIDEBY16 + Divide by 16 + 0x4 + + + DIVIDEBY32 + Divide by 32 + 0x5 + + + DIVIDEBY64 + Divide by 64 + 0x6 + + + DIVIDEBY128 + Divide by 128 + 0x7 + + + + + CPHA + Clock Phase + 30 + 1 + read-write + + + CAPTURED + Data is captured on the leading edge of SCK and changed on the following edge of SCK + 0 + + + CHANGED + Data is changed on the leading edge of SCK and captured on the following edge of SCK + 0x1 + + + + + CPOL + Clock Polarity + 31 + 1 + read-write + + + INACTIVE_LOW + The inactive state value of SCK is low + 0 + + + INACTIVE_HIGH + The inactive state value of SCK is high + 0x1 + + + + + + + TDR + Transmit Data Register + 0x64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 32 + write-only + + + + + RSR + Receive Status Register + 0x70 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SOF + Start Of Frame + 0 + 1 + read-only + + + NEXT_DATAWORD + Subsequent data word received after LPSPI_PCS assertion + 0 + + + FIRST_DATAWORD + First data word received after LPSPI_PCS assertion + 0x1 + + + + + RXEMPTY + RX FIFO Empty + 1 + 1 + read-only + + + NOT_EMPTY + RX FIFO is not empty + 0 + + + EMPTY + RX FIFO is empty + 0x1 + + + + + + + RDR + Receive Data Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + + + LPSPI2 + LPSPI + LPSPI + 0x40398000 + + 0 + 0x78 + registers + + + LPSPI2 + 33 + + + + LPSPI3 + LPSPI + LPSPI + 0x4039C000 + + 0 + 0x78 + registers + + + LPSPI3 + 34 + + + + LPSPI4 + LPSPI + LPSPI + 0x403A0000 + + 0 + 0x78 + registers + + + LPSPI4 + 35 + + + + ADC_ETC + ADC_ETC + ADC_ETC + 0x403B0000 + + 0 + 0x150 + registers + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + + CTRL + ADC_ETC Global Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + TRIG_ENABLE + TRIG enable register. + 0 + 8 + read-write + + + TRIG_ENABLE_0 + disable all 8 external XBAR triggers. + 0 + + + TRIG_ENABLE_1 + enable external XBAR trigger0. + 0x1 + + + TRIG_ENABLE_2 + enable external XBAR trigger1. + 0x2 + + + TRIG_ENABLE_3 + enable external XBAR trigger0 and trigger1. + 0x3 + + + TRIG_ENABLE_255 + enable all 8 external XBAR triggers. + 0xFF + + + + + EXT0_TRIG_ENABLE + TSC0 TRIG enable register. + 8 + 1 + read-write + + + EXT0_TRIG_ENABLE_0 + disable external TSC0 trigger. + 0 + + + EXT0_TRIG_ENABLE_1 + enable external TSC0 trigger. + 0x1 + + + + + EXT0_TRIG_PRIORITY + External TSC0 trigger priority, 7 is highest priority, while 0 is lowest. + 9 + 3 + read-write + + + EXT1_TRIG_ENABLE + TSC1 TRIG enable register. + 12 + 1 + read-write + + + EXT1_TRIG_ENABLE_0 + disable external TSC1 trigger. + 0 + + + EXT1_TRIG_ENABLE_1 + enable external TSC1 trigger. + 0x1 + + + + + EXT1_TRIG_PRIORITY + External TSC1 trigger priority, 7 is highest priority, while 0 is lowest. + 13 + 3 + read-write + + + PRE_DIVIDER + Pre-divider for trig delay and interval + 16 + 8 + read-write + + + DMA_MODE_SEL + Select the trigger type of the DMA_REQ. + 29 + 1 + read-write + + + DMA_MODE_SEL_0 + Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. + 0 + + + DMA_MODE_SEL_1 + Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. + 0x1 + + + + + TSC_BYPASS + TSC Bypass To use ADC2, this bit should be cleared. + 30 + 1 + read-write + + + TSC_BYPASS_0 + TSC not bypassed. + 0 + + + TSC_BYPASS_1 + TSC is bypassed to ADC2, that means TSC will control ADC2 directly. + 0x1 + + + + + SOFTRST + Software synchronous reset, active high. + 31 + 1 + read-write + + + SOFTRST_0 + ADC_ETC works normally. + 0 + + + SOFTRST_1 + All registers inside ADC_ETC will be reset to the default value. + 0x1 + + + + + + + DONE0_1_IRQ + ETC DONE0 and DONE1 IRQ State Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE0 + TRIG0 done0 interrupt detection. + 0 + 1 + read-write + oneToClear + + + TRIG0_DONE0_0 + No TRIG0_DONE0 interrupt detected + 0 + + + TRIG0_DONE0_1 + TRIG0_DONE0 interrupt detected + 0x1 + + + + + TRIG1_DONE0 + TRIG1 done0 interrupt detection. + 1 + 1 + read-write + oneToClear + + + TRIG1_DONE0_0 + No TRIG1_DONE0 interrupt detected + 0 + + + TRIG1_DONE0_1 + TRIG1_DONE0 interrupt detected + 0x1 + + + + + TRIG2_DONE0 + TRIG2 done0 interrupt detection. + 2 + 1 + read-write + oneToClear + + + TRIG2_DONE0_0 + No TRIG2_DONE0 interrupt detected + 0 + + + TRIG2_DONE0_1 + TRIG2_DONE0 interrupt detected + 0x1 + + + + + TRIG3_DONE0 + TRIG3 done0 interrupt detection. + 3 + 1 + read-write + oneToClear + + + TRIG3_DONE0_0 + No TRIG3_DONE0 interrupt detected + 0 + + + TRIG3_DONE0_1 + TRIG3_DONE0 interrupt detected + 0x1 + + + + + TRIG4_DONE0 + TRIG4 done0 interrupt detection. + 4 + 1 + read-write + oneToClear + + + TRIG4_DONE0_0 + No TRIG4_DONE0 interrupt detected + 0 + + + TRIG4_DONE0_1 + TRIG4_DONE0 interrupt detected + 0x1 + + + + + TRIG5_DONE0 + TRIG5 done0 interrupt detection. + 5 + 1 + read-write + oneToClear + + + TRIG5_DONE0_0 + No TRIG5_DONE0 interrupt detected + 0 + + + TRIG5_DONE0_1 + TRIG5_DONE0 interrupt detected + 0x1 + + + + + TRIG6_DONE0 + TRIG6 done0 interrupt detection. + 6 + 1 + read-write + oneToClear + + + TRIG6_DONE0_0 + No TRIG6_DONE0 interrupt detected + 0 + + + TRIG6_DONE0_1 + TRIG6_DONE0 interrupt detected + 0x1 + + + + + TRIG7_DONE0 + TRIG7 done0 interrupt detection. + 7 + 1 + read-write + oneToClear + + + TRIG7_DONE0_0 + No TRIG7_DONE0 interrupt detected + 0 + + + TRIG7_DONE0_1 + TRIG7_DONE0 interrupt detected + 0x1 + + + + + TRIG0_DONE1 + TRIG0 done1 interrupt detection. + 16 + 1 + read-write + oneToClear + + + TRIG0_DONE1_0 + No TRIG0_DONE1 interrupt detected + 0 + + + TRIG0_DONE1_1 + TRIG0_DONE1 interrupt detected + 0x1 + + + + + TRIG1_DONE1 + TRIG1 done1 interrupt detection. + 17 + 1 + read-write + oneToClear + + + TRIG1_DONE1_0 + No TRIG1_DONE1 interrupt detected + 0 + + + TRIG1_DONE1_1 + TRIG1_DONE1 interrupt detected + 0x1 + + + + + TRIG2_DONE1 + TRIG2 done1 interrupt detection. + 18 + 1 + read-write + oneToClear + + + TRIG2_DONE1_0 + No TRIG2_DONE1 interrupt detected + 0 + + + TRIG2_DONE1_1 + TRIG2_DONE1 interrupt detected + 0x1 + + + + + TRIG3_DONE1 + TRIG3 done1 interrupt detection. + 19 + 1 + read-write + oneToClear + + + TRIG3_DONE1_0 + No TRIG3_DONE1 interrupt detected + 0 + + + TRIG3_DONE1_1 + TRIG3_DONE1 interrupt detected + 0x1 + + + + + TRIG4_DONE1 + TRIG4 done1 interrupt detection. + 20 + 1 + read-write + oneToClear + + + TRIG4_DONE1_0 + No TRIG4_DONE1 interrupt detected + 0 + + + TRIG4_DONE1_1 + TRIG4_DONE1 interrupt detected + 0x1 + + + + + TRIG5_DONE1 + TRIG5 done1 interrupt detection. + 21 + 1 + read-write + oneToClear + + + TRIG5_DONE1_0 + No TRIG5_DONE1 interrupt detected + 0 + + + TRIG5_DONE1_1 + TRIG5_DONE1 interrupt detected + 0x1 + + + + + TRIG6_DONE1 + TRIG6 done1 interrupt detection. + 22 + 1 + read-write + oneToClear + + + TRIG6_DONE1_0 + No TRIG6_DONE1 interrupt detected + 0 + + + TRIG6_DONE1_1 + TRIG6_DONE1 interrupt detected + 0x1 + + + + + TRIG7_DONE1 + TRIG7 done1 interrupt detection. + 23 + 1 + read-write + oneToClear + + + TRIG7_DONE1_0 + No TRIG7_DONE1 interrupt detected + 0 + + + TRIG7_DONE1_1 + TRIG7_DONE1 interrupt detected + 0x1 + + + + + + + DONE2_3_ERR_IRQ + ETC DONE_2 and DONE_ERR IRQ State Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE2 + TRIG0 done2 interrupt detection. + 0 + 1 + read-write + oneToClear + + + TRIG0_DONE2_0 + No TRIG0_DONE2 interrupt detected + 0 + + + TRIG0_DONE2_1 + TRIG0_DONE2 interrupt detected + 0x1 + + + + + TRIG1_DONE2 + TRIG1 done2 interrupt detection. + 1 + 1 + read-write + oneToClear + + + TRIG1_DONE2_0 + No TRIG1_DONE2 interrupt detected + 0 + + + TRIG1_DONE2_1 + TRIG1_DONE2 interrupt detected + 0x1 + + + + + TRIG2_DONE2 + TRIG2 done2 interrupt detection. + 2 + 1 + read-write + oneToClear + + + TRIG2_DONE2_0 + No TRIG2_DONE2 interrupt detected + 0 + + + TRIG2_DONE2_1 + TRIG2_DONE2 interrupt detected + 0x1 + + + + + TRIG3_DONE2 + TRIG3 done2 interrupt detection. + 3 + 1 + read-write + oneToClear + + + TRIG3_DONE2_0 + No TRIG3_DONE2 interrupt detected + 0 + + + TRIG3_DONE2_1 + TRIG3_DONE2 interrupt detected + 0x1 + + + + + TRIG4_DONE2 + TRIG4 done2 interrupt detection. + 4 + 1 + read-write + oneToClear + + + TRIG4_DONE2_0 + No TRIG4_DONE2 interrupt detected + 0 + + + TRIG4_DONE2_1 + TRIG4_DONE2 interrupt detected + 0x1 + + + + + TRIG5_DONE2 + TRIG5 done2 interrupt detection. + 5 + 1 + read-write + oneToClear + + + TRIG5_DONE2_0 + No TRIG5_DONE2 interrupt detected + 0 + + + TRIG5_DONE2_1 + TRIG5_DONE2 interrupt detected + 0x1 + + + + + TRIG6_DONE2 + TRIG6 done2 interrupt detection. + 6 + 1 + read-write + oneToClear + + + TRIG6_DONE2_0 + No TRIG6_DONE2 interrupt detected + 0 + + + TRIG6_DONE2_1 + TRIG6_DONE2 interrupt detected + 0x1 + + + + + TRIG7_DONE2 + TRIG7 done2 interrupt detection. + 7 + 1 + read-write + oneToClear + + + TRIG7_DONE2_0 + No TRIG7_DONE2 interrupt detected + 0 + + + TRIG7_DONE2_1 + TRIG7_DONE2 interrupt detected + 0x1 + + + + + TRIG0_ERR + TRIG0 error interrupt detection. + 16 + 1 + read-write + + + TRIG0_ERR_0 + No TRIG0_ERR interrupt detected + 0 + + + TRIG0_ERR_1 + TRIG0_ERR interrupt detected + 0x1 + + + + + TRIG1_ERR + TRIG1 error interrupt detection. + 17 + 1 + read-write + + + TRIG1_ERR_0 + No TRIG1_ERR interrupt detected + 0 + + + TRIG1_ERR_1 + TRIG1_ERR interrupt detected + 0x1 + + + + + TRIG2_ERR + TRIG2 error interrupt detection. + 18 + 1 + read-write + + + TRIG2_ERR_0 + No TRIG2_ERR interrupt detected + 0 + + + TRIG2_ERR_1 + TRIG2_ERR interrupt detected + 0x1 + + + + + TRIG3_ERR + TRIG3 error interrupt detection. + 19 + 1 + read-write + + + TRIG3_ERR_0 + No TRIG3_ERR interrupt detected + 0 + + + TRIG3_ERR_1 + TRIG3_ERR interrupt detected + 0x1 + + + + + TRIG4_ERR + TRIG4 error interrupt detection. + 20 + 1 + read-write + + + TRIG4_ERR_0 + No TRIG4_ERR interrupt detected + 0 + + + TRIG4_ERR_1 + TRIG4_ERR interrupt detected + 0x1 + + + + + TRIG5_ERR + TRIG5 error interrupt detection. + 21 + 1 + read-write + + + TRIG5_ERR_0 + No TRIG5_ERR interrupt detected + 0 + + + TRIG5_ERR_1 + TRIG5_ERR interrupt detected + 0x1 + + + + + TRIG6_ERR + TRIG6 error interrupt detection. + 22 + 1 + read-write + + + TRIG6_ERR_0 + No TRIG6_ERR interrupt detected + 0 + + + TRIG6_ERR_1 + TRIG6_ERR interrupt detected + 0x1 + + + + + TRIG7_ERR + TRIG7 error interrupt detection. + 23 + 1 + read-write + + + TRIG7_ERR_0 + No TRIG7_ERR interrupt detected + 0 + + + TRIG7_ERR_1 + TRIG7_ERR interrupt detected + 0x1 + + + + + + + DMA_CTRL + ETC DMA control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_ENABLE + Enable DMA request when TRIG0 done. + 0 + 1 + read-write + + + TRIG0_ENABLE_0 + TRIG0 DMA request disabled. + 0 + + + TRIG0_ENABLE_1 + TRIG0 DMA request enabled. + 0x1 + + + + + TRIG1_ENABLE + Enable DMA request when TRIG1 done. + 1 + 1 + read-write + + + TRIG1_ENABLE_0 + TRIG1 DMA request disabled. + 0 + + + TRIG1_ENABLE_1 + TRIG1 DMA request enabled. + 0x1 + + + + + TRIG2_ENABLE + Enable DMA request when TRIG2 done. + 2 + 1 + read-write + + + TRIG2_ENABLE_0 + TRIG2 DMA request disabled. + 0 + + + TRIG2_ENABLE_1 + TRIG2 DMA request enabled. + 0x1 + + + + + TRIG3_ENABLE + Enable DMA request when TRIG3 done. + 3 + 1 + read-write + + + TRIG3_ENABLE_0 + TRIG3 DMA request disabled. + 0 + + + TRIG3_ENABLE_1 + TRIG3 DMA request enabled. + 0x1 + + + + + TRIG4_ENABLE + Enable DMA request when TRIG4 done. + 4 + 1 + read-write + + + TRIG4_ENABLE_0 + TRIG4 DMA request disabled. + 0 + + + TRIG4_ENABLE_1 + TRIG4 DMA request enabled. + 0x1 + + + + + TRIG5_ENABLE + Enable DMA request when TRIG5 done. + 5 + 1 + read-write + + + TRIG5_ENABLE_0 + TRIG5 DMA request disabled. + 0 + + + TRIG5_ENABLE_1 + TRIG5 DMA request enabled. + 0x1 + + + + + TRIG6_ENABLE + Enable DMA request when TRIG6 done. + 6 + 1 + read-write + + + TRIG6_ENABLE_0 + TRIG6 DMA request disabled. + 0 + + + TRIG6_ENABLE_1 + TRIG6 DMA request enabled. + 0x1 + + + + + TRIG7_ENABLE + Enable DMA request when TRIG7 done. + 7 + 1 + read-write + + + TRIG7_ENABLE_0 + TRIG7 DMA request disabled. + 0 + + + TRIG7_ENABLE_1 + TRIG7 DMA request enabled. + 0x1 + + + + + TRIG0_REQ + Flag bit for DMA request + 16 + 1 + read-write + oneToClear + + + TRIG0_REQ_0 + TRIG0_REQ not detected. + 0 + + + TRIG0_REQ_1 + TRIG0_REQ detected. + 0x1 + + + + + TRIG1_REQ + Flag bit for DMA request + 17 + 1 + read-write + oneToClear + + + TRIG1_REQ_0 + TRIG1_REQ not detected. + 0 + + + TRIG1_REQ_1 + TRIG1_REQ detected. + 0x1 + + + + + TRIG2_REQ + Flag bit for DMA request + 18 + 1 + read-write + oneToClear + + + TRIG2_REQ_0 + TRIG2_REQ not detected. + 0 + + + TRIG2_REQ_1 + TRIG2_REQ detected. + 0x1 + + + + + TRIG3_REQ + Flag bit for DMA request + 19 + 1 + read-write + oneToClear + + + TRIG3_REQ_0 + TRIG3_REQ not detected. + 0 + + + TRIG3_REQ_1 + TRIG3_REQ detected. + 0x1 + + + + + TRIG4_REQ + Flag bit for DMA request + 20 + 1 + read-write + oneToClear + + + TRIG4_REQ_0 + TRIG4_REQ not detected. + 0 + + + TRIG4_REQ_1 + TRIG4_REQ detected. + 0x1 + + + + + TRIG5_REQ + Flag bit for DMA request + 21 + 1 + read-write + oneToClear + + + TRIG5_REQ_0 + TRIG5_REQ not detected. + 0 + + + TRIG5_REQ_1 + TRIG5_REQ detected. + 0x1 + + + + + TRIG6_REQ + Flag bit for DMA request + 22 + 1 + read-write + oneToClear + + + TRIG6_REQ_0 + TRIG6_REQ not detected. + 0 + + + TRIG6_REQ_1 + TRIG6_REQ detected. + 0x1 + + + + + TRIG7_REQ + Flag bit for DMA request + 23 + 1 + read-write + oneToClear + + + TRIG7_REQ_0 + TRIG7_REQ not detected. + 0 + + + TRIG7_REQ_1 + TRIG7_REQ detected. + 0x1 + + + + + + + TRIG0_CTRL + ETC_TRIG Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG0_COUNTER + ETC_TRIG Counter Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG0_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG0_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG0_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG0_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG0_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG0_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG0_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG0_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG1_CTRL + ETC_TRIG Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG1_COUNTER + ETC_TRIG Counter Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG1_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG1_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG1_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG1_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG1_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG1_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG1_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG1_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG2_CTRL + ETC_TRIG Control Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG2_COUNTER + ETC_TRIG Counter Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG2_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG2_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG2_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG2_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG2_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG2_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG2_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG2_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG3_CTRL + ETC_TRIG Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG3_COUNTER + ETC_TRIG Counter Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG3_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG3_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG3_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG3_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG3_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG3_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG3_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xA8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG3_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG4_CTRL + ETC_TRIG Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG4_COUNTER + ETC_TRIG Counter Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG4_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG4_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG4_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG4_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG4_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG4_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG4_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG4_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG5_CTRL + ETC_TRIG Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG5_COUNTER + ETC_TRIG Counter Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG5_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG5_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG5_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG5_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG5_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG5_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG5_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG5_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG6_CTRL + ETC_TRIG Control Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG6_COUNTER + ETC_TRIG Counter Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG6_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG6_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG6_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG6_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG6_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG6_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG6_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG6_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG7_CTRL + ETC_TRIG Control Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software trigger. This field is self-clearing. + 0 + 1 + read-write + + + SW_TRIG_0 + No software trigger event generated. + 0 + + + SW_TRIG_1 + Software trigger event generated. + 0x1 + + + + + TRIG_MODE + Trigger mode selection. + 4 + 1 + read-write + + + TRIG_MODE_0 + Hardware trigger. The softerware trigger will be ignored. + 0 + + + TRIG_MODE_1 + Software trigger. The hardware trigger will be ignored. + 0x1 + + + + + TRIG_CHAIN + The number of segments inside the trigger chain of TRIGa. + 8 + 3 + read-write + + + TRIG_CHAIN_0 + Trigger chain length is 1 + 0 + + + TRIG_CHAIN_1 + Trigger chain length is 2 + 0x1 + + + TRIG_CHAIN_2 + Trigger chain length is 3 + 0x2 + + + TRIG_CHAIN_3 + Trigger chain length is 4 + 0x3 + + + TRIG_CHAIN_4 + Trigger chain length is 5 + 0x4 + + + TRIG_CHAIN_5 + Trigger chain length is 6 + 0x5 + + + TRIG_CHAIN_6 + Trigger chain length is 7 + 0x6 + + + TRIG_CHAIN_7 + Trigger chain length is 8 + 0x7 + + + + + TRIG_PRIORITY + External trigger priority, 7 is highest priority, while 0 is lowest + 12 + 3 + read-write + + + SYNC_MODE + Trigger synchronization mode selection + 16 + 1 + read-write + + + SYNC_MODE_0 + Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + 0 + + + SYNC_MODE_1 + Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + 0x1 + + + + + + + TRIG7_COUNTER + ETC_TRIG Counter Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter. Initial_delay = (INIT_DELAY+1)*(PRE_DIVIDER+1)*ipg_clk + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG7_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + ADC channel selection + 0 + 4 + read-write + + + CSEL0_0 + ADC Channel 0 selected + 0 + + + CSEL0_1 + ADC Channel 1 selected. + 0x1 + + + CSEL0_2 + ADC Channel 2 selected. + 0x2 + + + CSEL0_3 + ADC Channel 3 selected. + 0x3 + + + CSEL0_4 + ADC Channel 4 selected. + 0x4 + + + CSEL0_5 + ADC Channel 5 selected. + 0x5 + + + CSEL0_6 + ADC Channel 6 selected. + 0x6 + + + CSEL0_7 + ADC Channel 7 selected. + 0x7 + + + CSEL0_8 + ADC Channel 8 selected. + 0x8 + + + CSEL0_9 + ADC Channel 9 selected. + 0x9 + + + CSEL0_10 + ADC Channel 10 selected. + 0xA + + + CSEL0_11 + ADC Channel 11 selected. + 0xB + + + CSEL0_12 + ADC Channel 12 selected. + 0xC + + + CSEL0_13 + ADC Channel 13 selected. + 0xD + + + CSEL0_14 + ADC Channel 14 selected. + 0xE + + + CSEL0_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS0 + Segment 0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS0_0 + no trigger selected + 0 + + + HWTS0_1 + ADC TRIG0 selected + 0x1 + + + HWTS0_2 + ADC TRIG1 selected + 0x2 + + + HWTS0_4 + ADC TRIG2 selected + 0x4 + + + HWTS0_8 + ADC TRIG3 selected + 0x8 + + + HWTS0_16 + ADC TRIG4 selected + 0x10 + + + HWTS0_32 + ADC TRIG5 selected + 0x20 + + + HWTS0_64 + ADC TRIG6 selected + 0x40 + + + HWTS0_128 + ADC TRIG7 selected + 0x80 + + + + + B2B0 + Segment 0 B2B + 12 + 1 + read-write + + + B2B0_0 + Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B0_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE0 + Segment 0 done interrupt selection + 13 + 2 + read-write + + + IE0_0 + No interrupt when finished + 0 + + + IE0_1 + Generate interrupt on Done0 when segment 0 finish. + 0x1 + + + IE0_2 + Generate interrupt on Done1 when segment 0 finish. + 0x2 + + + IE0_3 + Generate interrupt on Done2 when segment 0 finish. + 0x3 + + + + + CSEL1 + ADC channel selection + 16 + 4 + read-write + + + CSEL1_0 + ADC Channel 0 selected + 0 + + + CSEL1_1 + ADC Channel 1 selected. + 0x1 + + + CSEL1_2 + ADC Channel 2 selected. + 0x2 + + + CSEL1_3 + ADC Channel 3 selected. + 0x3 + + + CSEL1_4 + ADC Channel 4 selected. + 0x4 + + + CSEL1_5 + ADC Channel 5 selected. + 0x5 + + + CSEL1_6 + ADC Channel 6 selected. + 0x6 + + + CSEL1_7 + ADC Channel 7 selected. + 0x7 + + + CSEL1_8 + ADC Channel 8 selected. + 0x8 + + + CSEL1_9 + ADC Channel 9 selected. + 0x9 + + + CSEL1_10 + ADC Channel 10 selected. + 0xA + + + CSEL1_11 + ADC Channel 11 selected. + 0xB + + + CSEL1_12 + ADC Channel 12 selected. + 0xC + + + CSEL1_13 + ADC Channel 13 selected. + 0xD + + + CSEL1_14 + ADC Channel 14 selected. + 0xE + + + CSEL1_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS1 + Segment 1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS1_0 + no trigger selected + 0 + + + HWTS1_1 + ADC TRIG0 selected + 0x1 + + + HWTS1_2 + ADC TRIG1 selected + 0x2 + + + HWTS1_4 + ADC TRIG2 selected + 0x4 + + + HWTS1_8 + ADC TRIG3 selected + 0x8 + + + HWTS1_16 + ADC TRIG4 selected + 0x10 + + + HWTS1_32 + ADC TRIG5 selected + 0x20 + + + HWTS1_64 + ADC TRIG6 selected + 0x40 + + + HWTS1_128 + ADC TRIG7 selected + 0x80 + + + + + B2B1 + Segment 1 B2B + 28 + 1 + read-write + + + B2B1_0 + Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B1_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE1 + Segment 1 done interrupt selection + 29 + 2 + read-write + + + IE1_0 + No interrupt when finished + 0 + + + IE1_1 + Generate interrupt on Done0 when Segment 1 finish. + 0x1 + + + IE1_2 + Generate interrupt on Done1 when Segment 1 finish. + 0x2 + + + IE1_3 + Generate interrupt on Done2 when Segment 1 finish. + 0x3 + + + + + + + TRIG7_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + ADC channel selection + 0 + 4 + read-write + + + CSEL2_0 + ADC Channel 0 selected + 0 + + + CSEL2_1 + ADC Channel 1 selected. + 0x1 + + + CSEL2_2 + ADC Channel 2 selected. + 0x2 + + + CSEL2_3 + ADC Channel 3 selected. + 0x3 + + + CSEL2_4 + ADC Channel 4 selected. + 0x4 + + + CSEL2_5 + ADC Channel 5 selected. + 0x5 + + + CSEL2_6 + ADC Channel 6 selected. + 0x6 + + + CSEL2_7 + ADC Channel 7 selected. + 0x7 + + + CSEL2_8 + ADC Channel 8 selected. + 0x8 + + + CSEL2_9 + ADC Channel 9 selected. + 0x9 + + + CSEL2_10 + ADC Channel 10 selected. + 0xA + + + CSEL2_11 + ADC Channel 11 selected. + 0xB + + + CSEL2_12 + ADC Channel 12 selected. + 0xC + + + CSEL2_13 + ADC Channel 13 selected. + 0xD + + + CSEL2_14 + ADC Channel 14 selected. + 0xE + + + CSEL2_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS2 + Segment 2 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS2_0 + no trigger selected + 0 + + + HWTS2_1 + ADC TRIG0 selected + 0x1 + + + HWTS2_2 + ADC TRIG1 selected + 0x2 + + + HWTS2_4 + ADC TRIG2 selected + 0x4 + + + HWTS2_8 + ADC TRIG3 selected + 0x8 + + + HWTS2_16 + ADC TRIG4 selected + 0x10 + + + HWTS2_32 + ADC TRIG5 selected + 0x20 + + + HWTS2_64 + ADC TRIG6 selected + 0x40 + + + HWTS2_128 + ADC TRIG7 selected + 0x80 + + + + + B2B2 + Segment 2 B2B + 12 + 1 + read-write + + + B2B2_0 + Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B2_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE2 + Segment 2 done interrupt selection + 13 + 2 + read-write + + + IE2_0 + No interrupt when finished + 0 + + + IE2_1 + Generate interrupt on Done0 when segment 2 finish. + 0x1 + + + IE2_2 + Generate interrupt on Done1 when segment 2 finish. + 0x2 + + + IE2_3 + Generate interrupt on Done2 when segment 2 finish. + 0x3 + + + + + CSEL3 + ADC channel selection + 16 + 4 + read-write + + + CSEL3_0 + ADC Channel 0 selected + 0 + + + CSEL3_1 + ADC Channel 1 selected. + 0x1 + + + CSEL3_2 + ADC Channel 2 selected. + 0x2 + + + CSEL3_3 + ADC Channel 3 selected. + 0x3 + + + CSEL3_4 + ADC Channel 4 selected. + 0x4 + + + CSEL3_5 + ADC Channel 5 selected. + 0x5 + + + CSEL3_6 + ADC Channel 6 selected. + 0x6 + + + CSEL3_7 + ADC Channel 7 selected. + 0x7 + + + CSEL3_8 + ADC Channel 8 selected. + 0x8 + + + CSEL3_9 + ADC Channel 9 selected. + 0x9 + + + CSEL3_10 + ADC Channel 10 selected. + 0xA + + + CSEL3_11 + ADC Channel 11 selected. + 0xB + + + CSEL3_12 + ADC Channel 12 selected. + 0xC + + + CSEL3_13 + ADC Channel 13 selected. + 0xD + + + CSEL3_14 + ADC Channel 14 selected. + 0xE + + + CSEL3_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS3 + Segment 3 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS3_0 + no trigger selected + 0 + + + HWTS3_1 + ADC TRIG0 selected + 0x1 + + + HWTS3_2 + ADC TRIG1 selected + 0x2 + + + HWTS3_4 + ADC TRIG2 selected + 0x4 + + + HWTS3_8 + ADC TRIG3 selected + 0x8 + + + HWTS3_16 + ADC TRIG4 selected + 0x10 + + + HWTS3_32 + ADC TRIG5 selected + 0x20 + + + HWTS3_64 + ADC TRIG6 selected + 0x40 + + + HWTS3_128 + ADC TRIG7 selected + 0x80 + + + + + B2B3 + Segment 3 B2B + 28 + 1 + read-write + + + B2B3_0 + Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B3_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE3 + Segment 3 done interrupt selection + 29 + 2 + read-write + + + IE3_0 + No interrupt when finished + 0 + + + IE3_1 + Generate interrupt on Done0 when segment 3 finish. + 0x1 + + + IE3_2 + Generate interrupt on Done1 when segment 3 finish. + 0x2 + + + IE3_3 + Generate interrupt on Done2 when segment 3 finish. + 0x3 + + + + + + + TRIG7_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + ADC channel selection + 0 + 4 + read-write + + + CSEL4_0 + ADC Channel 0 selected + 0 + + + CSEL4_1 + ADC Channel 1 selected. + 0x1 + + + CSEL4_2 + ADC Channel 2 selected. + 0x2 + + + CSEL4_3 + ADC Channel 3 selected. + 0x3 + + + CSEL4_4 + ADC Channel 4 selected. + 0x4 + + + CSEL4_5 + ADC Channel 5 selected. + 0x5 + + + CSEL4_6 + ADC Channel 6 selected. + 0x6 + + + CSEL4_7 + ADC Channel 7 selected. + 0x7 + + + CSEL4_8 + ADC Channel 8 selected. + 0x8 + + + CSEL4_9 + ADC Channel 9 selected. + 0x9 + + + CSEL4_10 + ADC Channel 10 selected. + 0xA + + + CSEL4_11 + ADC Channel 11 selected. + 0xB + + + CSEL4_12 + ADC Channel 12 selected. + 0xC + + + CSEL4_13 + ADC Channel 13 selected. + 0xD + + + CSEL4_14 + ADC Channel 14 selected. + 0xE + + + CSEL4_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS4 + Segment 4 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS4_0 + no trigger selected + 0 + + + HWTS4_1 + ADC TRIG0 selected + 0x1 + + + HWTS4_2 + ADC TRIG1 selected + 0x2 + + + HWTS4_4 + ADC TRIG2 selected + 0x4 + + + HWTS4_8 + ADC TRIG3 selected + 0x8 + + + HWTS4_16 + ADC TRIG4 selected + 0x10 + + + HWTS4_32 + ADC TRIG5 selected + 0x20 + + + HWTS4_64 + ADC TRIG6 selected + 0x40 + + + HWTS4_128 + ADC TRIG7 selected + 0x80 + + + + + B2B4 + Segment 4 B2B + 12 + 1 + read-write + + + B2B4_0 + Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B4_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE4 + Segment 4 done interrupt selection + 13 + 2 + read-write + + + IE4_0 + No interrupt when finished + 0 + + + IE4_1 + Generate interrupt on Done0 when segment 4 finish. + 0x1 + + + IE4_2 + Generate interrupt on Done1 when segment 4 finish. + 0x2 + + + IE4_3 + Generate interrupt on Done2 when segment 4 finish. + 0x3 + + + + + CSEL5 + ADC channel selection + 16 + 4 + read-write + + + CSEL5_0 + ADC Channel 0 selected + 0 + + + CSEL5_1 + ADC Channel 1 selected. + 0x1 + + + CSEL5_2 + ADC Channel 2 selected. + 0x2 + + + CSEL5_3 + ADC Channel 3 selected. + 0x3 + + + CSEL5_4 + ADC Channel 4 selected. + 0x4 + + + CSEL5_5 + ADC Channel 5 selected. + 0x5 + + + CSEL5_6 + ADC Channel 6 selected. + 0x6 + + + CSEL5_7 + ADC Channel 7 selected. + 0x7 + + + CSEL5_8 + ADC Channel 8 selected. + 0x8 + + + CSEL5_9 + ADC Channel 9 selected. + 0x9 + + + CSEL5_10 + ADC Channel 10 selected. + 0xA + + + CSEL5_11 + ADC Channel 11 selected. + 0xB + + + CSEL5_12 + ADC Channel 12 selected. + 0xC + + + CSEL5_13 + ADC Channel 13 selected. + 0xD + + + CSEL5_14 + ADC Channel 14 selected. + 0xE + + + CSEL5_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS5 + Segment 5 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS5_0 + no trigger selected + 0 + + + HWTS5_1 + ADC TRIG0 selected + 0x1 + + + HWTS5_2 + ADC TRIG1 selected + 0x2 + + + HWTS5_4 + ADC TRIG2 selected + 0x4 + + + HWTS5_8 + ADC TRIG3 selected + 0x8 + + + HWTS5_16 + ADC TRIG4 selected + 0x10 + + + HWTS5_32 + ADC TRIG5 selected + 0x20 + + + HWTS5_64 + ADC TRIG6 selected + 0x40 + + + HWTS5_128 + ADC TRIG7 selected + 0x80 + + + + + B2B5 + Segment 5 B2B + 28 + 1 + read-write + + + B2B5_0 + Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B5_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE5 + Segment 5 done interrupt selection + 29 + 2 + read-write + + + IE5_0 + No interrupt when finished + 0 + + + IE5_1 + Generate interrupt on Done0 when segment 5 finish. + 0x1 + + + IE5_2 + Generate interrupt on Done1 when segment 5 finish. + 0x2 + + + IE5_3 + Generate interrupt on Done2 when segment 5 finish. + 0x3 + + + + + + + TRIG7_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + ADC channel selection + 0 + 4 + read-write + + + CSEL6_0 + ADC Channel 0 selected + 0 + + + CSEL6_1 + ADC Channel 1 selected. + 0x1 + + + CSEL6_2 + ADC Channel 2 selected. + 0x2 + + + CSEL6_3 + ADC Channel 3 selected. + 0x3 + + + CSEL6_4 + ADC Channel 4 selected. + 0x4 + + + CSEL6_5 + ADC Channel 5 selected. + 0x5 + + + CSEL6_6 + ADC Channel 6 selected. + 0x6 + + + CSEL6_7 + ADC Channel 7 selected. + 0x7 + + + CSEL6_8 + ADC Channel 8 selected. + 0x8 + + + CSEL6_9 + ADC Channel 9 selected. + 0x9 + + + CSEL6_10 + ADC Channel 10 selected. + 0xA + + + CSEL6_11 + ADC Channel 11 selected. + 0xB + + + CSEL6_12 + ADC Channel 12 selected. + 0xC + + + CSEL6_13 + ADC Channel 13 selected. + 0xD + + + CSEL6_14 + ADC Channel 14 selected. + 0xE + + + CSEL6_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS6 + Segment 6 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + HWTS6_0 + no trigger selected + 0 + + + HWTS6_1 + ADC TRIG0 selected + 0x1 + + + HWTS6_2 + ADC TRIG1 selected + 0x2 + + + HWTS6_4 + ADC TRIG2 selected + 0x4 + + + HWTS6_8 + ADC TRIG3 selected + 0x8 + + + HWTS6_16 + ADC TRIG4 selected + 0x10 + + + HWTS6_32 + ADC TRIG5 selected + 0x20 + + + HWTS6_64 + ADC TRIG6 selected + 0x40 + + + HWTS6_128 + ADC TRIG7 selected + 0x80 + + + + + B2B6 + Segment 6 B2B + 12 + 1 + read-write + + + B2B6_0 + Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B6_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE6 + Segment 6 done interrupt selection + 13 + 2 + read-write + + + IE6_0 + No interrupt when finished + 0 + + + IE6_1 + Generate interrupt on Done0 when segment 6 finish. + 0x1 + + + IE6_2 + Generate interrupt on Done1 when segment 6 finish. + 0x2 + + + IE6_3 + Generate interrupt on Done2 when segment 6 finish. + 0x3 + + + + + CSEL7 + ADC channel selection + 16 + 4 + read-write + + + CSEL7_0 + ADC Channel 0 selected. + 0 + + + CSEL7_1 + ADC Channel 1 selected. + 0x1 + + + CSEL7_2 + ADC Channel 2 selected. + 0x2 + + + CSEL7_3 + ADC Channel 3 selected. + 0x3 + + + CSEL7_4 + ADC Channel 4 selected. + 0x4 + + + CSEL7_5 + ADC Channel 5 selected. + 0x5 + + + CSEL7_6 + ADC Channel 6 selected. + 0x6 + + + CSEL7_7 + ADC Channel 7 selected. + 0x7 + + + CSEL7_8 + ADC Channel 8 selected. + 0x8 + + + CSEL7_9 + ADC Channel 9 selected. + 0x9 + + + CSEL7_10 + ADC Channel 10 selected. + 0xA + + + CSEL7_11 + ADC Channel 11 selected. + 0xB + + + CSEL7_12 + ADC Channel 12 selected. + 0xC + + + CSEL7_13 + ADC Channel 13 selected. + 0xD + + + CSEL7_14 + ADC Channel 14 selected. + 0xE + + + CSEL7_15 + ADC Channel 15 selected. + 0xF + + + + + HWTS7 + Segment 7 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + HWTS7_0 + no trigger selected + 0 + + + HWTS7_1 + ADC TRIG0 selected + 0x1 + + + HWTS7_2 + ADC TRIG1 selected + 0x2 + + + HWTS7_4 + ADC TRIG2 selected + 0x4 + + + HWTS7_8 + ADC TRIG3 selected + 0x8 + + + HWTS7_16 + ADC TRIG4 selected + 0x10 + + + HWTS7_32 + ADC TRIG5 selected + 0x20 + + + HWTS7_64 + ADC TRIG6 selected + 0x40 + + + HWTS7_128 + ADC TRIG7 selected + 0x80 + + + + + B2B7 + Segment 7 B2B + 28 + 1 + read-write + + + B2B7_0 + Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + 0 + + + B2B7_1 + Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + 0x1 + + + + + IE7 + Segment 7 done interrupt selection + 29 + 2 + read-write + + + IE7_0 + No interrupt when finished + 0 + + + IE7_1 + Generate interrupt on Done0 when segment 7 finish. + 0x1 + + + IE7_2 + Generate interrupt on Done1 when segment 7 finish. + 0x2 + + + IE7_3 + Generate interrupt on Done2 when segment 7 finish. + 0x3 + + + + + + + TRIG7_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA1 + Result DATA1The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG7_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA3 + Result DATA3The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG7_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA5 + Result DATA5The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + TRIG7_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 0 + 12 + read-only + + + DATA7 + Result DATA7The sign bit from ADC result FIFO is ignored by ETC_TRIG result, so only 12-bit unsigned results is supported by ADC_ETC module + 16 + 12 + read-only + + + + + + + AOI1 + AND/OR/INVERT module + AOI + AOI1_ + AOI + 0x403B4000 + + 0 + 0x10 + registers + + + + 4 + 0x4 + 0,1,2,3 + BFCRT01%s + Boolean Function Term 0 and 1 Configuration Register for EVENTn + 0 + 16 + read-write + 0 + 0xFFFF + + + PT1_DC + Product term 1, D input configuration + 0 + 2 + read-write + + + PT1_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT1_DC_1 + Pass the D input in this product term + 0x1 + + + PT1_DC_2 + Complement the D input in this product term + 0x2 + + + PT1_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT1_CC + Product term 1, C input configuration + 2 + 2 + read-write + + + PT1_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT1_CC_1 + Pass the C input in this product term + 0x1 + + + PT1_CC_2 + Complement the C input in this product term + 0x2 + + + PT1_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT1_BC + Product term 1, B input configuration + 4 + 2 + read-write + + + PT1_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT1_BC_1 + Pass the B input in this product term + 0x1 + + + PT1_BC_2 + Complement the B input in this product term + 0x2 + + + PT1_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT1_AC + Product term 1, A input configuration + 6 + 2 + read-write + + + PT1_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT1_AC_1 + Pass the A input in this product term + 0x1 + + + PT1_AC_2 + Complement the A input in this product term + 0x2 + + + PT1_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT0_DC + Product term 0, D input configuration + 8 + 2 + read-write + + + PT0_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT0_DC_1 + Pass the D input in this product term + 0x1 + + + PT0_DC_2 + Complement the D input in this product term + 0x2 + + + PT0_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT0_CC + Product term 0, C input configuration + 10 + 2 + read-write + + + PT0_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT0_CC_1 + Pass the C input in this product term + 0x1 + + + PT0_CC_2 + Complement the C input in this product term + 0x2 + + + PT0_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT0_BC + Product term 0, B input configuration + 12 + 2 + read-write + + + PT0_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT0_BC_1 + Pass the B input in this product term + 0x1 + + + PT0_BC_2 + Complement the B input in this product term + 0x2 + + + PT0_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT0_AC + Product term 0, A input configuration + 14 + 2 + read-write + + + PT0_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT0_AC_1 + Pass the A input in this product term + 0x1 + + + PT0_AC_2 + Complement the A input in this product term + 0x2 + + + PT0_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + 4 + 0x4 + 0,1,2,3 + BFCRT23%s + Boolean Function Term 2 and 3 Configuration Register for EVENTn + 0x2 + 16 + read-write + 0 + 0xFFFF + + + PT3_DC + Product term 3, D input configuration + 0 + 2 + read-write + + + PT3_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT3_DC_1 + Pass the D input in this product term + 0x1 + + + PT3_DC_2 + Complement the D input in this product term + 0x2 + + + PT3_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT3_CC + Product term 3, C input configuration + 2 + 2 + read-write + + + PT3_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT3_CC_1 + Pass the C input in this product term + 0x1 + + + PT3_CC_2 + Complement the C input in this product term + 0x2 + + + PT3_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT3_BC + Product term 3, B input configuration + 4 + 2 + read-write + + + PT3_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT3_BC_1 + Pass the B input in this product term + 0x1 + + + PT3_BC_2 + Complement the B input in this product term + 0x2 + + + PT3_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT3_AC + Product term 3, A input configuration + 6 + 2 + read-write + + + PT3_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT3_AC_1 + Pass the A input in this product term + 0x1 + + + PT3_AC_2 + Complement the A input in this product term + 0x2 + + + PT3_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT2_DC + Product term 2, D input configuration + 8 + 2 + read-write + + + PT2_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT2_DC_1 + Pass the D input in this product term + 0x1 + + + PT2_DC_2 + Complement the D input in this product term + 0x2 + + + PT2_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT2_CC + Product term 2, C input configuration + 10 + 2 + read-write + + + PT2_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT2_CC_1 + Pass the C input in this product term + 0x1 + + + PT2_CC_2 + Complement the C input in this product term + 0x2 + + + PT2_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT2_BC + Product term 2, B input configuration + 12 + 2 + read-write + + + PT2_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT2_BC_1 + Pass the B input in this product term + 0x1 + + + PT2_BC_2 + Complement the B input in this product term + 0x2 + + + PT2_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT2_AC + Product term 2, A input configuration + 14 + 2 + read-write + + + PT2_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT2_AC_1 + Pass the A input in this product term + 0x1 + + + PT2_AC_2 + Complement the A input in this product term + 0x2 + + + PT2_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + + + AOI2 + AND/OR/INVERT module + AOI + AOI2_ + 0x403B8000 + + 0 + 0x10 + registers + + + + XBARA1 + Crossbar Switch + XBARA + XBARA1_ + 0x403BC000 + + 0 + 0x88 + registers + + + + SEL0 + Crossbar A Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL1 + Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL1 + Crossbar A Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL3 + Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL2 + Crossbar A Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL5 + Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL3 + Crossbar A Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL7 + Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL4 + Crossbar A Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL9 + Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL5 + Crossbar A Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL11 + Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL6 + Crossbar A Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL13 + Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL7 + Crossbar A Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL15 + Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL8 + Crossbar A Select Register 8 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + SEL16 + Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL17 + Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL9 + Crossbar A Select Register 9 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + SEL18 + Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL19 + Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL10 + Crossbar A Select Register 10 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + SEL20 + Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL21 + Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL11 + Crossbar A Select Register 11 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + SEL22 + Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL23 + Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL12 + Crossbar A Select Register 12 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + SEL24 + Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL25 + Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL13 + Crossbar A Select Register 13 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + SEL26 + Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL27 + Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL14 + Crossbar A Select Register 14 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + SEL28 + Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL29 + Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL15 + Crossbar A Select Register 15 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + SEL30 + Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL31 + Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL16 + Crossbar A Select Register 16 + 0x20 + 16 + read-write + 0 + 0xFFFF + + + SEL32 + Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL33 + Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL17 + Crossbar A Select Register 17 + 0x22 + 16 + read-write + 0 + 0xFFFF + + + SEL34 + Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL35 + Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL18 + Crossbar A Select Register 18 + 0x24 + 16 + read-write + 0 + 0xFFFF + + + SEL36 + Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL37 + Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL19 + Crossbar A Select Register 19 + 0x26 + 16 + read-write + 0 + 0xFFFF + + + SEL38 + Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL39 + Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL20 + Crossbar A Select Register 20 + 0x28 + 16 + read-write + 0 + 0xFFFF + + + SEL40 + Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL41 + Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL21 + Crossbar A Select Register 21 + 0x2A + 16 + read-write + 0 + 0xFFFF + + + SEL42 + Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL43 + Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL22 + Crossbar A Select Register 22 + 0x2C + 16 + read-write + 0 + 0xFFFF + + + SEL44 + Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL45 + Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL23 + Crossbar A Select Register 23 + 0x2E + 16 + read-write + 0 + 0xFFFF + + + SEL46 + Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL47 + Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL24 + Crossbar A Select Register 24 + 0x30 + 16 + read-write + 0 + 0xFFFF + + + SEL48 + Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL49 + Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL25 + Crossbar A Select Register 25 + 0x32 + 16 + read-write + 0 + 0xFFFF + + + SEL50 + Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL51 + Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL26 + Crossbar A Select Register 26 + 0x34 + 16 + read-write + 0 + 0xFFFF + + + SEL52 + Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL53 + Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL27 + Crossbar A Select Register 27 + 0x36 + 16 + read-write + 0 + 0xFFFF + + + SEL54 + Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL55 + Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL28 + Crossbar A Select Register 28 + 0x38 + 16 + read-write + 0 + 0xFFFF + + + SEL56 + Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL57 + Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL29 + Crossbar A Select Register 29 + 0x3A + 16 + read-write + 0 + 0xFFFF + + + SEL58 + Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL59 + Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL30 + Crossbar A Select Register 30 + 0x3C + 16 + read-write + 0 + 0xFFFF + + + SEL60 + Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL61 + Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL31 + Crossbar A Select Register 31 + 0x3E + 16 + read-write + 0 + 0xFFFF + + + SEL62 + Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL63 + Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL32 + Crossbar A Select Register 32 + 0x40 + 16 + read-write + 0 + 0xFFFF + + + SEL64 + Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL65 + Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL33 + Crossbar A Select Register 33 + 0x42 + 16 + read-write + 0 + 0xFFFF + + + SEL66 + Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL67 + Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL34 + Crossbar A Select Register 34 + 0x44 + 16 + read-write + 0 + 0xFFFF + + + SEL68 + Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL69 + Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL35 + Crossbar A Select Register 35 + 0x46 + 16 + read-write + 0 + 0xFFFF + + + SEL70 + Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL71 + Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL36 + Crossbar A Select Register 36 + 0x48 + 16 + read-write + 0 + 0xFFFF + + + SEL72 + Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL73 + Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL37 + Crossbar A Select Register 37 + 0x4A + 16 + read-write + 0 + 0xFFFF + + + SEL74 + Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL75 + Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL38 + Crossbar A Select Register 38 + 0x4C + 16 + read-write + 0 + 0xFFFF + + + SEL76 + Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL77 + Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL39 + Crossbar A Select Register 39 + 0x4E + 16 + read-write + 0 + 0xFFFF + + + SEL78 + Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL79 + Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL40 + Crossbar A Select Register 40 + 0x50 + 16 + read-write + 0 + 0xFFFF + + + SEL80 + Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL81 + Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL41 + Crossbar A Select Register 41 + 0x52 + 16 + read-write + 0 + 0xFFFF + + + SEL82 + Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL83 + Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL42 + Crossbar A Select Register 42 + 0x54 + 16 + read-write + 0 + 0xFFFF + + + SEL84 + Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL85 + Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL43 + Crossbar A Select Register 43 + 0x56 + 16 + read-write + 0 + 0xFFFF + + + SEL86 + Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL87 + Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL44 + Crossbar A Select Register 44 + 0x58 + 16 + read-write + 0 + 0xFFFF + + + SEL88 + Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL89 + Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL45 + Crossbar A Select Register 45 + 0x5A + 16 + read-write + 0 + 0xFFFF + + + SEL90 + Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL91 + Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL46 + Crossbar A Select Register 46 + 0x5C + 16 + read-write + 0 + 0xFFFF + + + SEL92 + Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL93 + Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL47 + Crossbar A Select Register 47 + 0x5E + 16 + read-write + 0 + 0xFFFF + + + SEL94 + Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL95 + Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL48 + Crossbar A Select Register 48 + 0x60 + 16 + read-write + 0 + 0xFFFF + + + SEL96 + Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL97 + Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL49 + Crossbar A Select Register 49 + 0x62 + 16 + read-write + 0 + 0xFFFF + + + SEL98 + Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL99 + Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL50 + Crossbar A Select Register 50 + 0x64 + 16 + read-write + 0 + 0xFFFF + + + SEL100 + Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL101 + Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL51 + Crossbar A Select Register 51 + 0x66 + 16 + read-write + 0 + 0xFFFF + + + SEL102 + Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL103 + Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL52 + Crossbar A Select Register 52 + 0x68 + 16 + read-write + 0 + 0xFFFF + + + SEL104 + Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL105 + Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL53 + Crossbar A Select Register 53 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + SEL106 + Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL107 + Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL54 + Crossbar A Select Register 54 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + SEL108 + Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL109 + Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL55 + Crossbar A Select Register 55 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + SEL110 + Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL111 + Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL56 + Crossbar A Select Register 56 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + SEL112 + Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL113 + Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL57 + Crossbar A Select Register 57 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + SEL114 + Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL115 + Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL58 + Crossbar A Select Register 58 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + SEL116 + Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL117 + Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL59 + Crossbar A Select Register 59 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + SEL118 + Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL119 + Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL60 + Crossbar A Select Register 60 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + SEL120 + Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL121 + Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL61 + Crossbar A Select Register 61 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + SEL122 + Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL123 + Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL62 + Crossbar A Select Register 62 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + SEL124 + Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL125 + Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL63 + Crossbar A Select Register 63 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + SEL126 + Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL127 + Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL64 + Crossbar A Select Register 64 + 0x80 + 16 + read-write + 0 + 0xFFFF + + + SEL128 + Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL129 + Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL65 + Crossbar A Select Register 65 + 0x82 + 16 + read-write + 0 + 0xFFFF + + + SEL130 + Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL131 + Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + CTRL0 + Crossbar A Control Register 0 + 0x84 + 16 + read-write + 0 + 0xFFFF + + + DEN0 + DMA Enable for XBAR_OUT0 + 0 + 1 + read-write + + + DEN0_0 + DMA disabled + 0 + + + DEN0_1 + DMA enabled + 0x1 + + + + + IEN0 + Interrupt Enable for XBAR_OUT0 + 1 + 1 + read-write + + + IEN0_0 + Interrupt disabled + 0 + + + IEN0_1 + Interrupt enabled + 0x1 + + + + + EDGE0 + Active edge for edge detection on XBAR_OUT0 + 2 + 2 + read-write + + + EDGE0_0 + STS0 never asserts + 0 + + + EDGE0_1 + STS0 asserts on rising edges of XBAR_OUT0 + 0x1 + + + EDGE0_2 + STS0 asserts on falling edges of XBAR_OUT0 + 0x2 + + + EDGE0_3 + STS0 asserts on rising and falling edges of XBAR_OUT0 + 0x3 + + + + + STS0 + Edge detection status for XBAR_OUT0 + 4 + 1 + read-write + oneToClear + + + STS0_0 + Active edge not yet detected on XBAR_OUT0 + 0 + + + STS0_1 + Active edge detected on XBAR_OUT0 + 0x1 + + + + + DEN1 + DMA Enable for XBAR_OUT1 + 8 + 1 + read-write + + + DEN1_0 + DMA disabled + 0 + + + DEN1_1 + DMA enabled + 0x1 + + + + + IEN1 + Interrupt Enable for XBAR_OUT1 + 9 + 1 + read-write + + + IEN1_0 + Interrupt disabled + 0 + + + IEN1_1 + Interrupt enabled + 0x1 + + + + + EDGE1 + Active edge for edge detection on XBAR_OUT1 + 10 + 2 + read-write + + + EDGE1_0 + STS1 never asserts + 0 + + + EDGE1_1 + STS1 asserts on rising edges of XBAR_OUT1 + 0x1 + + + EDGE1_2 + STS1 asserts on falling edges of XBAR_OUT1 + 0x2 + + + EDGE1_3 + STS1 asserts on rising and falling edges of XBAR_OUT1 + 0x3 + + + + + STS1 + Edge detection status for XBAR_OUT1 + 12 + 1 + read-write + oneToClear + + + STS1_0 + Active edge not yet detected on XBAR_OUT1 + 0 + + + STS1_1 + Active edge detected on XBAR_OUT1 + 0x1 + + + + + + + CTRL1 + Crossbar A Control Register 1 + 0x86 + 16 + read-write + 0 + 0xFFFF + + + DEN2 + DMA Enable for XBAR_OUT2 + 0 + 1 + read-write + + + DEN2_0 + DMA disabled + 0 + + + DEN2_1 + DMA enabled + 0x1 + + + + + IEN2 + Interrupt Enable for XBAR_OUT2 + 1 + 1 + read-write + + + IEN2_0 + Interrupt disabled + 0 + + + IEN2_1 + Interrupt enabled + 0x1 + + + + + EDGE2 + Active edge for edge detection on XBAR_OUT2 + 2 + 2 + read-write + + + EDGE2_0 + STS2 never asserts + 0 + + + EDGE2_1 + STS2 asserts on rising edges of XBAR_OUT2 + 0x1 + + + EDGE2_2 + STS2 asserts on falling edges of XBAR_OUT2 + 0x2 + + + EDGE2_3 + STS2 asserts on rising and falling edges of XBAR_OUT2 + 0x3 + + + + + STS2 + Edge detection status for XBAR_OUT2 + 4 + 1 + read-write + oneToClear + + + STS2_0 + Active edge not yet detected on XBAR_OUT2 + 0 + + + STS2_1 + Active edge detected on XBAR_OUT2 + 0x1 + + + + + DEN3 + DMA Enable for XBAR_OUT3 + 8 + 1 + read-write + + + DEN3_0 + DMA disabled + 0 + + + DEN3_1 + DMA enabled + 0x1 + + + + + IEN3 + Interrupt Enable for XBAR_OUT3 + 9 + 1 + read-write + + + IEN3_0 + Interrupt disabled + 0 + + + IEN3_1 + Interrupt enabled + 0x1 + + + + + EDGE3 + Active edge for edge detection on XBAR_OUT3 + 10 + 2 + read-write + + + EDGE3_0 + STS3 never asserts + 0 + + + EDGE3_1 + STS3 asserts on rising edges of XBAR_OUT3 + 0x1 + + + EDGE3_2 + STS3 asserts on falling edges of XBAR_OUT3 + 0x2 + + + EDGE3_3 + STS3 asserts on rising and falling edges of XBAR_OUT3 + 0x3 + + + + + STS3 + Edge detection status for XBAR_OUT3 + 12 + 1 + read-write + oneToClear + + + STS3_0 + Active edge not yet detected on XBAR_OUT3 + 0 + + + STS3_1 + Active edge detected on XBAR_OUT3 + 0x1 + + + + + + + + + XBARB2 + Crossbar Switch + XBARA + XBARB2_ + XBARA + 0x403C0000 + + 0 + 0x10 + registers + + + + SEL0 + Crossbar B Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL1 + Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL1 + Crossbar B Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL3 + Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL2 + Crossbar B Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL5 + Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL3 + Crossbar B Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL7 + Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL4 + Crossbar B Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL9 + Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL5 + Crossbar B Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL11 + Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL6 + Crossbar B Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL13 + Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL7 + Crossbar B Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL15 + Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + + + XBARB3 + Crossbar Switch + XBARA + XBARB3_ + 0x403C4000 + + 0 + 0x10 + registers + + + + ENC1 + ENC + ENC + ENC + 0x403C8000 + + 0 + 0x28 + registers + + + ENC1 + 129 + + + + CTRL + Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enable + 0 + 1 + read-write + + + CMPIE_0 + Disabled + 0 + + + CMPIE_1 + Enabled + 0x1 + + + + + CMPIRQ + Compare Interrupt Request + 1 + 1 + read-write + oneToClear + + + CMPIRQ_0 + No match has occurred (the counter does not match the COMP value) + 0 + + + CMPIRQ_1 + COMP match has occurred (the counter matches the COMP value) + 0x1 + + + + + WDE + Watchdog Enable + 2 + 1 + read-write + + + WDE_0 + Disabled + 0 + + + WDE_1 + Enabled + 0x1 + + + + + DIE + Watchdog Timeout Interrupt Enable + 3 + 1 + read-write + + + DIE_0 + Disabled + 0 + + + DIE_1 + Enabled + 0x1 + + + + + DIRQ + Watchdog Timeout Interrupt Request + 4 + 1 + read-write + oneToClear + + + DIRQ_0 + No Watchdog timeout interrupt has occurred + 0 + + + DIRQ_1 + Watchdog timeout interrupt has occurred + 0x1 + + + + + XNE + Use Negative Edge of INDEX Pulse + 5 + 1 + read-write + + + XNE_0 + Use positive edge of INDEX pulse + 0 + + + XNE_1 + Use negative edge of INDEX pulse + 0x1 + + + + + XIP + INDEX Triggered Initialization of Position Counters UPOS and LPOS + 6 + 1 + read-write + + + XIP_0 + INDEX pulse does not initialize the position counter + 0 + + + XIP_1 + INDEX pulse initializes the position counter + 0x1 + + + + + XIE + INDEX Pulse Interrupt Enable + 7 + 1 + read-write + + + XIE_0 + Disabled + 0 + + + XIE_1 + Enabled + 0x1 + + + + + XIRQ + INDEX Pulse Interrupt Request + 8 + 1 + read-write + oneToClear + + + XIRQ_0 + INDEX pulse has not occurred + 0 + + + XIRQ_1 + INDEX pulse has occurred + 0x1 + + + + + PH1 + Enable Signal Phase Count Mode + 9 + 1 + read-write + + + PH1_0 + Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + 0 + + + PH1_1 + Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down + 0x1 + + + + + REV + Enable Reverse Direction Counting + 10 + 1 + read-write + + + REV_0 + Count normally + 0 + + + REV_1 + Count in the reverse direction + 0x1 + + + + + SWIP + Software-Triggered Initialization of Position Counters UPOS and LPOS + 11 + 1 + read-write + + + SWIP_0 + No action + 0 + + + SWIP_1 + Initialize position counter (using upper and lower initialization registers, UINIT and LINIT) + 0x1 + + + + + HNE + Use Negative Edge of HOME Input + 12 + 1 + read-write + + + HNE_0 + Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + 0 + + + HNE_1 + Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + 0x1 + + + + + HIP + Enable HOME to Initialize Position Counters UPOS and LPOS + 13 + 1 + read-write + + + HIP_0 + No action + 0 + + + HIP_1 + HOME signal initializes the position counter + 0x1 + + + + + HIE + HOME Interrupt Enable + 14 + 1 + read-write + + + HIE_0 + Disabled + 0 + + + HIE_1 + Enabled + 0x1 + + + + + HIRQ + HOME Signal Transition Interrupt Request + 15 + 1 + read-write + oneToClear + + + HIRQ_0 + No transition on the HOME signal has occurred + 0 + + + HIRQ_1 + A transition on the HOME signal has occurred + 0x1 + + + + + + + FILT + Input Filter Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + WTR + Watchdog Timeout Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + WDOG + WDOG + 0 + 16 + read-write + + + + + POSD + Position Difference Counter Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + POSD + POSD + 0 + 16 + read-write + + + + + POSDH + Position Difference Hold Register + 0x8 + 16 + read-only + 0 + 0xFFFF + + + POSDH + POSDH + 0 + 16 + read-only + + + + + REV + Revolution Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + REV + REV + 0 + 16 + read-write + + + + + REVH + Revolution Hold Register + 0xC + 16 + read-only + 0 + 0xFFFF + + + REVH + REVH + 0 + 16 + read-only + + + + + UPOS + Upper Position Counter Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + POS + POS + 0 + 16 + read-write + + + + + LPOS + Lower Position Counter Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + POS + POS + 0 + 16 + read-write + + + + + UPOSH + Upper Position Hold Register + 0x12 + 16 + read-only + 0 + 0xFFFF + + + POSH + POSH + 0 + 16 + read-only + + + + + LPOSH + Lower Position Hold Register + 0x14 + 16 + read-only + 0 + 0xFFFF + + + POSH + POSH + 0 + 16 + read-only + + + + + UINIT + Upper Initialization Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + INIT + INIT + 0 + 16 + read-write + + + + + LINIT + Lower Initialization Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + INIT + INIT + 0 + 16 + read-write + + + + + IMR + Input Monitor Register + 0x1A + 16 + read-only + 0 + 0xFFFF + + + HOME + HOME + 0 + 1 + read-only + + + INDEX + INDEX + 1 + 1 + read-only + + + PHB + PHB + 2 + 1 + read-only + + + PHA + PHA + 3 + 1 + read-only + + + FHOM + FHOM + 4 + 1 + read-only + + + FIND + FIND + 5 + 1 + read-only + + + FPHB + FPHB + 6 + 1 + read-only + + + FPHA + FPHA + 7 + 1 + read-only + + + + + TST + Test Register + 0x1C + 16 + read-write + 0 + 0xFFFF + + + TEST_COUNT + TEST_COUNT + 0 + 8 + read-write + + + TEST_PERIOD + TEST_PERIOD + 8 + 5 + read-write + + + QDN + Quadrature Decoder Negative Signal + 13 + 1 + read-write + + + QDN_0 + Generates a positive quadrature decoder signal + 0 + + + QDN_1 + Generates a negative quadrature decoder signal + 0x1 + + + + + TCE + Test Counter Enable + 14 + 1 + read-write + + + TCE_0 + Disabled + 0 + + + TCE_1 + Enabled + 0x1 + + + + + TEN + Test Mode Enable + 15 + 1 + read-write + + + TEN_0 + Disabled + 0 + + + TEN_1 + Enabled + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x1E + 16 + read-write + 0 + 0xFFFF + + + UPDHLD + Update Hold Registers + 0 + 1 + read-write + + + UPDHLD_0 + Disable updates of hold registers on the rising edge of TRIGGER input signal + 0 + + + UPDHLD_1 + Enable updates of hold registers on the rising edge of TRIGGER input signal + 0x1 + + + + + UPDPOS + Update Position Registers + 1 + 1 + read-write + + + UPDPOS_0 + No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER + 0 + + + UPDPOS_1 + Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER + 0x1 + + + + + MOD + Enable Modulo Counting + 2 + 1 + read-write + + + MOD_0 + Disable modulo counting + 0 + + + MOD_1 + Enable modulo counting + 0x1 + + + + + DIR + Count Direction Flag + 3 + 1 + read-only + + + DIR_0 + Last count was in the down direction + 0 + + + DIR_1 + Last count was in the up direction + 0x1 + + + + + RUIE + Roll-under Interrupt Enable + 4 + 1 + read-write + + + RUIE_0 + Disabled + 0 + + + RUIE_1 + Enabled + 0x1 + + + + + RUIRQ + Roll-under Interrupt Request + 5 + 1 + read-write + oneToClear + + + RUIRQ_0 + No roll-under has occurred + 0 + + + RUIRQ_1 + Roll-under has occurred + 0x1 + + + + + ROIE + Roll-over Interrupt Enable + 6 + 1 + read-write + + + ROIE_0 + Disabled + 0 + + + ROIE_1 + Enabled + 0x1 + + + + + ROIRQ + Roll-over Interrupt Request + 7 + 1 + read-write + oneToClear + + + ROIRQ_0 + No roll-over has occurred + 0 + + + ROIRQ_1 + Roll-over has occurred + 0x1 + + + + + REVMOD + Revolution Counter Modulus Enable + 8 + 1 + read-write + + + REVMOD_0 + Use INDEX pulse to increment/decrement revolution counter (REV) + 0 + + + REVMOD_1 + Use modulus counting roll-over/under to increment/decrement revolution counter (REV) + 0x1 + + + + + OUTCTL + Output Control + 9 + 1 + read-write + + + OUTCTL_0 + POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + 0 + + + OUTCTL_1 + POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + 0x1 + + + + + + + UMOD + Upper Modulus Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + MOD + MOD + 0 + 16 + read-write + + + + + LMOD + Lower Modulus Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + MOD + MOD + 0 + 16 + read-write + + + + + UCOMP + Upper Position Compare Register + 0x24 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + COMP + 0 + 16 + read-write + + + + + LCOMP + Lower Position Compare Register + 0x26 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + COMP + 0 + 16 + read-write + + + + + + + ENC2 + ENC + ENC + 0x403CC000 + + 0 + 0x28 + registers + + + ENC2 + 130 + + + + ENC3 + ENC + ENC + 0x403D0000 + + 0 + 0x28 + registers + + + ENC3 + 131 + + + + ENC4 + ENC + ENC + 0x403D4000 + + 0 + 0x28 + registers + + + ENC4 + 132 + + + + PWM1 + PWM + PWM + PWM + 0x403DC000 + + 0 + 0x196 + registers + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + + SM0CNT + Counter Register + 0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM0INIT + Initial Count Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM0CTRL2 + Control 2 Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM0CTRL + Control Register + 0x6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM0VAL0 + Value Register 0 + 0xA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM0FRACVAL1 + Fractional Value Register 1 + 0xC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM0VAL1 + Value Register 1 + 0xE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM0FRACVAL2 + Fractional Value Register 2 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM0VAL2 + Value Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM0FRACVAL3 + Fractional Value Register 3 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM0VAL3 + Value Register 3 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM0FRACVAL4 + Fractional Value Register 4 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM0VAL4 + Value Register 4 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM0FRACVAL5 + Fractional Value Register 5 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM0VAL5 + Value Register 5 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM0FRCTRL + Fractional Control Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM0OCTRL + Output Control Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM0STS + Status Register + 0x24 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM0INTEN + Interrupt Enable Register + 0x26 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM0DMAEN + DMA Enable Register + 0x28 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM0TCTRL + Output Trigger Control Register + 0x2A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM0DISMAP0 + Fault Disable Mapping Register 0 + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM0DISMAP1 + Fault Disable Mapping Register 1 + 0x2E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM0DTCNT0 + Deadtime Count Register 0 + 0x30 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM0DTCNT1 + Deadtime Count Register 1 + 0x32 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM0CAPTCTRLA + Capture Control A Register + 0x34 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPA + Capture Compare A Register + 0x36 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM0CAPTCTRLB + Capture Control B Register + 0x38 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPB + Capture Compare B Register + 0x3A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM0CAPTCTRLX + Capture Control X Register + 0x3C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPX + Capture Compare X Register + 0x3E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM0CVAL0 + Capture Value 0 Register + 0x40 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM0CVAL0CYC + Capture Value 0 Cycle Register + 0x42 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM0CVAL1 + Capture Value 1 Register + 0x44 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM0CVAL1CYC + Capture Value 1 Cycle Register + 0x46 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM0CVAL2 + Capture Value 2 Register + 0x48 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM0CVAL2CYC + Capture Value 2 Cycle Register + 0x4A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM0CVAL3 + Capture Value 3 Register + 0x4C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM0CVAL3CYC + Capture Value 3 Cycle Register + 0x4E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM0CVAL4 + Capture Value 4 Register + 0x50 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM0CVAL4CYC + Capture Value 4 Cycle Register + 0x52 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM0CVAL5 + Capture Value 5 Register + 0x54 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM0CVAL5CYC + Capture Value 5 Cycle Register + 0x56 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM1CNT + Counter Register + 0x60 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM1INIT + Initial Count Register + 0x62 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM1CTRL2 + Control 2 Register + 0x64 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM1CTRL + Control Register + 0x66 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM1VAL0 + Value Register 0 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM1FRACVAL1 + Fractional Value Register 1 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM1VAL1 + Value Register 1 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM1FRACVAL2 + Fractional Value Register 2 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM1VAL2 + Value Register 2 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM1FRACVAL3 + Fractional Value Register 3 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM1VAL3 + Value Register 3 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM1FRACVAL4 + Fractional Value Register 4 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM1VAL4 + Value Register 4 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM1FRACVAL5 + Fractional Value Register 5 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM1VAL5 + Value Register 5 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM1FRCTRL + Fractional Control Register + 0x80 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM1OCTRL + Output Control Register + 0x82 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM1STS + Status Register + 0x84 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM1INTEN + Interrupt Enable Register + 0x86 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM1DMAEN + DMA Enable Register + 0x88 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM1TCTRL + Output Trigger Control Register + 0x8A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM1DISMAP0 + Fault Disable Mapping Register 0 + 0x8C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM1DISMAP1 + Fault Disable Mapping Register 1 + 0x8E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM1DTCNT0 + Deadtime Count Register 0 + 0x90 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM1DTCNT1 + Deadtime Count Register 1 + 0x92 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM1CAPTCTRLA + Capture Control A Register + 0x94 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPA + Capture Compare A Register + 0x96 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM1CAPTCTRLB + Capture Control B Register + 0x98 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPB + Capture Compare B Register + 0x9A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM1CAPTCTRLX + Capture Control X Register + 0x9C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPX + Capture Compare X Register + 0x9E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM1CVAL0 + Capture Value 0 Register + 0xA0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM1CVAL0CYC + Capture Value 0 Cycle Register + 0xA2 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM1CVAL1 + Capture Value 1 Register + 0xA4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM1CVAL1CYC + Capture Value 1 Cycle Register + 0xA6 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM1CVAL2 + Capture Value 2 Register + 0xA8 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM1CVAL2CYC + Capture Value 2 Cycle Register + 0xAA + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM1CVAL3 + Capture Value 3 Register + 0xAC + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM1CVAL3CYC + Capture Value 3 Cycle Register + 0xAE + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM1CVAL4 + Capture Value 4 Register + 0xB0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM1CVAL4CYC + Capture Value 4 Cycle Register + 0xB2 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM1CVAL5 + Capture Value 5 Register + 0xB4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM1CVAL5CYC + Capture Value 5 Cycle Register + 0xB6 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM2CNT + Counter Register + 0xC0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM2INIT + Initial Count Register + 0xC2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM2CTRL2 + Control 2 Register + 0xC4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM2CTRL + Control Register + 0xC6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM2VAL0 + Value Register 0 + 0xCA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM2FRACVAL1 + Fractional Value Register 1 + 0xCC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM2VAL1 + Value Register 1 + 0xCE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM2FRACVAL2 + Fractional Value Register 2 + 0xD0 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM2VAL2 + Value Register 2 + 0xD2 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM2FRACVAL3 + Fractional Value Register 3 + 0xD4 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM2VAL3 + Value Register 3 + 0xD6 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM2FRACVAL4 + Fractional Value Register 4 + 0xD8 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM2VAL4 + Value Register 4 + 0xDA + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM2FRACVAL5 + Fractional Value Register 5 + 0xDC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM2VAL5 + Value Register 5 + 0xDE + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM2FRCTRL + Fractional Control Register + 0xE0 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM2OCTRL + Output Control Register + 0xE2 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM2STS + Status Register + 0xE4 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM2INTEN + Interrupt Enable Register + 0xE6 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM2DMAEN + DMA Enable Register + 0xE8 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM2TCTRL + Output Trigger Control Register + 0xEA + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM2DISMAP0 + Fault Disable Mapping Register 0 + 0xEC + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM2DISMAP1 + Fault Disable Mapping Register 1 + 0xEE + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM2DTCNT0 + Deadtime Count Register 0 + 0xF0 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM2DTCNT1 + Deadtime Count Register 1 + 0xF2 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM2CAPTCTRLA + Capture Control A Register + 0xF4 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPA + Capture Compare A Register + 0xF6 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM2CAPTCTRLB + Capture Control B Register + 0xF8 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPB + Capture Compare B Register + 0xFA + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM2CAPTCTRLX + Capture Control X Register + 0xFC + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPX + Capture Compare X Register + 0xFE + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM2CVAL0 + Capture Value 0 Register + 0x100 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM2CVAL0CYC + Capture Value 0 Cycle Register + 0x102 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM2CVAL1 + Capture Value 1 Register + 0x104 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM2CVAL1CYC + Capture Value 1 Cycle Register + 0x106 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM2CVAL2 + Capture Value 2 Register + 0x108 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM2CVAL2CYC + Capture Value 2 Cycle Register + 0x10A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM2CVAL3 + Capture Value 3 Register + 0x10C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM2CVAL3CYC + Capture Value 3 Cycle Register + 0x10E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM2CVAL4 + Capture Value 4 Register + 0x110 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM2CVAL4CYC + Capture Value 4 Cycle Register + 0x112 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM2CVAL5 + Capture Value 5 Register + 0x114 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM2CVAL5CYC + Capture Value 5 Cycle Register + 0x116 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM3CNT + Counter Register + 0x120 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM3INIT + Initial Count Register + 0x122 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM3CTRL2 + Control 2 Register + 0x124 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM3CTRL + Control Register + 0x126 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM3VAL0 + Value Register 0 + 0x12A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM3FRACVAL1 + Fractional Value Register 1 + 0x12C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM3VAL1 + Value Register 1 + 0x12E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM3FRACVAL2 + Fractional Value Register 2 + 0x130 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM3VAL2 + Value Register 2 + 0x132 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM3FRACVAL3 + Fractional Value Register 3 + 0x134 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM3VAL3 + Value Register 3 + 0x136 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM3FRACVAL4 + Fractional Value Register 4 + 0x138 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM3VAL4 + Value Register 4 + 0x13A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM3FRACVAL5 + Fractional Value Register 5 + 0x13C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM3VAL5 + Value Register 5 + 0x13E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM3FRCTRL + Fractional Control Register + 0x140 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM3OCTRL + Output Control Register + 0x142 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM3STS + Status Register + 0x144 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM3INTEN + Interrupt Enable Register + 0x146 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM3DMAEN + DMA Enable Register + 0x148 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM3TCTRL + Output Trigger Control Register + 0x14A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM3DISMAP0 + Fault Disable Mapping Register 0 + 0x14C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM3DISMAP1 + Fault Disable Mapping Register 1 + 0x14E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM3DTCNT0 + Deadtime Count Register 0 + 0x150 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM3DTCNT1 + Deadtime Count Register 1 + 0x152 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM3CAPTCTRLA + Capture Control A Register + 0x154 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPA + Capture Compare A Register + 0x156 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM3CAPTCTRLB + Capture Control B Register + 0x158 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPB + Capture Compare B Register + 0x15A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM3CAPTCTRLX + Capture Control X Register + 0x15C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPX + Capture Compare X Register + 0x15E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM3CVAL0 + Capture Value 0 Register + 0x160 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM3CVAL0CYC + Capture Value 0 Cycle Register + 0x162 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM3CVAL1 + Capture Value 1 Register + 0x164 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM3CVAL1CYC + Capture Value 1 Cycle Register + 0x166 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM3CVAL2 + Capture Value 2 Register + 0x168 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM3CVAL2CYC + Capture Value 2 Cycle Register + 0x16A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM3CVAL3 + Capture Value 3 Register + 0x16C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM3CVAL3CYC + Capture Value 3 Cycle Register + 0x16E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM3CVAL4 + Capture Value 4 Register + 0x170 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM3CVAL4CYC + Capture Value 4 Cycle Register + 0x172 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM3CVAL5 + Capture Value 5 Register + 0x174 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM3CVAL5CYC + Capture Value 5 Cycle Register + 0x176 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + OUTEN + Output Enable Register + 0x180 + 16 + read-write + 0 + 0xFFFF + + + PWMX_EN + PWM_X Output Enables + 0 + 4 + read-write + + + PWMX_EN_0 + PWM_X output disabled. + 0 + + + PWMX_EN_1 + PWM_X output enabled. + 0x1 + + + + + PWMB_EN + PWM_B Output Enables + 4 + 4 + read-write + + + PWMB_EN_0 + PWM_B output disabled. + 0 + + + PWMB_EN_1 + PWM_B output enabled. + 0x1 + + + + + PWMA_EN + PWM_A Output Enables + 8 + 4 + read-write + + + PWMA_EN_0 + PWM_A output disabled. + 0 + + + PWMA_EN_1 + PWM_A output enabled. + 0x1 + + + + + + + MASK + Mask Register + 0x182 + 16 + read-write + 0 + 0xFFFF + + + MASKX + PWM_X Masks + 0 + 4 + read-write + + + MASKX_0 + PWM_X output normal. + 0 + + + MASKX_1 + PWM_X output masked. + 0x1 + + + + + MASKB + PWM_B Masks + 4 + 4 + read-write + + + MASKB_0 + PWM_B output normal. + 0 + + + MASKB_1 + PWM_B output masked. + 0x1 + + + + + MASKA + PWM_A Masks + 8 + 4 + read-write + + + MASKA_0 + PWM_A output normal. + 0 + + + MASKA_1 + PWM_A output masked. + 0x1 + + + + + + + SWCOUT + Software Controlled Output Register + 0x184 + 16 + read-write + 0 + 0xFFFF + + + SM0OUT45 + Submodule 0 Software Controlled Output 45 + 0 + 1 + read-write + + + SM0OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0 + + + SM0OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0x1 + + + + + SM0OUT23 + Submodule 0 Software Controlled Output 23 + 1 + 1 + read-write + + + SM0OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0 + + + SM0OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0x1 + + + + + SM1OUT45 + Submodule 1 Software Controlled Output 45 + 2 + 1 + read-write + + + SM1OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0 + + + SM1OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0x1 + + + + + SM1OUT23 + Submodule 1 Software Controlled Output 23 + 3 + 1 + read-write + + + SM1OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0 + + + SM1OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0x1 + + + + + SM2OUT45 + Submodule 2 Software Controlled Output 45 + 4 + 1 + read-write + + + SM2OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0 + + + SM2OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0x1 + + + + + SM2OUT23 + Submodule 2 Software Controlled Output 23 + 5 + 1 + read-write + + + SM2OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0 + + + SM2OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0x1 + + + + + SM3OUT45 + Submodule 3 Software Controlled Output 45 + 6 + 1 + read-write + + + SM3OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0 + + + SM3OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0x1 + + + + + SM3OUT23 + Submodule 3 Software Controlled Output 23 + 7 + 1 + read-write + + + SM3OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0 + + + SM3OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0x1 + + + + + + + DTSRCSEL + PWM Source Select Register + 0x186 + 16 + read-write + 0 + 0xFFFF + + + SM0SEL45 + Submodule 0 PWM45 Control Select + 0 + 2 + read-write + + + SM0SEL45_0 + Generated SM0PWM45 signal is used by the deadtime logic. + 0 + + + SM0SEL45_1 + Inverted generated SM0PWM45 signal is used by the deadtime logic. + 0x1 + + + SM0SEL45_2 + SWCOUT[SM0OUT45] is used by the deadtime logic. + 0x2 + + + SM0SEL45_3 + PWM0_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM0SEL23 + Submodule 0 PWM23 Control Select + 2 + 2 + read-write + + + SM0SEL23_0 + Generated SM0PWM23 signal is used by the deadtime logic. + 0 + + + SM0SEL23_1 + Inverted generated SM0PWM23 signal is used by the deadtime logic. + 0x1 + + + SM0SEL23_2 + SWCOUT[SM0OUT23] is used by the deadtime logic. + 0x2 + + + SM0SEL23_3 + PWM0_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL45 + Submodule 1 PWM45 Control Select + 4 + 2 + read-write + + + SM1SEL45_0 + Generated SM1PWM45 signal is used by the deadtime logic. + 0 + + + SM1SEL45_1 + Inverted generated SM1PWM45 signal is used by the deadtime logic. + 0x1 + + + SM1SEL45_2 + SWCOUT[SM1OUT45] is used by the deadtime logic. + 0x2 + + + SM1SEL45_3 + PWM1_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL23 + Submodule 1 PWM23 Control Select + 6 + 2 + read-write + + + SM1SEL23_0 + Generated SM1PWM23 signal is used by the deadtime logic. + 0 + + + SM1SEL23_1 + Inverted generated SM1PWM23 signal is used by the deadtime logic. + 0x1 + + + SM1SEL23_2 + SWCOUT[SM1OUT23] is used by the deadtime logic. + 0x2 + + + SM1SEL23_3 + PWM1_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL45 + Submodule 2 PWM45 Control Select + 8 + 2 + read-write + + + SM2SEL45_0 + Generated SM2PWM45 signal is used by the deadtime logic. + 0 + + + SM2SEL45_1 + Inverted generated SM2PWM45 signal is used by the deadtime logic. + 0x1 + + + SM2SEL45_2 + SWCOUT[SM2OUT45] is used by the deadtime logic. + 0x2 + + + SM2SEL45_3 + PWM2_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL23 + Submodule 2 PWM23 Control Select + 10 + 2 + read-write + + + SM2SEL23_0 + Generated SM2PWM23 signal is used by the deadtime logic. + 0 + + + SM2SEL23_1 + Inverted generated SM2PWM23 signal is used by the deadtime logic. + 0x1 + + + SM2SEL23_2 + SWCOUT[SM2OUT23] is used by the deadtime logic. + 0x2 + + + SM2SEL23_3 + PWM2_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL45 + Submodule 3 PWM45 Control Select + 12 + 2 + read-write + + + SM3SEL45_0 + Generated SM3PWM45 signal is used by the deadtime logic. + 0 + + + SM3SEL45_1 + Inverted generated SM3PWM45 signal is used by the deadtime logic. + 0x1 + + + SM3SEL45_2 + SWCOUT[SM3OUT45] is used by the deadtime logic. + 0x2 + + + SM3SEL45_3 + PWM3_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL23 + Submodule 3 PWM23 Control Select + 14 + 2 + read-write + + + SM3SEL23_0 + Generated SM3PWM23 signal is used by the deadtime logic. + 0 + + + SM3SEL23_1 + Inverted generated SM3PWM23 signal is used by the deadtime logic. + 0x1 + + + SM3SEL23_2 + SWCOUT[SM3OUT23] is used by the deadtime logic. + 0x2 + + + SM3SEL23_3 + PWM3_EXTA signal is used by the deadtime logic. + 0x3 + + + + + + + MCTRL + Master Control Register + 0x188 + 16 + read-write + 0 + 0xFFFF + + + LDOK + Load Okay + 0 + 4 + read-write + + + LDOK_0 + Do not load new values. + 0 + + + LDOK_1 + Load prescaler, modulus, and PWM values of the corresponding submodule. + 0x1 + + + + + CLDOK + Clear Load Okay + 4 + 4 + read-write + + + RUN + Run + 8 + 4 + read-write + + + RUN_0 + PWM generator is disabled in the corresponding submodule. + 0 + + + RUN_1 + PWM generator is enabled in the corresponding submodule. + 0x1 + + + + + IPOL + Current Polarity + 12 + 4 + read-write + + + IPOL_0 + PWM23 is used to generate complementary PWM pair in the corresponding submodule. + 0 + + + IPOL_1 + PWM45 is used to generate complementary PWM pair in the corresponding submodule. + 0x1 + + + + + + + MCTRL2 + Master Control 2 Register + 0x18A + 16 + read-write + 0 + 0xFFFF + + + MONPLL + Monitor PLL State + 0 + 2 + read-write + + + MONPLL_0 + Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + 0 + + + MONPLL_1 + Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + 0x1 + + + MONPLL_2 + Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + 0x2 + + + MONPLL_3 + Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + 0x3 + + + + + + + FCTRL0 + Fault Control Register + 0x18C + 16 + read-write + 0 + 0xFFFF + + + FIE + Fault Interrupt Enables + 0 + 4 + read-write + + + FIE_0 + FAULTx CPU interrupt requests disabled. + 0 + + + FIE_1 + FAULTx CPU interrupt requests enabled. + 0x1 + + + + + FSAFE + Fault Safety Mode + 4 + 4 + read-write + + + FSAFE_0 + Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is setm then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + 0 + + + FSAFE_1 + Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + 0x1 + + + + + FAUTO + Automatic Fault Clearing + 8 + 4 + read-write + + + FAUTO_0 + Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE]. + 0 + + + FAUTO_1 + Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. + 0x1 + + + + + FLVL + Fault Level + 12 + 4 + read-write + + + FLVL_0 + A logic 0 on the fault input indicates a fault condition. + 0 + + + FLVL_1 + A logic 1 on the fault input indicates a fault condition. + 0x1 + + + + + + + FSTS0 + Fault Status Register + 0x18E + 16 + read-write + 0 + 0xFFFF + + + FFLAG + Fault Flags + 0 + 4 + read-write + + + FFLAG_0 + No fault on the FAULTx pin. + 0 + + + FFLAG_1 + Fault on the FAULTx pin. + 0x1 + + + + + FFULL + Full Cycle + 4 + 4 + read-write + + + FFULL_0 + PWM outputs are not re-enabled at the start of a full cycle + 0 + + + FFULL_1 + PWM outputs are re-enabled at the start of a full cycle + 0x1 + + + + + FFPIN + Filtered Fault Pins + 8 + 4 + read-only + + + FHALF + Half Cycle Fault Recovery + 12 + 4 + read-write + + + FHALF_0 + PWM outputs are not re-enabled at the start of a half cycle. + 0 + + + FHALF_1 + PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + 0x1 + + + + + + + FFILT0 + Fault Filter Register + 0x190 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Fault Filter Period + 0 + 8 + read-write + + + FILT_CNT + Fault Filter Count + 8 + 3 + read-write + + + GSTR + Fault Glitch Stretch Enable + 15 + 1 + read-write + + + GSTR_0 + Fault input glitch stretching is disabled. + 0 + + + GSTR_1 + Input fault signals will be stretched to at least 2 IPBus clock cycles. + 0x1 + + + + + + + FTST0 + Fault Test Register + 0x192 + 16 + read-write + 0 + 0xFFFF + + + FTEST + Fault Test + 0 + 1 + read-write + + + FTEST_0 + No fault + 0 + + + FTEST_1 + Cause a simulated fault + 0x1 + + + + + + + FCTRL20 + Fault Control 2 Register + 0x194 + 16 + read-write + 0 + 0xFFFF + + + NOCOMB + No Combinational Path From Fault Input To PWM Output + 0 + 4 + read-write + + + NOCOMB_0 + There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + 0 + + + NOCOMB_1 + The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + 0x1 + + + + + + + + + PWM2 + PWM + PWM + 0x403E0000 + + 0 + 0x196 + registers + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + + PWM3 + PWM + PWM + 0x403E4000 + + 0 + 0x196 + registers + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + + PWM4 + PWM + PWM + 0x403E8000 + + 0 + 0x196 + registers + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + + BEE + Bus Encryption Engine + BEE + BEE_ + 0x403EC000 + + 0 + 0x48 + registers + + + BEE + 55 + + + + CTRL + Control Register + 0 + 32 + read-write + 0x7700 + 0xFFFFFFFF + + + BEE_ENABLE + BEE enable bit + 0 + 1 + read-write + + + BEE_ENABLE_0 + Disable BEE + 0 + + + BEE_ENABLE_1 + Enable BEE + 0x1 + + + + + CTRL_CLK_EN + Clock enable input, low inactive + 1 + 1 + read-write + + + CTRL_SFTRST_N + Soft reset input, low active + 2 + 1 + read-write + + + KEY_VALID + AES-128 key is ready + 4 + 1 + read-write + + + KEY_REGION_SEL + AES key region select + 5 + 1 + read-write + + + KEY_REGION_SEL_0 + Load AES key for region0 + 0 + + + KEY_REGION_SEL_1 + Load AES key for region1 + 0x1 + + + + + AC_PROT_EN + Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only + 6 + 1 + read-write + + + LITTLE_ENDIAN + Endian swap control for the 16 bytes input and output data of AES core. + 7 + 1 + read-write + + + LITTLE_ENDIAN_0 + The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + 0 + + + LITTLE_ENDIAN_1 + The input and output data of AES core is not swapped. + 0x1 + + + + + SECURITY_LEVEL_R0 + Security level of the allowed access for memory region0 + 8 + 2 + read-write + + + CTRL_AES_MODE_R0 + AES mode of region0 + 10 + 1 + read-write + + + CTRL_AES_MODE_R0_0 + ECB + 0 + + + CTRL_AES_MODE_R0_1 + CTR + 0x1 + + + + + SECURITY_LEVEL_R1 + Security level of the allowed access for memory region1 + 12 + 2 + read-write + + + CTRL_AES_MODE_R1 + AES mode of region1 + 14 + 1 + read-write + + + CTRL_AES_MODE_R1_0 + ECB + 0 + + + CTRL_AES_MODE_R1_1 + CTR + 0x1 + + + + + BEE_ENABLE_LOCK + Lock bit for bee_enable + 16 + 1 + read-write + + + CTRL_CLK_EN_LOCK + Lock bit for ctrl_clk_en + 17 + 1 + read-write + + + CTRL_SFTRST_N_LOCK + Lock bit for ctrl_sftrst + 18 + 1 + read-write + + + REGION1_ADDR_LOCK + Lock bit for region1 address boundary + 19 + 1 + read-write + + + KEY_VALID_LOCK + Lock bit for key_valid + 20 + 1 + read-write + + + KEY_REGION_SEL_LOCK + Lock bit for key_region_sel + 21 + 1 + read-write + + + AC_PROT_EN_LOCK + Lock bit for ac_prot + 22 + 1 + read-write + + + LITTLE_ENDIAN_LOCK + Lock bit for little_endian + 23 + 1 + read-write + + + SECURITY_LEVEL_R0_LOCK + Lock bits for security_level_r0 + 24 + 2 + read-write + + + CTRL_AES_MODE_R0_LOCK + Lock bit for region0 ctrl_aes_mode + 26 + 1 + read-write + + + REGION0_KEY_LOCK + Lock bit for region0 AES key + 27 + 1 + read-write + + + SECURITY_LEVEL_R1_LOCK + Lock bits for security_level_r1 + 28 + 2 + read-write + + + CTRL_AES_MODE_R1_LOCK + Lock bit for region1 ctrl_aes_mode + 30 + 1 + read-write + + + REGION1_KEY_LOCK + Lock bit for region1 AES key + 31 + 1 + read-write + + + + + ADDR_OFFSET0 + Offset region 0 Register + 0x4 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET0 + Signed offset for BEE region 0 + 0 + 16 + read-write + + + ADDR_OFFSET0_LOCK + Lock bits for addr_offset0 + 16 + 16 + read-write + + + + + ADDR_OFFSET1 + Offset region 1 Register + 0x8 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET1 + Signed offset for BEE region 1 + 0 + 16 + read-write + + + ADDR_OFFSET1_LOCK + Lock bits for addr_offset1 + 16 + 16 + read-write + + + + + AES_KEY0_W0 + AES Key 0 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY0 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W1 + AES Key 1 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY1 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W2 + AES Key 2 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY2 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W3 + AES Key 3 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY3 + AES 128 key from software + 0 + 32 + read-write + + + + + STATUS + Status Register + 0x1C + 32 + read-write + 0 + 0 + + + IRQ_VEC + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort + 0 + 8 + read-write + oneToClear + + + BEE_IDLE + 1'b1: BEE is idle; 1'b0: BEE is active + 8 + 1 + read-only + + + + + CTR_NONCE0_W0 + NONCE00 Register + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE00 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W1 + NONCE01 Register + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE01 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W2 + NONCE02 Register + 0x28 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE02 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W3 + NONCE03 Register + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE03 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE1_W0 + NONCE10 Register + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE10 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W1 + NONCE11 Register + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE11 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W2 + NONCE12 Register + 0x38 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE12 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W3 + NONCE13 Register + 0x3C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE13 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + REGION1_TOP + Region1 Top Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_TOP + Address upper limit of region1 + 0 + 32 + read-write + + + + + REGION1_BOT + Region1 Bottom Address Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_BOT + Address lower limit of region1 + 0 + 32 + read-write + + + + + + + LPI2C1 + LPI2C + LPI2C + LPI2C + 0x403F0000 + + 0 + 0x174 + registers + + + LPI2C1 + 28 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_2 + Master only, with standard feature set + 0x2 + + + FEATURE_3 + Master and slave, with standard feature set + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + MTXFIFO + Master Transmit FIFO Size + 0 + 4 + read-only + + + MRXFIFO + Master Receive FIFO Size + 8 + 4 + read-only + + + + + MCR + Master Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Master Enable + 0 + 1 + read-write + + + MEN_0 + Master logic is disabled + 0 + + + MEN_1 + Master logic is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Master logic is not reset + 0 + + + RST_1 + Master logic is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Master is enabled in Doze mode + 0 + + + DOZEN_1 + Master is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Master is disabled in debug mode + 0 + + + DBGEN_1 + Master is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + MSR + Master Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data is not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + EPF + End Packet Flag + 8 + 1 + read-write + oneToClear + + + EPF_0 + Master has not generated a STOP or Repeated START condition + 0 + + + EPF_1 + Master has generated a STOP or Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Master has not generated a STOP condition + 0 + + + SDF_1 + Master has generated a STOP condition + 0x1 + + + + + NDF + NACK Detect Flag + 10 + 1 + read-write + oneToClear + + + NDF_0 + Unexpected NACK was not detected + 0 + + + NDF_1 + Unexpected NACK was detected + 0x1 + + + + + ALF + Arbitration Lost Flag + 11 + 1 + read-write + oneToClear + + + ALF_0 + Master has not lost arbitration + 0 + + + ALF_1 + Master has lost arbitration + 0x1 + + + + + FEF + FIFO Error Flag + 12 + 1 + read-write + oneToClear + + + FEF_0 + No error + 0 + + + FEF_1 + Master sending or receiving data without a START condition + 0x1 + + + + + PLTF + Pin Low Timeout Flag + 13 + 1 + read-write + oneToClear + + + PLTF_0 + Pin low timeout has not occurred or is disabled + 0 + + + PLTF_1 + Pin low timeout has occurred + 0x1 + + + + + DMF + Data Match Flag + 14 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Master Busy Flag + 24 + 1 + read-only + + + MBF_0 + I2C Master is idle + 0 + + + MBF_1 + I2C Master is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + MIER + Master Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + EPIE + End Packet Interrupt Enable + 8 + 1 + read-write + + + EPIE_0 + Disabled + 0 + + + EPIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + NDIE + NACK Detect Interrupt Enable + 10 + 1 + read-write + + + NDIE_0 + Disabled + 0 + + + NDIE_1 + Enabled + 0x1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 11 + 1 + read-write + + + ALIE_0 + Disabled + 0 + + + ALIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 12 + 1 + read-write + + + FEIE_0 + Enabled + 0 + + + FEIE_1 + Disabled + 0x1 + + + + + PLTIE + Pin Low Timeout Interrupt Enable + 13 + 1 + read-write + + + PLTIE_0 + Disabled + 0 + + + PLTIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 14 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + MDER + Master DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + MCFGR0 + Master Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request input is disabled + 0 + + + HREN_1 + Host request input is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is pin HREQ + 0 + + + HRSEL_1 + Host request input is input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO + 0 + + + RDMO_1 + Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + 0x1 + + + + + + + MCFGR1 + Master Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALE + Prescaler + 0 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + AUTOSTOP + Automatic STOP Generation + 8 + 1 + read-write + + + AUTOSTOP_0 + No effect + 0 + + + AUTOSTOP_1 + STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + 0x1 + + + + + IGNACK + IGNACK + 9 + 1 + read-write + + + IGNACK_0 + LPI2C Master will receive ACK and NACK normally + 0 + + + IGNACK_1 + LPI2C Master will treat a received NACK as if it (NACK) was an ACK + 0x1 + + + + + TIMECFG + Timeout Configuration + 10 + 1 + read-write + + + TIMECFG_0 + Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + 0 + + + TIMECFG_1 + Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + Match is enabled (1st data word equals MATCH0 OR MATCH1) + 0x2 + + + MATCFG_3 + Match is enabled (any data word equals MATCH0 OR MATCH1) + 0x3 + + + MATCFG_4 + Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + 0x4 + + + MATCFG_5 + Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + 0x5 + + + MATCFG_6 + Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x6 + + + MATCFG_7 + Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 3 + read-write + + + PINCFG_0 + 2-pin open drain mode + 0 + + + PINCFG_1 + 2-pin output only mode (ultra-fast mode) + 0x1 + + + PINCFG_2 + 2-pin push-pull mode + 0x2 + + + PINCFG_3 + 4-pin push-pull mode + 0x3 + + + PINCFG_4 + 2-pin open drain mode with separate LPI2C slave + 0x4 + + + PINCFG_5 + 2-pin output only mode (ultra-fast mode) with separate LPI2C slave + 0x5 + + + PINCFG_6 + 2-pin push-pull mode with separate LPI2C slave + 0x6 + + + PINCFG_7 + 4-pin push-pull mode (inverted outputs) + 0x7 + + + + + + + MCFGR2 + Master Configuration Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSIDLE + Bus Idle Timeout + 0 + 12 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + MCFGR3 + Master Configuration Register 3 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PINLOW + Pin Low Timeout + 8 + 12 + read-write + + + + + MDMR + Master Data Match Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 8 + read-write + + + MATCH1 + Match 1 Value + 16 + 8 + read-write + + + + + MCCR0 + Master Clock Configuration Register 0 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MCCR1 + Master Clock Configuration Register 1 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MFCR + Master FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 2 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 2 + read-write + + + + + MFSR + Master FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 3 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 3 + read-only + + + + + MTDR + Master Transmit Data Register + 0x60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + CMD + Command Data + 8 + 3 + write-only + + + CMD_0 + Transmit DATA[7:0] + 0 + + + CMD_1 + Receive (DATA[7:0] + 1) bytes + 0x1 + + + CMD_2 + Generate STOP condition + 0x2 + + + CMD_3 + Receive and discard (DATA[7:0] + 1) bytes + 0x3 + + + CMD_4 + Generate (repeated) START and transmit address in DATA[7:0] + 0x4 + + + CMD_5 + Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + 0x5 + + + CMD_6 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + 0x6 + + + CMD_7 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + 0x7 + + + + + + + MRDR + Master Receive Data Register + 0x70 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + Receive FIFO is not empty + 0 + + + RXEMPTY_1 + Receive FIFO is empty + 0x1 + + + + + + + SCR + Slave Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEN + Slave Enable + 0 + 1 + read-write + + + SEN_0 + I2C Slave mode is disabled + 0 + + + SEN_1 + I2C Slave mode is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Slave mode logic is not reset + 0 + + + RST_1 + Slave mode logic is reset + 0x1 + + + + + FILTEN + Filter Enable + 4 + 1 + read-write + + + FILTEN_0 + Disable digital filter and output delay counter for slave mode + 0 + + + FILTEN_1 + Enable digital filter and output delay counter for slave mode + 0x1 + + + + + FILTDZ + Filter Doze Enable + 5 + 1 + read-write + + + FILTDZ_0 + Filter remains enabled in Doze mode + 0 + + + FILTDZ_1 + Filter is disabled in Doze mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit Data Register is now empty + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive Data Register is now empty + 0x1 + + + + + + + SSR + Slave Status Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + AVF + Address Valid Flag + 2 + 1 + read-only + + + AVF_0 + Address Status Register is not valid + 0 + + + AVF_1 + Address Status Register is valid + 0x1 + + + + + TAF + Transmit ACK Flag + 3 + 1 + read-only + + + TAF_0 + Transmit ACK/NACK is not required + 0 + + + TAF_1 + Transmit ACK/NACK is required + 0x1 + + + + + RSF + Repeated Start Flag + 8 + 1 + read-write + oneToClear + + + RSF_0 + Slave has not detected a Repeated START condition + 0 + + + RSF_1 + Slave has detected a Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Slave has not detected a STOP condition + 0 + + + SDF_1 + Slave has detected a STOP condition + 0x1 + + + + + BEF + Bit Error Flag + 10 + 1 + read-write + oneToClear + + + BEF_0 + Slave has not detected a bit error + 0 + + + BEF_1 + Slave has detected a bit error + 0x1 + + + + + FEF + FIFO Error Flag + 11 + 1 + read-write + oneToClear + + + FEF_0 + FIFO underflow or overflow was not detected + 0 + + + FEF_1 + FIFO underflow or overflow was detected + 0x1 + + + + + AM0F + Address Match 0 Flag + 12 + 1 + read-only + + + AM0F_0 + Have not received an ADDR0 matching address + 0 + + + AM0F_1 + Have received an ADDR0 matching address + 0x1 + + + + + AM1F + Address Match 1 Flag + 13 + 1 + read-only + + + AM1F_0 + Have not received an ADDR1 or ADDR0/ADDR1 range matching address + 0 + + + AM1F_1 + Have received an ADDR1 or ADDR0/ADDR1 range matching address + 0x1 + + + + + GCF + General Call Flag + 14 + 1 + read-only + + + GCF_0 + Slave has not detected the General Call Address or the General Call Address is disabled + 0 + + + GCF_1 + Slave has detected the General Call Address + 0x1 + + + + + SARF + SMBus Alert Response Flag + 15 + 1 + read-only + + + SARF_0 + SMBus Alert Response is disabled or not detected + 0 + + + SARF_1 + SMBus Alert Response is enabled and detected + 0x1 + + + + + SBF + Slave Busy Flag + 24 + 1 + read-only + + + SBF_0 + I2C Slave is idle + 0 + + + SBF_1 + I2C Slave is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + SIER + Slave Interrupt Enable Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + AVIE + Address Valid Interrupt Enable + 2 + 1 + read-write + + + AVIE_0 + Disabled + 0 + + + AVIE_1 + Enabled + 0x1 + + + + + TAIE + Transmit ACK Interrupt Enable + 3 + 1 + read-write + + + TAIE_0 + Disabled + 0 + + + TAIE_1 + Enabled + 0x1 + + + + + RSIE + Repeated Start Interrupt Enable + 8 + 1 + read-write + + + RSIE_0 + Disabled + 0 + + + RSIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + BEIE + Bit Error Interrupt Enable + 10 + 1 + read-write + + + BEIE_0 + Disabled + 0 + + + BEIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 11 + 1 + read-write + + + FEIE_0 + Disabled + 0 + + + FEIE_1 + Enabled + 0x1 + + + + + AM0IE + Address Match 0 Interrupt Enable + 12 + 1 + read-write + + + AM0IE_0 + Enabled + 0 + + + AM0IE_1 + Disabled + 0x1 + + + + + AM1F + Address Match 1 Interrupt Enable + 13 + 1 + read-write + + + AM1F_0 + Disabled + 0 + + + AM1F_1 + Enabled + 0x1 + + + + + GCIE + General Call Interrupt Enable + 14 + 1 + read-write + + + GCIE_0 + Disabled + 0 + + + GCIE_1 + Enabled + 0x1 + + + + + SARIE + SMBus Alert Response Interrupt Enable + 15 + 1 + read-write + + + SARIE_0 + Disabled + 0 + + + SARIE_1 + Enabled + 0x1 + + + + + + + SDER + Slave DMA Enable Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + AVDE + Address Valid DMA Enable + 2 + 1 + read-write + + + AVDE_0 + DMA request is disabled + 0 + + + AVDE_1 + DMA request is enabled + 0x1 + + + + + + + SCFGR1 + Slave Configuration Register 1 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADRSTALL + Address SCL Stall + 0 + 1 + read-write + + + ADRSTALL_0 + Clock stretching is disabled + 0 + + + ADRSTALL_1 + Clock stretching is enabled + 0x1 + + + + + RXSTALL + RX SCL Stall + 1 + 1 + read-write + + + RXSTALL_0 + Clock stretching is disabled + 0 + + + RXSTALL_1 + Clock stretching is enabled + 0x1 + + + + + TXDSTALL + TX Data SCL Stall + 2 + 1 + read-write + + + TXDSTALL_0 + Clock stretching is disabled + 0 + + + TXDSTALL_1 + Clock stretching is enabled + 0x1 + + + + + ACKSTALL + ACK SCL Stall + 3 + 1 + read-write + + + ACKSTALL_0 + Clock stretching is disabled + 0 + + + ACKSTALL_1 + Clock stretching is enabled + 0x1 + + + + + GCEN + General Call Enable + 8 + 1 + read-write + + + GCEN_0 + General Call address is disabled + 0 + + + GCEN_1 + General Call address is enabled + 0x1 + + + + + SAEN + SMBus Alert Enable + 9 + 1 + read-write + + + SAEN_0 + Disables match on SMBus Alert + 0 + + + SAEN_1 + Enables match on SMBus Alert + 0x1 + + + + + TXCFG + Transmit Flag Configuration + 10 + 1 + read-write + + + TXCFG_0 + Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + 0 + + + TXCFG_1 + Transmit Data Flag will assert whenever the Transmit Data register is empty + 0x1 + + + + + RXCFG + Receive Data Configuration + 11 + 1 + read-write + + + RXCFG_0 + Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + 0 + + + RXCFG_1 + Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + 0x1 + + + + + IGNACK + Ignore NACK + 12 + 1 + read-write + + + IGNACK_0 + Slave will end transfer when NACK is detected + 0 + + + IGNACK_1 + Slave will not end transfer when NACK detected + 0x1 + + + + + HSMEN + High Speed Mode Enable + 13 + 1 + read-write + + + HSMEN_0 + Disables detection of HS-mode master code + 0 + + + HSMEN_1 + Enables detection of HS-mode master code + 0x1 + + + + + ADDRCFG + Address Configuration + 16 + 3 + read-write + + + ADDRCFG_0 + Address match 0 (7-bit) + 0 + + + ADDRCFG_1 + Address match 0 (10-bit) + 0x1 + + + ADDRCFG_2 + Address match 0 (7-bit) or Address match 1 (7-bit) + 0x2 + + + ADDRCFG_3 + Address match 0 (10-bit) or Address match 1 (10-bit) + 0x3 + + + ADDRCFG_4 + Address match 0 (7-bit) or Address match 1 (10-bit) + 0x4 + + + ADDRCFG_5 + Address match 0 (10-bit) or Address match 1 (7-bit) + 0x5 + + + ADDRCFG_6 + From Address match 0 (7-bit) to Address match 1 (7-bit) + 0x6 + + + ADDRCFG_7 + From Address match 0 (10-bit) to Address match 1 (10-bit) + 0x7 + + + + + + + SCFGR2 + Slave Configuration Register 2 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKHOLD + Clock Hold Time + 0 + 4 + read-write + + + DATAVD + Data Valid Delay + 8 + 6 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + SAMR + Slave Address Match Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + Address 0 Value + 1 + 10 + read-write + + + ADDR1 + Address 1 Value + 17 + 10 + read-write + + + + + SASR + Slave Address Status Register + 0x150 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + RADDR + Received Address + 0 + 11 + read-only + + + ANV + Address Not Valid + 14 + 1 + read-only + + + ANV_0 + Received Address (RADDR) is valid + 0 + + + ANV_1 + Received Address (RADDR) is not valid + 0x1 + + + + + + + STAR + Slave Transmit ACK Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXNACK + Transmit NACK + 0 + 1 + read-write + + + TXNACK_0 + Write a Transmit ACK for each received word + 0 + + + TXNACK_1 + Write a Transmit NACK for each received word + 0x1 + + + + + + + STDR + Slave Transmit Data Register + 0x160 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + + + SRDR + Slave Receive Data Register + 0x170 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + The Receive Data Register is not empty + 0 + + + RXEMPTY_1 + The Receive Data Register is empty + 0x1 + + + + + SOF + Start Of Frame + 15 + 1 + read-only + + + SOF_0 + Indicates this is not the first data word since a (repeated) START or STOP condition + 0 + + + SOF_1 + Indicates this is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + + + LPI2C2 + LPI2C + LPI2C + 0x403F4000 + + 0 + 0x174 + registers + + + LPI2C2 + 29 + + + + LPI2C3 + LPI2C + LPI2C + 0x403F8000 + + 0 + 0x174 + registers + + + LPI2C3 + 30 + + + + LPI2C4 + LPI2C + LPI2C + 0x403FC000 + + 0 + 0x174 + registers + + + LPI2C4 + 31 + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xFAC + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + DISFOLD_0 + Normal operation. + 0 + + + + + FPEXCODIS + Disables FPU exception outputs. + 10 + 1 + read-write + + + FPEXCODIS_0 + Normal operation. + 0 + + + FPEXCODIS_1 + FPU exception outputs are disabled. + 0x1 + + + + + DISRAMODE + Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. + 11 + 1 + read-write + + + DISRAMODE_0 + Normal operation. + 0 + + + DISRAMODE_1 + Dynamic disabled. + 0x1 + + + + + DISITMATBFLUSH + Disables ITM and DWT ATB flush. + 12 + 1 + read-write + + + DISITMATBFLUSH_1 + ITM and DWT ATB flush disabled, this bit is always 1. + 0x1 + + + + + DISBTACREAD + Disables BTAC read. + 13 + 1 + read-write + + + DISBTACREAD_0 + Normal operation. + 0 + + + DISBTACREAD_1 + BTAC is not used and only static branch prediction can occur. + 0x1 + + + + + DISBTACALLOC + Disables BTAC allocate. + 14 + 1 + read-write + + + DISBTACALLOC_0 + Normal operation. + 0 + + + DISBTACALLOC_1 + No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. + 0x1 + + + + + DISCRITAXIRUR + Disables critical AXI Read-Under-Read. + 15 + 1 + read-write + + + DISCRITAXIRUR_0 + Normal operation. + 0 + + + DISCRITAXIRUR_1 + An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. + 0x1 + + + + + DISDI + Disables dual-issued. + 16 + 5 + read-write + + + DISDI_0 + Normal operation. + 0 + + + DISDI_1 + Nothing can be dual-issued when this instruction type is in channel 0. + 0x1 + + + + + DISISSCH1 + Disables dual-issued. + 21 + 5 + read-write + + + DISISSCH1_0 + Normal operation. + 0 + + + DISISSCH1_1 + Nothing can be dual-issued when this instruction type is in channel 1. + 0x1 + + + + + DISDYNADD + Disables dynamic allocation of ADD and SUB instructions + 26 + 1 + read-write + + + DISDYNADD_0 + Normal operation. Some ADD and SUB instrctions are resolved in EX1. + 0 + + + DISDYNADD_1 + All ADD and SUB instructions are resolved in EX2. + 0x1 + + + + + DISCRITAXIRUW + Disables critical AXI read-under-write + 27 + 1 + read-write + + + DISCRITAXIRUW_0 + Normal operation. This is backwards compatible with r0. + 0 + + + DISCRITAXIRUW_1 + AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. + 0x1 + + + + + DISFPUISSOPT + Disables critical AXI read-under-write + 28 + 1 + read-write + + + DISFPUISSOPT_0 + Normal operation. + 0 + + + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + ARCHITECTURE + ARCHITECTURE + 16 + 4 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + Indicates whether there are preempted active exceptions + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + read-only + + + ISRPENDING + Interrupt pending flag, excluding NMI and Faults + 22 + 1 + read-only + + + ISRPENDING_0 + No external interrupt pending. + 0 + + + ISRPENDING_1 + External interrupt pending. + 0x1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Writing 1 to this bit causes a local system reset + 0 + 1 + write-only + + + VECTRESET_0 + No change + 0 + + + VECTRESET_1 + Causes a local system reset + 0x1 + + + + + VECTCLRACTIVE + Writing 1 to this bit clears all active state information for fixed and configurable exceptions. + 1 + 1 + write-only + + + VECTCLRACTIVE_0 + No change + 0 + + + VECTCLRACTIVE_1 + Clears all active state information for fixed and configurable exceptions + 0x1 + + + + + SYSRESETREQ + System reset request + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + Data endianness + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + NONBASETHRDENA + Indicates how the processor enters Thread mode + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + DC + Enables L1 data cache. + 16 + 1 + read-write + + + DC_0 + L1 data cache disabled + 0 + + + DC_1 + L1 data cache enabled + 0x1 + + + + + IC + Enables L1 instruction cache. + 17 + 1 + read-write + + + IC_0 + L1 instruction cache disabled + 0 + + + IC_1 + L1 instruction cache enabled + 0x1 + + + + + BP + Always reads-as-one. It indicates branch prediction is enabled. + 18 + 1 + read-only + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + SVCall active bit + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + Debug monitor active bit + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + PendSV exception active bit + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + MemManage fault occurred during floating-point lazy state preservation + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + Instruction bus error + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + Precise data bus error + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + Bus fault occurred during floating-point lazy state preservation + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + No coprocessor UsageFault + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + Indicates a BusFault on a vector table read during exception processing. + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. + 31 + 1 + read-write + + + DEBUGEVT_0 + No Debug event has occurred. + 0 + + + DEBUGEVT_1 + Debug event has occurred. The Debug Fault Status Register has been updated. + 0x1 + + + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + Debug event generated by BKPT instruction execution or a breakpoint match in FPB + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + Debug event generated by the DWT + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + Indicates triggering of a Vector catch + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + Debug event generated because of the assertion of an external debug request + 4 + 1 + read-write + + + EXTERNAL_0 + No external debug request debug event + 0 + + + EXTERNAL_1 + External debug request debug event + 0x1 + + + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + ID_PFR0 + Processor Feature Register 0 + 0xD40 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATE0 + ARM instruction set support + 0 + 4 + read-only + + + STATE0_0 + ARMv7-M unused + 0 + + + STATE0_1 + ARMv7-M unused + 0x1 + + + STATE0_2 + ARMv7-M unused + 0x2 + + + STATE0_3 + Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. + 0x3 + + + + + STATE1 + Thumb instruction set support + 4 + 4 + read-only + + + STATE1_0 + The processor does not support the ARM instruction set. + 0 + + + STATE1_1 + ARMv7-M unused + 0x1 + + + + + STATE2 + ARMv7-M unused + 8 + 4 + read-only + + + STATE3 + ARMv7-M unused + 12 + 4 + read-only + + + + + ID_PFR1 + Processor Feature Register 1 + 0xD44 + 32 + read-only + 0 + 0xFFFFFFFF + + + PROGMODEL + M profile programmers' model + 8 + 4 + read-only + + + PROGMODEL_0 + ARMv7-M unused + 0 + + + PROGMODEL_2 + Two-stack programmers' model supported + 0x2 + + + + + + + ID_DFR0 + Debug Feature Register + 0xD48 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUGMODEL + Support for memory-mapped debug model for M profile processors + 20 + 4 + read-only + + + DEBUGMODEL_0 + Not supported + 0 + + + DEBUGMODEL_1 + Support for M profile Debug architecture, with memory-mapped access. + 0x1 + + + + + + + ID_AFR0 + Auxiliary Feature Register + 0xD4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IMPLEMENTATION_DEFINED0 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 0 + 4 + read-only + + + IMPLEMENTATION_DEFINED1 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 4 + 4 + read-only + + + IMPLEMENTATION_DEFINED2 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 8 + 4 + read-only + + + IMPLEMENTATION_DEFINED3 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 12 + 4 + read-only + + + + + ID_MMFR0 + Memory Model Feature Register 0 + 0xD50 + 32 + read-only + 0 + 0xFFFFFFFF + + + PMSASUPPORT + Indicates support for a PMSA + 4 + 4 + read-only + + + PMSASUPPORT_0 + Not supported + 0 + + + PMSASUPPORT_1 + ARMv7-M unused + 0x1 + + + PMSASUPPORT_2 + ARMv7-M unused + 0x2 + + + PMSASUPPORT_3 + PMSAv7, providing support for a base region and subregions. + 0x3 + + + + + OUTERMOST_SHAREABILITY + Indicates the outermost shareability domain implemented + 8 + 4 + read-only + + + OUTERMOST_SHAREABILITY_0 + Implemented as Non-cacheable + 0 + + + OUTERMOST_SHAREABILITY_1 + ARMv7-M unused + 0x1 + + + OUTERMOST_SHAREABILITY_2 + ARMv7-M unused + 0x2 + + + OUTERMOST_SHAREABILITY_3 + ARMv7-M unused + 0x3 + + + OUTERMOST_SHAREABILITY_4 + ARMv7-M unused + 0x4 + + + OUTERMOST_SHAREABILITY_5 + ARMv7-M unused + 0x5 + + + OUTERMOST_SHAREABILITY_6 + ARMv7-M unused + 0x6 + + + OUTERMOST_SHAREABILITY_7 + ARMv7-M unused + 0x7 + + + OUTERMOST_SHAREABILITY_8 + ARMv7-M unused + 0x8 + + + OUTERMOST_SHAREABILITY_9 + ARMv7-M unused + 0x9 + + + OUTERMOST_SHAREABILITY_10 + ARMv7-M unused + 0xA + + + OUTERMOST_SHAREABILITY_11 + ARMv7-M unused + 0xB + + + OUTERMOST_SHAREABILITY_12 + ARMv7-M unused + 0xC + + + OUTERMOST_SHAREABILITY_13 + ARMv7-M unused + 0xD + + + OUTERMOST_SHAREABILITY_14 + ARMv7-M unused + 0xE + + + OUTERMOST_SHAREABILITY_15 + Shareability ignored. + 0xF + + + + + SHAREABILITY_LEVELS + Indicates the number of shareability levels implemented + 12 + 4 + read-only + + + SHAREABILITY_LEVELS_0 + One level of shareability implemented + 0 + + + SHAREABILITY_LEVELS_1 + ARMv7-M unused + 0x1 + + + + + TCM_SUPPORT + Indicates the support for Tightly Coupled Memory + 16 + 4 + read-only + + + TCM_SUPPORT_0 + No tightly coupled memories implemented. + 0 + + + TCM_SUPPORT_1 + Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. + 0x1 + + + TCM_SUPPORT_2 + ARMv7-M unused + 0x2 + + + + + AUXILIARY_REGISTERS + Indicates the support for Auxiliary registers + 20 + 4 + read-only + + + AUXILIARY_REGISTERS_0 + Not supported + 0 + + + AUXILIARY_REGISTERS_1 + Support for Auxiliary Control Register only. + 0x1 + + + AUXILIARY_REGISTERS_2 + ARMv7-M unused + 0x2 + + + + + + + ID_MMFR1 + Memory Model Feature Register 1 + 0xD54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR1 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_MMFR2 + Memory Model Feature Register 2 + 0xD58 + 32 + read-only + 0 + 0xFFFFFFFF + + + WFI_STALL + Indicates the support for Wait For Interrupt (WFI) stalling + 24 + 4 + read-only + + + WFI_STALL_0 + Not supported + 0 + + + WFI_STALL_1 + Support for WFI stalling + 0x1 + + + + + + + ID_MMFR3 + Memory Model Feature Register 3 + 0xD5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR3 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_ISAR0 + Instruction Set Attributes Register 0 + 0xD60 + 32 + read-only + 0 + 0xFFFFFFFF + + + BITCOUNT_INSTRS + Indicates the supported Bit Counting instructions + 4 + 4 + read-only + + + BITCOUNT_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITCOUNT_INSTRS_1 + Adds support for the CLZ instruction + 0x1 + + + + + BITFIELD_INSTRS + Indicates the supported BitField instructions + 8 + 4 + read-only + + + BITFIELD_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITFIELD_INSTRS_1 + Adds support for the BFC, BFI, SBFX, and UBFX instructions + 0x1 + + + + + CMPBRANCH_INSTRS + Indicates the supported combined Compare and Branch instructions + 12 + 4 + read-only + + + CMPBRANCH_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + CMPBRANCH_INSTRS_1 + Adds support for the CBNZ and CBZ instructions + 0x1 + + + + + COPROC_INSTRS + Indicates the supported Coprocessor instructions + 16 + 4 + read-only + + + COPROC_INSTRS_0 + None supported, except for separately attributed architectures, for example the Floating-point extension + 0 + + + COPROC_INSTRS_1 + Adds support for generic CDP, LDC, MCR, MRC, and STC instructions + 0x1 + + + COPROC_INSTRS_2 + As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions + 0x2 + + + COPROC_INSTRS_3 + As for 2, and adds support for generic MCRR and MRRC instructions + 0x3 + + + COPROC_INSTRS_4 + As for 3, and adds support for generic MCRR2 and MRRC2 instructions + 0x4 + + + + + DEBUG_INSTRS + Indicates the supported Debug instructions + 20 + 4 + read-only + + + DEBUG_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DEBUG_INSTRS_1 + Adds support for the BKPT instruction + 0x1 + + + + + DIVIDE_INSTRS + Indicates the supported Divide instructions + 24 + 4 + read-only + + + DIVIDE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DIVIDE_INSTRS_1 + Adds support for the SDIV and UDIV instructions + 0x1 + + + + + + + ID_ISAR1 + Instruction Set Attributes Register 1 + 0xD64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EXTEND_INSTRS + Indicates the supported Extend instructions + 12 + 4 + read-only + + + EXTEND_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + EXTEND_INSTRS_1 + Adds support for the SXTB, SXTH, UXTB, and UXTH instructions + 0x1 + + + EXTEND_INSTRS_2 + As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions + 0x2 + + + + + IFTHEN_INSTRS + Indicates the supported IfThen instructions + 16 + 4 + read-only + + + IFTHEN_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IFTHEN_INSTRS_1 + Adds support for the IT instructions, and for the IT bits in the PSRs + 0x1 + + + + + IMMEDIATE_INSTRS + Indicates the support for data-processing instructions with long immediate + 20 + 4 + read-only + + + IMMEDIATE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IMMEDIATE_INSTRS_1 + Adds support for the ADDW, MOVW, MOVT, and SUBW instructions + 0x1 + + + + + INTERWORK_INSTRS + Indicates the supported Interworking instructions + 24 + 4 + read-only + + + INTERWORK_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + INTERWORK_INSTRS_1 + Adds support for the BX instruction, and the T bit in the PSR + 0x1 + + + INTERWORK_INSTRS_2 + As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior + 0x2 + + + INTERWORK_INSTRS_3 + ARMv7-M unused + 0x3 + + + + + + + ID_ISAR2 + Instruction Set Attributes Register 2 + 0xD68 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOADSTORE_INSTRS + Indicates the supported additional load and store instructions + 0 + 4 + read-only + + + LOADSTORE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + LOADSTORE_INSTRS_1 + Adds support for the LDRD and STRD instructions + 0x1 + + + + + MEMHINT_INSTRS + Indicates the supported Memory Hint instructions + 4 + 4 + read-only + + + MEMHINT_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + MEMHINT_INSTRS_1 + Adds support for the PLD instruction, ARMv7-M unused. + 0x1 + + + MEMHINT_INSTRS_2 + As for 1, ARMv7-M unused. + 0x2 + + + MEMHINT_INSTRS_3 + As for 1 or 2, and adds support for the PLI instruction. + 0x3 + + + + + MULTIACCESSINT_INSTRS + Indicates the support for multi-access interruptible instructions + 8 + 4 + read-only + + + MULTIACCESSINT_INSTRS_0 + None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. + 0 + + + MULTIACCESSINT_INSTRS_1 + LDM and STM instructions are restartable. + 0x1 + + + MULTIACCESSINT_INSTRS_2 + LDM and STM instructions are continuable. + 0x2 + + + + + MULT_INSTRS + Indicates the supported additional Multiply instructions + 12 + 4 + read-only + + + MULT_INSTRS_0 + None supported. This means only MUL is supported. ARMv7-M unused. + 0 + + + MULT_INSTRS_1 + Adds support for the MLA instruction, ARMv7-M unused. + 0x1 + + + MULT_INSTRS_2 + As for 1, and adds support for the MLS instruction. + 0x2 + + + + + MULTS_INSTRS + Indicates the supported advanced signed Multiply instructions + 16 + 4 + read-only + + + MULTS_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTS_INSTRS_1 + Adds support for the SMULL and SMLAL instructions + 0x1 + + + MULTS_INSTRS_2 + As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. + 0x2 + + + MULTS_INSTRS_3 + As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. + 0x3 + + + + + MULTU_INSTRS + Indicates the supported advanced unsigned Multiply instructions + 20 + 4 + read-only + + + MULTU_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTU_INSTRS_1 + Adds support for the UMULL and UMLAL instructions. + 0x1 + + + MULTU_INSTRS_2 + As for 1, and adds support for the UMAAL instruction. + 0x2 + + + + + REVERSAL_INSTRS + Indicates the supported Reversal instructions + 28 + 4 + read-only + + + REVERSAL_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + REVERSAL_INSTRS_1 + Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. + 0x1 + + + REVERSAL_INSTRS_2 + As for 1, and adds support for the RBIT instruction. + 0x2 + + + + + + + ID_ISAR3 + Instruction Set Attributes Register 3 + 0xD6C + 32 + read-only + 0 + 0xFFFFFFFF + + + SATURATE_INSTRS + Indicates the supported Saturate instructions + 0 + 4 + read-only + + + SATURATE_INSTRS_0 + None supported + 0 + + + SATURATE_INSTRS_1 + Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. + 0x1 + + + + + SIMD_INSTRS + Indicates the supported SIMD instructions + 4 + 4 + read-only + + + SIMD_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SIMD_INSTRS_1 + Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. + 0x1 + + + SIMD_INSTRS_3 + As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. + 0x3 + + + + + SVC_INSTRS + Indicates the supported SVC instructions + 8 + 4 + read-only + + + SVC_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SVC_INSTRS_1 + Adds support for the SVC instruction. + 0x1 + + + + + SYNCHPRIM_INSTRS + Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives + 12 + 4 + read-only + + + TABBRANCH_INSTRS + Indicates the supported Table Branch instructions + 16 + 4 + read-only + + + TABBRANCH_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TABBRANCH_INSTRS_1 + Adds support for the TBB and TBH instructions. + 0x1 + + + + + THUMBCOPY_INSTRS + Indicates the supported non flag-setting MOV instructions + 20 + 4 + read-only + + + THUMBCOPY_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + THUMBCOPY_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + TRUENOP_INSTRS + Indicates the supported non flag-setting MOV instructions + 24 + 4 + read-only + + + TRUENOP_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TRUENOP_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + + + ID_ISAR4 + Instruction Set Attributes Register 4 + 0xD70 + 32 + read-only + 0 + 0xFFFFFFFF + + + UNPRIV_INSTRS + Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. + 0 + 4 + read-only + + + UNPRIV_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + UNPRIV_INSTRS_1 + Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. + 0x1 + + + UNPRIV_INSTRS_2 + As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. + 0x2 + + + + + WITHSHIFTS_INSTRS + Indicates the support for instructions with shifts + 4 + 4 + read-only + + + WITHSHIFTS_INSTRS_0 + Nonzero shifts supported only in MOV and shift instructions. + 0 + + + WITHSHIFTS_INSTRS_1 + Adds support for shifts of loads and stores over the range LSL 0-3. + 0x1 + + + WITHSHIFTS_INSTRS_3 + As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. + 0x3 + + + WITHSHIFTS_INSTRS_4 + ARMv7-M unused. + 0x4 + + + + + WRITEBACK_INSTRS + Indicates the support for Writeback addressing modes + 8 + 4 + read-only + + + WRITEBACK_INSTRS_0 + Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. + 0 + + + WRITEBACK_INSTRS_1 + Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. + 0x1 + + + + + BARRIER_INSTRS + Indicates the supported Barrier instructions + 16 + 4 + read-only + + + BARRIER_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + BARRIER_INSTRS_1 + Adds support for the DMB, DSB, and ISB barrier instructions. + 0x1 + + + + + SYNCHPRIM_INSTRS_FRAC + Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives + 20 + 4 + read-only + + + PSR_M_INSTRS + Indicates the supported M profile instructions to modify the PSRs + 24 + 4 + read-only + + + PSR_M_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + PSR_M_INSTRS_1 + Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. + 0x1 + + + + + + + CLIDR + Cache Level ID register + 0xD78 + 32 + read-only + 0 + 0xFFFFFFFF + + + CL1 + Indicate the type of cache implemented at level 1. + 0 + 3 + read-only + + + CL1_0 + No cache + 0 + + + CL1_1 + Instruction cache only + 0x1 + + + CL1_2 + Data cache only + 0x2 + + + CL1_3 + Separate instruction and data caches + 0x3 + + + CL1_4 + Unified cache + 0x4 + + + + + CL2 + Indicate the type of cache implemented at level 2. + 3 + 3 + read-only + + + CL2_0 + No cache + 0 + + + CL2_1 + Instruction cache only + 0x1 + + + CL2_2 + Data cache only + 0x2 + + + CL2_3 + Separate instruction and data caches + 0x3 + + + CL2_4 + Unified cache + 0x4 + + + + + CL3 + Indicate the type of cache implemented at level 3. + 6 + 3 + read-only + + + CL3_0 + No cache + 0 + + + CL3_1 + Instruction cache only + 0x1 + + + CL3_2 + Data cache only + 0x2 + + + CL3_3 + Separate instruction and data caches + 0x3 + + + CL3_4 + Unified cache + 0x4 + + + + + CL4 + Indicate the type of cache implemented at level 4. + 9 + 3 + read-only + + + CL4_0 + No cache + 0 + + + CL4_1 + Instruction cache only + 0x1 + + + CL4_2 + Data cache only + 0x2 + + + CL4_3 + Separate instruction and data caches + 0x3 + + + CL4_4 + Unified cache + 0x4 + + + + + CL5 + Indicate the type of cache implemented at level 5. + 12 + 3 + read-only + + + CL5_0 + No cache + 0 + + + CL5_1 + Instruction cache only + 0x1 + + + CL5_2 + Data cache only + 0x2 + + + CL5_3 + Separate instruction and data caches + 0x3 + + + CL5_4 + Unified cache + 0x4 + + + + + CL6 + Indicate the type of cache implemented at level 6. + 15 + 3 + read-only + + + CL6_0 + No cache + 0 + + + CL6_1 + Instruction cache only + 0x1 + + + CL6_2 + Data cache only + 0x2 + + + CL6_3 + Separate instruction and data caches + 0x3 + + + CL6_4 + Unified cache + 0x4 + + + + + CL7 + Indicate the type of cache implemented at level 7. + 18 + 3 + read-only + + + CL7_0 + No cache + 0 + + + CL7_1 + Instruction cache only + 0x1 + + + CL7_2 + Data cache only + 0x2 + + + CL7_3 + Separate instruction and data caches + 0x3 + + + CL7_4 + Unified cache + 0x4 + + + + + LOUIS + Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. + 21 + 3 + read-only + + + LOUIS_0 + 0 + 0 + + + LOUIS_1 + 1 + 0x1 + + + LOUIS_2 + 2 + 0x2 + + + LOUIS_3 + 3 + 0x3 + + + LOUIS_4 + 4 + 0x4 + + + LOUIS_5 + 5 + 0x5 + + + LOUIS_6 + 6 + 0x6 + + + LOUIS_7 + 7 + 0x7 + + + + + LOC + Level of Coherency for the cache hierarchy + 24 + 3 + read-only + + + LOC_0 + 0 + 0 + + + LOC_1 + 1 + 0x1 + + + LOC_2 + 2 + 0x2 + + + LOC_3 + 3 + 0x3 + + + LOC_4 + 4 + 0x4 + + + LOC_5 + 5 + 0x5 + + + LOC_6 + 6 + 0x6 + + + LOC_7 + 7 + 0x7 + + + + + LOU + Level of Unification for the cache hierarchy + 27 + 3 + read-only + + + LOU_0 + 0 + 0 + + + LOU_1 + 1 + 0x1 + + + LOU_2 + 2 + 0x2 + + + LOU_3 + 3 + 0x3 + + + LOU_4 + 4 + 0x4 + + + LOU_5 + 5 + 0x5 + + + LOU_6 + 6 + 0x6 + + + LOU_7 + 7 + 0x7 + + + + + + + CTR + Cache Type register + 0xD7C + 32 + read-only + 0x8000C000 + 0xFFFFFFFF + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. + 0 + 4 + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. + 16 + 4 + read-only + + + ERG + Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. + 20 + 4 + read-only + + + CWG + Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. + 24 + 4 + read-only + + + FORMAT + Indicates the implemented CTR format. + 29 + 3 + read-only + + + FORMAT_4 + ARMv7 format. + 0x4 + + + + + + + CCSIDR + Cache Size ID Register + 0xD80 + 32 + read-only + 0 + 0xFFFFFFFF + + + LINESIZE + (Log2(Number of words in cache line)) - 2. + 0 + 3 + read-only + + + LINESIZE_0 + The line length of 4 words. + 0 + + + LINESIZE_1 + The line length of 8 words. + 0x1 + + + LINESIZE_2 + The line length of 16 words. + 0x2 + + + LINESIZE_3 + The line length of 32 words. + 0x3 + + + LINESIZE_4 + The line length of 64 words. + 0x4 + + + LINESIZE_5 + The line length of 128 words. + 0x5 + + + LINESIZE_6 + The line length of 256 words. + 0x6 + + + LINESIZE_7 + The line length of 512 words. + 0x7 + + + + + ASSOCIATIVITY + (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. + 3 + 10 + read-only + + + NUMSETS + (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. + 13 + 15 + read-only + + + WA + Indicates whether the cache level supports write-allocation + 28 + 1 + read-only + + + WA_0 + Feature not supported + 0 + + + WA_1 + Feature supported + 0x1 + + + + + RA + Indicates whether the cache level supports read-allocation + 29 + 1 + read-only + + + RA_0 + Feature not supported + 0 + + + RA_1 + Feature supported + 0x1 + + + + + WB + Indicates whether the cache level supports write-back + 30 + 1 + read-only + + + WB_0 + Feature not supported + 0 + + + WB_1 + Feature supported + 0x1 + + + + + WT + Indicates whether the cache level supports write-through + 31 + 1 + read-only + + + WT_0 + Feature not supported + 0 + + + WT_1 + Feature supported + 0x1 + + + + + + + CSSELR + Cache Size Selection Register + 0xD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IND + Instruction not data bit + 0 + 1 + read-write + + + IND_0 + Data or unified cache. + 0 + + + IND_1 + Instruction cache. + 0x1 + + + + + LEVEL + Cache level of required cache + 1 + 3 + read-write + + + LEVEL_0 + Level 1 cache. + 0 + + + LEVEL_1 + Level 2 cache. + 0x1 + + + LEVEL_2 + Level 3 cache. + 0x2 + + + LEVEL_3 + Level 4 cache. + 0x3 + + + LEVEL_4 + Level 5 cache. + 0x4 + + + LEVEL_5 + Level 6 cache. + 0x5 + + + LEVEL_6 + Level 7 cache. + 0x6 + + + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CP0 + Access privileges for coprocessor 0. + 0 + 2 + read-write + + + CP0_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP0_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP0_3 + Full access. + 0x3 + + + + + CP1 + Access privileges for coprocessor 1. + 2 + 2 + read-write + + + CP1_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP1_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP1_3 + Full access. + 0x3 + + + + + CP2 + Access privileges for coprocessor 2. + 4 + 2 + read-write + + + CP2_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP2_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP2_3 + Full access. + 0x3 + + + + + CP3 + Access privileges for coprocessor 3. + 6 + 2 + read-write + + + CP3_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP3_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP3_3 + Full access. + 0x3 + + + + + CP4 + Access privileges for coprocessor 4. + 8 + 2 + read-write + + + CP4_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP4_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP4_3 + Full access. + 0x3 + + + + + CP5 + Access privileges for coprocessor 5. + 10 + 2 + read-write + + + CP5_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP5_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP5_3 + Full access. + 0x3 + + + + + CP6 + Access privileges for coprocessor 6. + 12 + 2 + read-write + + + CP6_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP6_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP6_3 + Full access. + 0x3 + + + + + CP7 + Access privileges for coprocessor 7. + 14 + 2 + read-write + + + CP7_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP7_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP7_3 + Full access. + 0x3 + + + + + CP10 + Access privileges for coprocessor 10. + 20 + 2 + read-write + + + CP10_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP10_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP10_3 + Full access. + 0x3 + + + + + CP11 + Access privileges for coprocessor 11. + 22 + 2 + read-write + + + CP11_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP11_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP11_3 + Full access. + 0x3 + + + + + + + STIR + Instruction cache invalidate all to Point of Unification (PoU) + 0xF00 + 32 + write-only + 0 + 0xFFFFFFFF + + + INTID + Indicates the interrupt to be triggered + 0 + 9 + write-only + + + + + ICIALLU + Instruction cache invalidate all to Point of Unification (PoU) + 0xF50 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIALLU + I-cache invalidate all to PoU + 0 + 32 + write-only + + + + + ICIMVAU + Instruction cache invalidate by address to PoU + 0xF58 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIMVAU + I-cache invalidate by MVA to PoU + 0 + 32 + write-only + + + + + DCIMVAC + Data cache invalidate by address to Point of Coherency (PoC) + 0xF5C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCIMVAC + D-cache invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCISW + Data cache invalidate by set/way + 0xF60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCISW + D-cache invalidate by set-way + 0 + 32 + write-only + + + + + DCCMVAU + Data cache by address to PoU + 0xF64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAU + D-cache clean by MVA to PoU + 0 + 32 + write-only + + + + + DCCMVAC + Data cache clean by address to PoC + 0xF68 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAC + D-cache clean by MVA to PoC + 0 + 32 + write-only + + + + + DCCSW + Data cache clean by set/way + 0xF6C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCSW + D-cache clean by set-way + 0 + 32 + write-only + + + + + DCCIMVAC + Data cache clean and invalidate by address to PoC + 0xF70 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCIMVAC + D-cache clean and invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCCISW + Data cache clean and invalidate by set/way + 0xF74 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCISW + D-cache clean and invalidate by set-way + 0 + 32 + write-only + + + + + CM7_ITCMCR + Instruction Tightly-Coupled Memory Control Register + 0xF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_DTCMCR + Data Tightly-Coupled Memory Control Register + 0xF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_AHBPCR + AHBP Control Register + 0xF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + AHBP enable. + 0 + 1 + read-write + + + EN_0 + AHBP disabled. When disabled all accesses are made to the AXIM interface. + 0 + + + EN_1 + AHBP enabled. + 0x1 + + + + + SZ + AHBP size. + 1 + 3 + read-only + + + SZ_0 + 0MB. AHBP disabled. + 0 + + + SZ_1 + 64MB. + 0x1 + + + SZ_2 + 128MB. + 0x2 + + + SZ_3 + 256MB. + 0x3 + + + SZ_4 + 512MB. + 0x4 + + + + + + + CM7_CACR + L1 Cache Control Register + 0xF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + SIWT + Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. + 0 + 1 + read-write + + + SIWT_0 + Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. + 0 + + + SIWT_1 + Normal Cacheable shared locations are treated as Write-Through. + 0x1 + + + + + ECCDIS + Enables ECC in the instruction and data cache. + 1 + 1 + read-write + + + ECCDIS_0 + Enables ECC in the instruction and data cache. + 0 + + + ECCDIS_1 + Disables ECC in the instruction and data cache. + 0x1 + + + + + FORCEWT + Enables Force Write-Through in the data cache. + 2 + 1 + read-write + + + FORCEWT_0 + Disables Force Write-Through. + 0 + + + FORCEWT_1 + Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. + 0x1 + + + + + + + CM7_AHBSCR + AHB Slave Control Register + 0xFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTL + AHBS prioritization control. + 0 + 2 + read-write + + + CTL_0 + AHBS access priority demoted. This is the reset value. + 0 + + + CTL_1 + Software access priority demoted. + 0x1 + + + CTL_2 + AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. + 0x2 + + + CTL_3 + AHBSPRI signal has control of access priority. + 0x3 + + + + + TPRI + Threshold execution priority for AHBS traffic demotion. + 2 + 9 + read-write + + + INITCOUNT + Fairness counter initialization value. + 11 + 5 + read-write + + + + + CM7_ABFSR + Auxiliary Bus Fault Status Register + 0xFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM + Asynchronous fault on ITCM interface. + 0 + 1 + read-write + + + DTCM + Asynchronous fault on DTCM interface. + 1 + 1 + read-write + + + AHBP + Asynchronous fault on AHBP interface. + 2 + 1 + read-write + + + AXIM + Asynchronous fault on AXIM interface. + 3 + 1 + read-write + + + EPPB + Asynchronous fault on EPPB interface. + 4 + 1 + read-write + + + AXIMTYPE + Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. + 8 + 2 + read-write + + + AXIMTYPE_0 + OKAY. + 0 + + + AXIMTYPE_1 + EXOKAY. + 0x1 + + + AXIMTYPE_2 + SLVERR. + 0x2 + + + AXIMTYPE_3 + DECERR. + 0x3 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + CTI0_ERROR + 17 + + + CTI1_ERROR + 18 + + + CORE + 19 + + + LPUART1 + 20 + + + LPUART2 + 21 + + + LPUART3 + 22 + + + LPUART4 + 23 + + + LPUART5 + 24 + + + LPUART6 + 25 + + + LPUART7 + 26 + + + LPUART8 + 27 + + + LPI2C1 + 28 + + + LPI2C2 + 29 + + + LPI2C3 + 30 + + + LPI2C4 + 31 + + + LPSPI1 + 32 + + + LPSPI2 + 33 + + + LPSPI3 + 34 + + + LPSPI4 + 35 + + + CAN1 + 36 + + + CAN2 + 37 + + + FLEXRAM + 38 + + + KPP + 39 + + + TSC_DIG + 40 + + + GPR_IRQ + 41 + + + LCDIF + 42 + + + CSI + 43 + + + PXP + 44 + + + WDOG2 + 45 + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + CSU + 49 + + + DCP + 50 + + + DCP_VMI + 51 + + + Reserved68 + 52 + + + TRNG + 53 + + + SJC + 54 + + + BEE + 55 + + + SAI1 + 56 + + + SAI2 + 57 + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + SPDIF + 60 + + + PMU_EVENT + 61 + + + Reserved78 + 62 + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + USB_PHY1 + 65 + + + USB_PHY2 + 66 + + + ADC1 + 67 + + + ADC2 + 68 + + + DCDC + 69 + + + Reserved86 + 70 + + + Reserved87 + 71 + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + FLEXIO1 + 90 + + + FLEXIO2 + 91 + + + WDOG1 + 92 + + + RTWDOG + 93 + + + EWM + 94 + + + CCM_1 + 95 + + + CCM_2 + 96 + + + GPC + 97 + + + SRC + 98 + + + Reserved115 + 99 + + + GPT1 + 100 + + + GPT2 + 101 + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + Reserved123 + 107 + + + SEMC + 109 + + + USDHC1 + 110 + + + USDHC2 + 111 + + + USB_OTG2 + 112 + + + USB_OTG1 + 113 + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + XBAR1_IRQ_0_1 + 116 + + + XBAR1_IRQ_2_3 + 117 + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + PIT + 122 + + + ACMP1 + 123 + + + ACMP2 + 124 + + + ACMP3 + 125 + + + ACMP4 + 126 + + + Reserved143 + 127 + + + Reserved144 + 128 + + + ENC1 + 129 + + + ENC2 + 130 + + + ENC3 + 131 + + + ENC4 + 132 + + + TMR1 + 133 + + + TMR2 + 134 + + + TMR3 + 135 + + + TMR4 + 136 + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER4 + Interrupt Set Enable Register n + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER4 + Interrupt Clear Enable Register n + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR4 + Interrupt Set Pending Register n + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR4 + Interrupt Clear Pending Register n + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR4 + Interrupt Active bit Register n + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register 0 + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of the INT_DMA0_DMA16 interrupt 0 + 4 + 4 + read-write + + + + + NVICIP1 + Interrupt Priority Register 1 + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of the INT_DMA1_DMA17 interrupt 1 + 4 + 4 + read-write + + + + + NVICIP2 + Interrupt Priority Register 2 + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of the INT_DMA2_DMA18 interrupt 2 + 4 + 4 + read-write + + + + + NVICIP3 + Interrupt Priority Register 3 + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of the INT_DMA3_DMA19 interrupt 3 + 4 + 4 + read-write + + + + + NVICIP4 + Interrupt Priority Register 4 + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of the INT_DMA4_DMA20 interrupt 4 + 4 + 4 + read-write + + + + + NVICIP5 + Interrupt Priority Register 5 + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of the INT_DMA5_DMA21 interrupt 5 + 4 + 4 + read-write + + + + + NVICIP6 + Interrupt Priority Register 6 + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of the INT_DMA6_DMA22 interrupt 6 + 4 + 4 + read-write + + + + + NVICIP7 + Interrupt Priority Register 7 + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of the INT_DMA7_DMA23 interrupt 7 + 4 + 4 + read-write + + + + + NVICIP8 + Interrupt Priority Register 8 + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of the INT_DMA8_DMA24 interrupt 8 + 4 + 4 + read-write + + + + + NVICIP9 + Interrupt Priority Register 9 + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of the INT_DMA9_DMA25 interrupt 9 + 4 + 4 + read-write + + + + + NVICIP10 + Interrupt Priority Register 10 + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of the INT_DMA10_DMA26 interrupt 10 + 4 + 4 + read-write + + + + + NVICIP11 + Interrupt Priority Register 11 + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of the INT_DMA11_DMA27 interrupt 11 + 4 + 4 + read-write + + + + + NVICIP12 + Interrupt Priority Register 12 + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of the INT_DMA12_DMA28 interrupt 12 + 4 + 4 + read-write + + + + + NVICIP13 + Interrupt Priority Register 13 + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of the INT_DMA13_DMA29 interrupt 13 + 4 + 4 + read-write + + + + + NVICIP14 + Interrupt Priority Register 14 + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of the INT_DMA14_DMA30 interrupt 14 + 4 + 4 + read-write + + + + + NVICIP15 + Interrupt Priority Register 15 + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of the INT_DMA15_DMA31 interrupt 15 + 4 + 4 + read-write + + + + + NVICIP16 + Interrupt Priority Register 16 + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of the INT_DMA_ERROR interrupt 16 + 4 + 4 + read-write + + + + + NVICIP17 + Interrupt Priority Register 17 + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of the INT_CTI0_ERROR interrupt 17 + 4 + 4 + read-write + + + + + NVICIP18 + Interrupt Priority Register 18 + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of the INT_CTI1_ERROR interrupt 18 + 4 + 4 + read-write + + + + + NVICIP19 + Interrupt Priority Register 19 + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of the INT_CORE interrupt 19 + 4 + 4 + read-write + + + + + NVICIP20 + Interrupt Priority Register 20 + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of the INT_LPUART1 interrupt 20 + 4 + 4 + read-write + + + + + NVICIP21 + Interrupt Priority Register 21 + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of the INT_LPUART2 interrupt 21 + 4 + 4 + read-write + + + + + NVICIP22 + Interrupt Priority Register 22 + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of the INT_LPUART3 interrupt 22 + 4 + 4 + read-write + + + + + NVICIP23 + Interrupt Priority Register 23 + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of the INT_LPUART4 interrupt 23 + 4 + 4 + read-write + + + + + NVICIP24 + Interrupt Priority Register 24 + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of the INT_LPUART5 interrupt 24 + 4 + 4 + read-write + + + + + NVICIP25 + Interrupt Priority Register 25 + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of the INT_LPUART6 interrupt 25 + 4 + 4 + read-write + + + + + NVICIP26 + Interrupt Priority Register 26 + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of the INT_LPUART7 interrupt 26 + 4 + 4 + read-write + + + + + NVICIP27 + Interrupt Priority Register 27 + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of the INT_LPUART8 interrupt 27 + 4 + 4 + read-write + + + + + NVICIP28 + Interrupt Priority Register 28 + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of the INT_LPI2C1 interrupt 28 + 4 + 4 + read-write + + + + + NVICIP29 + Interrupt Priority Register 29 + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of the INT_LPI2C2 interrupt 29 + 4 + 4 + read-write + + + + + NVICIP30 + Interrupt Priority Register 30 + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of the INT_LPI2C3 interrupt 30 + 4 + 4 + read-write + + + + + NVICIP31 + Interrupt Priority Register 31 + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of the INT_LPI2C4 interrupt 31 + 4 + 4 + read-write + + + + + NVICIP32 + Interrupt Priority Register 32 + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of the INT_LPSPI1 interrupt 32 + 4 + 4 + read-write + + + + + NVICIP33 + Interrupt Priority Register 33 + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of the INT_LPSPI2 interrupt 33 + 4 + 4 + read-write + + + + + NVICIP34 + Interrupt Priority Register 34 + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of the INT_LPSPI3 interrupt 34 + 4 + 4 + read-write + + + + + NVICIP35 + Interrupt Priority Register 35 + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of the INT_LPSPI4 interrupt 35 + 4 + 4 + read-write + + + + + NVICIP36 + Interrupt Priority Register 36 + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of the INT_CAN1 interrupt 36 + 4 + 4 + read-write + + + + + NVICIP37 + Interrupt Priority Register 37 + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of the INT_CAN2 interrupt 37 + 4 + 4 + read-write + + + + + NVICIP38 + Interrupt Priority Register 38 + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of the INT_FLEXRAM interrupt 38 + 4 + 4 + read-write + + + + + NVICIP39 + Interrupt Priority Register 39 + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of the INT_KPP interrupt 39 + 4 + 4 + read-write + + + + + NVICIP40 + Interrupt Priority Register 40 + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of the INT_TSC_DIG interrupt 40 + 4 + 4 + read-write + + + + + NVICIP41 + Interrupt Priority Register 41 + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of the INT_GPR_IRQ interrupt 41 + 4 + 4 + read-write + + + + + NVICIP42 + Interrupt Priority Register 42 + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of the INT_LCDIF interrupt 42 + 4 + 4 + read-write + + + + + NVICIP43 + Interrupt Priority Register 43 + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of the INT_CSI interrupt 43 + 4 + 4 + read-write + + + + + NVICIP44 + Interrupt Priority Register 44 + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of the INT_PXP interrupt 44 + 4 + 4 + read-write + + + + + NVICIP45 + Interrupt Priority Register 45 + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of the INT_WDOG2 interrupt 45 + 4 + 4 + read-write + + + + + NVICIP46 + Interrupt Priority Register 46 + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of the INT_SNVS_HP_WRAPPER interrupt 46 + 4 + 4 + read-write + + + + + NVICIP47 + Interrupt Priority Register 47 + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47 + 4 + 4 + read-write + + + + + NVICIP48 + Interrupt Priority Register 48 + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of the INT_SNVS_LP_WRAPPER interrupt 48 + 4 + 4 + read-write + + + + + NVICIP49 + Interrupt Priority Register 49 + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of the INT_CSU interrupt 49 + 4 + 4 + read-write + + + + + NVICIP50 + Interrupt Priority Register 50 + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of the INT_DCP interrupt 50 + 4 + 4 + read-write + + + + + NVICIP51 + Interrupt Priority Register 51 + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of the INT_DCP_VMI interrupt 51 + 4 + 4 + read-write + + + + + NVICIP52 + Interrupt Priority Register 52 + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of the INT_Reserved68 interrupt 52 + 4 + 4 + read-write + + + + + NVICIP53 + Interrupt Priority Register 53 + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of the INT_TRNG interrupt 53 + 4 + 4 + read-write + + + + + NVICIP54 + Interrupt Priority Register 54 + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of the INT_SJC interrupt 54 + 4 + 4 + read-write + + + + + NVICIP55 + Interrupt Priority Register 55 + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of the INT_BEE interrupt 55 + 4 + 4 + read-write + + + + + NVICIP56 + Interrupt Priority Register 56 + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of the INT_SAI1 interrupt 56 + 4 + 4 + read-write + + + + + NVICIP57 + Interrupt Priority Register 57 + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of the INT_SAI2 interrupt 57 + 4 + 4 + read-write + + + + + NVICIP58 + Interrupt Priority Register 58 + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of the INT_SAI3_RX interrupt 58 + 4 + 4 + read-write + + + + + NVICIP59 + Interrupt Priority Register 59 + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of the INT_SAI3_TX interrupt 59 + 4 + 4 + read-write + + + + + NVICIP60 + Interrupt Priority Register 60 + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of the INT_SPDIF interrupt 60 + 4 + 4 + read-write + + + + + NVICIP61 + Interrupt Priority Register 61 + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of the INT_PMU_EVENT interrupt 61 + 4 + 4 + read-write + + + + + NVICIP62 + Interrupt Priority Register 62 + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of the INT_Reserved78 interrupt 62 + 4 + 4 + read-write + + + + + NVICIP63 + Interrupt Priority Register 63 + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of the INT_TEMP_LOW_HIGH interrupt 63 + 4 + 4 + read-write + + + + + NVICIP64 + Interrupt Priority Register 64 + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of the INT_TEMP_PANIC interrupt 64 + 4 + 4 + read-write + + + + + NVICIP65 + Interrupt Priority Register 65 + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of the INT_USB_PHY1 interrupt 65 + 4 + 4 + read-write + + + + + NVICIP66 + Interrupt Priority Register 66 + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of the INT_USB_PHY2 interrupt 66 + 4 + 4 + read-write + + + + + NVICIP67 + Interrupt Priority Register 67 + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of the INT_ADC1 interrupt 67 + 4 + 4 + read-write + + + + + NVICIP68 + Interrupt Priority Register 68 + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of the INT_ADC2 interrupt 68 + 4 + 4 + read-write + + + + + NVICIP69 + Interrupt Priority Register 69 + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of the INT_DCDC interrupt 69 + 4 + 4 + read-write + + + + + NVICIP70 + Interrupt Priority Register 70 + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of the INT_Reserved86 interrupt 70 + 4 + 4 + read-write + + + + + NVICIP71 + Interrupt Priority Register 71 + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of the INT_Reserved87 interrupt 71 + 4 + 4 + read-write + + + + + NVICIP72 + Interrupt Priority Register 72 + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of the INT_GPIO1_INT0 interrupt 72 + 4 + 4 + read-write + + + + + NVICIP73 + Interrupt Priority Register 73 + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of the INT_GPIO1_INT1 interrupt 73 + 4 + 4 + read-write + + + + + NVICIP74 + Interrupt Priority Register 74 + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of the INT_GPIO1_INT2 interrupt 74 + 4 + 4 + read-write + + + + + NVICIP75 + Interrupt Priority Register 75 + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of the INT_GPIO1_INT3 interrupt 75 + 4 + 4 + read-write + + + + + NVICIP76 + Interrupt Priority Register 76 + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of the INT_GPIO1_INT4 interrupt 76 + 4 + 4 + read-write + + + + + NVICIP77 + Interrupt Priority Register 77 + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of the INT_GPIO1_INT5 interrupt 77 + 4 + 4 + read-write + + + + + NVICIP78 + Interrupt Priority Register 78 + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of the INT_GPIO1_INT6 interrupt 78 + 4 + 4 + read-write + + + + + NVICIP79 + Interrupt Priority Register 79 + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of the INT_GPIO1_INT7 interrupt 79 + 4 + 4 + read-write + + + + + NVICIP80 + Interrupt Priority Register 80 + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of the INT_GPIO1_Combined_0_15 interrupt 80 + 4 + 4 + read-write + + + + + NVICIP81 + Interrupt Priority Register 81 + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of the INT_GPIO1_Combined_16_31 interrupt 81 + 4 + 4 + read-write + + + + + NVICIP82 + Interrupt Priority Register 82 + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of the INT_GPIO2_Combined_0_15 interrupt 82 + 4 + 4 + read-write + + + + + NVICIP83 + Interrupt Priority Register 83 + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of the INT_GPIO2_Combined_16_31 interrupt 83 + 4 + 4 + read-write + + + + + NVICIP84 + Interrupt Priority Register 84 + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of the INT_GPIO3_Combined_0_15 interrupt 84 + 4 + 4 + read-write + + + + + NVICIP85 + Interrupt Priority Register 85 + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of the INT_GPIO3_Combined_16_31 interrupt 85 + 4 + 4 + read-write + + + + + NVICIP86 + Interrupt Priority Register 86 + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of the INT_GPIO4_Combined_0_15 interrupt 86 + 4 + 4 + read-write + + + + + NVICIP87 + Interrupt Priority Register 87 + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of the INT_GPIO4_Combined_16_31 interrupt 87 + 4 + 4 + read-write + + + + + NVICIP88 + Interrupt Priority Register 88 + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of the INT_GPIO5_Combined_0_15 interrupt 88 + 4 + 4 + read-write + + + + + NVICIP89 + Interrupt Priority Register 89 + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of the INT_GPIO5_Combined_16_31 interrupt 89 + 4 + 4 + read-write + + + + + NVICIP90 + Interrupt Priority Register 90 + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of the INT_FLEXIO1 interrupt 90 + 4 + 4 + read-write + + + + + NVICIP91 + Interrupt Priority Register 91 + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of the INT_FLEXIO2 interrupt 91 + 4 + 4 + read-write + + + + + NVICIP92 + Interrupt Priority Register 92 + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of the INT_WDOG1 interrupt 92 + 4 + 4 + read-write + + + + + NVICIP93 + Interrupt Priority Register 93 + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of the INT_RTWDOG interrupt 93 + 4 + 4 + read-write + + + + + NVICIP94 + Interrupt Priority Register 94 + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of the INT_EWM interrupt 94 + 4 + 4 + read-write + + + + + NVICIP95 + Interrupt Priority Register 95 + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of the INT_CCM_1 interrupt 95 + 4 + 4 + read-write + + + + + NVICIP96 + Interrupt Priority Register 96 + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of the INT_CCM_2 interrupt 96 + 4 + 4 + read-write + + + + + NVICIP97 + Interrupt Priority Register 97 + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of the INT_GPC interrupt 97 + 4 + 4 + read-write + + + + + NVICIP98 + Interrupt Priority Register 98 + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of the INT_SRC interrupt 98 + 4 + 4 + read-write + + + + + NVICIP99 + Interrupt Priority Register 99 + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of the INT_Reserved115 interrupt 99 + 4 + 4 + read-write + + + + + NVICIP100 + Interrupt Priority Register 100 + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of the INT_GPT1 interrupt 100 + 4 + 4 + read-write + + + + + NVICIP101 + Interrupt Priority Register 101 + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of the INT_GPT2 interrupt 101 + 4 + 4 + read-write + + + + + NVICIP102 + Interrupt Priority Register 102 + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of the INT_PWM1_0 interrupt 102 + 4 + 4 + read-write + + + + + NVICIP103 + Interrupt Priority Register 103 + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of the INT_PWM1_1 interrupt 103 + 4 + 4 + read-write + + + + + NVICIP104 + Interrupt Priority Register 104 + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of the INT_PWM1_2 interrupt 104 + 4 + 4 + read-write + + + + + NVICIP105 + Interrupt Priority Register 105 + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of the INT_PWM1_3 interrupt 105 + 4 + 4 + read-write + + + + + NVICIP106 + Interrupt Priority Register 106 + 0x36A + 8 + read-write + 0 + 0xFF + + + PRI106 + Priority of the INT_PWM1_FAULT interrupt 106 + 4 + 4 + read-write + + + + + NVICIP107 + Interrupt Priority Register 107 + 0x36B + 8 + read-write + 0 + 0xFF + + + PRI107 + Priority of the INT_Reserved123 interrupt 107 + 4 + 4 + read-write + + + + + NVICIP108 + Interrupt Priority Register 108 + 0x36C + 8 + read-write + 0 + 0xFF + + + PRI108 + Priority of interrupt 108 + 4 + 4 + read-write + + + + + NVICIP109 + Interrupt Priority Register 109 + 0x36D + 8 + read-write + 0 + 0xFF + + + PRI109 + Priority of the INT_SEMC interrupt 109 + 4 + 4 + read-write + + + + + NVICIP110 + Interrupt Priority Register 110 + 0x36E + 8 + read-write + 0 + 0xFF + + + PRI110 + Priority of the INT_USDHC1 interrupt 110 + 4 + 4 + read-write + + + + + NVICIP111 + Interrupt Priority Register 111 + 0x36F + 8 + read-write + 0 + 0xFF + + + PRI111 + Priority of the INT_USDHC2 interrupt 111 + 4 + 4 + read-write + + + + + NVICIP112 + Interrupt Priority Register 112 + 0x370 + 8 + read-write + 0 + 0xFF + + + PRI112 + Priority of the INT_USB_OTG2 interrupt 112 + 4 + 4 + read-write + + + + + NVICIP113 + Interrupt Priority Register 113 + 0x371 + 8 + read-write + 0 + 0xFF + + + PRI113 + Priority of the INT_USB_OTG1 interrupt 113 + 4 + 4 + read-write + + + + + NVICIP114 + Interrupt Priority Register 114 + 0x372 + 8 + read-write + 0 + 0xFF + + + PRI114 + Priority of the INT_ENET interrupt 114 + 4 + 4 + read-write + + + + + NVICIP115 + Interrupt Priority Register 115 + 0x373 + 8 + read-write + 0 + 0xFF + + + PRI115 + Priority of the INT_ENET_1588_Timer interrupt 115 + 4 + 4 + read-write + + + + + NVICIP116 + Interrupt Priority Register 116 + 0x374 + 8 + read-write + 0 + 0xFF + + + PRI116 + Priority of the INT_XBAR1_IRQ_0_1 interrupt 116 + 4 + 4 + read-write + + + + + NVICIP117 + Interrupt Priority Register 117 + 0x375 + 8 + read-write + 0 + 0xFF + + + PRI117 + Priority of the INT_XBAR1_IRQ_2_3 interrupt 117 + 4 + 4 + read-write + + + + + NVICIP118 + Interrupt Priority Register 118 + 0x376 + 8 + read-write + 0 + 0xFF + + + PRI118 + Priority of the INT_ADC_ETC_IRQ0 interrupt 118 + 4 + 4 + read-write + + + + + NVICIP119 + Interrupt Priority Register 119 + 0x377 + 8 + read-write + 0 + 0xFF + + + PRI119 + Priority of the INT_ADC_ETC_IRQ1 interrupt 119 + 4 + 4 + read-write + + + + + NVICIP120 + Interrupt Priority Register 120 + 0x378 + 8 + read-write + 0 + 0xFF + + + PRI120 + Priority of the INT_ADC_ETC_IRQ2 interrupt 120 + 4 + 4 + read-write + + + + + NVICIP121 + Interrupt Priority Register 121 + 0x379 + 8 + read-write + 0 + 0xFF + + + PRI121 + Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 121 + 4 + 4 + read-write + + + + + NVICIP122 + Interrupt Priority Register 122 + 0x37A + 8 + read-write + 0 + 0xFF + + + PRI122 + Priority of the INT_PIT interrupt 122 + 4 + 4 + read-write + + + + + NVICIP123 + Interrupt Priority Register 123 + 0x37B + 8 + read-write + 0 + 0xFF + + + PRI123 + Priority of the INT_ACMP1 interrupt 123 + 4 + 4 + read-write + + + + + NVICIP124 + Interrupt Priority Register 124 + 0x37C + 8 + read-write + 0 + 0xFF + + + PRI124 + Priority of the INT_ACMP2 interrupt 124 + 4 + 4 + read-write + + + + + NVICIP125 + Interrupt Priority Register 125 + 0x37D + 8 + read-write + 0 + 0xFF + + + PRI125 + Priority of the INT_ACMP3 interrupt 125 + 4 + 4 + read-write + + + + + NVICIP126 + Interrupt Priority Register 126 + 0x37E + 8 + read-write + 0 + 0xFF + + + PRI126 + Priority of the INT_ACMP4 interrupt 126 + 4 + 4 + read-write + + + + + NVICIP127 + Interrupt Priority Register 127 + 0x37F + 8 + read-write + 0 + 0xFF + + + PRI127 + Priority of the INT_Reserved143 interrupt 127 + 4 + 4 + read-write + + + + + NVICIP128 + Interrupt Priority Register 128 + 0x380 + 8 + read-write + 0 + 0xFF + + + PRI128 + Priority of the INT_Reserved144 interrupt 128 + 4 + 4 + read-write + + + + + NVICIP129 + Interrupt Priority Register 129 + 0x381 + 8 + read-write + 0 + 0xFF + + + PRI129 + Priority of the INT_ENC1 interrupt 129 + 4 + 4 + read-write + + + + + NVICIP130 + Interrupt Priority Register 130 + 0x382 + 8 + read-write + 0 + 0xFF + + + PRI130 + Priority of the INT_ENC2 interrupt 130 + 4 + 4 + read-write + + + + + NVICIP131 + Interrupt Priority Register 131 + 0x383 + 8 + read-write + 0 + 0xFF + + + PRI131 + Priority of the INT_ENC3 interrupt 131 + 4 + 4 + read-write + + + + + NVICIP132 + Interrupt Priority Register 132 + 0x384 + 8 + read-write + 0 + 0xFF + + + PRI132 + Priority of the INT_ENC4 interrupt 132 + 4 + 4 + read-write + + + + + NVICIP133 + Interrupt Priority Register 133 + 0x385 + 8 + read-write + 0 + 0xFF + + + PRI133 + Priority of the INT_TMR1 interrupt 133 + 4 + 4 + read-write + + + + + NVICIP134 + Interrupt Priority Register 134 + 0x386 + 8 + read-write + 0 + 0xFF + + + PRI134 + Priority of the INT_TMR2 interrupt 134 + 4 + 4 + read-write + + + + + NVICIP135 + Interrupt Priority Register 135 + 0x387 + 8 + read-write + 0 + 0xFF + + + PRI135 + Priority of the INT_TMR3 interrupt 135 + 4 + 4 + read-write + + + + + NVICIP136 + Interrupt Priority Register 136 + 0x388 + 8 + read-write + 0 + 0xFF + + + PRI136 + Priority of the INT_TMR4 interrupt 136 + 4 + 4 + read-write + + + + + NVICIP137 + Interrupt Priority Register 137 + 0x389 + 8 + read-write + 0 + 0xFF + + + PRI137 + Priority of the INT_PWM2_0 interrupt 137 + 4 + 4 + read-write + + + + + NVICIP138 + Interrupt Priority Register 138 + 0x38A + 8 + read-write + 0 + 0xFF + + + PRI138 + Priority of the INT_PWM2_1 interrupt 138 + 4 + 4 + read-write + + + + + NVICIP139 + Interrupt Priority Register 139 + 0x38B + 8 + read-write + 0 + 0xFF + + + PRI139 + Priority of the INT_PWM2_2 interrupt 139 + 4 + 4 + read-write + + + + + NVICIP140 + Interrupt Priority Register 140 + 0x38C + 8 + read-write + 0 + 0xFF + + + PRI140 + Priority of the INT_PWM2_3 interrupt 140 + 4 + 4 + read-write + + + + + NVICIP141 + Interrupt Priority Register 141 + 0x38D + 8 + read-write + 0 + 0xFF + + + PRI141 + Priority of the INT_PWM2_FAULT interrupt 141 + 4 + 4 + read-write + + + + + NVICIP142 + Interrupt Priority Register 142 + 0x38E + 8 + read-write + 0 + 0xFF + + + PRI142 + Priority of the INT_PWM3_0 interrupt 142 + 4 + 4 + read-write + + + + + NVICIP143 + Interrupt Priority Register 143 + 0x38F + 8 + read-write + 0 + 0xFF + + + PRI143 + Priority of the INT_PWM3_1 interrupt 143 + 4 + 4 + read-write + + + + + NVICIP144 + Interrupt Priority Register 144 + 0x390 + 8 + read-write + 0 + 0xFF + + + PRI144 + Priority of the INT_PWM3_2 interrupt 144 + 4 + 4 + read-write + + + + + NVICIP145 + Interrupt Priority Register 145 + 0x391 + 8 + read-write + 0 + 0xFF + + + PRI145 + Priority of the INT_PWM3_3 interrupt 145 + 4 + 4 + read-write + + + + + NVICIP146 + Interrupt Priority Register 146 + 0x392 + 8 + read-write + 0 + 0xFF + + + PRI146 + Priority of the INT_PWM3_FAULT interrupt 146 + 4 + 4 + read-write + + + + + NVICIP147 + Interrupt Priority Register 147 + 0x393 + 8 + read-write + 0 + 0xFF + + + PRI147 + Priority of the INT_PWM4_0 interrupt 147 + 4 + 4 + read-write + + + + + NVICIP148 + Interrupt Priority Register 148 + 0x394 + 8 + read-write + 0 + 0xFF + + + PRI148 + Priority of the INT_PWM4_1 interrupt 148 + 4 + 4 + read-write + + + + + NVICIP149 + Interrupt Priority Register 149 + 0x395 + 8 + read-write + 0 + 0xFF + + + PRI149 + Priority of the INT_PWM4_2 interrupt 149 + 4 + 4 + read-write + + + + + NVICIP150 + Interrupt Priority Register 150 + 0x396 + 8 + read-write + 0 + 0xFF + + + PRI150 + Priority of the INT_PWM4_3 interrupt 150 + 4 + 4 + read-write + + + + + NVICIP151 + Interrupt Priority Register 151 + 0x397 + 8 + read-write + 0 + 0xFF + + + PRI151 + Priority of the INT_PWM4_FAULT interrupt 151 + 4 + 4 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + + + CM7_MCM + CM7_MCM + CM7_MCM + 0xE0080000 + + 0 + 0x1000 + registers + + + + ISCR + Interrupt Status and Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + WABS + Write Abort on Slave + 5 + 1 + read-write + oneToClear + + + noabort + No abort + 0 + + + abort + Abort + 0x1 + + + + + WABSO + Write Abort on Slave Overrun + 6 + 1 + read-only + + + no + No write abort overrun + 0 + + + yes + Write abort overrun occurred + 0x1 + + + + + FIOC + FPU Invalid Operation interrupt Status + 8 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + FDZC + FPU Divide-by-Zero Interrupt Status + 9 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + FOFC + FPU Overflow interrupt status + 10 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + FUFC + FPU Underflow Interrupt Status + 11 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + FIXC + FPU Inexact Interrupt Status + 12 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + FIDC + FPU Input Denormal Interrupt Status + 15 + 1 + read-only + + + No + No interrupt + 0 + + + Yes + Interrupt occured + 0x1 + + + + + WABE + TCM Write Abort Interrupt enable + 21 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FIOCE + FPU Invalid Operation Interrupt Enable + 24 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FDZCE + FPU Divide-by-Zero Interrupt Enable + 25 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FOFCE + FPU Overflow Interrupt Enable + 26 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FUFCE + FPU Underflow Interrupt Enable + 27 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FIXCE + FPU Inexact Interrupt Enable + 28 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + FIDCE + FPU Input Denormal Interrupt Enable + 31 + 1 + read-write + + + DISABLE + Disable interrupt + 0 + + + ENABLE + Enable interrupt + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/assets/MIMXRT105x_QuadSPI_4KB_SEC.FLM b/assets/MIMXRT105x_QuadSPI_4KB_SEC.FLM new file mode 100644 index 0000000..9c1917f Binary files /dev/null and b/assets/MIMXRT105x_QuadSPI_4KB_SEC.FLM differ diff --git a/board/clock_config.c b/board/clock_config.c index 2b11cda..3adc216 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v12.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 14.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -38,7 +38,7 @@ processor_version: 13.0.1 ******************************************************************************/ void BOARD_InitBootClocks(void) { - Board_BootClockPLL480MHz(); + Board_BootClockPLL600MHz(); } /******************************************************************************* @@ -47,6 +47,7 @@ void BOARD_InitBootClocks(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: Board_BootClockPLL600MHz +called_from_default_init: true outputs: - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} @@ -61,8 +62,8 @@ outputs: - {id: GPT1_ipg_clk_highfreq.outFreq, value: 5 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 5 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 33.60000125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 3 MHz} @@ -87,6 +88,10 @@ outputs: settings: - {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '1'} +- {id: CCM.LCDIF_PODF.scale, value: '5', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '1', locked: true} +- {id: CCM.LCDIF_PRE_CLK_SEL.sel, value: CCM_ANALOG.PLL5_MAIN_CLK} +- {id: CCM.LPI2C_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK} - {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '30'} - {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} @@ -101,6 +106,11 @@ settings: - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL5.denom, value: '960000'} +- {id: CCM_ANALOG.PLL5.div, value: '28'} +- {id: CCM_ANALOG.PLL5.num, value: '1'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* @@ -118,6 +128,14 @@ const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz = .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; +const clock_video_pll_config_t videoPllConfig_Board_BootClockPLL600MHz = + { + .loopDivider = 28, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 4, /* Divider after PLL */ + .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz = { .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ @@ -263,7 +281,7 @@ void Board_BootClockPLL600MHz(void) /* Set LPI2C_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + CLOCK_SetMux(kCLOCK_Lpi2cMux, 1); /* Disable CAN clock gate. */ CLOCK_DisableClock(kCLOCK_Can1); CLOCK_DisableClock(kCLOCK_Can2); @@ -289,11 +307,11 @@ void Board_BootClockPLL600MHz(void) /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 0); /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + CLOCK_SetDiv(kCLOCK_LcdifDiv, 4); /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); /* Disable SPDIF clock gate. */ CLOCK_DisableClock(kCLOCK_Spdif); /* Set SPDIF0_CLK_PRED. */ @@ -360,14 +378,25 @@ void Board_BootClockPLL600MHz(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(1); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(960000); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(28); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* Init Enet PLL. */ CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL600MHz); /* Bypass Enet PLL. */ @@ -437,7 +466,6 @@ void Board_BootClockPLL600MHz(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: Board_BootClockPLL480MHz -called_from_default_init: true outputs: - {id: AHB_CLK_ROOT.outFreq, value: 480 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} diff --git a/board/clock_config.h b/board/clock_config.h index 379e02f..1cc31ea 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -36,52 +36,52 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 33600001UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 24000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration. */ @@ -89,6 +89,9 @@ extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz; /*! @brief Sys PLL for Board_BootClockPLL600MHz configuration. */ extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz; +/*! @brief Video PLL set for Board_BootClockPLL600MHz configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_Board_BootClockPLL600MHz; /*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration. */ extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz; @@ -119,52 +122,52 @@ void Board_BootClockPLL600MHz(void); #define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration. */ @@ -202,52 +205,52 @@ void Board_BootClockPLL480MHz(void); #define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration. */ diff --git a/board/dcd.c b/board/dcd.c index b4902c3..b9f8b64 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -24,7 +24,7 @@ product: DCDx v3.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 14.0.0 output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ @@ -33,9 +33,271 @@ const uint8_t dcd_data[] = { /* Tag */ 0xD2, /* Image Length */ - 0x00, 0x04, + 0x04, 0x10, /* Version */ - 0x41 + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ diff --git a/board/peripherals.c b/board/peripherals.c index f35aa88..16384cf 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -6,11 +6,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Peripherals v12.0 +product: Peripherals v13.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 14.0.0 functionalGroups: - name: BOARD_InitPeripherals UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830 @@ -76,6 +76,78 @@ instance: static void NVIC_init(void) { } */ +/*********************************************************************************************************************** + * SEMC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'SEMC' +- type: 'semc' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'semc_e185781b9c9b915bcac54a638e3461f6' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'SEMC' +- config_sets: + - fsl_semc: + - enableDCD: 'true' + - clockConfig: + - clockSource: 'kSEMC_ClkSrcPeri' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - semc_config_t: + - dqsMode: 'kSEMC_Loopbackdqspad' + - cmdTimeoutCycles: '0' + - busTimeoutCycles: '0' + - queueWeight: + - queueaEnable: 'false' + - queueaWeight: + - structORvalue: 'structure' + - queueaConfig: + - qos: '0' + - aging: '0' + - slaveHitNoswitch: '0' + - slaveHitSwitch: '0' + - queuebEnable: 'false' + - queuebWeight: + - structORvalue: 'structure' + - queuebConfig: + - qos: '0' + - aging: '0' + - weightPagehit: '0' + - slaveHitNoswitch: '0' + - bankRotation: '0' + - semc_sdram_config_t: + - csxPinMux: 'kSEMC_MUXCSX0' + - semcSdramCs: 'kSEMC_SDRAM_CS0' + - address: '0x80000000' + - memsize_input: '32MB' + - portSize: 'kSEMC_PortSize16Bit' + - burstLen: 'kSEMC_Sdram_BurstLen1' + - columnAddrBitNum: 'kSEMC_SdramColunm_9bit' + - casLatency: 'kSEMC_LatencyTwo' + - tPrecharge2Act_Ns: '15' + - tAct2ReadWrite_Ns: '15' + - tRefreshRecovery_Ns: '67' + - tWriteRecovery_Ns: '16' + - tCkeOff_Ns: '8' + - tAct2Prechage_Ns: '42' + - tSelfRefRecovery_Ns: '67' + - tRefresh2Refresh_Ns: '60' + - tAct2Act_Ns: '60' + - tPrescalePeriod_Ns: '1203' + - tIdleTimeout_Ns: '0' + - refreshPeriod_nsPerRow: '7813' + - refreshUrgThreshold: '7813' + - refreshBurstLen: '1' + - sdramArray: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void SEMC_init(void) { +} */ + /*********************************************************************************************************************** * Initialization functions **********************************************************************************************************************/ diff --git a/board/peripherals.h b/board/peripherals.h index 2a75809..42b2cc3 100644 --- a/board/peripherals.h +++ b/board/peripherals.h @@ -15,6 +15,14 @@ extern "C" { #endif /* __cplusplus */ +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals functional group */ +/* BOARD_InitPeripherals defines for SEMC */ +/* Definition of peripheral ID. */ +#define SEMC_PERIPHERAL SEMC + /*********************************************************************************************************************** * Initialization functions **********************************************************************************************************************/ diff --git a/board/pin_mux.c b/board/pin_mux.c index 2aed03a..7548d31 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.0 +product: Pins v14.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 14.0.0 pin_labels: - {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B} - {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G} @@ -21,6 +21,8 @@ pin_labels: - {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: CSI_RST, identifier: CSI_RST} - {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BUZZER, identifier: BUZZER} - {pin_num: L6, pin_signal: WAKEUP, label: WAKEUP, identifier: WAKEUP} +- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: LCD_BL, identifier: LCD_BL} +- {pin_num: G10, pin_signal: GPIO_AD_B0_11, label: LCD_INT, identifier: LCD_INT} power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH: '3.3', DCDC_SENSE: '1.25', NVCC_EMC: '3.3', NVCC_GPIO: '3.3', NVCC_SD0: '3.3', NVCC_SD1: '3.3', VDDA_ADC_3P3: '3.3', VDD_HIGH_CAP: '1.1', VDD_HIGH_IN: '3.3', VDD_SNVS_CAP: '1.1', VDD_SNVS_IN: '3.3', VDD_SOC_IN: '1.25', VDD_USB_CAP: '2.5'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** @@ -41,6 +43,7 @@ void BOARD_InitBootPins(void) { BOARD_InitUARTDbgPins(); BOARD_InitSWDPins(); BOARD_InitFlexSPIPins(); + BOARD_InitI2C1Pins(); } /* @@ -434,6 +437,8 @@ BOARD_InitLCDPins: - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02} - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03} - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: L10, peripheral: GPIO1, signal: 'gpio_io, 15', pin_signal: GPIO_AD_B0_15, direction: OUTPUT} + - {pin_num: G10, peripheral: GPIO1, signal: 'gpio_io, 11', pin_signal: GPIO_AD_B0_11, direction: INPUT} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -455,7 +460,27 @@ void BOARD_InitLCDPins(void) { /* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */ GPIO_PinInit(GPIO1, 2U, &LCD_RST_config); + /* GPIO configuration of LCD_INT on GPIO_AD_B0_11 (pin G10) */ + gpio_pin_config_t LCD_INT_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_11 (pin G10) */ + GPIO_PinInit(GPIO1, 11U, &LCD_INT_config); + + /* GPIO configuration of LCD_BL on GPIO_AD_B0_15 (pin L10) */ + gpio_pin_config_t LCD_BL_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_15 (pin L10) */ + GPIO_PinInit(GPIO1, 15U, &LCD_BL_config); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); @@ -740,10 +765,10 @@ void BOARD_InitBasicIOPins(void) { /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitI2C1Pins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01} - - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00} + - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, software_input_on: Enable, open_drain: Enable} + - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, software_input_on: Enable, open_drain: Enable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -756,8 +781,10 @@ BOARD_InitI2C1Pins: void BOARD_InitI2C1Pins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0x18B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0x18B0U); } diff --git a/board/pin_mux.h b/board/pin_mux.h index d87c119..c89d39b 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -107,6 +107,34 @@ void BOARD_InitSEMCPins(void); #define BOARD_INITLCDPINS_LCD_RST_PIN 2U /*!< PORT pin number */ #define BOARD_INITLCDPINS_LCD_RST_PIN_MASK (1U << 2U) /*!< PORT pin mask */ +/* GPIO_AD_B0_15 (coord L10), LCD_BL */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCD_BL_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCD_BL_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLCDPINS_LCD_BL_CHANNEL 15U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLCDPINS_LCD_BL_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLCDPINS_LCD_BL_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITLCDPINS_LCD_BL_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ +#define BOARD_INITLCDPINS_LCD_BL_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLCDPINS_LCD_BL_PIN 15U /*!< PORT pin number */ +#define BOARD_INITLCDPINS_LCD_BL_PIN_MASK (1U << 15U) /*!< PORT pin mask */ + +/* GPIO_AD_B0_11 (coord G10), LCD_INT */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCD_INT_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCD_INT_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLCDPINS_LCD_INT_CHANNEL 11U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLCDPINS_LCD_INT_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLCDPINS_LCD_INT_GPIO_PIN 11U /*!< GPIO pin number */ +#define BOARD_INITLCDPINS_LCD_INT_GPIO_PIN_MASK (1U << 11U) /*!< GPIO pin mask */ +#define BOARD_INITLCDPINS_LCD_INT_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLCDPINS_LCD_INT_PIN 11U /*!< PORT pin number */ +#define BOARD_INITLCDPINS_LCD_INT_PIN_MASK (1U << 11U) /*!< PORT pin mask */ + /*! * @brief Configures pin routing and optionally pin electrical features. @@ -218,6 +246,11 @@ void BOARD_InitBasicIOPins(void); */ void BOARD_InitI2C1Pins(void); +/* GPIO_AD_B0_15 (coord L10), LCD_BL */ +/* Routed pin properties */ +#define BOARD_INITCAN2PINS_LCD_BL_PERIPHERAL CAN2 /*!< Peripheral name */ +#define BOARD_INITCAN2PINS_LCD_BL_SIGNAL RX /*!< Signal name */ + /*! * @brief Configures pin routing and optionally pin electrical features. diff --git a/gcc/flexspi_nor_sdram.ld b/gcc/flexspi_nor_sdram.ld new file mode 100644 index 0000000..e81918e --- /dev/null +++ b/gcc/flexspi_nor_sdram.ld @@ -0,0 +1,288 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.0, 2018-09-21 +** Build: b210709 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; +NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81000000 - HEAP_SIZE; +NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01000000 : 0x01000000 - HEAP_SIZE + m_ncache (RW) : ORIGIN = 0x81000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01000000 - HEAP_SIZE : 0x01000000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_ncache); + __NCACHE_REGION_SIZE = LENGTH(m_ncache) + NCACHE_HEAP_SIZE; + + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ + + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .qadata : + { + . = ALIGN(4); + *(DataQuickAccess) /* quick access data section */ + . = ALIGN(4); + } > m_data2 + + .mempool : + { + . = ALIGN(4); + *(.mempool) + *(.mempool*) + . = ALIGN(4); + } > m_data3 + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/include/FreeRTOSConfig.h b/include/FreeRTOSConfig.h new file mode 100644 index 0000000..8a338e3 --- /dev/null +++ b/include/FreeRTOSConfig.h @@ -0,0 +1,153 @@ +/* +* FreeRTOS Kernel V10.4.3 +* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of +* this software and associated documentation files (the "Software"), to deal in +* the Software without restriction, including without limitation the rights to +* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +* the Software, and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all +* copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* https://www.FreeRTOS.org +* https://github.com/FreeRTOS +* +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html. +*----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 8 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(96 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) +/* Clock manager provides in this variable system core clock frequency */ +#include +extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/include/app_lvgl.h b/include/app_lvgl.h new file mode 100644 index 0000000..54ab380 --- /dev/null +++ b/include/app_lvgl.h @@ -0,0 +1,7 @@ +#ifndef APP_LVGL_H +#define APP_LVGL_H + +int app_lvgl_init(void); +uint32_t app_lvgl_ticks(void); + +#endif //APP_LVGL_H diff --git a/include/lv_conf.h b/include/lv_conf.h new file mode 100644 index 0000000..35518cc --- /dev/null +++ b/include/lv_conf.h @@ -0,0 +1,770 @@ +/** + * @file lv_conf.h + * Configuration file for v8.3.9 + */ + +/* + * Copy this file as `lv_conf.h` + * 1. simply next to the `lvgl` folder + * 2. or any other places and + * - define `LV_CONF_INCLUDE_SIMPLE` + * - add the path as include path + */ + +/* clang-format off */ +#if 1 /*Set it to "1" to enable content*/ + +#ifndef LV_CONF_H +#define LV_CONF_H + +#include + +/*==================== + COLOR SETTINGS + *====================*/ + +/*Color depth: 1 (1 byte per pixel), 8 (RGB332), 16 (RGB565), 32 (ARGB8888)*/ +#define LV_COLOR_DEPTH 16 + +/*Swap the 2 bytes of RGB565 color. Useful if the display has an 8-bit interface (e.g. SPI)*/ +#define LV_COLOR_16_SWAP 0 + +/*Enable features to draw on transparent background. + *It's required if opa, and transform_* style properties are used. + *Can be also used if the UI is above another layer, e.g. an OSD menu or video player.*/ +#define LV_COLOR_SCREEN_TRANSP 0 + +/* Adjust color mix functions rounding. GPUs might calculate color mix (blending) differently. + * 0: round down, 64: round up from x.75, 128: round up from half, 192: round up from x.25, 254: round up */ +#define LV_COLOR_MIX_ROUND_OFS 0 + +/*Images pixels with this color will not be drawn if they are chroma keyed)*/ +#define LV_COLOR_CHROMA_KEY lv_color_hex(0x00ff00) /*pure green*/ + +/*========================= + MEMORY SETTINGS + *=========================*/ + +/*1: use custom malloc/free, 0: use the built-in `lv_mem_alloc()` and `lv_mem_free()`*/ +#define LV_MEM_CUSTOM 0 +#if LV_MEM_CUSTOM == 0 + /*Size of the memory available for `lv_mem_alloc()` in bytes (>= 2kB)*/ + #define LV_MEM_SIZE (96U * 1024U) /*[bytes]*/ + + /*Set an address for the memory pool instead of allocating it as a normal array. Can be in external SRAM too.*/ + #define LV_MEM_ADR 0 /*0: unused*/ + /*Instead of an address give a memory allocator that will be called to get a memory pool for LVGL. E.g. my_malloc*/ + #if LV_MEM_ADR == 0 + #undef LV_MEM_POOL_INCLUDE + #undef LV_MEM_POOL_ALLOC + #endif + +#else /*LV_MEM_CUSTOM*/ + #define LV_MEM_CUSTOM_INCLUDE /*Header for the dynamic memory function*/ + #define LV_MEM_CUSTOM_ALLOC malloc + #define LV_MEM_CUSTOM_FREE free + #define LV_MEM_CUSTOM_REALLOC realloc +#endif /*LV_MEM_CUSTOM*/ + +/*Number of the intermediate memory buffer used during rendering and other internal processing mechanisms. + *You will see an error log message if there wasn't enough buffers. */ +#define LV_MEM_BUF_MAX_NUM 16 + +/*Use the standard `memcpy` and `memset` instead of LVGL's own functions. (Might or might not be faster).*/ +#define LV_MEMCPY_MEMSET_STD 0 + +/*==================== + HAL SETTINGS + *====================*/ + +/*Default display refresh period. LVG will redraw changed areas with this period time*/ +#define LV_DISP_DEF_REFR_PERIOD 30 /*[ms]*/ + +/*Input device read period in milliseconds*/ +#define LV_INDEV_DEF_READ_PERIOD 30 /*[ms]*/ + +/*Use a custom tick source that tells the elapsed time in milliseconds. + *It removes the need to manually update the tick with `lv_tick_inc()`)*/ +#define LV_TICK_CUSTOM 1 +#if LV_TICK_CUSTOM + #define LV_TICK_CUSTOM_INCLUDE "app_lvgl.h" /*Header for the system time function*/ + #define LV_TICK_CUSTOM_SYS_TIME_EXPR (app_lvgl_ticks()) /*Expression evaluating to current system time in ms*/ + /*If using lvgl as ESP32 component*/ + // #define LV_TICK_CUSTOM_INCLUDE "esp_timer.h" + // #define LV_TICK_CUSTOM_SYS_TIME_EXPR ((esp_timer_get_time() / 1000LL)) +#endif /*LV_TICK_CUSTOM*/ + +/*Default Dot Per Inch. Used to initialize default sizes such as widgets sized, style paddings. + *(Not so important, you can adjust it to modify default sizes and spaces)*/ +#define LV_DPI_DEF 130 /*[px/inch]*/ + +/*======================= + * FEATURE CONFIGURATION + *=======================*/ + +/*------------- + * Drawing + *-----------*/ + +/*Enable complex draw engine. + *Required to draw shadow, gradient, rounded corners, circles, arc, skew lines, image transformations or any masks*/ +#define LV_DRAW_COMPLEX 1 +#if LV_DRAW_COMPLEX != 0 + + /*Allow buffering some shadow calculation. + *LV_SHADOW_CACHE_SIZE is the max. shadow size to buffer, where shadow size is `shadow_width + radius` + *Caching has LV_SHADOW_CACHE_SIZE^2 RAM cost*/ + #define LV_SHADOW_CACHE_SIZE 0 + + /* Set number of maximally cached circle data. + * The circumference of 1/4 circle are saved for anti-aliasing + * radius * 4 bytes are used per circle (the most often used radiuses are saved) + * 0: to disable caching */ + #define LV_CIRCLE_CACHE_SIZE 4 +#endif /*LV_DRAW_COMPLEX*/ + +/** + * "Simple layers" are used when a widget has `style_opa < 255` to buffer the widget into a layer + * and blend it as an image with the given opacity. + * Note that `bg_opa`, `text_opa` etc don't require buffering into layer) + * The widget can be buffered in smaller chunks to avoid using large buffers. + * + * - LV_LAYER_SIMPLE_BUF_SIZE: [bytes] the optimal target buffer size. LVGL will try to allocate it + * - LV_LAYER_SIMPLE_FALLBACK_BUF_SIZE: [bytes] used if `LV_LAYER_SIMPLE_BUF_SIZE` couldn't be allocated. + * + * Both buffer sizes are in bytes. + * "Transformed layers" (where transform_angle/zoom properties are used) use larger buffers + * and can't be drawn in chunks. So these settings affects only widgets with opacity. + */ +#define LV_LAYER_SIMPLE_BUF_SIZE (24 * 1024) +#define LV_LAYER_SIMPLE_FALLBACK_BUF_SIZE (3 * 1024) + +/*Default image cache size. Image caching keeps the images opened. + *If only the built-in image formats are used there is no real advantage of caching. (I.e. if no new image decoder is added) + *With complex image decoders (e.g. PNG or JPG) caching can save the continuous open/decode of images. + *However the opened images might consume additional RAM. + *0: to disable caching*/ +#define LV_IMG_CACHE_DEF_SIZE 0 + +/*Number of stops allowed per gradient. Increase this to allow more stops. + *This adds (sizeof(lv_color_t) + 1) bytes per additional stop*/ +#define LV_GRADIENT_MAX_STOPS 2 + +/*Default gradient buffer size. + *When LVGL calculates the gradient "maps" it can save them into a cache to avoid calculating them again. + *LV_GRAD_CACHE_DEF_SIZE sets the size of this cache in bytes. + *If the cache is too small the map will be allocated only while it's required for the drawing. + *0 mean no caching.*/ +#define LV_GRAD_CACHE_DEF_SIZE 0 + +/*Allow dithering the gradients (to achieve visual smooth color gradients on limited color depth display) + *LV_DITHER_GRADIENT implies allocating one or two more lines of the object's rendering surface + *The increase in memory consumption is (32 bits * object width) plus 24 bits * object width if using error diffusion */ +#define LV_DITHER_GRADIENT 0 +#if LV_DITHER_GRADIENT + /*Add support for error diffusion dithering. + *Error diffusion dithering gets a much better visual result, but implies more CPU consumption and memory when drawing. + *The increase in memory consumption is (24 bits * object's width)*/ + #define LV_DITHER_ERROR_DIFFUSION 0 +#endif + +/*Maximum buffer size to allocate for rotation. + *Only used if software rotation is enabled in the display driver.*/ +#define LV_DISP_ROT_MAX_BUF (10*1024) + +/*------------- + * GPU + *-----------*/ + +/*Use Arm's 2D acceleration library Arm-2D */ +#define LV_USE_GPU_ARM2D 0 + +/*Use STM32's DMA2D (aka Chrom Art) GPU*/ +#define LV_USE_GPU_STM32_DMA2D 0 +#if LV_USE_GPU_STM32_DMA2D + /*Must be defined to include path of CMSIS header of target processor + e.g. "stm32f7xx.h" or "stm32f4xx.h"*/ + #define LV_GPU_DMA2D_CMSIS_INCLUDE +#endif + +/*Enable RA6M3 G2D GPU*/ +#define LV_USE_GPU_RA6M3_G2D 0 +#if LV_USE_GPU_RA6M3_G2D + /*include path of target processor + e.g. "hal_data.h"*/ + #define LV_GPU_RA6M3_G2D_INCLUDE "hal_data.h" +#endif + +/*Use SWM341's DMA2D GPU*/ +#define LV_USE_GPU_SWM341_DMA2D 0 +#if LV_USE_GPU_SWM341_DMA2D + #define LV_GPU_SWM341_DMA2D_INCLUDE "SWM341.h" +#endif + +/*Use NXP's PXP GPU iMX RTxxx platforms*/ +#define LV_USE_GPU_NXP_PXP 0 +#if LV_USE_GPU_NXP_PXP + /*1: Add default bare metal and FreeRTOS interrupt handling routines for PXP (lv_gpu_nxp_pxp_osa.c) + * and call lv_gpu_nxp_pxp_init() automatically during lv_init(). Note that symbol SDK_OS_FREE_RTOS + * has to be defined in order to use FreeRTOS OSA, otherwise bare-metal implementation is selected. + *0: lv_gpu_nxp_pxp_init() has to be called manually before lv_init() + */ + #define LV_USE_GPU_NXP_PXP_AUTO_INIT 0 +#endif + +/*Use NXP's VG-Lite GPU iMX RTxxx platforms*/ +#define LV_USE_GPU_NXP_VG_LITE 0 + +/*Use SDL renderer API*/ +#define LV_USE_GPU_SDL 0 +#if LV_USE_GPU_SDL + #define LV_GPU_SDL_INCLUDE_PATH + /*Texture cache size, 8MB by default*/ + #define LV_GPU_SDL_LRU_SIZE (1024 * 1024 * 8) + /*Custom blend mode for mask drawing, disable if you need to link with older SDL2 lib*/ + #define LV_GPU_SDL_CUSTOM_BLEND_MODE (SDL_VERSION_ATLEAST(2, 0, 6)) +#endif + +/*------------- + * Logging + *-----------*/ + +/*Enable the log module*/ +#define LV_USE_LOG 0 +#if LV_USE_LOG + + /*How important log should be added: + *LV_LOG_LEVEL_TRACE A lot of logs to give detailed information + *LV_LOG_LEVEL_INFO Log important events + *LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem + *LV_LOG_LEVEL_ERROR Only critical issue, when the system may fail + *LV_LOG_LEVEL_USER Only logs added by the user + *LV_LOG_LEVEL_NONE Do not log anything*/ + #define LV_LOG_LEVEL LV_LOG_LEVEL_WARN + + /*1: Print the log with 'printf'; + *0: User need to register a callback with `lv_log_register_print_cb()`*/ + #define LV_LOG_PRINTF 0 + + /*Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs*/ + #define LV_LOG_TRACE_MEM 1 + #define LV_LOG_TRACE_TIMER 1 + #define LV_LOG_TRACE_INDEV 1 + #define LV_LOG_TRACE_DISP_REFR 1 + #define LV_LOG_TRACE_EVENT 1 + #define LV_LOG_TRACE_OBJ_CREATE 1 + #define LV_LOG_TRACE_LAYOUT 1 + #define LV_LOG_TRACE_ANIM 1 + +#endif /*LV_USE_LOG*/ + +/*------------- + * Asserts + *-----------*/ + +/*Enable asserts if an operation is failed or an invalid data is found. + *If LV_USE_LOG is enabled an error message will be printed on failure*/ +#define LV_USE_ASSERT_NULL 1 /*Check if the parameter is NULL. (Very fast, recommended)*/ +#define LV_USE_ASSERT_MALLOC 1 /*Checks is the memory is successfully allocated or no. (Very fast, recommended)*/ +#define LV_USE_ASSERT_STYLE 0 /*Check if the styles are properly initialized. (Very fast, recommended)*/ +#define LV_USE_ASSERT_MEM_INTEGRITY 0 /*Check the integrity of `lv_mem` after critical operations. (Slow)*/ +#define LV_USE_ASSERT_OBJ 0 /*Check the object's type and existence (e.g. not deleted). (Slow)*/ + +/*Add a custom handler when assert happens e.g. to restart the MCU*/ +#define LV_ASSERT_HANDLER_INCLUDE +#define LV_ASSERT_HANDLER while(1); /*Halt by default*/ + +/*------------- + * Others + *-----------*/ + +/*1: Show CPU usage and FPS count*/ +#define LV_USE_PERF_MONITOR 1 +#if LV_USE_PERF_MONITOR + #define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT +#endif + +/*1: Show the used memory and the memory fragmentation + * Requires LV_MEM_CUSTOM = 0*/ +#define LV_USE_MEM_MONITOR 1 +#if LV_USE_MEM_MONITOR + #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT +#endif + +/*1: Draw random colored rectangles over the redrawn areas*/ +#define LV_USE_REFR_DEBUG 0 + +/*Change the built in (v)snprintf functions*/ +#define LV_SPRINTF_CUSTOM 0 +#if LV_SPRINTF_CUSTOM + #define LV_SPRINTF_INCLUDE + #define lv_snprintf snprintf + #define lv_vsnprintf vsnprintf +#else /*LV_SPRINTF_CUSTOM*/ + #define LV_SPRINTF_USE_FLOAT 0 +#endif /*LV_SPRINTF_CUSTOM*/ + +#define LV_USE_USER_DATA 1 + +/*Garbage Collector settings + *Used if lvgl is bound to higher level language and the memory is managed by that language*/ +#define LV_ENABLE_GC 0 +#if LV_ENABLE_GC != 0 + #define LV_GC_INCLUDE "gc.h" /*Include Garbage Collector related things*/ +#endif /*LV_ENABLE_GC*/ + +/*===================== + * COMPILER SETTINGS + *====================*/ + +/*For big endian systems set to 1*/ +#define LV_BIG_ENDIAN_SYSTEM 0 + +/*Define a custom attribute to `lv_tick_inc` function*/ +#define LV_ATTRIBUTE_TICK_INC + +/*Define a custom attribute to `lv_timer_handler` function*/ +#define LV_ATTRIBUTE_TIMER_HANDLER __attribute__((section("CodeQuickAccess"))) + +/*Define a custom attribute to `lv_disp_flush_ready` function*/ +#define LV_ATTRIBUTE_FLUSH_READY + +/*Required alignment size for buffers*/ +#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 1 + +/*Will be added where memories needs to be aligned (with -Os data might not be aligned to boundary by default). + * E.g. __attribute__((aligned(4)))*/ +#define LV_ATTRIBUTE_MEM_ALIGN + +/*Attribute to mark large constant arrays for example font's bitmaps*/ +#define LV_ATTRIBUTE_LARGE_CONST + +/*Compiler prefix for a big array declaration in RAM*/ +#define LV_ATTRIBUTE_LARGE_RAM_ARRAY __attribute__((section(".mempool"))) + +/*Place performance critical functions into a faster memory (e.g RAM)*/ +#define LV_ATTRIBUTE_FAST_MEM __attribute__((section("CodeQuickAccess"))) + +/*Prefix variables that are used in GPU accelerated operations, often these need to be placed in RAM sections that are DMA accessible*/ +#define LV_ATTRIBUTE_DMA + +/*Export integer constant to binding. This macro is used with constants in the form of LV_ that + *should also appear on LVGL binding API such as Micropython.*/ +#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning /*The default value just prevents GCC warning*/ + +/*Extend the default -32k..32k coordinate range to -4M..4M by using int32_t for coordinates instead of int16_t*/ +#define LV_USE_LARGE_COORD 0 + +/*================== + * FONT USAGE + *===================*/ + +/*Montserrat fonts with ASCII range and some symbols using bpp = 4 + *https://fonts.google.com/specimen/Montserrat*/ +#define LV_FONT_MONTSERRAT_8 0 +#define LV_FONT_MONTSERRAT_10 0 +#define LV_FONT_MONTSERRAT_12 0 +#define LV_FONT_MONTSERRAT_14 1 +#define LV_FONT_MONTSERRAT_16 1 +#define LV_FONT_MONTSERRAT_18 0 +#define LV_FONT_MONTSERRAT_20 0 +#define LV_FONT_MONTSERRAT_22 1 +#define LV_FONT_MONTSERRAT_24 0 +#define LV_FONT_MONTSERRAT_26 0 +#define LV_FONT_MONTSERRAT_28 0 +#define LV_FONT_MONTSERRAT_30 0 +#define LV_FONT_MONTSERRAT_32 1 +#define LV_FONT_MONTSERRAT_34 0 +#define LV_FONT_MONTSERRAT_36 0 +#define LV_FONT_MONTSERRAT_38 0 +#define LV_FONT_MONTSERRAT_40 0 +#define LV_FONT_MONTSERRAT_42 0 +#define LV_FONT_MONTSERRAT_44 0 +#define LV_FONT_MONTSERRAT_46 0 +#define LV_FONT_MONTSERRAT_48 0 + +/*Demonstrate special features*/ +#define LV_FONT_MONTSERRAT_12_SUBPX 0 +#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /*bpp = 3*/ +#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /*Hebrew, Arabic, Persian letters and all their forms*/ +#define LV_FONT_SIMSUN_16_CJK 0 /*1000 most common CJK radicals*/ + +/*Pixel perfect monospace fonts*/ +#define LV_FONT_UNSCII_8 0 +#define LV_FONT_UNSCII_16 0 + +/*Optionally declare custom fonts here. + *You can use these fonts as default font too and they will be available globally. + *E.g. #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) LV_FONT_DECLARE(my_font_2)*/ +#define LV_FONT_CUSTOM_DECLARE + +/*Always set a default font*/ +#define LV_FONT_DEFAULT &lv_font_montserrat_14 + +/*Enable handling large font and/or fonts with a lot of characters. + *The limit depends on the font size, font face and bpp. + *Compiler error will be triggered if a font needs it.*/ +#define LV_FONT_FMT_TXT_LARGE 0 + +/*Enables/disables support for compressed fonts.*/ +#define LV_USE_FONT_COMPRESSED 0 + +/*Enable subpixel rendering*/ +#define LV_USE_FONT_SUBPX 0 +#if LV_USE_FONT_SUBPX + /*Set the pixel order of the display. Physical order of RGB channels. Doesn't matter with "normal" fonts.*/ + #define LV_FONT_SUBPX_BGR 0 /*0: RGB; 1:BGR order*/ +#endif + +/*Enable drawing placeholders when glyph dsc is not found*/ +#define LV_USE_FONT_PLACEHOLDER 1 + +/*================= + * TEXT SETTINGS + *=================*/ + +/** + * Select a character encoding for strings. + * Your IDE or editor should have the same character encoding + * - LV_TXT_ENC_UTF8 + * - LV_TXT_ENC_ASCII + */ +#define LV_TXT_ENC LV_TXT_ENC_UTF8 + +/*Can break (wrap) texts on these chars*/ +#define LV_TXT_BREAK_CHARS " ,.;:-_" + +/*If a word is at least this long, will break wherever "prettiest" + *To disable, set to a value <= 0*/ +#define LV_TXT_LINE_BREAK_LONG_LEN 0 + +/*Minimum number of characters in a long word to put on a line before a break. + *Depends on LV_TXT_LINE_BREAK_LONG_LEN.*/ +#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3 + +/*Minimum number of characters in a long word to put on a line after a break. + *Depends on LV_TXT_LINE_BREAK_LONG_LEN.*/ +#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3 + +/*The control character to use for signalling text recoloring.*/ +#define LV_TXT_COLOR_CMD "#" + +/*Support bidirectional texts. Allows mixing Left-to-Right and Right-to-Left texts. + *The direction will be processed according to the Unicode Bidirectional Algorithm: + *https://www.w3.org/International/articles/inline-bidi-markup/uba-basics*/ +#define LV_USE_BIDI 0 +#if LV_USE_BIDI + /*Set the default direction. Supported values: + *`LV_BASE_DIR_LTR` Left-to-Right + *`LV_BASE_DIR_RTL` Right-to-Left + *`LV_BASE_DIR_AUTO` detect texts base direction*/ + #define LV_BIDI_BASE_DIR_DEF LV_BASE_DIR_AUTO +#endif + +/*Enable Arabic/Persian processing + *In these languages characters should be replaced with an other form based on their position in the text*/ +#define LV_USE_ARABIC_PERSIAN_CHARS 0 + +/*================== + * WIDGET USAGE + *================*/ + +/*Documentation of the widgets: https://docs.lvgl.io/latest/en/html/widgets/index.html*/ + +#define LV_USE_ARC 1 + +#define LV_USE_BAR 1 + +#define LV_USE_BTN 1 + +#define LV_USE_BTNMATRIX 1 + +#define LV_USE_CANVAS 1 + +#define LV_USE_CHECKBOX 1 + +#define LV_USE_DROPDOWN 1 /*Requires: lv_label*/ + +#define LV_USE_IMG 1 /*Requires: lv_label*/ + +#define LV_USE_LABEL 1 +#if LV_USE_LABEL + #define LV_LABEL_TEXT_SELECTION 1 /*Enable selecting text of the label*/ + #define LV_LABEL_LONG_TXT_HINT 1 /*Store some extra info in labels to speed up drawing of very long texts*/ +#endif + +#define LV_USE_LINE 1 + +#define LV_USE_ROLLER 1 /*Requires: lv_label*/ +#if LV_USE_ROLLER + #define LV_ROLLER_INF_PAGES 7 /*Number of extra "pages" when the roller is infinite*/ +#endif + +#define LV_USE_SLIDER 1 /*Requires: lv_bar*/ + +#define LV_USE_SWITCH 1 + +#define LV_USE_TEXTAREA 1 /*Requires: lv_label*/ +#if LV_USE_TEXTAREA != 0 + #define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /*ms*/ +#endif + +#define LV_USE_TABLE 1 + +/*================== + * EXTRA COMPONENTS + *==================*/ + +/*----------- + * Widgets + *----------*/ +#define LV_USE_ANIMIMG 1 + +#define LV_USE_CALENDAR 1 +#if LV_USE_CALENDAR + #define LV_CALENDAR_WEEK_STARTS_MONDAY 0 + #if LV_CALENDAR_WEEK_STARTS_MONDAY + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Mo", "Tu", "We", "Th", "Fr", "Sa", "Su"} + #else + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Su", "Mo", "Tu", "We", "Th", "Fr", "Sa"} + #endif + + #define LV_CALENDAR_DEFAULT_MONTH_NAMES {"January", "February", "March", "April", "May", "June", "July", "August", "September", "October", "November", "December"} + #define LV_USE_CALENDAR_HEADER_ARROW 1 + #define LV_USE_CALENDAR_HEADER_DROPDOWN 1 +#endif /*LV_USE_CALENDAR*/ + +#define LV_USE_CHART 1 + +#define LV_USE_COLORWHEEL 1 + +#define LV_USE_IMGBTN 1 + +#define LV_USE_KEYBOARD 1 + +#define LV_USE_LED 1 + +#define LV_USE_LIST 1 + +#define LV_USE_MENU 1 + +#define LV_USE_METER 1 + +#define LV_USE_MSGBOX 1 + +#define LV_USE_SPAN 1 +#if LV_USE_SPAN + /*A line text can contain maximum num of span descriptor */ + #define LV_SPAN_SNIPPET_STACK_SIZE 64 +#endif + +#define LV_USE_SPINBOX 1 + +#define LV_USE_SPINNER 1 + +#define LV_USE_TABVIEW 1 + +#define LV_USE_TILEVIEW 1 + +#define LV_USE_WIN 1 + +/*----------- + * Themes + *----------*/ + +/*A simple, impressive and very complete theme*/ +#define LV_USE_THEME_DEFAULT 1 +#if LV_USE_THEME_DEFAULT + + /*0: Light mode; 1: Dark mode*/ + #define LV_THEME_DEFAULT_DARK 0 + + /*1: Enable grow on press*/ + #define LV_THEME_DEFAULT_GROW 1 + + /*Default transition time in [ms]*/ + #define LV_THEME_DEFAULT_TRANSITION_TIME 80 +#endif /*LV_USE_THEME_DEFAULT*/ + +/*A very simple theme that is a good starting point for a custom theme*/ +#define LV_USE_THEME_BASIC 1 + +/*A theme designed for monochrome displays*/ +#define LV_USE_THEME_MONO 1 + +/*----------- + * Layouts + *----------*/ + +/*A layout similar to Flexbox in CSS.*/ +#define LV_USE_FLEX 1 + +/*A layout similar to Grid in CSS.*/ +#define LV_USE_GRID 1 + +/*--------------------- + * 3rd party libraries + *--------------------*/ + +/*File system interfaces for common APIs */ + +/*API for fopen, fread, etc*/ +#define LV_USE_FS_STDIO 0 +#if LV_USE_FS_STDIO + #define LV_FS_STDIO_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_STDIO_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_STDIO_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for open, read, etc*/ +#define LV_USE_FS_POSIX 0 +#if LV_USE_FS_POSIX + #define LV_FS_POSIX_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_POSIX_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_POSIX_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for CreateFile, ReadFile, etc*/ +#define LV_USE_FS_WIN32 0 +#if LV_USE_FS_WIN32 + #define LV_FS_WIN32_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_WIN32_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_WIN32_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for FATFS (needs to be added separately). Uses f_open, f_read, etc*/ +#define LV_USE_FS_FATFS 0 +#if LV_USE_FS_FATFS + #define LV_FS_FATFS_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_FATFS_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*PNG decoder library*/ +#define LV_USE_PNG 0 + +/*BMP decoder library*/ +#define LV_USE_BMP 0 + +/* JPG + split JPG decoder library. + * Split JPG is a custom format optimized for embedded systems. */ +#define LV_USE_SJPG 0 + +/*GIF decoder library*/ +#define LV_USE_GIF 0 + +/*QR code library*/ +#define LV_USE_QRCODE 0 + +/*FreeType library*/ +#define LV_USE_FREETYPE 0 +#if LV_USE_FREETYPE + /*Memory used by FreeType to cache characters [bytes] (-1: no caching)*/ + #define LV_FREETYPE_CACHE_SIZE (16 * 1024) + #if LV_FREETYPE_CACHE_SIZE >= 0 + /* 1: bitmap cache use the sbit cache, 0:bitmap cache use the image cache. */ + /* sbit cache:it is much more memory efficient for small bitmaps(font size < 256) */ + /* if font size >= 256, must be configured as image cache */ + #define LV_FREETYPE_SBIT_CACHE 0 + /* Maximum number of opened FT_Face/FT_Size objects managed by this cache instance. */ + /* (0:use system defaults) */ + #define LV_FREETYPE_CACHE_FT_FACES 0 + #define LV_FREETYPE_CACHE_FT_SIZES 0 + #endif +#endif + +/*Rlottie library*/ +#define LV_USE_RLOTTIE 0 + +/*FFmpeg library for image decoding and playing videos + *Supports all major image formats so do not enable other image decoder with it*/ +#define LV_USE_FFMPEG 0 +#if LV_USE_FFMPEG + /*Dump input information to stderr*/ + #define LV_FFMPEG_DUMP_FORMAT 0 +#endif + +/*----------- + * Others + *----------*/ + +/*1: Enable API to take snapshot for object*/ +#define LV_USE_SNAPSHOT 0 + +/*1: Enable Monkey test*/ +#define LV_USE_MONKEY 0 + +/*1: Enable grid navigation*/ +#define LV_USE_GRIDNAV 0 + +/*1: Enable lv_obj fragment*/ +#define LV_USE_FRAGMENT 0 + +/*1: Support using images as font in label or span widgets */ +#define LV_USE_IMGFONT 0 + +/*1: Enable a published subscriber based messaging system */ +#define LV_USE_MSG 0 + +/*1: Enable Pinyin input method*/ +/*Requires: lv_keyboard*/ +#define LV_USE_IME_PINYIN 0 +#if LV_USE_IME_PINYIN + /*1: Use default thesaurus*/ + /*If you do not use the default thesaurus, be sure to use `lv_ime_pinyin` after setting the thesauruss*/ + #define LV_IME_PINYIN_USE_DEFAULT_DICT 1 + /*Set the maximum number of candidate panels that can be displayed*/ + /*This needs to be adjusted according to the size of the screen*/ + #define LV_IME_PINYIN_CAND_TEXT_NUM 6 + + /*Use 9 key input(k9)*/ + #define LV_IME_PINYIN_USE_K9_MODE 1 + #if LV_IME_PINYIN_USE_K9_MODE == 1 + #define LV_IME_PINYIN_K9_CAND_TEXT_NUM 3 + #endif // LV_IME_PINYIN_USE_K9_MODE +#endif + +/*================== +* EXAMPLES +*==================*/ + +/*Enable the examples to be built with the library*/ +#define LV_BUILD_EXAMPLES 1 + +/*=================== + * DEMO USAGE + ====================*/ + +/*Show some widget. It might be required to increase `LV_MEM_SIZE` */ +#define LV_USE_DEMO_WIDGETS 1 +#if LV_USE_DEMO_WIDGETS +#define LV_DEMO_WIDGETS_SLIDESHOW 0 +#endif + +/*Demonstrate the usage of encoder and keyboard*/ +#define LV_USE_DEMO_KEYPAD_AND_ENCODER 0 + +/*Benchmark your system*/ +#define LV_USE_DEMO_BENCHMARK 1 +#if LV_USE_DEMO_BENCHMARK +/*Use RGB565A8 images with 16 bit color depth instead of ARGB8565*/ +#define LV_DEMO_BENCHMARK_RGB565A8 0 +#endif + +/*Stress test for LVGL*/ +#define LV_USE_DEMO_STRESS 0 + +/*Music player demo*/ +#define LV_USE_DEMO_MUSIC 1 +#if LV_USE_DEMO_MUSIC + #define LV_DEMO_MUSIC_SQUARE 0 + #define LV_DEMO_MUSIC_LANDSCAPE 1 + #define LV_DEMO_MUSIC_ROUND 0 + #define LV_DEMO_MUSIC_LARGE 1 + #define LV_DEMO_MUSIC_AUTO_PLAY 0 +#endif + +/*--END OF LV_CONF_H--*/ + +#endif /*LV_CONF_H*/ + +#endif /*End of "Content enable"*/ diff --git a/lib/freertos b/lib/freertos new file mode 160000 index 0000000..18ed888 --- /dev/null +++ b/lib/freertos @@ -0,0 +1 @@ +Subproject commit 18ed8886fe3eed9dbe433a82cdc62ce5dc0315eb diff --git a/lib/lvgl b/lib/lvgl new file mode 160000 index 0000000..06e229c --- /dev/null +++ b/lib/lvgl @@ -0,0 +1 @@ +Subproject commit 06e229cc7679c01119ca5d905a1f9dad96f475f0 diff --git a/pyocd_user.py b/pyocd_user.py new file mode 100644 index 0000000..4d243f4 --- /dev/null +++ b/pyocd_user.py @@ -0,0 +1,6 @@ +def will_connect(): + extFlash = target.memory_map.get_first_matching_region(start=0x60000000) + extFlash.flm = "assets/MIMXRT105x_QuadSPI_4KB_SEC.FLM" + +def did_connect(): + target.aps[0].hprot = 0xb \ No newline at end of file diff --git a/src/app_lvgl.c b/src/app_lvgl.c new file mode 100644 index 0000000..34da076 --- /dev/null +++ b/src/app_lvgl.c @@ -0,0 +1,246 @@ +/* Board */ +#include "pin_mux.h" + +/* LVGL */ +#include "lvgl.h" + +/* SDK drivers */ +#include "fsl_debug_console.h" +#include "fsl_elcdif.h" +#include "fsl_gpio.h" +#include "fsl_gt911.h" +#include "fsl_lpi2c.h" + +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" + +/* App */ +#include "app_lvgl.h" + +#define APP_LCD_WIDTH (800) +#define APP_LCD_HEIGHT (480) +#define APP_LCD_HSW (20) +#define APP_LCD_HFP (210) +#define APP_LCD_HBP (46) +#define APP_LCD_VSW (10) +#define APP_LCD_VFP (22) +#define APP_LCD_VBP (23) +#define APP_LCD_FLAGS \ + (kELCDIF_DataEnableActiveHigh | kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DriveDataOnRisingClkEdge) +#define APP_LCD_BUFFER_SIZE (APP_LCD_WIDTH * APP_LCD_HEIGHT * 2) + +SDK_ALIGN(static uint8_t s_lcd_buffers[2][APP_LCD_BUFFER_SIZE], 64); +AT_QUICKACCESS_SECTION_DATA(static lv_disp_draw_buf_t s_lcd_draw_buf); +AT_QUICKACCESS_SECTION_DATA(static lv_disp_drv_t s_lcd_drv); +AT_QUICKACCESS_SECTION_DATA(static lv_indev_drv_t s_ctp_drv); +AT_QUICKACCESS_SECTION_DATA(static volatile bool s_frame_done); +AT_QUICKACCESS_SECTION_DATA(static gt911_handle_t s_ctp_handle); + +static void app_lvgl_task(void *parameters); + +static void app_lvgl_ctp_reset(bool pullUp) { + if (pullUp) { + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_RST_GPIO, BOARD_INITLCDPINS_LCD_RST_PIN, 1U); + } else { + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_RST_GPIO, BOARD_INITLCDPINS_LCD_RST_PIN, 0U); + } +} + +static void app_lvgl_ctp_int(gt911_int_pin_mode_t mode) { + switch (mode) { + case kGT911_IntPinInput: + BOARD_INITLCDPINS_LCD_INT_GPIO->GDIR &= ~(1UL << BOARD_INITLCDPINS_LCD_INT_PIN); + break; + case kGT911_IntPinPullDown: + BOARD_INITLCDPINS_LCD_INT_GPIO->GDIR |= (1UL << BOARD_INITLCDPINS_LCD_INT_PIN); + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_INT_GPIO, BOARD_INITLCDPINS_LCD_INT_PIN, 0U); + break; + case kGT911_IntPinPullUp: + BOARD_INITLCDPINS_LCD_INT_GPIO->GDIR |= (1UL << BOARD_INITLCDPINS_LCD_INT_PIN); + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_INT_GPIO, BOARD_INITLCDPINS_LCD_INT_PIN, 1U); + break; + default: + break; + } +} + +RAMFUNCTION_SECTION_CODE(static void app_lvgl_delay_ms(uint32_t msec)) { + SDK_DelayAtLeastUs(msec * 1000, CLOCK_GetCoreSysClkFreq()); +} + +RAMFUNCTION_SECTION_CODE(static status_t app_lvgl_i2c_send(uint8_t deviceAddress, uint32_t subAddress, + uint8_t subaddressSize, const uint8_t *txBuff, + uint8_t txBuffSize)) { + lpi2c_master_transfer_t xfer = { + .direction = kLPI2C_Write, + .slaveAddress = deviceAddress, + .subaddress = subAddress, + .subaddressSize = subaddressSize, + .data = (void *)txBuff, + .dataSize = txBuffSize, + }; + + return LPI2C_MasterTransferBlocking(LPI2C1, &xfer); +} + +RAMFUNCTION_SECTION_CODE(static status_t app_lvgl_i2c_recv(uint8_t deviceAddress, uint32_t subAddress, + uint8_t subaddressSize, uint8_t *rxBuff, + uint8_t txBuffSize)) { + lpi2c_master_transfer_t xfer = { + .direction = kLPI2C_Read, + .slaveAddress = deviceAddress, + .subaddress = subAddress, + .subaddressSize = subaddressSize, + .data = (void *)rxBuff, + .dataSize = txBuffSize, + }; + + return LPI2C_MasterTransferBlocking(LPI2C1, &xfer); +} + +static void app_lvgl_backlight(const bool on) { + if (on) { + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_BL_GPIO, BOARD_INITLCDPINS_LCD_BL_PIN, 1U); + } else { + GPIO_PinWrite(BOARD_INITLCDPINS_LCD_BL_GPIO, BOARD_INITLCDPINS_LCD_BL_PIN, 0U); + } +} + +RAMFUNCTION_SECTION_CODE(static void app_lvgl_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, + lv_color_t *color_p)) { + SCB_CleanDCache_by_Addr(color_p, APP_LCD_BUFFER_SIZE); + ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)color_p); + + s_frame_done = false; + + while (s_frame_done == false) { + } + + lv_disp_flush_ready(disp_drv); +} + +RAMFUNCTION_SECTION_CODE(void app_lvgl_read_cb(lv_indev_drv_t *drv, lv_indev_data_t *data)) { + uint8_t t_count = 5; + touch_point_t t_arr[5]; + + GT911_GetMultiTouch(&s_ctp_handle, &t_count, t_arr); + + for (uint8_t i = 0; i < t_count; i++) { + if (t_arr[i].valid && (t_arr[i].touchID == 0U)) { + data->point.x = t_arr[i].x; + data->point.y = t_arr[i].y; + + data->state = LV_INDEV_STATE_PRESSED; + + goto found_track; + } + } + data->state = LV_INDEV_STATE_RELEASED; +found_track: +} + +int app_lvgl_init(void) { + BOARD_InitLCDPins(); + + CLOCK_EnableClock(kCLOCK_Lpi2c1); + + lpi2c_master_config_t i2c_cfg; + + i2c_cfg.baudRate_Hz = 400000; + + LPI2C_MasterGetDefaultConfig(&i2c_cfg); + + LPI2C_MasterInit(LPI2C1, &i2c_cfg, 24000000); + + const gt911_config_t ctp_config = { + .i2cAddrMode = kGT911_I2cAddrAny, + .I2C_SendFunc = app_lvgl_i2c_send, + .I2C_ReceiveFunc = app_lvgl_i2c_recv, + .intPinFunc = app_lvgl_ctp_int, + .pullResetPinFunc = app_lvgl_ctp_reset, + .intTrigMode = kGT911_IntFallingEdge, + .touchPointNum = 5, + .timeDelayMsFunc = app_lvgl_delay_ms, + }; + + GT911_Init(&s_ctp_handle, &ctp_config); + + const elcdif_rgb_mode_config_t rgb_cfg = { + .panelWidth = APP_LCD_WIDTH, + .panelHeight = APP_LCD_HEIGHT, + .hsw = APP_LCD_HSW, + .hfp = APP_LCD_HFP, + .hbp = APP_LCD_HBP, + .vsw = APP_LCD_VSW, + .vfp = APP_LCD_VFP, + .vbp = APP_LCD_VBP, + .polarityFlags = APP_LCD_FLAGS, + .bufferAddr = (uint32_t)s_lcd_buffers[1], + .pixelFormat = kELCDIF_PixelFormatRGB565, + .dataBus = kELCDIF_DataBus16Bit, + }; + + ELCDIF_RgbModeInit(LCDIF, &rgb_cfg); + + ELCDIF_EnableInterrupts(LCDIF, kELCDIF_CurFrameDoneInterruptEnable); + + NVIC_SetPriority(LCDIF_IRQn, 5); + EnableIRQ(LCDIF_IRQn); + + ELCDIF_RgbModeStart(LCDIF); + + app_lvgl_backlight(true); + + s_frame_done = true; + + lv_init(); + lv_disp_draw_buf_init(&s_lcd_draw_buf, s_lcd_buffers[0], s_lcd_buffers[1], APP_LCD_WIDTH * APP_LCD_HEIGHT); + lv_disp_drv_init(&s_lcd_drv); + + s_lcd_drv.hor_res = APP_LCD_WIDTH; + s_lcd_drv.ver_res = APP_LCD_HEIGHT; + s_lcd_drv.draw_buf = &s_lcd_draw_buf; + s_lcd_drv.flush_cb = app_lvgl_flush_cb; + s_lcd_drv.full_refresh = true; + + lv_disp_drv_register(&s_lcd_drv); + + lv_indev_drv_init(&s_ctp_drv); + s_ctp_drv.type = LV_INDEV_TYPE_POINTER; + s_ctp_drv.read_cb = app_lvgl_read_cb; + + lv_indev_drv_register(&s_ctp_drv); + + if (xTaskCreate(app_lvgl_task, "LVGL", 8192, NULL, 4, NULL) != pdPASS) { + return -1; + } + + return 0; +} + +uint32_t app_lvgl_ticks(void) { + return xTaskGetTickCount(); +} + +static void app_lvgl_task(void *parameters) { + for (;;) { + TickType_t t_start = xTaskGetTickCount(); + lv_timer_handler(); + TickType_t t_end = xTaskGetTickCount(); + + if (t_end - t_start < 10) { + vTaskDelay(10 - (t_end - t_start)); + } + } +} + +void LCDIF_IRQHandler(void) { + const uint32_t status = ELCDIF_GetInterruptStatus(LCDIF); + ELCDIF_ClearInterruptStatus(LCDIF, status); + + if (status & kELCDIF_CurFrameDone) { + s_frame_done = true; + } + SDK_ISR_EXIT_BARRIER; +} \ No newline at end of file diff --git a/src/main.c b/src/main.c index 4c63a63..6f77867 100644 --- a/src/main.c +++ b/src/main.c @@ -1,3 +1,4 @@ +/* Board */ #include "board.h" #include "clock_config.h" #include "peripherals.h" @@ -6,18 +7,41 @@ /* Debug console */ #include "fsl_debug_console.h" +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" + +/* LVGL */ +#include "lvgl.h" +#include "lv_demos.h" + +/* App */ +#include "app_lvgl.h" + +__attribute__((section(".mempool"))) uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + int main(void) { BOARD_InitBootPins(); BOARD_InitBootClocks(); - BOARD_InitBootPeripherals(); - BOARD_ConfigMPU(); BOARD_InitDebugConsole(); + BOARD_InitBootPeripherals(); + + CLOCK_EnableClock(kCLOCK_Ocram); + + BOARD_ConfigMPU(); + CLOCK_SetMode(kCLOCK_ModeRun); PRINTF("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq()); + app_lvgl_init(); + + lv_demo_benchmark(); + + vTaskStartScheduler(); + for (;;) { __WFI(); } diff --git a/xip/fire_rt1052_pro_flexspi_nor_config.c b/xip/fire_rt1052_pro_flexspi_nor_config.c index 7de28f0..7634dd3 100644 --- a/xip/fire_rt1052_pro_flexspi_nor_config.c +++ b/xip/fire_rt1052_pro_flexspi_nor_config.c @@ -38,7 +38,7 @@ const flexspi_nor_config_t spiflash_config = { .busyBitPolarity = 1U, .lookupTable = { // Fast read quad IO (EBh) [NOR_CMD_LUT_SEQ_IDX_READ] - [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20), [4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04), [4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),