diff --git a/.drone.yml b/.drone.yml new file mode 100644 index 0000000..63eeaa8 --- /dev/null +++ b/.drone.yml @@ -0,0 +1,17 @@ +--- +kind: pipeline +type: docker +name: Build + +steps: + - name: Submodules + image: alpine/git + commands: + - git submodule update --init --recursive + + - name: Build + image: "git.minori.work/embedded_sdk/embedded-builder-arm:latest" + commands: + - mkdir build && cd build + - cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake .. + - make fire_rt1052_pro_template_FLASH.elf diff --git a/CMakeLists.txt b/CMakeLists.txt index dc88217..9c017c6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -105,6 +105,7 @@ set(TARGET_C_DEFINES "PRINTF_ADVANCED_ENABLE=1" "PRINTF_FLOAT_ENABLE=1" "SERIAL_PORT_TYPE_UART" + "SDK_DEBUGCONSOLE_UART=1" "__STARTUP_CLEAR_BSS" "__STARTUP_INITIALIZE_NONCACHEDATA" ) diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex index 6d55fc0..b9cc9f2 100644 --- a/MIMXRT1052xxxxB.mex +++ b/MIMXRT1052xxxxB.mex @@ -1,5 +1,5 @@ - + MIMXRT1052xxxxB MIMXRT1052DVL6B @@ -17,13 +17,13 @@ false - + - 13.0.1 + 15.0.1 @@ -63,7 +63,7 @@ true - + true @@ -92,7 +92,7 @@ true - + true @@ -121,7 +121,7 @@ true - + true @@ -155,7 +155,7 @@ true - + true @@ -200,7 +200,7 @@ true - + true @@ -233,7 +233,7 @@ true - + true @@ -301,7 +301,7 @@ true - + true @@ -359,7 +359,7 @@ true - + true @@ -392,7 +392,7 @@ true - + true @@ -437,27 +437,27 @@ true - + true - + true - + true - + true - + true @@ -554,7 +554,7 @@ true - + true @@ -591,7 +591,7 @@ true - + true @@ -633,7 +633,7 @@ true - + true @@ -662,7 +662,7 @@ true - + true @@ -691,7 +691,7 @@ true - + true @@ -714,13 +714,13 @@ - + - 13.0.1 + 15.0.1 @@ -984,7 +984,7 @@ - 13.0.1 + 15.0.1 c_array @@ -995,13 +995,13 @@ - + - 13.0.1 + 15.0.1 @@ -1023,6 +1023,7 @@ + diff --git a/SDK b/SDK index 75f3218..6baf442 160000 --- a/SDK +++ b/SDK @@ -1 +1 @@ -Subproject commit 75f32185d29dbd53f964f34b51e332c04700871d +Subproject commit 6baf4427ce5ad19f990c7ab53f7a75d331a280a3 diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake index a9ef74e..5882a22 100644 --- a/arm-none-eabi.cmake +++ b/arm-none-eabi.cmake @@ -11,7 +11,7 @@ set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size) set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16") set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16") -set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments") +set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage") # Make CMake happy about those compilers set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") diff --git a/board/clock_config.c b/board/clock_config.c index 2b11cda..fd6342f 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v13.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 15.0.1 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" diff --git a/board/clock_config.h b/board/clock_config.h index 379e02f..0f84936 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -36,52 +36,52 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration. */ @@ -119,52 +119,52 @@ void Board_BootClockPLL600MHz(void); #define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration. */ @@ -202,52 +202,52 @@ void Board_BootClockPLL480MHz(void); #define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration. */ diff --git a/board/dcd.c b/board/dcd.c index b4902c3..6d51c6f 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -24,7 +24,7 @@ product: DCDx v3.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 15.0.1 output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ diff --git a/board/peripherals.c b/board/peripherals.c index f35aa88..a824909 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -6,11 +6,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Peripherals v12.0 +product: Peripherals v14.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 15.0.1 functionalGroups: - name: BOARD_InitPeripherals UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830 @@ -25,6 +25,7 @@ component: - global_system_definitions: - user_definitions: '' - user_includes: '' + - global_init: '' * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* diff --git a/board/pin_mux.c b/board/pin_mux.c index 2aed03a..9129401 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.0 +product: Pins v15.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 13.0.1 +processor_version: 15.0.1 pin_labels: - {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B} - {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G} @@ -74,7 +74,6 @@ void BOARD_InitUARTDbgPins(void) { #endif } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSWDPins: @@ -98,7 +97,6 @@ void BOARD_InitSWDPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_JTAG_TCK, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitFlexSPIPins: @@ -160,7 +158,6 @@ void BOARD_InitFlexSPIPins(void) { #endif } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InituSDPins: @@ -205,7 +202,6 @@ void BOARD_InituSDPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSDWiFiPins: @@ -237,7 +233,6 @@ void BOARD_InitSDWiFiPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSEMCPins: @@ -407,7 +402,6 @@ void BOARD_InitSEMCPins(void) { #endif } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLCDPins: @@ -478,7 +472,6 @@ void BOARD_InitLCDPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCodecPins: @@ -510,7 +503,6 @@ void BOARD_InitCodecPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCSIPins: @@ -558,7 +550,6 @@ void BOARD_InitCSIPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_CSI_PIXCLK, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSYSPins: @@ -653,7 +644,6 @@ void BOARD_InitSYSPins(void) { #endif } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitENETPins: @@ -693,7 +683,6 @@ void BOARD_InitENETPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitBasicIOPins: @@ -736,7 +725,6 @@ void BOARD_InitBasicIOPins(void) { IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitI2C1Pins: @@ -760,7 +748,6 @@ void BOARD_InitI2C1Pins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCAN2Pins: @@ -784,7 +771,6 @@ void BOARD_InitCAN2Pins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSPDIFPins: @@ -807,7 +793,6 @@ void BOARD_InitSPDIFPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_SPDIF_OUT, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_SPDIF_IN, 0U); } - /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/src/main.c b/src/main.c index 4c63a63..fd199ab 100644 --- a/src/main.c +++ b/src/main.c @@ -1,22 +1,23 @@ +#include + +/* Board */ #include "board.h" #include "clock_config.h" #include "peripherals.h" #include "pin_mux.h" -/* Debug console */ -#include "fsl_debug_console.h" - int main(void) { + BOARD_ConfigMPU(); + BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); - BOARD_ConfigMPU(); BOARD_InitDebugConsole(); CLOCK_SetMode(kCLOCK_ModeRun); - PRINTF("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq()); + printf("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq()); for (;;) { __WFI();