Removed on-board peripherals.
continuous-integration/drone/push Build is passing
Details
continuous-integration/drone/push Build is passing
Details
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
parent
34fb80830f
commit
bf572d66ff
GPG Key ID:
17F01E106F9F5E0A
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@ -1,8 +1,9 @@
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BasedOnStyle: Google
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IndentWidth: 4
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AlignConsecutiveMacros: AcrossEmptyLines
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AlignConsecutiveDeclarations: AcrossEmptyLines
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AlignConsecutiveAssignments: AcrossEmptyLinesAndComments
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AlignConsecutiveMacros: Consecutive
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AlignConsecutiveDeclarations: Consecutive
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AlignConsecutiveAssignments: Consecutive
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AllowShortFunctionsOnASingleLine: None
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BreakBeforeBraces: Custom
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BraceWrapping:
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AfterEnum: false
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1097
MIMXRT1052xxxxB.mex
1097
MIMXRT1052xxxxB.mex
File diff suppressed because it is too large
Load Diff
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@ -38,98 +38,128 @@ processor_version: 15.0.1
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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Board_BootClockPLL480MHz();
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}
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/*******************************************************************************
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******************* Configuration Board_BootClockPLL600MHz ********************
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******************** Configuration BOARD_BootClockPLL600M *********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: Board_BootClockPLL600MHz
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name: BOARD_BootClockPLL600M
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outputs:
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- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
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- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz}
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- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
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- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
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- {id: CLK_1M.outFreq, value: 1 MHz}
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- {id: CLK_24M.outFreq, value: 24 MHz}
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- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
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- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
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- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
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- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
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- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 5 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 5 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
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- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
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- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
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- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
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- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
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- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
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- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
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- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
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- {id: MQS_MCLK.outFreq, value: 3 MHz}
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- {id: PERCLK_CLK_ROOT.outFreq, value: 5 MHz}
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- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
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- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
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- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
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- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
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- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
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- {id: SAI1_MCLK2.outFreq, value: 3 MHz}
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- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz}
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- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz}
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- {id: SAI2_MCLK1.outFreq, value: 3 MHz}
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- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz}
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- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz}
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- {id: SAI3_MCLK1.outFreq, value: 3 MHz}
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- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz}
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- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
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- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz}
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- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
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- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
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- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
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- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
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- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
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- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
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settings:
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- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
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- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
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- {id: CCM.FLEXSPI_PODF.scale, value: '1'}
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- {id: CCM.LPSPI_PODF.scale, value: '5'}
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- {id: CCM.PERCLK_PODF.scale, value: '30'}
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- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL}
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- {id: CCM.SEMC_PODF.scale, value: '3', locked: true}
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- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
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- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
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- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
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- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
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- {id: CCM.SEMC_PODF.scale, value: '8'}
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- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
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- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
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- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
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- {id: CCM_ANALOG.PLL2.denom, value: '1'}
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- {id: CCM_ANALOG.PLL2.num, value: '0'}
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- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
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- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
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- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
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- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
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- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
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- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
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- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
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- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
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- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
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- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
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- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
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- {id: CCM_ANALOG.PLL4.denom, value: '50'}
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- {id: CCM_ANALOG.PLL4.div, value: '47'}
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- {id: CCM_ANALOG.PLL5.denom, value: '1'}
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- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
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- {id: CCM_ANALOG.PLL5.num, value: '0'}
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- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
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- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
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- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
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- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
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- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
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- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
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sources:
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- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for Board_BootClockPLL600MHz configuration
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* Variables for BOARD_BootClockPLL600M configuration
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******************************************************************************/
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const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz =
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const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL600M =
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{
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.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz =
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const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL600M =
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{
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz =
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const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL600M =
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{
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.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
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.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
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.loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
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.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL600M =
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{
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.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.postDivider = 8, /* Divider after PLL */
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.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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/*******************************************************************************
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* Code for Board_BootClockPLL600MHz configuration
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* Code for BOARD_BootClockPLL600M configuration
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******************************************************************************/
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void Board_BootClockPLL600MHz(void)
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void BOARD_BootClockPLL600M(void)
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{
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/* Init RTC OSC clock frequency. */
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CLOCK_SetRtcXtalFreq(32768U);
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/* Enable 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
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/* Use free 1MHz clock output. */
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@ -174,7 +204,7 @@ void Board_BootClockPLL600MHz(void)
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CLOCK_DisableClock(kCLOCK_Gpt2S);
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CLOCK_DisableClock(kCLOCK_Pit);
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/* Set PERCLK_PODF. */
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CLOCK_SetDiv(kCLOCK_PerclkDiv, 29);
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CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
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/* Disable USDHC1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc1);
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/* Set USDHC1_PODF. */
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@ -194,11 +224,11 @@ void Board_BootClockPLL600MHz(void)
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/* Disable Semc clock gate. */
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CLOCK_DisableClock(kCLOCK_Semc);
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/* Set SEMC_PODF. */
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CLOCK_SetDiv(kCLOCK_SemcDiv, 2);
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CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
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/* Set Semc alt clock source. */
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
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/* Set Semc clock source. */
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CLOCK_SetMux(kCLOCK_SemcMux, 1);
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CLOCK_SetMux(kCLOCK_SemcMux, 0);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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@ -207,9 +237,9 @@ void Board_BootClockPLL600MHz(void)
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/* Disable Flexspi clock gate. */
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CLOCK_DisableClock(kCLOCK_FlexSpi);
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/* Set FLEXSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
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/* Set Flexspi clock source. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
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CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
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#endif
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/* Disable CSI clock gate. */
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CLOCK_DisableClock(kCLOCK_Csi);
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@ -231,7 +261,7 @@ void Board_BootClockPLL600MHz(void)
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/* Set TRACE_PODF. */
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CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
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/* Set Trace clock source. */
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CLOCK_SetMux(kCLOCK_TraceMux, 2);
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CLOCK_SetMux(kCLOCK_TraceMux, 0);
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/* Disable SAI1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai1);
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/* Set SAI1_CLK_PRED. */
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@ -321,7 +351,7 @@ void Board_BootClockPLL600MHz(void)
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/* Set Pll3 sw clock source. */
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CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
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/* Init ARM PLL. */
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CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL600MHz);
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CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockPLL600M);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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@ -330,7 +360,7 @@ void Board_BootClockPLL600MHz(void)
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#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
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#endif
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/* Init System PLL. */
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CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL600MHz);
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CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockPLL600M);
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/* Init System pfd0. */
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
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/* Init System pfd1. */
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@ -344,12 +374,18 @@ void Board_BootClockPLL600MHz(void)
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* DeInit Usb1 PLL. */
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CLOCK_DeinitUsb1Pll();
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/* Bypass Usb1 PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
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/* Enable Usb1 PLL output. */
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CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
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/* Init Usb1 PLL. */
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CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockPLL600M);
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/* Init Usb1 pfd0. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
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/* Init Usb1 pfd1. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
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/* Init Usb1 pfd2. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
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/* Init Usb1 pfd3. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
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/* Disable Usb1 PLL output for USBPHY1. */
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CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
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#endif
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/* DeInit Audio PLL. */
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CLOCK_DeinitAudioPll();
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@ -360,18 +396,35 @@ void Board_BootClockPLL600MHz(void)
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CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
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/* Enable Audio PLL output. */
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CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
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/* DeInit Video PLL. */
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CLOCK_DeinitVideoPll();
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/* Bypass Video PLL. */
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CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
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/* Set divider for Video PLL. */
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CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
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/* Enable Video PLL output. */
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CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
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/* Init Enet PLL. */
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CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL600MHz);
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/* Init Video PLL. */
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uint32_t pllVideo;
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/* Disable Video PLL output before initial Video PLL. */
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CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
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/* Bypass PLL first */
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CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
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CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
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CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
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CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||||
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||||
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
/* Disable bypass for Video PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
|
|
@ -428,99 +481,130 @@ void Board_BootClockPLL600MHz(void)
|
|||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK;
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL600M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration Board_BootClockPLL480MHz ********************
|
||||
******************** Configuration BOARD_BootClockPLL528M *********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: Board_BootClockPLL480MHz
|
||||
called_from_default_init: true
|
||||
name: BOARD_BootClockPLL528M
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 480 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz}
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 4 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 4 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 120 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 960 MHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 3 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 4 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '1'}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5'}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '30'}
|
||||
- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0'}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
|
||||
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
|
||||
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
|
||||
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for Board_BootClockPLL480MHz configuration
|
||||
* Variables for BOARD_BootClockPLL528M configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz =
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL528M =
|
||||
{
|
||||
.loopDivider = 80, /* PLL loop divider, Fout = Fin * 40 */
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz =
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL528M =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz =
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL528M =
|
||||
{
|
||||
.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
|
||||
.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
|
||||
.loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL528M =
|
||||
{
|
||||
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.postDivider = 8, /* Divider after PLL */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for Board_BootClockPLL480MHz configuration
|
||||
* Code for BOARD_BootClockPLL528M configuration
|
||||
******************************************************************************/
|
||||
void Board_BootClockPLL480MHz(void)
|
||||
void BOARD_BootClockPLL528M(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
|
|
@ -559,7 +643,7 @@ void Board_BootClockPLL480MHz(void)
|
|||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 29);
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
|
|
@ -579,11 +663,11 @@ void Board_BootClockPLL480MHz(void)
|
|||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 2);
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
|
|
@ -592,9 +676,9 @@ void Board_BootClockPLL480MHz(void)
|
|||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
|
||||
#endif
|
||||
/* Disable CSI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Csi);
|
||||
|
|
@ -616,7 +700,7 @@ void Board_BootClockPLL480MHz(void)
|
|||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
|
|
@ -706,7 +790,7 @@ void Board_BootClockPLL480MHz(void)
|
|||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL480MHz);
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockPLL528M);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
|
|
@ -715,7 +799,7 @@ void Board_BootClockPLL480MHz(void)
|
|||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL480MHz);
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockPLL528M);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
|
|
@ -729,12 +813,18 @@ void Board_BootClockPLL480MHz(void)
|
|||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* DeInit Usb1 PLL. */
|
||||
CLOCK_DeinitUsb1Pll();
|
||||
/* Bypass Usb1 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
|
||||
/* Enable Usb1 PLL output. */
|
||||
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockPLL528M);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
|
|
@ -745,381 +835,35 @@ void Board_BootClockPLL480MHz(void)
|
|||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* DeInit Video PLL. */
|
||||
CLOCK_DeinitVideoPll();
|
||||
/* Bypass Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
|
||||
/* Set divider for Video PLL. */
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
|
||||
/* Enable Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Init Enet PLL. */
|
||||
CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL480MHz);
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||||
/* Enable Usb2 PLL output. */
|
||||
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Ref clock source. */
|
||||
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
|
||||
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
|
||||
/* Backward compatibility for original bitfield name */
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
|
||||
#else
|
||||
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
|
||||
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockXT24MHz *********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockXT24MHz
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 6 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 6 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 6 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 24 MHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 3 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 6 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 3 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 3 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
settings:
|
||||
- {id: CCM.ARM_PODF.scale, value: '1'}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '1'}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0'}
|
||||
- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_SYS_POWERDOWN_CFG, value: 'Yes'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockXT24MHz configuration
|
||||
******************************************************************************/
|
||||
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz =
|
||||
/* Init Video PLL. */
|
||||
uint32_t pllVideo;
|
||||
/* Disable Video PLL output before initial Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Bypass PLL first */
|
||||
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
|
||||
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
|
||||
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||||
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||||
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||||
{
|
||||
.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
|
||||
.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
|
||||
.loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockXT24MHz configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockXT24MHz(void)
|
||||
{
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar3);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 0);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
|
||||
#endif
|
||||
/* Disable CSI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Csi);
|
||||
/* Set CSI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||
/* Set Csi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable LCDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||||
/* Set LCDIF_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
|
||||
/* Set LCDIF_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
|
||||
/* Set Lcdif pre clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Disable Flexio2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||||
/* Set FLEXIO2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||
/* Set FLEXIO2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||
/* Set Flexio2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* DeInit ARM PLL. */
|
||||
CLOCK_DeinitArmPll();
|
||||
/* Bypass ARM PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1);
|
||||
/* Enable ARM PLL output. */
|
||||
CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK;
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* DeInit System PLL. */
|
||||
CLOCK_DeinitSysPll();
|
||||
/* Bypass System PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1);
|
||||
/* Enable System PLL output. */
|
||||
CCM_ANALOG->PLL_SYS |= CCM_ANALOG_PLL_SYS_ENABLE_MASK;
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* DeInit Usb1 PLL. */
|
||||
CLOCK_DeinitUsb1Pll();
|
||||
/* Bypass Usb1 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
|
||||
/* Enable Usb1 PLL output. */
|
||||
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* DeInit Video PLL. */
|
||||
CLOCK_DeinitVideoPll();
|
||||
/* Bypass Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
|
||||
/* Set divider for Video PLL. */
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
|
||||
/* Enable Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Init Enet PLL. */
|
||||
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockXT24MHz);
|
||||
}
|
||||
/* Disable bypass for Video PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
|
|
@ -1127,7 +871,7 @@ void BOARD_BootClockXT24MHz(void)
|
|||
/* Enable Usb2 PLL output. */
|
||||
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 0);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
|
|
@ -1176,6 +920,6 @@ void BOARD_BootClockXT24MHz(void)
|
|||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK;
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL528M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,73 +28,76 @@ void BOARD_InitBootClocks(void);
|
|||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration Board_BootClockPLL600MHz ********************
|
||||
******************** Configuration BOARD_BootClockPLL600M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for Board_BootClockPLL600MHz configuration
|
||||
* Definitions for BOARD_BootClockPLL600M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
|
||||
#define BOARD_BOOTCLOCKPLL600M_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600M_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600M_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL600M_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL600M_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600M_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKPLL600M_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600M_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL600M_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKPLL600M_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKPLL600M_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
|
||||
/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration.
|
||||
/*! @brief Arm PLL set for BOARD_BootClockPLL600M configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz;
|
||||
/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration.
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL600M;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockPLL600M configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz;
|
||||
/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration.
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL600M;
|
||||
/*! @brief Sys PLL for BOARD_BootClockPLL600M configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz;
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL600M;
|
||||
/*! @brief Video PLL set for BOARD_BootClockPLL600M configuration.
|
||||
*/
|
||||
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL600M;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for Board_BootClockPLL600MHz configuration
|
||||
* API for BOARD_BootClockPLL600M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -104,80 +107,83 @@ extern "C" {
|
|||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void Board_BootClockPLL600MHz(void);
|
||||
void BOARD_BootClockPLL600M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration Board_BootClockPLL480MHz ********************
|
||||
******************** Configuration BOARD_BootClockPLL528M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for Board_BootClockPLL480MHz configuration
|
||||
* Definitions for BOARD_BootClockPLL528M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL /* Clock consumers of LVDS1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_AHB_CLK_ROOT 528000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
|
||||
#define BOARD_BOOTCLOCKPLL528M_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL528M_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL528M_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKPLL528M_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKPLL528M_GPT1_IPG_CLK_HIGHFREQ 66000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_GPT2_IPG_CLK_HIGHFREQ 66000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_IPG_CLK_ROOT 132000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
|
||||
#define BOARD_BOOTCLOCKPLL528M_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_PERCLK_CLK_ROOT 66000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKPLL528M_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SEMC_CLK_ROOT 66000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL528M_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKPLL528M_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKPLL528M_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKPLL528M_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
|
||||
/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration.
|
||||
/*! @brief Arm PLL set for BOARD_BootClockPLL528M configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz;
|
||||
/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration.
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL528M;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockPLL528M configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz;
|
||||
/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration.
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL528M;
|
||||
/*! @brief Sys PLL for BOARD_BootClockPLL528M configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz;
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL528M;
|
||||
/*! @brief Video PLL set for BOARD_BootClockPLL528M configuration.
|
||||
*/
|
||||
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL528M;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for Board_BootClockPLL480MHz configuration
|
||||
* API for BOARD_BootClockPLL528M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -187,84 +193,7 @@ extern "C" {
|
|||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void Board_BootClockPLL480MHz(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockXT24MHz *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockXT24MHz configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL /* Clock consumers of LVDS1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
|
||||
/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockXT24MHz configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockXT24MHz(void);
|
||||
void BOARD_BootClockPLL528M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
266
board/dcd.c
266
board/dcd.c
|
|
@ -33,9 +33,271 @@ const uint8_t dcd_data[] = {
|
|||
/* Tag */
|
||||
0xD2,
|
||||
/* Image Length */
|
||||
0x00, 0x04,
|
||||
0x04, 0x10,
|
||||
/* Version */
|
||||
0x41
|
||||
0x41,
|
||||
|
||||
/* COMMANDS */
|
||||
|
||||
/* group: 'Imported Commands' */
|
||||
/* #1.1-113, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x03, 0x8C, 0x04,
|
||||
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B,
|
||||
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
|
||||
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
|
||||
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||
/* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
|
||||
/* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
|
||||
/* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
|
||||
/* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
|
||||
/* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
|
||||
/* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
|
||||
/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07,
|
||||
/* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||
/* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||
/* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||
/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
/* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||
/* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x1C, 0x04,
|
||||
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30,
|
||||
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
};
|
||||
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||
|
||||
|
|
|
|||
736
board/pin_mux.c
736
board/pin_mux.c
|
|
@ -21,6 +21,11 @@ pin_labels:
|
|||
- {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: CSI_RST, identifier: CSI_RST}
|
||||
- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BUZZER, identifier: BUZZER}
|
||||
- {pin_num: L6, pin_signal: WAKEUP, label: WAKEUP, identifier: WAKEUP}
|
||||
- {pin_num: D11, pin_signal: GPIO_B1_03, label: RST, identifier: RST}
|
||||
- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LEDB, identifier: LEDB}
|
||||
- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: LEDR, identifier: LEDR}
|
||||
- {pin_num: M13, pin_signal: GPIO_AD_B1_09, label: LEDG, identifier: LEDG}
|
||||
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: LEDA, identifier: LEDA}
|
||||
power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH: '3.3', DCDC_SENSE: '1.25', NVCC_EMC: '3.3', NVCC_GPIO: '3.3', NVCC_SD0: '3.3', NVCC_SD1: '3.3',
|
||||
VDDA_ADC_3P3: '3.3', VDD_HIGH_CAP: '1.1', VDD_HIGH_IN: '3.3', VDD_SNVS_CAP: '1.1', VDD_SNVS_IN: '3.3', VDD_SOC_IN: '1.25', VDD_USB_CAP: '2.5'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
|
|
@ -28,7 +33,6 @@ power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH:
|
|||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
|
|
@ -38,14 +42,12 @@ power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH:
|
|||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitUARTDbgPins();
|
||||
BOARD_InitSWDPins();
|
||||
BOARD_InitFlexSPIPins();
|
||||
BOARD_InitDbgUARTPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitUARTDbgPins:
|
||||
BOARD_InitDbgUARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
|
||||
|
|
@ -55,11 +57,11 @@ BOARD_InitUARTDbgPins:
|
|||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitUARTDbgPins
|
||||
* Function Name : BOARD_InitDbgUARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitUARTDbgPins(void) {
|
||||
void BOARD_InitDbgUARTPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
|
|
@ -73,726 +75,6 @@ void BOARD_InitUARTDbgPins(void) {
|
|||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWDPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: E14, peripheral: JTAG, signal: TMS, pin_signal: GPIO_AD_B0_06}
|
||||
- {pin_num: F12, peripheral: JTAG, signal: TCK, pin_signal: GPIO_AD_B0_07}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWDPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSWDPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_JTAG_TMS, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_JTAG_TCK, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitFlexSPIPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
|
||||
- {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
|
||||
- {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
|
||||
- {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
|
||||
- {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
|
||||
- {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
|
||||
- {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitFlexSPIPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitFlexSPIPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InituSDPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
|
||||
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
|
||||
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
|
||||
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
|
||||
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
|
||||
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
|
||||
- {pin_num: G14, peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, gpio_init_state: 'true'}
|
||||
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InituSDPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InituSDPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
/* GPIO configuration of USDHC1_PWR on GPIO_AD_B0_05 (pin G14) */
|
||||
gpio_pin_config_t USDHC1_PWR_config = {
|
||||
.direction = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_AD_B0_05 (pin G14) */
|
||||
GPIO_PinInit(GPIO1, 5U, &USDHC1_PWR_config);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSDWiFiPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: N3, peripheral: USDHC2, signal: usdhc_cmd, pin_signal: GPIO_SD_B1_05}
|
||||
- {pin_num: P2, peripheral: USDHC2, signal: usdhc_clk, pin_signal: GPIO_SD_B1_04}
|
||||
- {pin_num: M4, peripheral: USDHC2, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B1_03}
|
||||
- {pin_num: M3, peripheral: USDHC2, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B1_02}
|
||||
- {pin_num: M5, peripheral: USDHC2, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B1_01}
|
||||
- {pin_num: L5, peripheral: USDHC2, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B1_00}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSDWiFiPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSDWiFiPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSEMCPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
|
||||
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
|
||||
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
|
||||
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
|
||||
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
|
||||
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
|
||||
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
|
||||
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
|
||||
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
|
||||
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
|
||||
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
|
||||
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
|
||||
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
|
||||
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
|
||||
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
|
||||
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
|
||||
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
|
||||
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
|
||||
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
|
||||
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
|
||||
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
|
||||
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
|
||||
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
|
||||
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
|
||||
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
|
||||
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
|
||||
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
|
||||
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
|
||||
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
|
||||
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
|
||||
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
|
||||
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
|
||||
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
|
||||
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
|
||||
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
|
||||
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
|
||||
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
|
||||
- {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
|
||||
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
|
||||
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
|
||||
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSEMCPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSEMCPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
|
||||
#endif
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
|
||||
#endif
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
|
||||
#endif
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLCDPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
|
||||
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
|
||||
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
|
||||
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
|
||||
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
|
||||
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
|
||||
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
|
||||
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
|
||||
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
|
||||
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
|
||||
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
|
||||
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
|
||||
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
|
||||
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
|
||||
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
|
||||
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
|
||||
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
|
||||
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
|
||||
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
|
||||
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
|
||||
- {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, direction: OUTPUT, gpio_init_state: 'true'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLCDPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitLCDPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
/* GPIO configuration of LCD_RST on GPIO_AD_B0_02 (pin M11) */
|
||||
gpio_pin_config_t LCD_RST_config = {
|
||||
.direction = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */
|
||||
GPIO_PinInit(GPIO1, 2U, &LCD_RST_config);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitCodecPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: G12, peripheral: SAI1, signal: sai_tx_bclk, pin_signal: GPIO_AD_B1_14}
|
||||
- {pin_num: J14, peripheral: SAI1, signal: sai_tx_sync, pin_signal: GPIO_AD_B1_15}
|
||||
- {pin_num: H11, peripheral: SAI1, signal: sai_tx_data0, pin_signal: GPIO_AD_B1_13}
|
||||
- {pin_num: H12, peripheral: SAI1, signal: sai_rx_data0, pin_signal: GPIO_AD_B1_12}
|
||||
- {pin_num: M13, peripheral: SAI1, signal: sai_mclk, pin_signal: GPIO_AD_B1_09}
|
||||
- {pin_num: H13, peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitCodecPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitCodecPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitCSIPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
|
||||
- {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
|
||||
- {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
|
||||
- {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
|
||||
- {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
|
||||
- {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
|
||||
- {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
|
||||
- {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
|
||||
- {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
|
||||
- {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
|
||||
- {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
|
||||
- {pin_num: D13, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_B1_12}
|
||||
- {pin_num: M14, peripheral: GPIO1, signal: 'gpio_io, 00', pin_signal: GPIO_AD_B0_00, identifier: CSI_PDN}
|
||||
- {pin_num: H10, peripheral: GPIO1, signal: 'gpio_io, 01', pin_signal: GPIO_AD_B0_01}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitCSIPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitCSIPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_GPIO1_IO01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_CSI_PIXCLK, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSYSPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: N1, peripheral: SUPPLY, signal: 'DCDC_GND, 0', pin_signal: DCDC_GND0}
|
||||
- {pin_num: N2, peripheral: SUPPLY, signal: 'DCDC_GND, 1', pin_signal: DCDC_GND1}
|
||||
- {pin_num: L1, peripheral: SUPPLY, signal: 'DCDC_IN, 0', pin_signal: DCDC_IN0}
|
||||
- {pin_num: L2, peripheral: SUPPLY, signal: 'DCDC_IN, 1', pin_signal: DCDC_IN1}
|
||||
- {pin_num: K4, peripheral: SUPPLY, signal: dcdc_in_q, pin_signal: DCDC_IN_Q}
|
||||
- {pin_num: M1, peripheral: SUPPLY, signal: 'DCDC_LP, 0', pin_signal: DCDC_LP0}
|
||||
- {pin_num: M2, peripheral: SUPPLY, signal: 'DCDC_LP, 1', pin_signal: DCDC_LP1}
|
||||
- {pin_num: K3, peripheral: SUPPLY, signal: dcdc_pswitch, pin_signal: DCDC_PSWITCH}
|
||||
- {pin_num: J5, peripheral: SUPPLY, signal: dcdc_sense, pin_signal: DCDC_SENSE}
|
||||
- {pin_num: N10, peripheral: SUPPLY, signal: gpanaio, pin_signal: GPANAIO}
|
||||
- {pin_num: K9, peripheral: SUPPLY, signal: ngnd_kel0, pin_signal: NGND_KEL0}
|
||||
- {pin_num: F5, peripheral: SUPPLY, signal: 'NVCC_EMC, 0', pin_signal: NVCC_EMC0}
|
||||
- {pin_num: E6, peripheral: SUPPLY, signal: 'NVCC_EMC, 1', pin_signal: NVCC_EMC1}
|
||||
- {pin_num: E9, peripheral: SUPPLY, signal: 'NVCC_GPIO, 0', pin_signal: NVCC_GPIO0}
|
||||
- {pin_num: F10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 1', pin_signal: NVCC_GPIO1}
|
||||
- {pin_num: J10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 2', pin_signal: NVCC_GPIO2}
|
||||
- {pin_num: P10, peripheral: SUPPLY, signal: nvcc_pll, pin_signal: NVCC_PLL}
|
||||
- {pin_num: J6, peripheral: SUPPLY, signal: nvcc_sd0, pin_signal: NVCC_SD0}
|
||||
- {pin_num: K5, peripheral: SUPPLY, signal: nvcc_sd1, pin_signal: NVCC_SD1}
|
||||
- {pin_num: K6, peripheral: SUPPLY, signal: test_mode, pin_signal: TEST_MODE}
|
||||
- {pin_num: N12, peripheral: SUPPLY, signal: usb_otg1_chd_b, pin_signal: USB_OTG1_CHD_B}
|
||||
- {pin_num: M8, peripheral: SUPPLY, signal: usb_otg1_dn, pin_signal: USB_OTG1_DN}
|
||||
- {pin_num: L8, peripheral: SUPPLY, signal: usb_otg1_dp, pin_signal: USB_OTG1_DP}
|
||||
- {pin_num: N6, peripheral: SUPPLY, signal: usb_otg1_vbus, pin_signal: USB_OTG1_VBUS}
|
||||
- {pin_num: N7, peripheral: SUPPLY, signal: usb_otg2_dn, pin_signal: USB_OTG2_DN}
|
||||
- {pin_num: P7, peripheral: SUPPLY, signal: usb_otg2_dp, pin_signal: USB_OTG2_DP}
|
||||
- {pin_num: P6, peripheral: SUPPLY, signal: usb_otg2_vbus, pin_signal: USB_OTG2_VBUS}
|
||||
- {pin_num: P12, peripheral: SUPPLY, signal: VDD_HIGH_IN, pin_signal: VDD_HIGH_IN}
|
||||
- {pin_num: P8, peripheral: SUPPLY, signal: VDD_HIGH_CAP, pin_signal: VDD_HIGH_CAP}
|
||||
- {pin_num: M10, peripheral: SUPPLY, signal: VDD_SNVS_CAP, pin_signal: VDD_SNVS_CAP}
|
||||
- {pin_num: M9, peripheral: SUPPLY, signal: VDD_SNVS_IN, pin_signal: VDD_SNVS_IN}
|
||||
- {pin_num: F6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 0', pin_signal: VDD_SOC_IN0}
|
||||
- {pin_num: G6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 1', pin_signal: VDD_SOC_IN1}
|
||||
- {pin_num: H6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 2', pin_signal: VDD_SOC_IN2}
|
||||
- {pin_num: F7, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 3', pin_signal: VDD_SOC_IN3}
|
||||
- {pin_num: F8, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 4', pin_signal: VDD_SOC_IN4}
|
||||
- {pin_num: F9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 5', pin_signal: VDD_SOC_IN5}
|
||||
- {pin_num: G9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 6', pin_signal: VDD_SOC_IN6}
|
||||
- {pin_num: H9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 7', pin_signal: VDD_SOC_IN7}
|
||||
- {pin_num: J9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 8', pin_signal: VDD_SOC_IN8}
|
||||
- {pin_num: N14, peripheral: SUPPLY, signal: VDDA_ADC_3P3, pin_signal: VDDA_ADC_3P3}
|
||||
- {pin_num: K8, peripheral: SUPPLY, signal: VDD_USB_CAP, pin_signal: VDD_USB_CAP}
|
||||
- {pin_num: A1, peripheral: SUPPLY, signal: 'VSS, 0', pin_signal: VSS0}
|
||||
- {pin_num: P1, peripheral: SUPPLY, signal: 'VSS, 1', pin_signal: VSS1}
|
||||
- {pin_num: E2, peripheral: SUPPLY, signal: 'VSS, 2', pin_signal: VSS2}
|
||||
- {pin_num: K2, peripheral: SUPPLY, signal: 'VSS, 3', pin_signal: VSS3}
|
||||
- {pin_num: B5, peripheral: SUPPLY, signal: 'VSS, 4', pin_signal: VSS4}
|
||||
- {pin_num: N5, peripheral: SUPPLY, signal: 'VSS, 5', pin_signal: VSS5}
|
||||
- {pin_num: G7, peripheral: SUPPLY, signal: 'VSS, 6', pin_signal: VSS6}
|
||||
- {pin_num: H7, peripheral: SUPPLY, signal: 'VSS, 7', pin_signal: VSS7}
|
||||
- {pin_num: J7, peripheral: SUPPLY, signal: 'VSS, 8', pin_signal: VSS8}
|
||||
- {pin_num: G8, peripheral: SUPPLY, signal: 'VSS, 9', pin_signal: VSS9}
|
||||
- {pin_num: H8, peripheral: SUPPLY, signal: 'VSS, 10', pin_signal: VSS10}
|
||||
- {pin_num: J8, peripheral: SUPPLY, signal: 'VSS, 11', pin_signal: VSS11}
|
||||
- {pin_num: N8, peripheral: SUPPLY, signal: 'VSS, 12', pin_signal: VSS12}
|
||||
- {pin_num: L9, peripheral: SUPPLY, signal: 'VSS, 13', pin_signal: VSS13}
|
||||
- {pin_num: B10, peripheral: SUPPLY, signal: 'VSS, 14', pin_signal: VSS14}
|
||||
- {pin_num: E13, peripheral: SUPPLY, signal: 'VSS, 15', pin_signal: VSS15}
|
||||
- {pin_num: K13, peripheral: SUPPLY, signal: 'VSS, 16', pin_signal: VSS16}
|
||||
- {pin_num: A14, peripheral: SUPPLY, signal: 'VSS, 17', pin_signal: VSS17}
|
||||
- {pin_num: P14, peripheral: SUPPLY, signal: 'VSS, 18', pin_signal: VSS18}
|
||||
- {pin_num: P13, peripheral: CCM, signal: CLK1_N, pin_signal: CCM_CLK1_N}
|
||||
- {pin_num: N13, peripheral: CCM, signal: CLK1_P, pin_signal: CCM_CLK1_P}
|
||||
- {pin_num: K7, peripheral: SNVS, signal: snvs_pmic_on_req, pin_signal: PMIC_ON_REQ}
|
||||
- {pin_num: M6, peripheral: SRC, signal: RESET_B, pin_signal: ONOFF}
|
||||
- {pin_num: M7, peripheral: SRC, signal: POR_B, pin_signal: POR_B}
|
||||
- {pin_num: P9, peripheral: XTALOSC24M, signal: rtc_xtalo, pin_signal: RTC_XTALO}
|
||||
- {pin_num: N9, peripheral: XTALOSC24M, signal: rtc_xtali, pin_signal: RTC_XTALI}
|
||||
- {pin_num: P11, peripheral: XTALOSC24M, signal: xtali, pin_signal: XTALI}
|
||||
- {pin_num: N11, peripheral: XTALOSC24M, signal: xtalo, pin_signal: XTALO}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSYSPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSYSPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
|
||||
|
||||
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
|
||||
IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ, 0U);
|
||||
#else
|
||||
IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ, 0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitENETPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: L12, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_AD_B1_04}
|
||||
- {pin_num: B14, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_B1_15}
|
||||
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
|
||||
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
|
||||
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
|
||||
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
|
||||
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
|
||||
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
|
||||
- {pin_num: B13, peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_B1_10}
|
||||
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitENETPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitENETPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_ENET_MDC, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_TX_CLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitBasicIOPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03, direction: OUTPUT}
|
||||
- {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBasicIOPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBasicIOPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
|
||||
|
||||
/* GPIO configuration of BUZZER on GPIO_AD_B0_03 (pin G11) */
|
||||
gpio_pin_config_t BUZZER_config = {
|
||||
.direction = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_AD_B0_03 (pin G11) */
|
||||
GPIO_PinInit(GPIO1, 3U, &BUZZER_config);
|
||||
|
||||
/* GPIO configuration of WAKEUP on WAKEUP (pin L6) */
|
||||
gpio_pin_config_t WAKEUP_config = {
|
||||
.direction = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on WAKEUP (pin L6) */
|
||||
GPIO_PinInit(GPIO5, 0U, &WAKEUP_config);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitI2C1Pins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01}
|
||||
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitI2C1Pins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitI2C1Pins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitCAN2Pins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
|
||||
- {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitCAN2Pins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitCAN2Pins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSPDIFPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: M12, peripheral: SPDIF, signal: spdif_in, pin_signal: GPIO_AD_B1_03}
|
||||
- {pin_num: L11, peripheral: SPDIF, signal: spdif_out, pin_signal: GPIO_AD_B1_02}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSPDIFPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSPDIFPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_SPDIF_OUT, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_SPDIF_IN, 0U);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
|
|||
190
board/pin_mux.h
190
board/pin_mux.h
|
|
@ -42,195 +42,7 @@ void BOARD_InitBootPins(void);
|
|||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitUARTDbgPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWDPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitFlexSPIPins(void);
|
||||
|
||||
/* GPIO_AD_B0_05 (coord G14), USDHC1_PWR */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_PERIPHERAL GPIO1 /*!< Peripheral name */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_CHANNEL 5U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO GPIO1 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN 5U /*!< GPIO pin number */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_PORT GPIO1 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_PIN 5U /*!< PORT pin number */
|
||||
#define BOARD_INITUSDPINS_USDHC1_PWR_PIN_MASK (1U << 5U) /*!< PORT pin mask */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InituSDPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSDWiFiPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSEMCPins(void);
|
||||
|
||||
/* GPIO_AD_B0_02 (coord M11), LCD_RST */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_PERIPHERAL GPIO1 /*!< Peripheral name */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_CHANNEL 2U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN 2U /*!< GPIO pin number */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_PORT GPIO1 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_PIN 2U /*!< PORT pin number */
|
||||
#define BOARD_INITLCDPINS_LCD_RST_PIN_MASK (1U << 2U) /*!< PORT pin mask */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLCDPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitCodecPins(void);
|
||||
|
||||
/* GPIO_AD_B0_00 (coord M14), CSI_ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_PERIPHERAL GPIO1 /*!< Peripheral name */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_CHANNEL 0U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN 0U /*!< GPIO pin number */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_PORT GPIO1 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_PIN 0U /*!< PORT pin number */
|
||||
#define BOARD_INITCSIPINS_CSI_PDN_PIN_MASK (1U << 0U) /*!< PORT pin mask */
|
||||
|
||||
/* GPIO_AD_B0_01 (coord H10), CSI_RST */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_PERIPHERAL GPIO1 /*!< Peripheral name */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_CHANNEL 1U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN 1U /*!< GPIO pin number */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN_MASK (1U << 1U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_PORT GPIO1 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_PIN 1U /*!< PORT pin number */
|
||||
#define BOARD_INITCSIPINS_CSI_RST_PIN_MASK (1U << 1U) /*!< PORT pin mask */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitCSIPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSYSPins(void);
|
||||
|
||||
/* GPIO_B1_07 (coord B12), LED_G */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITENETPINS_LED_G_PERIPHERAL ENET /*!< Peripheral name */
|
||||
#define BOARD_INITENETPINS_LED_G_SIGNAL enet_tx_data /*!< Signal name */
|
||||
#define BOARD_INITENETPINS_LED_G_CHANNEL 0U /*!< Signal channel */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitENETPins(void);
|
||||
|
||||
/* GPIO_AD_B0_03 (coord G11), BUZZER */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_PERIPHERAL GPIO1 /*!< Peripheral name */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_CHANNEL 3U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_GPIO GPIO1 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN 3U /*!< GPIO pin number */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_PORT GPIO1 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_PIN 3U /*!< PORT pin number */
|
||||
#define BOARD_INITBASICIOPINS_BUZZER_PIN_MASK (1U << 3U) /*!< PORT pin mask */
|
||||
|
||||
/* WAKEUP (coord L6), WAKEUP */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_PERIPHERAL GPIO5 /*!< Peripheral name */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_CHANNEL 0U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_GPIO GPIO5 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN 0U /*!< GPIO pin number */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_PORT GPIO5 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_PIN 0U /*!< PORT pin number */
|
||||
#define BOARD_INITBASICIOPINS_WAKEUP_PIN_MASK (1U << 0U) /*!< PORT pin mask */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBasicIOPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitI2C1Pins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitCAN2Pins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSPDIFPins(void);
|
||||
void BOARD_InitDbgUARTPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ int main(void) {
|
|||
|
||||
CLOCK_SetMode(kCLOCK_ModeRun);
|
||||
|
||||
printf("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq());
|
||||
printf("CPU frequency: %ld\r\n", CLOCK_GetCoreSysClkFreq());
|
||||
|
||||
for (;;) {
|
||||
__WFI();
|
||||
|
|
|
|||
|
|
@ -23,42 +23,44 @@ __attribute__((section(".boot_hdr.conf"), used))
|
|||
#endif
|
||||
|
||||
const flexspi_nor_config_t spiflash_config = {
|
||||
.memConfig = {
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
|
||||
.csHoldTime = 3U,
|
||||
.csSetupTime = 3U,
|
||||
.columnAddressWidth = 0U,
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = 32U * 1024U * 1024U,
|
||||
.busyOffset = 0U,
|
||||
.busyBitPolarity = 1U,
|
||||
.lookupTable = {
|
||||
// Fast read quad IO (ECh) [NOR_CMD_LUT_SEQ_IDX_READ]
|
||||
[4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
|
||||
[4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04),
|
||||
[4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
|
||||
.csHoldTime = 3U,
|
||||
.csSetupTime = 3U,
|
||||
.columnAddressWidth = 0U,
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = 32U * 1024U * 1024U,
|
||||
.busyOffset = 0U,
|
||||
.busyBitPolarity = 1U,
|
||||
.lookupTable =
|
||||
{
|
||||
// Fast read quad IO (ECh) [NOR_CMD_LUT_SEQ_IDX_READ]
|
||||
[4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
|
||||
[4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04),
|
||||
[4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
|
||||
|
||||
// Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS]
|
||||
[4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00),
|
||||
// Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS]
|
||||
[4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00),
|
||||
|
||||
// Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE]
|
||||
[4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00),
|
||||
// Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE]
|
||||
[4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00),
|
||||
|
||||
// Page program (34h) [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM]
|
||||
[4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x34, RADDR_SDR, FLEXSPI_4PAD, 0x20),
|
||||
[4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
|
||||
// Page program (34h) [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM]
|
||||
[4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x34, RADDR_SDR, FLEXSPI_4PAD, 0x20),
|
||||
[4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
|
||||
|
||||
// Erase sector (21h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR]
|
||||
[4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
// Erase sector (21h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR]
|
||||
[4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
|
||||
// Erase block 64kB (DCh) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK]
|
||||
[4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
// Erase block 64kB (DCh) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK]
|
||||
[4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
},
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 64u * 1024u,
|
||||
|
|
|
|||
Loading…
Reference in New Issue