128 lines
6.1 KiB
C
128 lines
6.1 KiB
C
/*
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* Copyright 2017-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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#include "board.h"
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* MPU configuration. */
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void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
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{
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
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{
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size)
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* API in mpu_armv7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
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* disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and
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* Privileged mode.
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* Use MACROS defined in mpu_armv7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write
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* through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write
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* back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write
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* through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write
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* back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner
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* noncache
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* 1 1 0 0 Normal shareable outer and inner
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* noncache
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* 1 0 1 1 Normal not shareable outer and inner write
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* back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write
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* back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
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* policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
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* mpu_armv7.h.
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*/
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/*
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* Add default region to deny access to whole address space to workaround speculative prefetch.
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* Refer to Arm errata 1013783-B for more details.
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*
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*/
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/* Region 0 setting: Instruction access disabled, No data access permission. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
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#endif
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/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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