diff --git a/.clang-format b/.clang-format index 7ba2003..214adf0 100644 --- a/.clang-format +++ b/.clang-format @@ -1,8 +1,9 @@ BasedOnStyle: Google IndentWidth: 4 -AlignConsecutiveMacros: AcrossEmptyLines -AlignConsecutiveDeclarations: AcrossEmptyLines -AlignConsecutiveAssignments: AcrossEmptyLinesAndComments +AlignConsecutiveMacros: Consecutive +AlignConsecutiveDeclarations: Consecutive +AlignConsecutiveAssignments: Consecutive +AllowShortFunctionsOnASingleLine: None BreakBeforeBraces: Custom BraceWrapping: AfterEnum: false diff --git a/.drone.yml b/.drone.yml index 63eeaa8..f6441c4 100644 --- a/.drone.yml +++ b/.drone.yml @@ -14,4 +14,4 @@ steps: commands: - mkdir build && cd build - cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake .. - - make fire_rt1052_pro_template_FLASH.elf + - make fire_rt1052_pro_watch_FLASH.elf diff --git a/.gitmodules b/.gitmodules index 9539495..f47cd73 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,12 @@ [submodule "SDK"] path = SDK url = https://git.minori.work/Embedded_SDK/MCUXpresso_MIMXRT1052xxxxB.git +[submodule "lib/freertos"] + path = lib/freertos + url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git +[submodule "lib/lcd"] + path = lib/lcd + url = https://git.minori.work/Embedded_Drivers/epd-spi.git +[submodule "lib/lvgl"] + path = lib/lvgl + url = https://github.com/lvgl/lvgl.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 9c017c6..e02d3a8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,13 +1,12 @@ cmake_minimum_required(VERSION 3.10) -project(fire_rt1052_pro_template) +project(fire_rt1052_pro_watch) enable_language(CXX) enable_language(ASM) # Different linker scripts -set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld") -set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld") +set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/gcc/MIMXRT1052xxxxx_flexspi_nor.ld") set(TARGET_SOURCES "SDK/components/serial_manager/fsl_component_serial_manager.c" @@ -95,6 +94,8 @@ set(TARGET_SOURCES "board/dcd.c" "board/peripherals.c" "board/pin_mux.c" + "src/app_impl_lcd.c" + "src/app_lvgl.c" "src/main.c" "xip/fire_rt1052_pro_flexspi_nor_config.c" ) @@ -104,10 +105,11 @@ set(TARGET_C_DEFINES "MCUXPRESSO_SDK" "PRINTF_ADVANCED_ENABLE=1" "PRINTF_FLOAT_ENABLE=1" - "SERIAL_PORT_TYPE_UART" "SDK_DEBUGCONSOLE_UART=1" + "SERIAL_PORT_TYPE_UART" "__STARTUP_CLEAR_BSS" "__STARTUP_INITIALIZE_NONCACHEDATA" + "__STARTUP_INITIALIZE_RAMFUNCTION" ) set(TARGET_C_DEFINES_XIP @@ -132,6 +134,10 @@ set(TARGET_C_INCLUDES # Shared libraries linked with application set(TARGET_LIBS + "lvgl" + "lvgl_demos" + "epd-spi" + "freertos_kernel" "c" "m" "nosys" @@ -159,6 +165,17 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp") set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections") +add_library(freertos_config INTERFACE) +target_include_directories(freertos_config SYSTEM INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/include") +set(FREERTOS_PORT "GCC_ARM_CM4F" CACHE STRING "") +set(FREERTOS_HEAP "4" CACHE STRING "") +add_subdirectory(lib/freertos) + +add_subdirectory(lib/lcd) + +set(LV_CONF_PATH "${CMAKE_CURRENT_SOURCE_DIR}/include/lv_conf.h" CACHE STRING "") +add_subdirectory(lib/lvgl) + # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) include_directories(${TARGET_C_INCLUDES}) @@ -189,23 +206,3 @@ add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH.elf" ) endif() - -# Create ELF -add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${TARGET_SOURCES}) -target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf" - PRIVATE "-T${TARGET_LDSCRIPT_RAM}" - PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_RAM.map" -) -set_property(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" APPEND - PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_RAM.map" -) -add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex" - COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_RAM.elf" "${CMAKE_PROJECT_NAME}_RAM.hex" - DEPENDS "${CMAKE_PROJECT_NAME}_RAM.elf" -) -add_custom_target("${CMAKE_PROJECT_NAME}_RAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_RAM.hex") -if(DEFINED TARGET_TOOLCHAIN_SIZE) -add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" POST_BUILD - COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_RAM.elf" -) -endif() diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex index b9cc9f2..80829dc 100644 --- a/MIMXRT1052xxxxB.mex +++ b/MIMXRT1052xxxxB.mex @@ -1,5 +1,5 @@ - + MIMXRT1052xxxxB MIMXRT1052DVL6B @@ -34,6 +34,11 @@ + + + + + @@ -55,7 +60,7 @@ - + Configures pin routing and optionally pin electrical features. true @@ -63,17 +68,17 @@ true - + true - + true - + true @@ -84,7 +89,7 @@ - + Configures pin routing and optionally pin electrical features. true @@ -92,28 +97,41 @@ true - + true - + true - + + + true + + + true - - + + + + + + + + + + - + Configures pin routing and optionally pin electrical features. true @@ -121,597 +139,49 @@ true - - - true - - - + true - + + + true + + + true - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - + - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - + + - + - + + - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - @@ -723,259 +193,271 @@ 15.0.1 - + - + true - + INPUT - + true - + OUTPUT - + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + true - + true - + + + - + + - - - - - + + + + + - - + + - - + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - + + + + + + - - + + + + + + + + + + + + + + + + + + + + false - + - + true - + INPUT - + true - + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + OUTPUT - + + + - - + + + - - - - - - - - + + + + + + + + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - + + + + + + + - - - + + + + + + + + + + + + + + + + + + + + + true - - - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - false - @@ -991,7 +473,137 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SDK b/SDK new file mode 160000 index 0000000..6baf442 --- /dev/null +++ b/SDK @@ -0,0 +1 @@ +Subproject commit 6baf4427ce5ad19f990c7ab53f7a75d331a280a3 diff --git a/board/clock_config.c b/board/clock_config.c index fd6342f..a600004 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -38,98 +38,129 @@ processor_version: 15.0.1 ******************************************************************************/ void BOARD_InitBootClocks(void) { - Board_BootClockPLL480MHz(); + BOARD_BootClockPLL528M(); } /******************************************************************************* - ******************* Configuration Board_BootClockPLL600MHz ******************** + ******************** Configuration BOARD_BootClockPLL600M ********************* ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration -name: Board_BootClockPLL600MHz +name: BOARD_BootClockPLL600M outputs: - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 5 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 5 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 5 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '1'} -- {id: CCM.LPSPI_PODF.scale, value: '5'} -- {id: CCM.PERCLK_PODF.scale, value: '30'} -- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} -- {id: CCM.SEMC_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* - * Variables for Board_BootClockPLL600MHz configuration + * Variables for BOARD_BootClockPLL600M configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz = +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL600M = { .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz = +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL600M = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz = +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL600M = { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL600M = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* - * Code for Board_BootClockPLL600MHz configuration + * Code for BOARD_BootClockPLL600M configuration ******************************************************************************/ -void Board_BootClockPLL600MHz(void) +void BOARD_BootClockPLL600M(void) { + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; /* Use free 1MHz clock output. */ @@ -174,7 +205,7 @@ void Board_BootClockPLL600MHz(void) CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 29); + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ @@ -194,11 +225,11 @@ void Board_BootClockPLL600MHz(void) /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 2); + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 1); + CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. @@ -207,9 +238,9 @@ void Board_BootClockPLL600MHz(void) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); #endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); @@ -231,7 +262,7 @@ void Board_BootClockPLL600MHz(void) /* Set TRACE_PODF. */ CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -321,7 +352,7 @@ void Board_BootClockPLL600MHz(void) /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL600MHz); + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockPLL600M); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ @@ -330,7 +361,7 @@ void Board_BootClockPLL600MHz(void) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." #endif /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL600MHz); + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockPLL600M); /* Init System pfd0. */ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); /* Init System pfd1. */ @@ -344,12 +375,18 @@ void Board_BootClockPLL600MHz(void) * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockPLL600M); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -360,18 +397,35 @@ void Board_BootClockPLL600MHz(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL600MHz); + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; /* DeInit Usb2 PLL. */ CLOCK_DeinitUsb2Pll(); /* Bypass Usb2 PLL. */ @@ -428,99 +482,131 @@ void Board_BootClockPLL600MHz(void) /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK; + SystemCoreClock = BOARD_BOOTCLOCKPLL600M_CORE_CLOCK; } /******************************************************************************* - ******************* Configuration Board_BootClockPLL480MHz ******************** + ******************** Configuration BOARD_BootClockPLL528M ********************* ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration -name: Board_BootClockPLL480MHz +name: BOARD_BootClockPLL528M called_from_default_init: true outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 480 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 4 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 4 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 120 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 960 MHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 4 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '1'} -- {id: CCM.LPSPI_PODF.scale, value: '5'} -- {id: CCM.PERCLK_PODF.scale, value: '30'} -- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} -- {id: CCM.SEMC_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* - * Variables for Board_BootClockPLL480MHz configuration + * Variables for BOARD_BootClockPLL528M configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz = +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL528M = { - .loopDivider = 80, /* PLL loop divider, Fout = Fin * 40 */ + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz = +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL528M = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz = +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL528M = { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL528M = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* - * Code for Board_BootClockPLL480MHz configuration + * Code for BOARD_BootClockPLL528M configuration ******************************************************************************/ -void Board_BootClockPLL480MHz(void) +void BOARD_BootClockPLL528M(void) { + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; /* Use free 1MHz clock output. */ @@ -559,7 +645,7 @@ void Board_BootClockPLL480MHz(void) CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 29); + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ @@ -579,11 +665,11 @@ void Board_BootClockPLL480MHz(void) /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 2); + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 1); + CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. @@ -592,9 +678,9 @@ void Board_BootClockPLL480MHz(void) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); #endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); @@ -616,7 +702,7 @@ void Board_BootClockPLL480MHz(void) /* Set TRACE_PODF. */ CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -706,7 +792,7 @@ void Board_BootClockPLL480MHz(void) /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL480MHz); + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockPLL528M); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ @@ -715,7 +801,7 @@ void Board_BootClockPLL480MHz(void) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." #endif /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL480MHz); + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockPLL528M); /* Init System pfd0. */ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); /* Init System pfd1. */ @@ -729,12 +815,18 @@ void Board_BootClockPLL480MHz(void) * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockPLL528M); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -745,381 +837,35 @@ void Board_BootClockPLL480MHz(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL480MHz); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK; -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockXT24MHz ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockXT24MHz -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 6 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 6 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 6 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} -- {id: LVDS1_CLK.outFreq, value: 24 MHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 6 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} -settings: -- {id: CCM.ARM_PODF.scale, value: '1'} -- {id: CCM.FLEXSPI_PODF.scale, value: '1'} -- {id: CCM.SEMC_PODF.scale, value: '1'} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} -- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_SYS_POWERDOWN_CFG, value: 'Yes'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockXT24MHz configuration - ******************************************************************************/ -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz = + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockXT24MHz configuration - ******************************************************************************/ -void BOARD_BootClockXT24MHz(void) -{ - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 0); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 0); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* DeInit ARM PLL. */ - CLOCK_DeinitArmPll(); - /* Bypass ARM PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1); - /* Enable ARM PLL output. */ - CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK; - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* DeInit System PLL. */ - CLOCK_DeinitSysPll(); - /* Bypass System PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); - /* Enable System PLL output. */ - CCM_ANALOG->PLL_SYS |= CCM_ANALOG_PLL_SYS_ENABLE_MASK; -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockXT24MHz); + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; /* DeInit Usb2 PLL. */ CLOCK_DeinitUsb2Pll(); /* Bypass Usb2 PLL. */ @@ -1127,7 +873,7 @@ void BOARD_BootClockXT24MHz(void) /* Enable Usb2 PLL output. */ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ @@ -1176,6 +922,6 @@ void BOARD_BootClockXT24MHz(void) /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK; + SystemCoreClock = BOARD_BOOTCLOCKPLL528M_CORE_CLOCK; } diff --git a/board/clock_config.h b/board/clock_config.h index 0f84936..658ef1a 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -28,73 +28,76 @@ void BOARD_InitBootClocks(void); #endif /* __cplusplus*/ /******************************************************************************* - ******************* Configuration Board_BootClockPLL600MHz ******************** + ******************** Configuration BOARD_BootClockPLL600M ********************* ******************************************************************************/ /******************************************************************************* - * Definitions for Board_BootClockPLL600MHz configuration + * Definitions for BOARD_BootClockPLL600M configuration ******************************************************************************/ -#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ +#define BOARD_BOOTCLOCKPLL600M_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ -#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ -#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ -#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ -#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ -#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ -#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ -#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ -#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ -#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ -#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ -#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ -#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKPLL600M_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600M_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL600M_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL600M_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL600M_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL600M_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL600M_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600M_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600M_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL600M_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL600M_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL600M_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL600M_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL600M_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL600M_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL600M_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL600M_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL600M_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL600M_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL600M_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600M_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL600M_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600M_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL600M_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600M_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL600M_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL600M_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600M_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL600M_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL600M_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL600M_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL600M_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL600M_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL600M_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ -/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration. +/*! @brief Arm PLL set for BOARD_BootClockPLL600M configuration. */ -extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz; -/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration. +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL600M; +/*! @brief Usb1 PLL set for BOARD_BootClockPLL600M configuration. */ -extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz; -/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration. +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL600M; +/*! @brief Sys PLL for BOARD_BootClockPLL600M configuration. */ -extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz; +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL600M; +/*! @brief Video PLL set for BOARD_BootClockPLL600M configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL600M; /******************************************************************************* - * API for Board_BootClockPLL600MHz configuration + * API for BOARD_BootClockPLL600M configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { @@ -104,80 +107,83 @@ extern "C" { * @brief This function executes configuration of clocks. * */ -void Board_BootClockPLL600MHz(void); +void BOARD_BootClockPLL600M(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ /******************************************************************************* - ******************* Configuration Board_BootClockPLL480MHz ******************** + ******************** Configuration BOARD_BootClockPLL528M ********************* ******************************************************************************/ /******************************************************************************* - * Definitions for Board_BootClockPLL480MHz configuration + * Definitions for BOARD_BootClockPLL528M configuration ******************************************************************************/ -#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */ +#define BOARD_BOOTCLOCKPLL528M_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ -#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ -#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ -#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ -#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ -#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ -#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ -#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL /* Clock consumers of LVDS1_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ -#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ -#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ -#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ -#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ -#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ -#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKPLL528M_AHB_CLK_ROOT 528000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKPLL528M_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKPLL528M_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKPLL528M_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKPLL528M_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKPLL528M_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKPLL528M_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL528M_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL528M_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKPLL528M_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKPLL528M_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKPLL528M_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKPLL528M_GPT1_IPG_CLK_HIGHFREQ 66000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKPLL528M_GPT2_IPG_CLK_HIGHFREQ 66000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKPLL528M_IPG_CLK_ROOT 132000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKPLL528M_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKPLL528M_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKPLL528M_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKPLL528M_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_PERCLK_CLK_ROOT 66000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKPLL528M_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL528M_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKPLL528M_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL528M_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKPLL528M_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL528M_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKPLL528M_SEMC_CLK_ROOT 66000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKPLL528M_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL528M_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKPLL528M_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKPLL528M_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKPLL528M_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKPLL528M_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKPLL528M_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKPLL528M_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ -/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration. +/*! @brief Arm PLL set for BOARD_BootClockPLL528M configuration. */ -extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz; -/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration. +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockPLL528M; +/*! @brief Usb1 PLL set for BOARD_BootClockPLL528M configuration. */ -extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz; -/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration. +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockPLL528M; +/*! @brief Sys PLL for BOARD_BootClockPLL528M configuration. */ -extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz; +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockPLL528M; +/*! @brief Video PLL set for BOARD_BootClockPLL528M configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockPLL528M; /******************************************************************************* - * API for Board_BootClockPLL480MHz configuration + * API for BOARD_BootClockPLL528M configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { @@ -187,84 +193,7 @@ extern "C" { * @brief This function executes configuration of clocks. * */ -void Board_BootClockPLL480MHz(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockXT24MHz ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockXT24MHz configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ -#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ -#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ -#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ -#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ -#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ -#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ -#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ -#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ -#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ -#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ -#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ -#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ -#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ -#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ -#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ -#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL /* Clock consumers of LVDS1_CLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL /* Clock consumers of MQS_MCLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ -#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ -#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ -#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ -#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ -#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ -#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ -#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */ -#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ -#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ - -/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz; - -/******************************************************************************* - * API for BOARD_BootClockXT24MHz configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockXT24MHz(void); +void BOARD_BootClockPLL528M(void); #if defined(__cplusplus) } diff --git a/board/dcd.c b/board/dcd.c index 6d51c6f..5726b18 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -33,9 +33,271 @@ const uint8_t dcd_data[] = { /* Tag */ 0xD2, /* Image Length */ - 0x00, 0x04, + 0x04, 0x10, /* Version */ - 0x41 + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ diff --git a/board/pin_mux.c b/board/pin_mux.c index 9129401..d9a6941 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -21,6 +21,11 @@ pin_labels: - {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: CSI_RST, identifier: CSI_RST} - {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BUZZER, identifier: BUZZER} - {pin_num: L6, pin_signal: WAKEUP, label: WAKEUP, identifier: WAKEUP} +- {pin_num: D11, pin_signal: GPIO_B1_03, label: RST, identifier: RST} +- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LEDB, identifier: LEDB} +- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: LEDR, identifier: LEDR} +- {pin_num: M13, pin_signal: GPIO_AD_B1_09, label: LEDG, identifier: LEDG} +- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: LEDA, identifier: LEDA} power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH: '3.3', DCDC_SENSE: '1.25', NVCC_EMC: '3.3', NVCC_GPIO: '3.3', NVCC_SD0: '3.3', NVCC_SD1: '3.3', VDDA_ADC_3P3: '3.3', VDD_HIGH_CAP: '1.1', VDD_HIGH_IN: '3.3', VDD_SNVS_CAP: '1.1', VDD_SNVS_IN: '3.3', VDD_SOC_IN: '1.25', VDD_USB_CAP: '2.5'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** @@ -38,14 +43,14 @@ power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH: * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { - BOARD_InitUARTDbgPins(); - BOARD_InitSWDPins(); - BOARD_InitFlexSPIPins(); + BOARD_InitDbgUARTPins(); + BOARD_InitSPILCDPins(); + BOARD_InitLEDPins(); } /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitUARTDbgPins: +BOARD_InitDbgUARTPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12} @@ -55,11 +60,11 @@ BOARD_InitUARTDbgPins: /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitUARTDbgPins + * Function Name : BOARD_InitDbgUARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitUARTDbgPins(void) { +void BOARD_InitDbgUARTPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); #if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) @@ -76,722 +81,103 @@ void BOARD_InitUARTDbgPins(void) { /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSWDPins: +BOARD_InitSPILCDPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - - {pin_num: E14, peripheral: JTAG, signal: TMS, pin_signal: GPIO_AD_B0_06} - - {pin_num: F12, peripheral: JTAG, signal: TCK, pin_signal: GPIO_AD_B0_07} + - {pin_num: E8, peripheral: LPSPI4, signal: SDO, pin_signal: GPIO_B0_02} + - {pin_num: D8, peripheral: LPSPI4, signal: SCK, pin_signal: GPIO_B0_03} + - {pin_num: E7, peripheral: LPSPI4, signal: SDI, pin_signal: GPIO_B0_01} + - {pin_num: D7, peripheral: LPSPI4, signal: PCS0, pin_signal: GPIO_B0_00} + - {pin_num: D11, peripheral: GPIO2, signal: 'gpio_io, 19', pin_signal: GPIO_B1_03, direction: OUTPUT, gpio_init_state: 'true'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitSWDPins + * Function Name : BOARD_InitSPILCDPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSWDPins(void) { +void BOARD_InitSPILCDPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_JTAG_TMS, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_JTAG_TCK, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitFlexSPIPins: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} - - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} - - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} - - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} - - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} - - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} - - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitFlexSPIPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitFlexSPIPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); -#endif -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InituSDPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01} - - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00} - - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02} - - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03} - - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04} - - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05} - - {pin_num: G14, peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, gpio_init_state: 'true'} - - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InituSDPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InituSDPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of USDHC1_PWR on GPIO_AD_B0_05 (pin G14) */ - gpio_pin_config_t USDHC1_PWR_config = { + /* GPIO configuration of RST on GPIO_B1_03 (pin D11) */ + gpio_pin_config_t RST_config = { .direction = kGPIO_DigitalOutput, .outputLogic = 1U, .interruptMode = kGPIO_NoIntmode }; - /* Initialize GPIO functionality on GPIO_AD_B0_05 (pin G14) */ - GPIO_PinInit(GPIO1, 5U, &USDHC1_PWR_config); + /* Initialize GPIO functionality on GPIO_B1_03 (pin D11) */ + GPIO_PinInit(GPIO2, 19U, &RST_config); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LPSPI4_PCS0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_GPIO2_IO19, 0U); } /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSDWiFiPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +BOARD_InitLEDPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - - {pin_num: N3, peripheral: USDHC2, signal: usdhc_cmd, pin_signal: GPIO_SD_B1_05} - - {pin_num: P2, peripheral: USDHC2, signal: usdhc_clk, pin_signal: GPIO_SD_B1_04} - - {pin_num: M4, peripheral: USDHC2, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B1_03} - - {pin_num: M3, peripheral: USDHC2, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B1_02} - - {pin_num: M5, peripheral: USDHC2, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B1_01} - - {pin_num: L5, peripheral: USDHC2, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B1_00} + - {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: H13, peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: M13, peripheral: GPIO1, signal: 'gpio_io, 25', pin_signal: GPIO_AD_B1_09, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, gpio_init_state: 'true'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitSDWiFiPins + * Function Name : BOARD_InitLEDPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSDWiFiPins(void) { +void BOARD_InitLEDPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSEMCPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00} - - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01} - - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02} - - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03} - - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04} - - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05} - - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06} - - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07} - - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30} - - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31} - - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32} - - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33} - - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34} - - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35} - - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36} - - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37} - - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08} - - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38} - - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09} - - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10} - - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11} - - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12} - - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13} - - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14} - - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15} - - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16} - - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17} - - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18} - - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23} - - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19} - - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20} - - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21} - - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24} - - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25} - - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28} - - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27} - - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26} - - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40} - - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29} - - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41} - - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitSEMCPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitSEMCPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U); -#endif - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U); -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U); -#endif - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U); -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U); -#endif -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitLCDPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00} - - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04} - - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06} - - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05} - - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07} - - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08} - - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09} - - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10} - - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11} - - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12} - - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13} - - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14} - - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15} - - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00} - - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01} - - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02} - - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03} - - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01} - - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02} - - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03} - - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, direction: OUTPUT, gpio_init_state: 'true'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitLCDPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitLCDPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of LCD_RST on GPIO_AD_B0_02 (pin M11) */ - gpio_pin_config_t LCD_RST_config = { + /* GPIO configuration of LEDA on GPIO_AD_B0_09 (pin F14) */ + gpio_pin_config_t LEDA_config = { .direction = kGPIO_DigitalOutput, .outputLogic = 1U, .interruptMode = kGPIO_NoIntmode }; - /* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */ - GPIO_PinInit(GPIO1, 2U, &LCD_RST_config); + /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ + GPIO_PinInit(GPIO1, 9U, &LEDA_config); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); -} + /* GPIO configuration of LEDB on GPIO_AD_B0_10 (pin G13) */ + gpio_pin_config_t LEDB_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_10 (pin G13) */ + GPIO_PinInit(GPIO1, 10U, &LEDB_config); -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitCodecPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: G12, peripheral: SAI1, signal: sai_tx_bclk, pin_signal: GPIO_AD_B1_14} - - {pin_num: J14, peripheral: SAI1, signal: sai_tx_sync, pin_signal: GPIO_AD_B1_15} - - {pin_num: H11, peripheral: SAI1, signal: sai_tx_data0, pin_signal: GPIO_AD_B1_13} - - {pin_num: H12, peripheral: SAI1, signal: sai_rx_data0, pin_signal: GPIO_AD_B1_12} - - {pin_num: M13, peripheral: SAI1, signal: sai_mclk, pin_signal: GPIO_AD_B1_09} - - {pin_num: H13, peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ + /* GPIO configuration of LEDR on GPIO_AD_B1_08 (pin H13) */ + gpio_pin_config_t LEDR_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B1_08 (pin H13) */ + GPIO_PinInit(GPIO1, 24U, &LEDR_config); -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitCodecPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitCodecPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); + /* GPIO configuration of LEDG on GPIO_AD_B1_09 (pin M13) */ + gpio_pin_config_t LEDG_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B1_09 (pin M13) */ + GPIO_PinInit(GPIO1, 25U, &LEDG_config); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitCSIPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15} - - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14} - - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13} - - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12} - - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11} - - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10} - - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09} - - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08} - - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07} - - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06} - - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05} - - {pin_num: D13, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_B1_12} - - {pin_num: M14, peripheral: GPIO1, signal: 'gpio_io, 00', pin_signal: GPIO_AD_B0_00, identifier: CSI_PDN} - - {pin_num: H10, peripheral: GPIO1, signal: 'gpio_io, 01', pin_signal: GPIO_AD_B0_01} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitCSIPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitCSIPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_GPIO1_IO01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_CSI_PIXCLK, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSYSPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: N1, peripheral: SUPPLY, signal: 'DCDC_GND, 0', pin_signal: DCDC_GND0} - - {pin_num: N2, peripheral: SUPPLY, signal: 'DCDC_GND, 1', pin_signal: DCDC_GND1} - - {pin_num: L1, peripheral: SUPPLY, signal: 'DCDC_IN, 0', pin_signal: DCDC_IN0} - - {pin_num: L2, peripheral: SUPPLY, signal: 'DCDC_IN, 1', pin_signal: DCDC_IN1} - - {pin_num: K4, peripheral: SUPPLY, signal: dcdc_in_q, pin_signal: DCDC_IN_Q} - - {pin_num: M1, peripheral: SUPPLY, signal: 'DCDC_LP, 0', pin_signal: DCDC_LP0} - - {pin_num: M2, peripheral: SUPPLY, signal: 'DCDC_LP, 1', pin_signal: DCDC_LP1} - - {pin_num: K3, peripheral: SUPPLY, signal: dcdc_pswitch, pin_signal: DCDC_PSWITCH} - - {pin_num: J5, peripheral: SUPPLY, signal: dcdc_sense, pin_signal: DCDC_SENSE} - - {pin_num: N10, peripheral: SUPPLY, signal: gpanaio, pin_signal: GPANAIO} - - {pin_num: K9, peripheral: SUPPLY, signal: ngnd_kel0, pin_signal: NGND_KEL0} - - {pin_num: F5, peripheral: SUPPLY, signal: 'NVCC_EMC, 0', pin_signal: NVCC_EMC0} - - {pin_num: E6, peripheral: SUPPLY, signal: 'NVCC_EMC, 1', pin_signal: NVCC_EMC1} - - {pin_num: E9, peripheral: SUPPLY, signal: 'NVCC_GPIO, 0', pin_signal: NVCC_GPIO0} - - {pin_num: F10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 1', pin_signal: NVCC_GPIO1} - - {pin_num: J10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 2', pin_signal: NVCC_GPIO2} - - {pin_num: P10, peripheral: SUPPLY, signal: nvcc_pll, pin_signal: NVCC_PLL} - - {pin_num: J6, peripheral: SUPPLY, signal: nvcc_sd0, pin_signal: NVCC_SD0} - - {pin_num: K5, peripheral: SUPPLY, signal: nvcc_sd1, pin_signal: NVCC_SD1} - - {pin_num: K6, peripheral: SUPPLY, signal: test_mode, pin_signal: TEST_MODE} - - {pin_num: N12, peripheral: SUPPLY, signal: usb_otg1_chd_b, pin_signal: USB_OTG1_CHD_B} - - {pin_num: M8, peripheral: SUPPLY, signal: usb_otg1_dn, pin_signal: USB_OTG1_DN} - - {pin_num: L8, peripheral: SUPPLY, signal: usb_otg1_dp, pin_signal: USB_OTG1_DP} - - {pin_num: N6, peripheral: SUPPLY, signal: usb_otg1_vbus, pin_signal: USB_OTG1_VBUS} - - {pin_num: N7, peripheral: SUPPLY, signal: usb_otg2_dn, pin_signal: USB_OTG2_DN} - - {pin_num: P7, peripheral: SUPPLY, signal: usb_otg2_dp, pin_signal: USB_OTG2_DP} - - {pin_num: P6, peripheral: SUPPLY, signal: usb_otg2_vbus, pin_signal: USB_OTG2_VBUS} - - {pin_num: P12, peripheral: SUPPLY, signal: VDD_HIGH_IN, pin_signal: VDD_HIGH_IN} - - {pin_num: P8, peripheral: SUPPLY, signal: VDD_HIGH_CAP, pin_signal: VDD_HIGH_CAP} - - {pin_num: M10, peripheral: SUPPLY, signal: VDD_SNVS_CAP, pin_signal: VDD_SNVS_CAP} - - {pin_num: M9, peripheral: SUPPLY, signal: VDD_SNVS_IN, pin_signal: VDD_SNVS_IN} - - {pin_num: F6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 0', pin_signal: VDD_SOC_IN0} - - {pin_num: G6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 1', pin_signal: VDD_SOC_IN1} - - {pin_num: H6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 2', pin_signal: VDD_SOC_IN2} - - {pin_num: F7, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 3', pin_signal: VDD_SOC_IN3} - - {pin_num: F8, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 4', pin_signal: VDD_SOC_IN4} - - {pin_num: F9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 5', pin_signal: VDD_SOC_IN5} - - {pin_num: G9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 6', pin_signal: VDD_SOC_IN6} - - {pin_num: H9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 7', pin_signal: VDD_SOC_IN7} - - {pin_num: J9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 8', pin_signal: VDD_SOC_IN8} - - {pin_num: N14, peripheral: SUPPLY, signal: VDDA_ADC_3P3, pin_signal: VDDA_ADC_3P3} - - {pin_num: K8, peripheral: SUPPLY, signal: VDD_USB_CAP, pin_signal: VDD_USB_CAP} - - {pin_num: A1, peripheral: SUPPLY, signal: 'VSS, 0', pin_signal: VSS0} - - {pin_num: P1, peripheral: SUPPLY, signal: 'VSS, 1', pin_signal: VSS1} - - {pin_num: E2, peripheral: SUPPLY, signal: 'VSS, 2', pin_signal: VSS2} - - {pin_num: K2, peripheral: SUPPLY, signal: 'VSS, 3', pin_signal: VSS3} - - {pin_num: B5, peripheral: SUPPLY, signal: 'VSS, 4', pin_signal: VSS4} - - {pin_num: N5, peripheral: SUPPLY, signal: 'VSS, 5', pin_signal: VSS5} - - {pin_num: G7, peripheral: SUPPLY, signal: 'VSS, 6', pin_signal: VSS6} - - {pin_num: H7, peripheral: SUPPLY, signal: 'VSS, 7', pin_signal: VSS7} - - {pin_num: J7, peripheral: SUPPLY, signal: 'VSS, 8', pin_signal: VSS8} - - {pin_num: G8, peripheral: SUPPLY, signal: 'VSS, 9', pin_signal: VSS9} - - {pin_num: H8, peripheral: SUPPLY, signal: 'VSS, 10', pin_signal: VSS10} - - {pin_num: J8, peripheral: SUPPLY, signal: 'VSS, 11', pin_signal: VSS11} - - {pin_num: N8, peripheral: SUPPLY, signal: 'VSS, 12', pin_signal: VSS12} - - {pin_num: L9, peripheral: SUPPLY, signal: 'VSS, 13', pin_signal: VSS13} - - {pin_num: B10, peripheral: SUPPLY, signal: 'VSS, 14', pin_signal: VSS14} - - {pin_num: E13, peripheral: SUPPLY, signal: 'VSS, 15', pin_signal: VSS15} - - {pin_num: K13, peripheral: SUPPLY, signal: 'VSS, 16', pin_signal: VSS16} - - {pin_num: A14, peripheral: SUPPLY, signal: 'VSS, 17', pin_signal: VSS17} - - {pin_num: P14, peripheral: SUPPLY, signal: 'VSS, 18', pin_signal: VSS18} - - {pin_num: P13, peripheral: CCM, signal: CLK1_N, pin_signal: CCM_CLK1_N} - - {pin_num: N13, peripheral: CCM, signal: CLK1_P, pin_signal: CCM_CLK1_P} - - {pin_num: K7, peripheral: SNVS, signal: snvs_pmic_on_req, pin_signal: PMIC_ON_REQ} - - {pin_num: M6, peripheral: SRC, signal: RESET_B, pin_signal: ONOFF} - - {pin_num: M7, peripheral: SRC, signal: POR_B, pin_signal: POR_B} - - {pin_num: P9, peripheral: XTALOSC24M, signal: rtc_xtalo, pin_signal: RTC_XTALO} - - {pin_num: N9, peripheral: XTALOSC24M, signal: rtc_xtali, pin_signal: RTC_XTALI} - - {pin_num: P11, peripheral: XTALOSC24M, signal: xtali, pin_signal: XTALI} - - {pin_num: N11, peripheral: XTALOSC24M, signal: xtalo, pin_signal: XTALO} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitSYSPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitSYSPins(void) { - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ, 0U); -#endif -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitENETPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: L12, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_AD_B1_04} - - {pin_num: B14, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_B1_15} - - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04} - - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05} - - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07} - - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08} - - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09} - - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11} - - {pin_num: B13, peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_B1_10} - - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitENETPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitENETPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_ENET_MDC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_TX_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitBasicIOPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03, direction: OUTPUT} - - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBasicIOPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitBasicIOPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); - - /* GPIO configuration of BUZZER on GPIO_AD_B0_03 (pin G11) */ - gpio_pin_config_t BUZZER_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_AD_B0_03 (pin G11) */ - GPIO_PinInit(GPIO1, 3U, &BUZZER_config); - - /* GPIO configuration of WAKEUP on WAKEUP (pin L6) */ - gpio_pin_config_t WAKEUP_config = { - .direction = kGPIO_DigitalInput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on WAKEUP (pin L6) */ - GPIO_PinInit(GPIO5, 0U, &WAKEUP_config); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0U); - IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitI2C1Pins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01} - - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitI2C1Pins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitI2C1Pins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitCAN2Pins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15} - - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitCAN2Pins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitCAN2Pins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSPDIFPins: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: M12, peripheral: SPDIF, signal: spdif_in, pin_signal: GPIO_AD_B1_03} - - {pin_num: L11, peripheral: SPDIF, signal: spdif_out, pin_signal: GPIO_AD_B1_02} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitSPDIFPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitSPDIFPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_SPDIF_OUT, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_SPDIF_IN, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, 0U); } /*********************************************************************************************************************** * EOF diff --git a/board/pin_mux.h b/board/pin_mux.h index d87c119..b9232a8 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -42,195 +42,91 @@ void BOARD_InitBootPins(void); * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InitUARTDbgPins(void); +void BOARD_InitDbgUARTPins(void); - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSWDPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitFlexSPIPins(void); - -/* GPIO_AD_B0_05 (coord G14), USDHC1_PWR */ +/* GPIO_B1_03 (coord D11), RST */ /* Routed pin properties */ -#define BOARD_INITUSDPINS_USDHC1_PWR_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITUSDPINS_USDHC1_PWR_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITUSDPINS_USDHC1_PWR_CHANNEL 5U /*!< Signal channel */ +#define BOARD_INITSPILCDPINS_RST_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITSPILCDPINS_RST_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITSPILCDPINS_RST_CHANNEL 19U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN 5U /*!< GPIO pin number */ -#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ -#define BOARD_INITUSDPINS_USDHC1_PWR_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITUSDPINS_USDHC1_PWR_PIN 5U /*!< PORT pin number */ -#define BOARD_INITUSDPINS_USDHC1_PWR_PIN_MASK (1U << 5U) /*!< PORT pin mask */ +#define BOARD_INITSPILCDPINS_RST_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITSPILCDPINS_RST_GPIO_PIN 19U /*!< GPIO pin number */ +#define BOARD_INITSPILCDPINS_RST_GPIO_PIN_MASK (1U << 19U) /*!< GPIO pin mask */ +#define BOARD_INITSPILCDPINS_RST_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITSPILCDPINS_RST_PIN 19U /*!< PORT pin number */ +#define BOARD_INITSPILCDPINS_RST_PIN_MASK (1U << 19U) /*!< PORT pin mask */ /*! * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InituSDPins(void); +void BOARD_InitSPILCDPins(void); - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSDWiFiPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSEMCPins(void); - -/* GPIO_AD_B0_02 (coord M11), LCD_RST */ +/* GPIO_AD_B0_10 (coord G13), LEDB */ /* Routed pin properties */ -#define BOARD_INITLCDPINS_LCD_RST_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITLCDPINS_LCD_RST_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITLCDPINS_LCD_RST_CHANNEL 2U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LEDB_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LEDB_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LEDB_CHANNEL 10U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITLCDPINS_LCD_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN 2U /*!< GPIO pin number */ -#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */ -#define BOARD_INITLCDPINS_LCD_RST_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITLCDPINS_LCD_RST_PIN 2U /*!< PORT pin number */ -#define BOARD_INITLCDPINS_LCD_RST_PIN_MASK (1U << 2U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LEDB_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDB_GPIO_PIN 10U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LEDB_GPIO_PIN_MASK (1U << 10U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LEDB_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDB_PIN 10U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LEDB_PIN_MASK (1U << 10U) /*!< PORT pin mask */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitLCDPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitCodecPins(void); - -/* GPIO_AD_B0_00 (coord M14), CSI_ */ +/* GPIO_AD_B1_08 (coord H13), LEDR */ /* Routed pin properties */ -#define BOARD_INITCSIPINS_CSI_PDN_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITCSIPINS_CSI_PDN_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITCSIPINS_CSI_PDN_CHANNEL 0U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LEDR_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LEDR_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LEDR_CHANNEL 24U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITCSIPINS_CSI_PDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN 0U /*!< GPIO pin number */ -#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ -#define BOARD_INITCSIPINS_CSI_PDN_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITCSIPINS_CSI_PDN_PIN 0U /*!< PORT pin number */ -#define BOARD_INITCSIPINS_CSI_PDN_PIN_MASK (1U << 0U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LEDR_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDR_GPIO_PIN 24U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LEDR_GPIO_PIN_MASK (1U << 24U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LEDR_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDR_PIN 24U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LEDR_PIN_MASK (1U << 24U) /*!< PORT pin mask */ -/* GPIO_AD_B0_01 (coord H10), CSI_RST */ +/* GPIO_AD_B1_09 (coord M13), LEDG */ /* Routed pin properties */ -#define BOARD_INITCSIPINS_CSI_RST_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITCSIPINS_CSI_RST_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITCSIPINS_CSI_RST_CHANNEL 1U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LEDG_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LEDG_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LEDG_CHANNEL 25U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITCSIPINS_CSI_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN 1U /*!< GPIO pin number */ -#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN_MASK (1U << 1U) /*!< GPIO pin mask */ -#define BOARD_INITCSIPINS_CSI_RST_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITCSIPINS_CSI_RST_PIN 1U /*!< PORT pin number */ -#define BOARD_INITCSIPINS_CSI_RST_PIN_MASK (1U << 1U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LEDG_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDG_GPIO_PIN 25U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LEDG_GPIO_PIN_MASK (1U << 25U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LEDG_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDG_PIN 25U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LEDG_PIN_MASK (1U << 25U) /*!< PORT pin mask */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitCSIPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSYSPins(void); - -/* GPIO_B1_07 (coord B12), LED_G */ +/* GPIO_AD_B0_09 (coord F14), LEDA */ /* Routed pin properties */ -#define BOARD_INITENETPINS_LED_G_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENETPINS_LED_G_SIGNAL enet_tx_data /*!< Signal name */ -#define BOARD_INITENETPINS_LED_G_CHANNEL 0U /*!< Signal channel */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitENETPins(void); - -/* GPIO_AD_B0_03 (coord G11), BUZZER */ -/* Routed pin properties */ -#define BOARD_INITBASICIOPINS_BUZZER_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITBASICIOPINS_BUZZER_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITBASICIOPINS_BUZZER_CHANNEL 3U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LEDA_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LEDA_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LEDA_CHANNEL 9U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITBASICIOPINS_BUZZER_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN 3U /*!< GPIO pin number */ -#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ -#define BOARD_INITBASICIOPINS_BUZZER_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITBASICIOPINS_BUZZER_PIN 3U /*!< PORT pin number */ -#define BOARD_INITBASICIOPINS_BUZZER_PIN_MASK (1U << 3U) /*!< PORT pin mask */ - -/* WAKEUP (coord L6), WAKEUP */ -/* Routed pin properties */ -#define BOARD_INITBASICIOPINS_WAKEUP_PERIPHERAL GPIO5 /*!< Peripheral name */ -#define BOARD_INITBASICIOPINS_WAKEUP_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITBASICIOPINS_WAKEUP_CHANNEL 0U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITBASICIOPINS_WAKEUP_GPIO GPIO5 /*!< GPIO peripheral base pointer */ -#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN 0U /*!< GPIO pin number */ -#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ -#define BOARD_INITBASICIOPINS_WAKEUP_PORT GPIO5 /*!< PORT peripheral base pointer */ -#define BOARD_INITBASICIOPINS_WAKEUP_PIN 0U /*!< PORT pin number */ -#define BOARD_INITBASICIOPINS_WAKEUP_PIN_MASK (1U << 0U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LEDA_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDA_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LEDA_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LEDA_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LEDA_PIN 9U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LEDA_PIN_MASK (1U << 9U) /*!< PORT pin mask */ /*! * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InitBasicIOPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitI2C1Pins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitCAN2Pins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSPDIFPins(void); +void BOARD_InitLEDPins(void); #if defined(__cplusplus) } diff --git a/gcc/MIMXRT1052xxxxx_flexspi_nor.ld b/gcc/MIMXRT1052xxxxx_flexspi_nor.ld new file mode 100644 index 0000000..c9911e7 --- /dev/null +++ b/gcc/MIMXRT1052xxxxx_flexspi_nor.ld @@ -0,0 +1,281 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.0, 2018-09-21 +** Build: b210709 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x02000000 +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_data2); + __NCACHE_REGION_SIZE = 0; + + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ + + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + .ext_data : + { + . = ALIGN(8); + *(.lvgl_largemem) + *(.lvgl_largemem*) + . = ALIGN(8); + } > m_sdram + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/include/FreeRTOSConfig.h b/include/FreeRTOSConfig.h new file mode 100644 index 0000000..b1a1a2f --- /dev/null +++ b/include/FreeRTOSConfig.h @@ -0,0 +1,156 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 32 +#define configMINIMAL_STACK_SIZE ((unsigned short)128) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(48 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Port specific settings */ +#define configUSE_FPU 1 + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/include/app_impl_lcd.h b/include/app_impl_lcd.h new file mode 100644 index 0000000..5bb4db4 --- /dev/null +++ b/include/app_impl_lcd.h @@ -0,0 +1,11 @@ +#ifndef APP_LCD_IMPL_H +#define APP_LCD_IMPL_H + +#include "epd-spi/epd_common.h" + +int app_lcd_impl_init(void *handle); +epd_ret_t app_lcd_impl_write_command(void *handle, uint8_t *command, uint32_t len); +epd_ret_t app_lcd_impl_write_data(void *handle, const uint8_t *data, uint32_t len); +epd_ret_t app_lcd_impl_delay(void *handle, uint32_t msec); + +#endif // APP_LCD_IMPL_H diff --git a/include/app_lvgl.h b/include/app_lvgl.h new file mode 100644 index 0000000..0c0acfe --- /dev/null +++ b/include/app_lvgl.h @@ -0,0 +1,11 @@ +#ifndef APP_LVGL_H +#define APP_LVGL_H + +#include +#include + +int app_lvgl_init(void); +bool app_lvgl_lock(uint32_t timeout_ms); +void app_lvgl_unlock(void); + +#endif // APP_LVGL_H diff --git a/include/lv_conf.h b/include/lv_conf.h new file mode 100644 index 0000000..1f7b1d2 --- /dev/null +++ b/include/lv_conf.h @@ -0,0 +1,954 @@ +/** + * @file lv_conf.h + * Configuration file for v9.0.0 + */ + +/* + * Copy this file as `lv_conf.h` + * 1. simply next to the `lvgl` folder + * 2. or any other places and + * - define `LV_CONF_INCLUDE_SIMPLE` + * - add the path as include path + */ + +/* clang-format off */ +#if 1 /*Set it to "1" to enable content*/ + +#ifndef LV_CONF_H +#define LV_CONF_H + +/*==================== + COLOR SETTINGS + *====================*/ + +/*Color depth: 8 (A8), 16 (RGB565), 24 (RGB888), 32 (XRGB8888)*/ +#define LV_COLOR_DEPTH 16 + +/*========================= + STDLIB WRAPPER SETTINGS + *=========================*/ + +/* Possible values + * - LV_STDLIB_BUILTIN: LVGL's built in implementation + * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc + * - LV_STDLIB_MICROPYTHON: MicroPython implementation + * - LV_STDLIB_RTTHREAD: RT-Thread implementation + * - LV_STDLIB_CUSTOM: Implement the functions externally + */ +#define LV_USE_STDLIB_MALLOC LV_STDLIB_BUILTIN +#define LV_USE_STDLIB_STRING LV_STDLIB_BUILTIN +#define LV_USE_STDLIB_SPRINTF LV_STDLIB_BUILTIN + + +#if LV_USE_STDLIB_MALLOC == LV_STDLIB_BUILTIN + /*Size of the memory available for `lv_malloc()` in bytes (>= 2kB)*/ + #define LV_MEM_SIZE (64 * 1024U) /*[bytes]*/ + + /*Size of the memory expand for `lv_malloc()` in bytes*/ + #define LV_MEM_POOL_EXPAND_SIZE 0 + + /*Set an address for the memory pool instead of allocating it as a normal array. Can be in external SRAM too.*/ + #define LV_MEM_ADR 0 + /*Instead of an address give a memory allocator that will be called to get a memory pool for LVGL. E.g. my_malloc*/ + #if LV_MEM_ADR == 0 + #undef LV_MEM_POOL_INCLUDE + #undef LV_MEM_POOL_ALLOC + #endif +#endif /*LV_USE_MALLOC == LV_STDLIB_BUILTIN*/ + +/*==================== + HAL SETTINGS + *====================*/ + +/*Default display refresh, input device read and animation step period.*/ +#define LV_DEF_REFR_PERIOD 33 /*[ms]*/ + +/*Default Dot Per Inch. Used to initialize default sizes such as widgets sized, style paddings. + *(Not so important, you can adjust it to modify default sizes and spaces)*/ +#define LV_DPI_DEF 130 /*[px/inch]*/ + +/*================= + * OPERATING SYSTEM + *=================*/ +/*Select an operating system to use. Possible options: + * - LV_OS_NONE + * - LV_OS_PTHREAD + * - LV_OS_FREERTOS + * - LV_OS_CMSIS_RTOS2 + * - LV_OS_RTTHREAD + * - LV_OS_WINDOWS + * - LV_OS_CUSTOM */ +#define LV_USE_OS LV_OS_NONE + +#if LV_USE_OS == LV_OS_CUSTOM + #define LV_OS_CUSTOM_INCLUDE +#endif + +/*======================== + * RENDERING CONFIGURATION + *========================*/ + +/*Align the stride of all layers and images to this bytes*/ +#define LV_DRAW_BUF_STRIDE_ALIGN 1 + +/*Align the start address of draw_buf addresses to this bytes*/ +#define LV_DRAW_BUF_ALIGN 4 + +#define LV_USE_DRAW_SW 1 +#if LV_USE_DRAW_SW == 1 + /* Set the number of draw unit. + * > 1 requires an operating system enabled in `LV_USE_OS` + * > 1 means multiply threads will render the screen in parallel */ + #define LV_DRAW_SW_DRAW_UNIT_CNT 1 + + /* Use Arm-2D to accelerate the sw render */ + #define LV_USE_DRAW_ARM2D_SYNC 0 + + /* If a widget has `style_opa < 255` (not `bg_opa`, `text_opa` etc) or not NORMAL blend mode + * it is buffered into a "simple" layer before rendering. The widget can be buffered in smaller chunks. + * "Transformed layers" (if `transform_angle/zoom` are set) use larger buffers + * and can't be drawn in chunks. */ + + /*The target buffer size for simple layer chunks.*/ + #define LV_DRAW_SW_LAYER_SIMPLE_BUF_SIZE (24 * 1024) /*[bytes]*/ + + /* 0: use a simple renderer capable of drawing only simple rectangles with gradient, images, texts, and straight lines only + * 1: use a complex renderer capable of drawing rounded corners, shadow, skew lines, and arcs too */ + #define LV_DRAW_SW_COMPLEX 1 + + #if LV_DRAW_SW_COMPLEX == 1 + /*Allow buffering some shadow calculation. + *LV_DRAW_SW_SHADOW_CACHE_SIZE is the max. shadow size to buffer, where shadow size is `shadow_width + radius` + *Caching has LV_DRAW_SW_SHADOW_CACHE_SIZE^2 RAM cost*/ + #define LV_DRAW_SW_SHADOW_CACHE_SIZE 0 + + /* Set number of maximally cached circle data. + * The circumference of 1/4 circle are saved for anti-aliasing + * radius * 4 bytes are used per circle (the most often used radiuses are saved) + * 0: to disable caching */ + #define LV_DRAW_SW_CIRCLE_CACHE_SIZE 4 + #endif + + #define LV_USE_DRAW_SW_ASM LV_DRAW_SW_ASM_NONE + + #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_CUSTOM + #define LV_DRAW_SW_ASM_CUSTOM_INCLUDE "" + #endif +#endif + +/* Use NXP's VG-Lite GPU on iMX RTxxx platforms. */ +#define LV_USE_DRAW_VGLITE 0 + +#if LV_USE_DRAW_VGLITE + /* Enable blit quality degradation workaround recommended for screen's dimension > 352 pixels. */ + #define LV_USE_VGLITE_BLIT_SPLIT 0 + + #if LV_USE_OS + /* Enable VGLite draw async. Queue multiple tasks and flash them once to the GPU. */ + #define LV_USE_VGLITE_DRAW_ASYNC 1 + #endif + + /* Enable VGLite asserts. */ + #define LV_USE_VGLITE_ASSERT 0 +#endif + +/* Use NXP's PXP on iMX RTxxx platforms. */ +#define LV_USE_DRAW_PXP 0 + +#if LV_USE_DRAW_PXP + /* Enable PXP asserts. */ + #define LV_USE_PXP_ASSERT 0 +#endif + +/* Use Renesas Dave2D on RA platforms. */ +#define LV_USE_DRAW_DAVE2D 0 + +/* Draw using cached SDL textures*/ +#define LV_USE_DRAW_SDL 0 + +/* Use VG-Lite GPU. */ +#define LV_USE_DRAW_VG_LITE 0 + +#if LV_USE_DRAW_VG_LITE +/* Enable VG-Lite custom external 'gpu_init()' function */ +#define LV_VG_LITE_USE_GPU_INIT 0 + +/* Enable VG-Lite assert. */ +#define LV_VG_LITE_USE_ASSERT 0 + +#endif + +/*======================= + * FEATURE CONFIGURATION + *=======================*/ + +/*------------- + * Logging + *-----------*/ + +/*Enable the log module*/ +#define LV_USE_LOG 0 +#if LV_USE_LOG + + /*How important log should be added: + *LV_LOG_LEVEL_TRACE A lot of logs to give detailed information + *LV_LOG_LEVEL_INFO Log important events + *LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem + *LV_LOG_LEVEL_ERROR Only critical issue, when the system may fail + *LV_LOG_LEVEL_USER Only logs added by the user + *LV_LOG_LEVEL_NONE Do not log anything*/ + #define LV_LOG_LEVEL LV_LOG_LEVEL_WARN + + /*1: Print the log with 'printf'; + *0: User need to register a callback with `lv_log_register_print_cb()`*/ + #define LV_LOG_PRINTF 0 + + /*1: Enable print timestamp; + *0: Disable print timestamp*/ + #define LV_LOG_USE_TIMESTAMP 1 + + /*1: Print file and line number of the log; + *0: Do not print file and line number of the log*/ + #define LV_LOG_USE_FILE_LINE 1 + + /*Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs*/ + #define LV_LOG_TRACE_MEM 1 + #define LV_LOG_TRACE_TIMER 1 + #define LV_LOG_TRACE_INDEV 1 + #define LV_LOG_TRACE_DISP_REFR 1 + #define LV_LOG_TRACE_EVENT 1 + #define LV_LOG_TRACE_OBJ_CREATE 1 + #define LV_LOG_TRACE_LAYOUT 1 + #define LV_LOG_TRACE_ANIM 1 + #define LV_LOG_TRACE_CACHE 1 + +#endif /*LV_USE_LOG*/ + +/*------------- + * Asserts + *-----------*/ + +/*Enable asserts if an operation is failed or an invalid data is found. + *If LV_USE_LOG is enabled an error message will be printed on failure*/ +#define LV_USE_ASSERT_NULL 1 /*Check if the parameter is NULL. (Very fast, recommended)*/ +#define LV_USE_ASSERT_MALLOC 1 /*Checks is the memory is successfully allocated or no. (Very fast, recommended)*/ +#define LV_USE_ASSERT_STYLE 0 /*Check if the styles are properly initialized. (Very fast, recommended)*/ +#define LV_USE_ASSERT_MEM_INTEGRITY 0 /*Check the integrity of `lv_mem` after critical operations. (Slow)*/ +#define LV_USE_ASSERT_OBJ 0 /*Check the object's type and existence (e.g. not deleted). (Slow)*/ + +/*Add a custom handler when assert happens e.g. to restart the MCU*/ +#define LV_ASSERT_HANDLER_INCLUDE +#define LV_ASSERT_HANDLER while(1); /*Halt by default*/ + +/*------------- + * Debug + *-----------*/ + +/*1: Draw random colored rectangles over the redrawn areas*/ +#define LV_USE_REFR_DEBUG 0 + +/*1: Draw a red overlay for ARGB layers and a green overlay for RGB layers*/ +#define LV_USE_LAYER_DEBUG 0 + +/*1: Draw overlays with different colors for each draw_unit's tasks. + *Also add the index number of the draw unit on white background. + *For layers add the index number of the draw unit on black background.*/ +#define LV_USE_PARALLEL_DRAW_DEBUG 0 + +/*------------- + * Others + *-----------*/ + +#define LV_ENABLE_GLOBAL_CUSTOM 0 +#if LV_ENABLE_GLOBAL_CUSTOM + /*Header to include for the custom 'lv_global' function"*/ + #define LV_GLOBAL_CUSTOM_INCLUDE +#endif + +/*Default cache size in bytes. + *Used by image decoders such as `lv_lodepng` to keep the decoded image in the memory. + *If size is not set to 0, the decoder will fail to decode when the cache is full. + *If size is 0, the cache function is not enabled and the decoded mem will be released immediately after use.*/ +#define LV_CACHE_DEF_SIZE 0 + +/*Default number of image header cache entries. The cache is used to store the headers of images + *The main logic is like `LV_CACHE_DEF_SIZE` but for image headers.*/ +#define LV_IMAGE_HEADER_CACHE_DEF_CNT 0 + +/*Number of stops allowed per gradient. Increase this to allow more stops. + *This adds (sizeof(lv_color_t) + 1) bytes per additional stop*/ +#define LV_GRADIENT_MAX_STOPS 2 + +/* Adjust color mix functions rounding. GPUs might calculate color mix (blending) differently. + * 0: round down, 64: round up from x.75, 128: round up from half, 192: round up from x.25, 254: round up */ +#define LV_COLOR_MIX_ROUND_OFS 0 + +/* Add 2 x 32 bit variables to each lv_obj_t to speed up getting style properties */ +#define LV_OBJ_STYLE_CACHE 0 + +/* Add `id` field to `lv_obj_t` */ +#define LV_USE_OBJ_ID 0 + +/* Use lvgl builtin method for obj ID */ +#define LV_USE_OBJ_ID_BUILTIN 0 + +/*Use obj property set/get API*/ +#define LV_USE_OBJ_PROPERTY 0 + +/* VG-Lite Simulator */ +/*Requires: LV_USE_THORVG_INTERNAL or LV_USE_THORVG_EXTERNAL */ +#define LV_USE_VG_LITE_THORVG 0 + +#if LV_USE_VG_LITE_THORVG + + /*Enable LVGL's blend mode support*/ + #define LV_VG_LITE_THORVG_LVGL_BLEND_SUPPORT 0 + + /*Enable YUV color format support*/ + #define LV_VG_LITE_THORVG_YUV_SUPPORT 0 + + /*Enable 16 pixels alignment*/ + #define LV_VG_LITE_THORVG_16PIXELS_ALIGN 1 + + /*Enable multi-thread render*/ + #define LV_VG_LITE_THORVG_THREAD_RENDER 0 + +#endif + +/*===================== + * COMPILER SETTINGS + *====================*/ + +/*For big endian systems set to 1*/ +#define LV_BIG_ENDIAN_SYSTEM 0 + +/*Define a custom attribute to `lv_tick_inc` function*/ +#define LV_ATTRIBUTE_TICK_INC + +/*Define a custom attribute to `lv_timer_handler` function*/ +#define LV_ATTRIBUTE_TIMER_HANDLER __attribute__((section("CodeQuickAccess"))) + +/*Define a custom attribute to `lv_display_flush_ready` function*/ +#define LV_ATTRIBUTE_FLUSH_READY __attribute__((section("CodeQuickAccess"))) + +/*Required alignment size for buffers*/ +#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 1 + +/*Will be added where memories needs to be aligned (with -Os data might not be aligned to boundary by default). + * E.g. __attribute__((aligned(4)))*/ +#define LV_ATTRIBUTE_MEM_ALIGN + +/*Attribute to mark large constant arrays for example font's bitmaps*/ +#define LV_ATTRIBUTE_LARGE_CONST + +/*Compiler prefix for a big array declaration in RAM*/ +#define LV_ATTRIBUTE_LARGE_RAM_ARRAY __attribute__((section(".lvgl_largemem"))) + +/*Place performance critical functions into a faster memory (e.g RAM)*/ +#define LV_ATTRIBUTE_FAST_MEM + +/*Export integer constant to binding. This macro is used with constants in the form of LV_ that + *should also appear on LVGL binding API such as Micropython.*/ +#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning /*The default value just prevents GCC warning*/ + +/*Prefix all global extern data with this*/ +#define LV_ATTRIBUTE_EXTERN_DATA + +/* Use `float` as `lv_value_precise_t` */ +#define LV_USE_FLOAT 1 + +/*================== + * FONT USAGE + *===================*/ + +/*Montserrat fonts with ASCII range and some symbols using bpp = 4 + *https://fonts.google.com/specimen/Montserrat*/ +#define LV_FONT_MONTSERRAT_8 0 +#define LV_FONT_MONTSERRAT_10 0 +#define LV_FONT_MONTSERRAT_12 0 +#define LV_FONT_MONTSERRAT_14 1 +#define LV_FONT_MONTSERRAT_16 0 +#define LV_FONT_MONTSERRAT_18 0 +#define LV_FONT_MONTSERRAT_20 0 +#define LV_FONT_MONTSERRAT_22 0 +#define LV_FONT_MONTSERRAT_24 0 +#define LV_FONT_MONTSERRAT_26 0 +#define LV_FONT_MONTSERRAT_28 0 +#define LV_FONT_MONTSERRAT_30 0 +#define LV_FONT_MONTSERRAT_32 0 +#define LV_FONT_MONTSERRAT_34 0 +#define LV_FONT_MONTSERRAT_36 0 +#define LV_FONT_MONTSERRAT_38 0 +#define LV_FONT_MONTSERRAT_40 0 +#define LV_FONT_MONTSERRAT_42 0 +#define LV_FONT_MONTSERRAT_44 0 +#define LV_FONT_MONTSERRAT_46 0 +#define LV_FONT_MONTSERRAT_48 0 + +/*Demonstrate special features*/ +#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /*bpp = 3*/ +#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /*Hebrew, Arabic, Persian letters and all their forms*/ +#define LV_FONT_SIMSUN_16_CJK 0 /*1000 most common CJK radicals*/ + +/*Pixel perfect monospace fonts*/ +#define LV_FONT_UNSCII_8 0 +#define LV_FONT_UNSCII_16 0 + +/*Optionally declare custom fonts here. + *You can use these fonts as default font too and they will be available globally. + *E.g. #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) LV_FONT_DECLARE(my_font_2)*/ +#define LV_FONT_CUSTOM_DECLARE + +/*Always set a default font*/ +#define LV_FONT_DEFAULT &lv_font_montserrat_14 + +/*Enable handling large font and/or fonts with a lot of characters. + *The limit depends on the font size, font face and bpp. + *Compiler error will be triggered if a font needs it.*/ +#define LV_FONT_FMT_TXT_LARGE 0 + +/*Enables/disables support for compressed fonts.*/ +#define LV_USE_FONT_COMPRESSED 0 + +/*Enable drawing placeholders when glyph dsc is not found*/ +#define LV_USE_FONT_PLACEHOLDER 1 + +/*================= + * TEXT SETTINGS + *=================*/ + +/** + * Select a character encoding for strings. + * Your IDE or editor should have the same character encoding + * - LV_TXT_ENC_UTF8 + * - LV_TXT_ENC_ASCII + */ +#define LV_TXT_ENC LV_TXT_ENC_UTF8 + +/*Can break (wrap) texts on these chars*/ +#define LV_TXT_BREAK_CHARS " ,.;:-_)]}" + +/*If a word is at least this long, will break wherever "prettiest" + *To disable, set to a value <= 0*/ +#define LV_TXT_LINE_BREAK_LONG_LEN 0 + +/*Minimum number of characters in a long word to put on a line before a break. + *Depends on LV_TXT_LINE_BREAK_LONG_LEN.*/ +#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3 + +/*Minimum number of characters in a long word to put on a line after a break. + *Depends on LV_TXT_LINE_BREAK_LONG_LEN.*/ +#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3 + +/*Support bidirectional texts. Allows mixing Left-to-Right and Right-to-Left texts. + *The direction will be processed according to the Unicode Bidirectional Algorithm: + *https://www.w3.org/International/articles/inline-bidi-markup/uba-basics*/ +#define LV_USE_BIDI 0 +#if LV_USE_BIDI + /*Set the default direction. Supported values: + *`LV_BASE_DIR_LTR` Left-to-Right + *`LV_BASE_DIR_RTL` Right-to-Left + *`LV_BASE_DIR_AUTO` detect texts base direction*/ + #define LV_BIDI_BASE_DIR_DEF LV_BASE_DIR_AUTO +#endif + +/*Enable Arabic/Persian processing + *In these languages characters should be replaced with an other form based on their position in the text*/ +#define LV_USE_ARABIC_PERSIAN_CHARS 0 + +/*================== + * WIDGETS + *================*/ + +/*Documentation of the widgets: https://docs.lvgl.io/latest/en/html/widgets/index.html*/ + +#define LV_WIDGETS_HAS_DEFAULT_VALUE 1 + +#define LV_USE_ANIMIMG 1 + +#define LV_USE_ARC 1 + +#define LV_USE_BAR 1 + +#define LV_USE_BUTTON 1 + +#define LV_USE_BUTTONMATRIX 1 + +#define LV_USE_CALENDAR 1 +#if LV_USE_CALENDAR + #define LV_CALENDAR_WEEK_STARTS_MONDAY 0 + #if LV_CALENDAR_WEEK_STARTS_MONDAY + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Mo", "Tu", "We", "Th", "Fr", "Sa", "Su"} + #else + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Su", "Mo", "Tu", "We", "Th", "Fr", "Sa"} + #endif + + #define LV_CALENDAR_DEFAULT_MONTH_NAMES {"January", "February", "March", "April", "May", "June", "July", "August", "September", "October", "November", "December"} + #define LV_USE_CALENDAR_HEADER_ARROW 1 + #define LV_USE_CALENDAR_HEADER_DROPDOWN 1 +#endif /*LV_USE_CALENDAR*/ + +#define LV_USE_CANVAS 1 + +#define LV_USE_CHART 1 + +#define LV_USE_CHECKBOX 1 + +#define LV_USE_DROPDOWN 1 /*Requires: lv_label*/ + +#define LV_USE_IMAGE 1 /*Requires: lv_label*/ + +#define LV_USE_IMAGEBUTTON 1 + +#define LV_USE_KEYBOARD 1 + +#define LV_USE_LABEL 1 +#if LV_USE_LABEL + #define LV_LABEL_TEXT_SELECTION 1 /*Enable selecting text of the label*/ + #define LV_LABEL_LONG_TXT_HINT 1 /*Store some extra info in labels to speed up drawing of very long texts*/ + #define LV_LABEL_WAIT_CHAR_COUNT 3 /*The count of wait chart*/ +#endif + +#define LV_USE_LED 1 + +#define LV_USE_LINE 1 + +#define LV_USE_LIST 1 + +#define LV_USE_MENU 1 + +#define LV_USE_MSGBOX 1 + +#define LV_USE_ROLLER 1 /*Requires: lv_label*/ + +#define LV_USE_SCALE 1 + +#define LV_USE_SLIDER 1 /*Requires: lv_bar*/ + +#define LV_USE_SPAN 1 +#if LV_USE_SPAN + /*A line text can contain maximum num of span descriptor */ + #define LV_SPAN_SNIPPET_STACK_SIZE 64 +#endif + +#define LV_USE_SPINBOX 1 + +#define LV_USE_SPINNER 1 + +#define LV_USE_SWITCH 1 + +#define LV_USE_TEXTAREA 1 /*Requires: lv_label*/ +#if LV_USE_TEXTAREA != 0 + #define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /*ms*/ +#endif + +#define LV_USE_TABLE 1 + +#define LV_USE_TABVIEW 1 + +#define LV_USE_TILEVIEW 1 + +#define LV_USE_WIN 1 + +/*================== + * THEMES + *==================*/ + +/*A simple, impressive and very complete theme*/ +#define LV_USE_THEME_DEFAULT 1 +#if LV_USE_THEME_DEFAULT + + /*0: Light mode; 1: Dark mode*/ + #define LV_THEME_DEFAULT_DARK 0 + + /*1: Enable grow on press*/ + #define LV_THEME_DEFAULT_GROW 1 + + /*Default transition time in [ms]*/ + #define LV_THEME_DEFAULT_TRANSITION_TIME 80 +#endif /*LV_USE_THEME_DEFAULT*/ + +/*A very simple theme that is a good starting point for a custom theme*/ +#define LV_USE_THEME_SIMPLE 1 + +/*A theme designed for monochrome displays*/ +#define LV_USE_THEME_MONO 1 + +/*================== + * LAYOUTS + *==================*/ + +/*A layout similar to Flexbox in CSS.*/ +#define LV_USE_FLEX 1 + +/*A layout similar to Grid in CSS.*/ +#define LV_USE_GRID 1 + +/*==================== + * 3RD PARTS LIBRARIES + *====================*/ + +/*File system interfaces for common APIs */ + +/*API for fopen, fread, etc*/ +#define LV_USE_FS_STDIO 0 +#if LV_USE_FS_STDIO + #define LV_FS_STDIO_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_STDIO_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_STDIO_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for open, read, etc*/ +#define LV_USE_FS_POSIX 0 +#if LV_USE_FS_POSIX + #define LV_FS_POSIX_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_POSIX_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_POSIX_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for CreateFile, ReadFile, etc*/ +#define LV_USE_FS_WIN32 0 +#if LV_USE_FS_WIN32 + #define LV_FS_WIN32_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_WIN32_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/ + #define LV_FS_WIN32_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for FATFS (needs to be added separately). Uses f_open, f_read, etc*/ +#define LV_USE_FS_FATFS 0 +#if LV_USE_FS_FATFS + #define LV_FS_FATFS_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ + #define LV_FS_FATFS_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/ +#endif + +/*API for memory-mapped file access. */ +#define LV_USE_FS_MEMFS 0 +#if LV_USE_FS_MEMFS + #define LV_FS_MEMFS_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/ +#endif + +/*LODEPNG decoder library*/ +#define LV_USE_LODEPNG 0 + +/*PNG decoder(libpng) library*/ +#define LV_USE_LIBPNG 0 + +/*BMP decoder library*/ +#define LV_USE_BMP 0 + +/* JPG + split JPG decoder library. + * Split JPG is a custom format optimized for embedded systems. */ +#define LV_USE_TJPGD 0 + +/* libjpeg-turbo decoder library. + * Supports complete JPEG specifications and high-performance JPEG decoding. */ +#define LV_USE_LIBJPEG_TURBO 0 + +/*GIF decoder library*/ +#define LV_USE_GIF 0 +#if LV_USE_GIF +/*GIF decoder accelerate*/ +#define LV_GIF_CACHE_DECODE_DATA 0 +#endif + + +/*Decode bin images to RAM*/ +#define LV_BIN_DECODER_RAM_LOAD 0 + +/*RLE decompress library*/ +#define LV_USE_RLE 0 + +/*QR code library*/ +#define LV_USE_QRCODE 0 + +/*Barcode code library*/ +#define LV_USE_BARCODE 0 + +/*FreeType library*/ +#define LV_USE_FREETYPE 0 +#if LV_USE_FREETYPE + /*Memory used by FreeType to cache characters in kilobytes*/ + #define LV_FREETYPE_CACHE_SIZE 768 + + /*Let FreeType to use LVGL memory and file porting*/ + #define LV_FREETYPE_USE_LVGL_PORT 0 + + /* Maximum number of opened FT_Face/FT_Size objects managed by this cache instance. */ + /* (0:use system defaults) */ + #define LV_FREETYPE_CACHE_FT_FACES 8 + #define LV_FREETYPE_CACHE_FT_SIZES 8 + #define LV_FREETYPE_CACHE_FT_GLYPH_CNT 256 +#endif + +/* Built-in TTF decoder */ +#define LV_USE_TINY_TTF 0 +#if LV_USE_TINY_TTF + /* Enable loading TTF data from files */ + #define LV_TINY_TTF_FILE_SUPPORT 0 +#endif + +/*Rlottie library*/ +#define LV_USE_RLOTTIE 0 + +/*Enable Vector Graphic APIs*/ +#define LV_USE_VECTOR_GRAPHIC 0 + +/* Enable ThorVG (vector graphics library) from the src/libs folder */ +#define LV_USE_THORVG_INTERNAL 0 + +/* Enable ThorVG by assuming that its installed and linked to the project */ +#define LV_USE_THORVG_EXTERNAL 0 + +/*Enable LZ4 compress/decompress lib*/ +#define LV_USE_LZ4 0 + +/*Use lvgl built-in LZ4 lib*/ +#define LV_USE_LZ4_INTERNAL 0 + +/*Use external LZ4 library*/ +#define LV_USE_LZ4_EXTERNAL 0 + +/*FFmpeg library for image decoding and playing videos + *Supports all major image formats so do not enable other image decoder with it*/ +#define LV_USE_FFMPEG 0 +#if LV_USE_FFMPEG + /*Dump input information to stderr*/ + #define LV_FFMPEG_DUMP_FORMAT 0 +#endif + +/*================== + * OTHERS + *==================*/ + +/*1: Enable API to take snapshot for object*/ +#define LV_USE_SNAPSHOT 0 + +/*1: Enable system monitor component*/ +#define LV_USE_SYSMON 1 +#if LV_USE_SYSMON + /*Get the idle percentage. E.g. uint32_t my_get_idle(void);*/ + #define LV_SYSMON_GET_IDLE lv_timer_get_idle + + /*1: Show CPU usage and FPS count + * Requires `LV_USE_SYSMON = 1`*/ + #define LV_USE_PERF_MONITOR 1 + #if LV_USE_PERF_MONITOR + #define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT + + /*0: Displays performance data on the screen, 1: Prints performance data using log.*/ + #define LV_USE_PERF_MONITOR_LOG_MODE 0 + #endif + + /*1: Show the used memory and the memory fragmentation + * Requires `LV_USE_BUILTIN_MALLOC = 1` + * Requires `LV_USE_SYSMON = 1`*/ + #define LV_USE_MEM_MONITOR 0 + #if LV_USE_MEM_MONITOR + #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT + #endif + +#endif /*LV_USE_SYSMON*/ + +/*1: Enable the runtime performance profiler*/ +#define LV_USE_PROFILER 0 +#if LV_USE_PROFILER + /*1: Enable the built-in profiler*/ + #define LV_USE_PROFILER_BUILTIN 1 + #if LV_USE_PROFILER_BUILTIN + /*Default profiler trace buffer size*/ + #define LV_PROFILER_BUILTIN_BUF_SIZE (16 * 1024) /*[bytes]*/ + #endif + + /*Header to include for the profiler*/ + #define LV_PROFILER_INCLUDE "lvgl/src/misc/lv_profiler_builtin.h" + + /*Profiler start point function*/ + #define LV_PROFILER_BEGIN LV_PROFILER_BUILTIN_BEGIN + + /*Profiler end point function*/ + #define LV_PROFILER_END LV_PROFILER_BUILTIN_END + + /*Profiler start point function with custom tag*/ + #define LV_PROFILER_BEGIN_TAG LV_PROFILER_BUILTIN_BEGIN_TAG + + /*Profiler end point function with custom tag*/ + #define LV_PROFILER_END_TAG LV_PROFILER_BUILTIN_END_TAG +#endif + +/*1: Enable Monkey test*/ +#define LV_USE_MONKEY 0 + +/*1: Enable grid navigation*/ +#define LV_USE_GRIDNAV 0 + +/*1: Enable lv_obj fragment*/ +#define LV_USE_FRAGMENT 0 + +/*1: Support using images as font in label or span widgets */ +#define LV_USE_IMGFONT 0 + +/*1: Enable an observer pattern implementation*/ +#define LV_USE_OBSERVER 1 + +/*1: Enable Pinyin input method*/ +/*Requires: lv_keyboard*/ +#define LV_USE_IME_PINYIN 0 +#if LV_USE_IME_PINYIN + /*1: Use default thesaurus*/ + /*If you do not use the default thesaurus, be sure to use `lv_ime_pinyin` after setting the thesauruss*/ + #define LV_IME_PINYIN_USE_DEFAULT_DICT 1 + /*Set the maximum number of candidate panels that can be displayed*/ + /*This needs to be adjusted according to the size of the screen*/ + #define LV_IME_PINYIN_CAND_TEXT_NUM 6 + + /*Use 9 key input(k9)*/ + #define LV_IME_PINYIN_USE_K9_MODE 1 + #if LV_IME_PINYIN_USE_K9_MODE == 1 + #define LV_IME_PINYIN_K9_CAND_TEXT_NUM 3 + #endif /*LV_IME_PINYIN_USE_K9_MODE*/ +#endif + +/*1: Enable file explorer*/ +/*Requires: lv_table*/ +#define LV_USE_FILE_EXPLORER 0 +#if LV_USE_FILE_EXPLORER + /*Maximum length of path*/ + #define LV_FILE_EXPLORER_PATH_MAX_LEN (128) + /*Quick access bar, 1:use, 0:not use*/ + /*Requires: lv_list*/ + #define LV_FILE_EXPLORER_QUICK_ACCESS 1 +#endif + +/*================== + * DEVICES + *==================*/ + +/*Use SDL to open window on PC and handle mouse and keyboard*/ +#define LV_USE_SDL 0 +#if LV_USE_SDL + #define LV_SDL_INCLUDE_PATH + #define LV_SDL_RENDER_MODE LV_DISPLAY_RENDER_MODE_DIRECT /*LV_DISPLAY_RENDER_MODE_DIRECT is recommended for best performance*/ + #define LV_SDL_BUF_COUNT 1 /*1 or 2*/ + #define LV_SDL_FULLSCREEN 0 /*1: Make the window full screen by default*/ + #define LV_SDL_DIRECT_EXIT 1 /*1: Exit the application when all SDL windows are closed*/ +#endif + +/*Use X11 to open window on Linux desktop and handle mouse and keyboard*/ +#define LV_USE_X11 0 +#if LV_USE_X11 + #define LV_X11_DIRECT_EXIT 1 /*Exit the application when all X11 windows have been closed*/ + #define LV_X11_DOUBLE_BUFFER 1 /*Use double buffers for endering*/ + /*select only 1 of the following render modes (LV_X11_RENDER_MODE_PARTIAL preferred!)*/ + #define LV_X11_RENDER_MODE_PARTIAL 1 /*Partial render mode (preferred)*/ + #define LV_X11_RENDER_MODE_DIRECT 0 /*direct render mode*/ + #define LV_X11_RENDER_MODE_FULL 0 /*Full render mode*/ +#endif + +/*Driver for /dev/fb*/ +#define LV_USE_LINUX_FBDEV 0 +#if LV_USE_LINUX_FBDEV + #define LV_LINUX_FBDEV_BSD 0 + #define LV_LINUX_FBDEV_RENDER_MODE LV_DISPLAY_RENDER_MODE_PARTIAL + #define LV_LINUX_FBDEV_BUFFER_COUNT 0 + #define LV_LINUX_FBDEV_BUFFER_SIZE 60 +#endif + +/*Use Nuttx to open window and handle touchscreen*/ +#define LV_USE_NUTTX 0 + +#if LV_USE_NUTTX + #define LV_USE_NUTTX_LIBUV 0 + + /*Use Nuttx custom init API to open window and handle touchscreen*/ + #define LV_USE_NUTTX_CUSTOM_INIT 0 + + /*Driver for /dev/lcd*/ + #define LV_USE_NUTTX_LCD 0 + #if LV_USE_NUTTX_LCD + #define LV_NUTTX_LCD_BUFFER_COUNT 0 + #define LV_NUTTX_LCD_BUFFER_SIZE 60 + #endif + + /*Driver for /dev/input*/ + #define LV_USE_NUTTX_TOUCHSCREEN 0 + +#endif + +/*Driver for /dev/dri/card*/ +#define LV_USE_LINUX_DRM 0 + +/*Interface for TFT_eSPI*/ +#define LV_USE_TFT_ESPI 0 + +/*Driver for evdev input devices*/ +#define LV_USE_EVDEV 0 + +/*Drivers for LCD devices connected via SPI/parallel port*/ +#define LV_USE_ST7735 0 +#define LV_USE_ST7789 0 +#define LV_USE_ST7796 0 +#define LV_USE_ILI9341 0 + +#define LV_USE_GENERIC_MIPI (LV_USE_ST7735 | LV_USE_ST7789 | LV_USE_ST7796 | LV_USE_ILI9341) + +/* LVGL Windows backend */ +#define LV_USE_WINDOWS 0 + +/*================== +* EXAMPLES +*==================*/ + +/*Enable the examples to be built with the library*/ +#define LV_BUILD_EXAMPLES 1 + +/*=================== + * DEMO USAGE + ====================*/ + +/*Show some widget. It might be required to increase `LV_MEM_SIZE` */ +#define LV_USE_DEMO_WIDGETS 1 +#if LV_USE_DEMO_WIDGETS + #define LV_DEMO_WIDGETS_SLIDESHOW 0 +#endif + +/*Demonstrate the usage of encoder and keyboard*/ +#define LV_USE_DEMO_KEYPAD_AND_ENCODER 0 + +/*Benchmark your system*/ +#define LV_USE_DEMO_BENCHMARK 0 + +/*Render test for each primitives. Requires at least 480x272 display*/ +#define LV_USE_DEMO_RENDER 0 + +/*Stress test for LVGL*/ +#define LV_USE_DEMO_STRESS 0 + +/*Music player demo*/ +#define LV_USE_DEMO_MUSIC 0 +#if LV_USE_DEMO_MUSIC + #define LV_DEMO_MUSIC_SQUARE 0 + #define LV_DEMO_MUSIC_LANDSCAPE 0 + #define LV_DEMO_MUSIC_ROUND 0 + #define LV_DEMO_MUSIC_LARGE 0 + #define LV_DEMO_MUSIC_AUTO_PLAY 0 +#endif + +/*Flex layout demo*/ +#define LV_USE_DEMO_FLEX_LAYOUT 0 + +/*Smart-phone like multi-language demo*/ +#define LV_USE_DEMO_MULTILANG 0 + +/*Widget transformation demo*/ +#define LV_USE_DEMO_TRANSFORM 0 + +/*Demonstrate scroll settings*/ +#define LV_USE_DEMO_SCROLL 0 + +/*Vector graphic demo*/ +#define LV_USE_DEMO_VECTOR_GRAPHIC 0 +/*--END OF LV_CONF_H--*/ + +#endif /*LV_CONF_H*/ + +#endif /*End of "Content enable"*/ diff --git a/lib/freertos b/lib/freertos new file mode 160000 index 0000000..625b24a --- /dev/null +++ b/lib/freertos @@ -0,0 +1 @@ +Subproject commit 625b24a104dd901d86759668b6b272590d154308 diff --git a/lib/lcd b/lib/lcd new file mode 160000 index 0000000..651efeb --- /dev/null +++ b/lib/lcd @@ -0,0 +1 @@ +Subproject commit 651efeb64848a969657f58171ae1dbab2f7e454d diff --git a/lib/lvgl b/lib/lvgl new file mode 160000 index 0000000..3c8ef96 --- /dev/null +++ b/lib/lvgl @@ -0,0 +1 @@ +Subproject commit 3c8ef962132fc3910d2ca629b9810ac6335a35d4 diff --git a/src/app_impl_lcd.c b/src/app_impl_lcd.c new file mode 100644 index 0000000..0ec9308 --- /dev/null +++ b/src/app_impl_lcd.c @@ -0,0 +1,46 @@ +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" + +/* SDK drivers */ +#include "fsl_lpspi.h" + +/* Board */ +#include "board.h" +#include "clock_config.h" +#include "peripherals.h" +#include "pin_mux.h" + +/* LCD */ +#include "app_impl_lcd.h" + +int app_lcd_impl_init(void *handle) { + CLOCK_EnableClock(kCLOCK_Lpspi4); + + lpspi_master_config_t spi_cfg; + LPSPI_MasterGetDefaultConfig(&spi_cfg); + + spi_cfg.baudRate = 24000000UL; + + LPSPI_MasterInit(LPSPI4, &spi_cfg, CLOCK_GetClockRootFreq(kCLOCK_LpspiClkRoot)); + + return 0; +} + +epd_ret_t app_lcd_impl_write_command(void *handle, uint8_t *command, uint32_t len) { + /* 02 - 00 - CMD - 00 - DATA0 - ... - DATAN */ + + return EPD_OK; +} + +epd_ret_t app_lcd_impl_write_data(void *handle, const uint8_t *data, uint32_t len) { + /* 02 - 00 - CMD(2C) - 00 - DATA0 - ... - DATAN */ + + return EPD_OK; +} + +epd_ret_t app_lcd_impl_delay(void *handle, uint32_t msec) { + vTaskDelay(pdMS_TO_TICKS(msec)); + + return EPD_OK; +} \ No newline at end of file diff --git a/src/app_lvgl.c b/src/app_lvgl.c new file mode 100644 index 0000000..35237a7 --- /dev/null +++ b/src/app_lvgl.c @@ -0,0 +1,98 @@ + +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* LVGL */ +#include "lv_demos.h" +#include "lvgl.h" + +/* App */ +#include "app_impl_lcd.h" +#include "app_lvgl.h" + +#define APP_LVGL_WIDTH (360) +#define APP_LVGL_HEIGHT (360) + +static SemaphoreHandle_t s_lvgl_semphr = NULL; + +static uint16_t s_lcd_buffer[APP_LVGL_WIDTH * 10]; + +static uint32_t app_lvgl_get_tick_cb(void); +static void app_lvgl_lcd_flush_cb(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map); +static void app_lvgl_task(void *arguments); + +int app_lvgl_init(void) { + s_lvgl_semphr = xSemaphoreCreateBinary(); + if (s_lvgl_semphr == NULL) { + return -1; + } + + xSemaphoreGive(s_lvgl_semphr); + + app_lcd_impl_init(NULL); + + lv_init(); + + lv_tick_set_cb(app_lvgl_get_tick_cb); + + uint16_t hor_res = APP_LVGL_WIDTH; + uint16_t ver_res = APP_LVGL_HEIGHT; + + lv_display_t *display = lv_display_create(hor_res, ver_res); + if (display == NULL) { + goto deinit_lv_exit; + } + + lv_display_set_flush_cb(display, app_lvgl_lcd_flush_cb); + lv_display_set_buffers(display, s_lcd_buffer, NULL, sizeof(s_lcd_buffer), LV_DISPLAY_RENDER_MODE_PARTIAL); + + lv_demo_widgets(); + + if (xTaskCreate(app_lvgl_task, "LVGL", 2048, NULL, 3, NULL) != pdPASS) { + goto destroy_display_exit; + } + + return 0; + +destroy_display_exit: + lv_display_delete(display); + +deinit_lv_exit: + lv_deinit(); + vSemaphoreDelete(s_lvgl_semphr); + + return -1; +} + +bool app_lvgl_lock(uint32_t timeout_ms) { + if (xSemaphoreTake(s_lvgl_semphr, pdMS_TO_TICKS(timeout_ms)) != pdPASS) { + return false; + } + + return true; +} + +void app_lvgl_unlock(void) { + xSemaphoreGive(s_lvgl_semphr); +} + +static uint32_t app_lvgl_get_tick_cb(void) { + return xTaskGetTickCount(); +} + +static void app_lvgl_lcd_flush_cb(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map) { + lv_display_flush_ready(disp); +} + +static void app_lvgl_task(void *arguments) { + for (;;) { + if (app_lvgl_lock(portMAX_DELAY)) { + lv_task_handler(); + app_lvgl_unlock(); + } + + vTaskDelay(pdMS_TO_TICKS(5)); + } +} \ No newline at end of file diff --git a/src/main.c b/src/main.c index fd199ab..644fc62 100644 --- a/src/main.c +++ b/src/main.c @@ -1,25 +1,70 @@ +/* + * Copyright 2024 NXP + * Copyright 2024 Yilin Sun + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + #include /* Board */ #include "board.h" #include "clock_config.h" -#include "peripherals.h" #include "pin_mux.h" -int main(void) { - BOARD_ConfigMPU(); +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" +/* App */ +#include "app_lvgl.h" + +static void app_task_initialization(void *arguments); + +int main(void) { + /* Init board hardware. */ + BOARD_ConfigMPU(); BOARD_InitBootPins(); BOARD_InitBootClocks(); - BOARD_InitBootPeripherals(); - - BOARD_InitDebugConsole(); CLOCK_SetMode(kCLOCK_ModeRun); - printf("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq()); + BOARD_InitDebugConsole(); + + if (xTaskCreate(app_task_initialization, "Init", 2048, NULL, 2, NULL) != pdPASS) { + goto dead_loop; + } + + vTaskStartScheduler(); + +dead_loop: + for (;;) { + __WFI(); + } +} + +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) { + printf("Task stack overflow in %s.\r\n", pcTaskName); for (;;) { __WFI(); } } + +void vApplicationMallocFailedHook(void) { + printf("Malloc failed.\r\n"); + + for (;;) { + __WFI(); + } +} + +static void app_task_initialization(void *arguments) { + app_lvgl_init(); + + for (;;) { + GPIO_PortToggle(BOARD_INITLEDPINS_LEDA_GPIO, BOARD_INITLEDPINS_LEDA_PIN_MASK); + vTaskDelay(pdMS_TO_TICKS(100)); + } +} \ No newline at end of file diff --git a/xip/fire_rt1052_pro_flexspi_nor_config.c b/xip/fire_rt1052_pro_flexspi_nor_config.c index 89e852e..54eb684 100644 --- a/xip/fire_rt1052_pro_flexspi_nor_config.c +++ b/xip/fire_rt1052_pro_flexspi_nor_config.c @@ -23,42 +23,44 @@ __attribute__((section(".boot_hdr.conf"), used)) #endif const flexspi_nor_config_t spiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, - .csHoldTime = 3U, - .csSetupTime = 3U, - .columnAddressWidth = 0U, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 32U * 1024U * 1024U, - .busyOffset = 0U, - .busyBitPolarity = 1U, - .lookupTable = { - // Fast read quad IO (ECh) [NOR_CMD_LUT_SEQ_IDX_READ] - [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20), - [4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04), - [4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00), + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3U, + .csSetupTime = 3U, + .columnAddressWidth = 0U, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 32U * 1024U * 1024U, + .busyOffset = 0U, + .busyBitPolarity = 1U, + .lookupTable = + { + // Fast read quad IO (ECh) [NOR_CMD_LUT_SEQ_IDX_READ] + [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20), + [4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04), + [4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00), - // Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS] - [4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00), + // Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS] + [4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00), - // Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] - [4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00), + // Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] + [4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00), - // Page program (34h) [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] - [4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x34, RADDR_SDR, FLEXSPI_4PAD, 0x20), - [4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00), + // Page program (34h) [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] + [4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x34, RADDR_SDR, FLEXSPI_4PAD, 0x20), + [4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00), - // Erase sector (21h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] - [4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20), + // Erase sector (21h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] + [4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20), - // Erase block 64kB (DCh) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK] - [4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20), + // Erase block 64kB (DCh) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK] + [4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xDC, RADDR_SDR, FLEXSPI_1PAD, 0x20), + }, }, - }, .pageSize = 256u, .sectorSize = 4u * 1024u, .blockSize = 64u * 1024u,