/*
 * Copyright 2017-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include "fire_rt1052_pro_flexspi_nor_config.h"

/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif

/*******************************************************************************
 * Code
 ******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif

const flexspi_nor_config_t spiflash_config = {
    .memConfig = {
        .tag                 = FLEXSPI_CFG_BLK_TAG,
        .version             = FLEXSPI_CFG_BLK_VERSION,
        .readSampleClkSrc    = kFlexSPIReadSampleClk_LoopbackInternally,
        .csHoldTime          = 3U,
        .csSetupTime         = 3U,
        .columnAddressWidth  = 0U,
        .deviceType      = kFlexSpiDeviceType_SerialNOR,
        .sflashPadType   = kSerialFlash_4Pads,
        .serialClkFreq   = kFlexSpiSerialClk_133MHz,
        .sflashA1Size    = 32U * 1024U * 1024U,
        .busyOffset      = 0U,
        .busyBitPolarity = 1U,
        .lookupTable = {
            // Fast read quad IO (EBh) [NOR_CMD_LUT_SEQ_IDX_READ]
            [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
            [4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04),
            [4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),

            // Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS]
            [4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00),

            // Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE]
            [4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00),

            // Page program () [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM]
            [4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_4PAD, 0x18),
            [4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),

            // Erase sector (20h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR]
            [4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),

            // Erase block 32kB (52h) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK]
            [4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x52, RADDR_SDR, FLEXSPI_1PAD, 0x18),
        },
    },
    .pageSize   = 256u,
    .sectorSize = 4u * 1024u,
    .blockSize  = 32u * 1024u,
};
#endif /* XIP_BOOT_HEADER_ENABLE */
