#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_

#include "fsl_common.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */

#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
 ************************ BOARD_InitBootClocks function ************************
 ******************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes default configuration of clocks.
 *
 */
void BOARD_InitBootClocks(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************* Configuration Board_BootClockPLL600MHz ********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for Board_BootClockPLL600MHz configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK       600000000U  /*!< Core clock frequency: 600000000Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT         600000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT         2000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT   0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK            0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK            0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M               1000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M              24000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT         12000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK        2400000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK     1200000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK         0UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK          0UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT     1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT     1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT     132000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT         150000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT       3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT       3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT       105600000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK            1200000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK             3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT      5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK        24000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2           3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2           0UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2           0UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT        132000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT      1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT    0UL
#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT       88000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT        4000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK          0UL
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK          0UL
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT      198000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT      198000000UL

/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration.
 */
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz;
/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration.
 */
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz;
/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration.
 */
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz;

/*******************************************************************************
 * API for Board_BootClockPLL600MHz configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void Board_BootClockPLL600MHz(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************* Configuration Board_BootClockPLL480MHz ********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for Board_BootClockPLL480MHz configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK       480000000U  /*!< Core clock frequency: 480000000Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT         480000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT         2000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT   0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK            0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK            0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M               1000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M              24000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT         12000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK        2400000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK     1200000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK         0UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK          0UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT     1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT     1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT     132000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT         120000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT       3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT       3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT       105600000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK            960000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK             3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT      4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK        24000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2           3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2           0UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT        3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1           3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2           0UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3           1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT        132000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT      1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT    0UL
#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT       88000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT        4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK          0UL
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK          0UL
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT      198000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT      198000000UL

/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration.
 */
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz;
/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration.
 */
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz;
/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration.
 */
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz;

/*******************************************************************************
 * API for Board_BootClockPLL480MHz configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void Board_BootClockPLL480MHz(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
 ******************** Configuration BOARD_BootClockXT24MHz *********************
 ******************************************************************************/
/*******************************************************************************
 * Definitions for BOARD_BootClockXT24MHz configuration
 ******************************************************************************/
#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK          24000000U  /*!< Core clock frequency: 24000000Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT           24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT           2000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT     0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK              0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK              0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M                 1000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M                24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT           12000000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK          2400000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK       1200000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK           0UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK            0UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT       1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT       1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT       24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ  6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ  6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT           6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT         3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT         3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT         6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK              24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK               3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT        6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK          24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT          3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1             3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2             3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3             1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT          3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1             3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2             0UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3             1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT          3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1             3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2             0UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3             1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT          24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT        1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT      0UL
#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT         6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT          4000000UL
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK            0UL
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK            0UL
#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT        12000000UL
#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT        12000000UL

/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration.
 */
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz;

/*******************************************************************************
 * API for BOARD_BootClockXT24MHz configuration
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
 * @brief This function executes configuration of clocks.
 *
 */
void BOARD_BootClockXT24MHz(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

#endif /* _CLOCK_CONFIG_H_ */

