From 3c90aa2c45526296cda6bcb0d80b75d6497578da Mon Sep 17 00:00:00 2001
From: Embedded_Projects <>
Date: Sat, 10 Dec 2022 08:44:10 +0000
Subject: [PATCH] Initial commit
---
.clang-format | 11 +
.clang-tidy | 4 +
.gitignore | 6 +
.gitmodules | 3 +
CMakeLists.txt | 211 ++++
MIMXRT1052xxxxB.mex | 1055 +++++++++++++++++++
arm-none-eabi.cmake | 17 +
board/board.c | 194 ++++
board/board.h | 111 ++
board/clock_config.c | 1181 ++++++++++++++++++++++
board/clock_config.h | 274 +++++
board/dcd.c | 45 +
board/dcd.h | 25 +
board/peripherals.c | 93 ++
board/peripherals.h | 33 +
board/pin_mux.c | 813 +++++++++++++++
board/pin_mux.h | 246 +++++
include/.gitkeep | 0
lib/.gitkeep | 0
src/main.c | 24 +
xip/fire_rt1052_pro_flexspi_nor_config.c | 66 ++
xip/fire_rt1052_pro_flexspi_nor_config.h | 267 +++++
22 files changed, 4679 insertions(+)
create mode 100644 .clang-format
create mode 100644 .clang-tidy
create mode 100644 .gitignore
create mode 100644 .gitmodules
create mode 100644 CMakeLists.txt
create mode 100644 MIMXRT1052xxxxB.mex
create mode 100644 arm-none-eabi.cmake
create mode 100644 board/board.c
create mode 100644 board/board.h
create mode 100644 board/clock_config.c
create mode 100644 board/clock_config.h
create mode 100644 board/dcd.c
create mode 100644 board/dcd.h
create mode 100644 board/peripherals.c
create mode 100644 board/peripherals.h
create mode 100644 board/pin_mux.c
create mode 100644 board/pin_mux.h
create mode 100644 include/.gitkeep
create mode 100644 lib/.gitkeep
create mode 100644 src/main.c
create mode 100644 xip/fire_rt1052_pro_flexspi_nor_config.c
create mode 100644 xip/fire_rt1052_pro_flexspi_nor_config.h
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..7ba2003
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,11 @@
+BasedOnStyle: Google
+IndentWidth: 4
+AlignConsecutiveMacros: AcrossEmptyLines
+AlignConsecutiveDeclarations: AcrossEmptyLines
+AlignConsecutiveAssignments: AcrossEmptyLinesAndComments
+BreakBeforeBraces: Custom
+BraceWrapping:
+ AfterEnum: false
+ AfterStruct: false
+ SplitEmptyFunction: false
+ColumnLimit: 120
\ No newline at end of file
diff --git a/.clang-tidy b/.clang-tidy
new file mode 100644
index 0000000..8ccd448
--- /dev/null
+++ b/.clang-tidy
@@ -0,0 +1,4 @@
+Checks: >
+ *,
+ -altera-unroll-loops,
+ -hicpp-no-assembler
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ee1fbdd
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,6 @@
+/board/*.bak
+/build
+/cmake-build-*
+/.vscode
+/*.jdebug*
+/*.jflash
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..e537b8d
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "SDK"]
+ path = SDK
+ url = git@git.minori.work:Embedded_SDK/MCUXpresso_MIMXRT1052xxxxB.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 0000000..5698557
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,211 @@
+cmake_minimum_required(VERSION 3.10)
+
+project(fire_rt1052_pro_template)
+
+enable_language(CXX)
+enable_language(ASM)
+
+# Different linker scripts
+set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld")
+set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld")
+
+set(TARGET_SOURCES
+ "SDK/components/serial_manager/fsl_component_serial_manager.c"
+ "SDK/components/serial_manager/fsl_component_serial_port_uart.c"
+ "SDK/components/uart/fsl_adapter_lpuart.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_adc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_adc_etc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_aipstz.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_aoi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_bee.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_cache.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_clock.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_cmp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_common.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_common_arm.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_csi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_dcdc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_dcp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_dmamux.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_elcdif.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_enc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_enet.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_ewm.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexcan.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_camera.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_camera_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_i2s.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_mculcd.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_mculcd_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_spi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_uart.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexram.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexram_allocate.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexspi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_flexspi_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_gpc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_gpio.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_gpt.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_kpp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpi2c.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpspi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpspi_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpuart.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_lpuart_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_ocotp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_pit.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_pmu.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_pwm.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_pxp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_qtmr.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_romapi.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_rtwdog.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_sai.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_sai_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_semc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_snvs_hp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_snvs_lp.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_spdif.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_spdif_edma.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_src.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_tempmon.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_trng.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_tsc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_usdhc.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_wdog.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_xbara.c"
+ "SDK/devices/MIMXRT1052/drivers/fsl_xbarb.c"
+ "SDK/devices/MIMXRT1052/gcc/startup_MIMXRT1052.S"
+ "SDK/devices/MIMXRT1052/system_MIMXRT1052.c"
+ "SDK/devices/MIMXRT1052/utilities/debug_console/fsl_debug_console.c"
+ "SDK/devices/MIMXRT1052/utilities/fsl_assert.c"
+ "SDK/devices/MIMXRT1052/utilities/fsl_notifier.c"
+ "SDK/devices/MIMXRT1052/utilities/fsl_sbrk.c"
+ "SDK/devices/MIMXRT1052/utilities/str/fsl_str.c"
+ "SDK/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c"
+ "board/board.c"
+ "board/clock_config.c"
+ "board/dcd.c"
+ "board/peripherals.c"
+ "board/pin_mux.c"
+ "src/main.c"
+ "xip/fire_rt1052_pro_flexspi_nor_config.c"
+)
+
+set(TARGET_C_DEFINES
+ "CPU_MIMXRT1052DVL6B"
+ "MCUXPRESSO_SDK"
+ "PRINTF_ADVANCED_ENABLE=1"
+ "PRINTF_FLOAT_ENABLE=1"
+ "SERIAL_PORT_TYPE_UART"
+ "__STARTUP_CLEAR_BSS"
+ "__STARTUP_INITIALIZE_NONCACHEDATA"
+)
+
+set(TARGET_C_DEFINES_XIP
+ "SKIP_SYSCLK_INIT"
+ "XIP_BOOT_HEADER_ENABLE=1"
+ "XIP_BOOT_HEADER_DCD_ENABLE=1"
+ "XIP_EXTERNAL_FLASH=1"
+)
+
+set(TARGET_C_INCLUDES
+ "SDK/CMSIS/Core/Include"
+ "SDK/components/serial_manager"
+ "SDK/components/uart"
+ "SDK/devices/MIMXRT1052"
+ "SDK/devices/MIMXRT1052/drivers"
+ "SDK/devices/MIMXRT1052/utilities"
+ "SDK/devices/MIMXRT1052/utilities/debug_console"
+ "SDK/devices/MIMXRT1052/utilities/str"
+ "board"
+ "include"
+)
+
+# Shared libraries linked with application
+set(TARGET_LIBS
+ "c"
+ "m"
+ "nosys"
+)
+
+# Shared library and linker script search paths
+set(TARGET_LIB_DIRECTORIES
+
+)
+
+# Conditional flags
+# DEBUG
+set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_ASM_FLAGS_DEBUG "-DDEBUG -O0 -g")
+
+# RELEASE
+set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
+set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto")
+
+# Final compiler flags
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
+set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections")
+
+# Shared sources, includes and definitions
+add_compile_definitions(${TARGET_C_DEFINES})
+include_directories(${TARGET_C_INCLUDES})
+link_directories(${TARGET_LIB_DIRECTORIES})
+link_libraries(${TARGET_LIBS})
+
+# Main targets are added here
+
+# Create ELF
+add_executable("${CMAKE_PROJECT_NAME}_FLASH.elf" ${TARGET_SOURCES})
+target_compile_definitions("${CMAKE_PROJECT_NAME}_FLASH.elf"
+ PRIVATE ${TARGET_C_DEFINES_XIP}
+)
+target_link_options("${CMAKE_PROJECT_NAME}_FLASH.elf"
+ PRIVATE "-T${TARGET_LDSCRIPT_FLASH}"
+ PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_FLASH.map"
+)
+set_property(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" APPEND
+ PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_FLASH.map"
+)
+add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH.hex"
+ COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLASH.elf" "${CMAKE_PROJECT_NAME}_FLASH.hex"
+ DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.elf"
+)
+add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.hex")
+if(DEFINED TARGET_TOOLCHAIN_SIZE)
+add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD
+ COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH.elf"
+)
+endif()
+
+# Create ELF
+add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${TARGET_SOURCES})
+target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf"
+ PRIVATE "-T${TARGET_LDSCRIPT_RAM}"
+ PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_RAM.map"
+)
+set_property(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" APPEND
+ PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_RAM.map"
+)
+add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex"
+ COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_RAM.elf" "${CMAKE_PROJECT_NAME}_RAM.hex"
+ DEPENDS "${CMAKE_PROJECT_NAME}_RAM.elf"
+)
+add_custom_target("${CMAKE_PROJECT_NAME}_RAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_RAM.hex")
+if(DEFINED TARGET_TOOLCHAIN_SIZE)
+add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" POST_BUILD
+ COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_RAM.elf"
+)
+endif()
diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex
new file mode 100644
index 0000000..bda67f2
--- /dev/null
+++ b/MIMXRT1052xxxxB.mex
@@ -0,0 +1,1055 @@
+
+
+
+ MIMXRT1052xxxxB
+ MIMXRT1052DVL6B
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
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+
+
+ 12.0.0
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
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+
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+
+
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+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
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+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
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+ true
+
+
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+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
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+ true
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+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
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+ true
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+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
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+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
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+ true
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+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
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+ true
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+
+
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+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
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+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
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+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+
+
+
+
+
+
+
+
+
+ 12.0.0
+ c_array
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 12.0.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ N/A
+
+
+
+
\ No newline at end of file
diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake
new file mode 100644
index 0000000..a9ef74e
--- /dev/null
+++ b/arm-none-eabi.cmake
@@ -0,0 +1,17 @@
+# Poor old Windows...
+if(WIN32)
+ set(CMAKE_SYSTEM_NAME "Generic")
+endif()
+
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+
+# Optionally set size binary name, for elf section size reporting.
+set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size)
+
+set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16")
+set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16")
+set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments")
+
+# Make CMake happy about those compilers
+set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY")
diff --git a/board/board.c b/board/board.c
new file mode 100644
index 0000000..4a5d727
--- /dev/null
+++ b/board/board.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#include "fsl_iomuxc.h"
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get debug console frequency. */
+uint32_t BOARD_DebugConsoleSrcFreq(void)
+{
+ uint32_t freq;
+
+ /* To make it simple, we assume default PLL and divider settings, and the only variable
+ from application is use PLL3 source or OSC source */
+ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
+ {
+ freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+ else
+ {
+ freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+ }
+
+ return freq;
+}
+
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+/* MPU configuration. */
+void BOARD_ConfigMPU(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$RW_m_ncache$$Base[];
+ /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
+ extern uint32_t Image$$RW_m_ncache_unused$$Base[];
+ extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
+ uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
+ uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
+ 0 :
+ ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
+#elif defined(__MCUXPRESSO)
+ extern uint32_t __base_NCACHE_REGION;
+ extern uint32_t __top_NCACHE_REGION;
+ uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
+ uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
+#elif defined(__ICCARM__) || defined(__GNUC__)
+ extern uint32_t __NCACHE_REGION_START[];
+ extern uint32_t __NCACHE_REGION_SIZE[];
+ uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
+ uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
+#endif
+ volatile uint32_t i = 0;
+
+ /* Disable I cache and D cache */
+ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+ {
+ SCB_DisableICache();
+ }
+ if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+ {
+ SCB_DisableDCache();
+ }
+
+ /* Disable MPU */
+ ARM_MPU_Disable();
+
+ /* MPU configure:
+ * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+ * SubRegionDisable, Size)
+ * API in mpu_armv7.h.
+ * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+ * disabled.
+ * param AccessPermission Data access permissions, allows you to configure read/write access for User and
+ * Privileged mode.
+ * Use MACROS defined in mpu_armv7.h:
+ * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+ * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+ * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
+ * 0 x 0 0 Strongly Ordered shareable
+ * 0 x 0 1 Device shareable
+ * 0 0 1 0 Normal not shareable Outer and inner write
+ * through no write allocate
+ * 0 0 1 1 Normal not shareable Outer and inner write
+ * back no write allocate
+ * 0 1 1 0 Normal shareable Outer and inner write
+ * through no write allocate
+ * 0 1 1 1 Normal shareable Outer and inner write
+ * back no write allocate
+ * 1 0 0 0 Normal not shareable outer and inner
+ * noncache
+ * 1 1 0 0 Normal shareable outer and inner
+ * noncache
+ * 1 0 1 1 Normal not shareable outer and inner write
+ * back write/read acllocate
+ * 1 1 1 1 Normal shareable outer and inner write
+ * back write/read acllocate
+ * 2 x 0 0 Device not shareable
+ * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
+ * policy.
+ * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide
+ * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+ * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+ * mpu_armv7.h.
+ */
+
+ /*
+ * Add default region to deny access to whole address space to workaround speculative prefetch.
+ * Refer to Arm errata 1013783-B for more details.
+ *
+ */
+ /* Region 0 setting: Instruction access disabled, No data access permission. */
+ MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
+
+ /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+ /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+ /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
+ MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
+#endif
+
+ /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
+ MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+ /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+ /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+ /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
+ MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert(!(nonCacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
+ }
+
+ /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
+ MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
+ MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
+
+ /* Enable MPU */
+ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+ /* Enable I cache and D cache */
+ SCB_EnableDCache();
+ SCB_EnableICache();
+}
diff --git a/board/board.h b/board/board.h
new file mode 100644
index 0000000..d2af34c
--- /dev/null
+++ b/board/board.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "FIRE-RT1052-PRO"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_INSTANCE 1U
+
+#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
+
+#define BOARD_UART_IRQ LPUART1_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/*! @brief The USER_LED used for board */
+#define LOGIC_LED_ON (0U)
+#define LOGIC_LED_OFF (1U)
+#ifndef BOARD_USER_LED_GPIO
+#define BOARD_USER_LED_GPIO GPIO1
+#endif
+#ifndef BOARD_USER_LED_GPIO_PIN
+#define BOARD_USER_LED_GPIO_PIN (9U)
+#endif
+
+#define USER_LED_INIT(output) \
+ GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
+ BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
+#define USER_LED_ON() \
+ GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
+#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 29);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 2);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 1);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+#endif
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 2);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL600MHz);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL600MHz);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* DeInit Usb1 PLL. */
+ CLOCK_DeinitUsb1Pll();
+ /* Bypass Usb1 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
+ /* Enable Usb1 PLL output. */
+ CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* DeInit Video PLL. */
+ CLOCK_DeinitVideoPll();
+ /* Bypass Video PLL. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+ /* Set divider for Video PLL. */
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
+ /* Enable Video PLL output. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL600MHz);
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* DeInit Usb2 PLL. */
+ CLOCK_DeinitUsb2Pll();
+ /* Bypass Usb2 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+ /* Enable Usb2 PLL output. */
+ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration Board_BootClockPLL480MHz ********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: Board_BootClockPLL480MHz
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 480 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 4 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 4 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 120 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 960 MHz}
+- {id: MQS_MCLK.outFreq, value: 3 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 4 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '1'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '30'}
+- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL}
+- {id: CCM.SEMC_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for Board_BootClockPLL480MHz configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz =
+ {
+ .loopDivider = 80, /* PLL loop divider, Fout = Fin * 40 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz =
+ {
+ .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
+ .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
+ .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for Board_BootClockPLL480MHz configuration
+ ******************************************************************************/
+void Board_BootClockPLL480MHz(void)
+{
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 29);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 2);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 1);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+#endif
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 2);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL480MHz);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL480MHz);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* DeInit Usb1 PLL. */
+ CLOCK_DeinitUsb1Pll();
+ /* Bypass Usb1 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
+ /* Enable Usb1 PLL output. */
+ CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* DeInit Video PLL. */
+ CLOCK_DeinitVideoPll();
+ /* Bypass Video PLL. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+ /* Set divider for Video PLL. */
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
+ /* Enable Video PLL output. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL480MHz);
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* DeInit Usb2 PLL. */
+ CLOCK_DeinitUsb2Pll();
+ /* Bypass Usb2 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+ /* Enable Usb2 PLL output. */
+ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockXT24MHz *********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockXT24MHz
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 6 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 6 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 24 MHz}
+- {id: MQS_MCLK.outFreq, value: 3 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 3 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 3 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
+settings:
+- {id: CCM.ARM_PODF.scale, value: '1'}
+- {id: CCM.FLEXSPI_PODF.scale, value: '1'}
+- {id: CCM.SEMC_PODF.scale, value: '1'}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_SYS_POWERDOWN_CFG, value: 'Yes'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockXT24MHz configuration
+ ******************************************************************************/
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz =
+ {
+ .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
+ .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
+ .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockXT24MHz configuration
+ ******************************************************************************/
+void BOARD_BootClockXT24MHz(void)
+{
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 0);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+#endif
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 2);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* DeInit ARM PLL. */
+ CLOCK_DeinitArmPll();
+ /* Bypass ARM PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1);
+ /* Enable ARM PLL output. */
+ CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK;
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* DeInit System PLL. */
+ CLOCK_DeinitSysPll();
+ /* Bypass System PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1);
+ /* Enable System PLL output. */
+ CCM_ANALOG->PLL_SYS |= CCM_ANALOG_PLL_SYS_ENABLE_MASK;
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* DeInit Usb1 PLL. */
+ CLOCK_DeinitUsb1Pll();
+ /* Bypass Usb1 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1);
+ /* Enable Usb1 PLL output. */
+ CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* DeInit Video PLL. */
+ CLOCK_DeinitVideoPll();
+ /* Bypass Video PLL. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+ /* Set divider for Video PLL. */
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
+ /* Enable Video PLL output. */
+ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockXT24MHz);
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* DeInit Usb2 PLL. */
+ CLOCK_DeinitUsb2Pll();
+ /* Bypass Usb2 PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+ /* Enable Usb2 PLL output. */
+ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK;
+}
+
diff --git a/board/clock_config.h b/board/clock_config.h
new file mode 100644
index 0000000..379e02f
--- /dev/null
+++ b/board/clock_config.h
@@ -0,0 +1,274 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration Board_BootClockPLL600MHz ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for Board_BootClockPLL600MHz configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz;
+/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz;
+/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz;
+
+/*******************************************************************************
+ * API for Board_BootClockPLL600MHz configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void Board_BootClockPLL600MHz(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration Board_BootClockPLL480MHz ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for Board_BootClockPLL480MHz configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz;
+/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz;
+/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz;
+
+/*******************************************************************************
+ * API for Board_BootClockPLL480MHz configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void Board_BootClockPLL480MHz(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockXT24MHz *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockXT24MHz configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL
+#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL
+
+/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz;
+
+/*******************************************************************************
+ * API for BOARD_BootClockXT24MHz configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockXT24MHz(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/board/dcd.c b/board/dcd.c
new file mode 100644
index 0000000..d3bf9dc
--- /dev/null
+++ b/board/dcd.c
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "dcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.dcd_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.dcd_data"
+#endif
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx v3.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 12.0.0
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
+const uint8_t dcd_data[] = {
+ /* HEADER */
+ /* Tag */
+ 0xD2,
+ /* Image Length */
+ 0x00, 0x04,
+ /* Version */
+ 0x41
+ };
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
+#else
+const uint8_t dcd_data[] = {0x00};
+#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/board/dcd.h b/board/dcd.h
new file mode 100644
index 0000000..3d8b7cd
--- /dev/null
+++ b/board/dcd.h
@@ -0,0 +1,25 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef __DCD__
+#define __DCD__
+
+#include
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*************************************
+ * DCD Data
+ *************************************/
+#define DCD_TAG_HEADER (0xD2)
+#define DCD_VERSION (0x41)
+#define DCD_TAG_HEADER_SHIFT (24)
+#define DCD_ARRAY_SIZE 1
+
+#endif /* __DCD__ */
diff --git a/board/peripherals.c b/board/peripherals.c
new file mode 100644
index 0000000..2007c30
--- /dev/null
+++ b/board/peripherals.c
@@ -0,0 +1,93 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v11.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 12.0.0
+functionalGroups:
+- name: BOARD_InitPeripherals
+ UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830
+ called_from_default_init: true
+ selectedCore: core0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions:
+ - user_definitions: ''
+ - user_includes: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6'
+- global_gpio_adapter_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8'
+- global_USART_CMSIS_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'NVIC'
+- config_sets:
+ - nvic:
+ - interrupt_table: []
+ - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+ /* Initialize components */
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
diff --git a/board/peripherals.h b/board/peripherals.h
new file mode 100644
index 0000000..2a75809
--- /dev/null
+++ b/board/peripherals.h
@@ -0,0 +1,33 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/board/pin_mux.c b/board/pin_mux.c
new file mode 100644
index 0000000..2874cf0
--- /dev/null
+++ b/board/pin_mux.c
@@ -0,0 +1,813 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 12.0.0
+pin_labels:
+- {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B}
+- {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G}
+- {pin_num: A7, pin_signal: GPIO_EMC_40, label: LED_R, identifier: LED_B;LED_R}
+- {pin_num: G14, pin_signal: GPIO_AD_B0_05, label: USDHC1_PWR, identifier: USDHC1_PWR}
+- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: LCD_RST, identifier: LCD_RST}
+- {pin_num: M14, pin_signal: GPIO_AD_B0_00, label: CSI_, identifier: CSI_;CSI_PDN}
+- {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: CSI_RST, identifier: CSI_RST}
+- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BUZZER, identifier: BUZZER}
+- {pin_num: L6, pin_signal: WAKEUP, label: WAKEUP, identifier: WAKEUP}
+power_domains: {DCDC_IN: '3.3', DCDC_IN_Q: '3.3', DCDC_LP: '1.25', DCDC_PSWITCH: '3.3', DCDC_SENSE: '1.25', NVCC_EMC: '3.3', NVCC_GPIO: '3.3', NVCC_SD0: '3.3', NVCC_SD1: '3.3',
+ VDDA_ADC_3P3: '3.3', VDD_HIGH_CAP: '1.1', VDD_HIGH_IN: '3.3', VDD_SNVS_CAP: '1.1', VDD_SNVS_IN: '3.3', VDD_SOC_IN: '1.25', VDD_USB_CAP: '2.5'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitUARTDbgPins();
+ BOARD_InitSWDPins();
+ BOARD_InitFlexSPIPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUARTDbgPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
+ - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUARTDbgPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUARTDbgPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSWDPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: E14, peripheral: JTAG, signal: TMS, pin_signal: GPIO_AD_B0_06}
+ - {pin_num: F12, peripheral: JTAG, signal: TCK, pin_signal: GPIO_AD_B0_07}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSWDPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSWDPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_JTAG_TMS, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_JTAG_TCK, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitFlexSPIPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
+ - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
+ - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
+ - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
+ - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
+ - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
+ - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitFlexSPIPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitFlexSPIPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InituSDPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
+ - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
+ - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
+ - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
+ - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
+ - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
+ - {pin_num: G14, peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, gpio_init_state: 'true'}
+ - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InituSDPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InituSDPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ /* GPIO configuration of USDHC1_PWR on GPIO_AD_B0_05 (pin G14) */
+ gpio_pin_config_t USDHC1_PWR_config = {
+ .direction = kGPIO_DigitalOutput,
+ .outputLogic = 1U,
+ .interruptMode = kGPIO_NoIntmode
+ };
+ /* Initialize GPIO functionality on GPIO_AD_B0_05 (pin G14) */
+ GPIO_PinInit(GPIO1, 5U, &USDHC1_PWR_config);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSDWiFiPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: N3, peripheral: USDHC2, signal: usdhc_cmd, pin_signal: GPIO_SD_B1_05}
+ - {pin_num: P2, peripheral: USDHC2, signal: usdhc_clk, pin_signal: GPIO_SD_B1_04}
+ - {pin_num: M4, peripheral: USDHC2, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B1_03}
+ - {pin_num: M3, peripheral: USDHC2, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B1_02}
+ - {pin_num: M5, peripheral: USDHC2, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B1_01}
+ - {pin_num: L5, peripheral: USDHC2, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSDWiFiPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSDWiFiPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSEMCPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+ - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+ - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+ - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+ - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+ - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+ - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+ - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+ - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+ - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+ - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+ - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+ - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+ - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+ - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+ - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+ - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+ - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+ - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+ - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+ - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+ - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+ - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+ - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+ - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+ - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+ - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+ - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+ - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+ - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+ - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+ - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+ - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+ - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+ - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
+ - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+ - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+ - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
+ - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
+ - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
+ - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSEMCPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSEMCPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+#endif
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
+#endif
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
+#endif
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLCDPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
+ - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
+ - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
+ - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
+ - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
+ - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
+ - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
+ - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
+ - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
+ - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
+ - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
+ - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
+ - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
+ - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
+ - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
+ - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
+ - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
+ - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
+ - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
+ - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
+ - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, direction: OUTPUT, gpio_init_state: 'true'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLCDPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLCDPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ /* GPIO configuration of LCD_RST on GPIO_AD_B0_02 (pin M11) */
+ gpio_pin_config_t LCD_RST_config = {
+ .direction = kGPIO_DigitalOutput,
+ .outputLogic = 1U,
+ .interruptMode = kGPIO_NoIntmode
+ };
+ /* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */
+ GPIO_PinInit(GPIO1, 2U, &LCD_RST_config);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCodecPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: G12, peripheral: SAI1, signal: sai_tx_bclk, pin_signal: GPIO_AD_B1_14}
+ - {pin_num: J14, peripheral: SAI1, signal: sai_tx_sync, pin_signal: GPIO_AD_B1_15}
+ - {pin_num: H11, peripheral: SAI1, signal: sai_tx_data0, pin_signal: GPIO_AD_B1_13}
+ - {pin_num: H12, peripheral: SAI1, signal: sai_rx_data0, pin_signal: GPIO_AD_B1_12}
+ - {pin_num: M13, peripheral: SAI1, signal: sai_mclk, pin_signal: GPIO_AD_B1_09}
+ - {pin_num: H13, peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCodecPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCodecPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCSIPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
+ - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
+ - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
+ - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
+ - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
+ - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
+ - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
+ - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
+ - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
+ - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
+ - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
+ - {pin_num: D13, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_B1_12}
+ - {pin_num: M14, peripheral: GPIO1, signal: 'gpio_io, 00', pin_signal: GPIO_AD_B0_00, identifier: CSI_PDN}
+ - {pin_num: H10, peripheral: GPIO1, signal: 'gpio_io, 01', pin_signal: GPIO_AD_B0_01}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCSIPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCSIPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_GPIO1_IO01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_CSI_PIXCLK, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSYSPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: N1, peripheral: SUPPLY, signal: 'DCDC_GND, 0', pin_signal: DCDC_GND0}
+ - {pin_num: N2, peripheral: SUPPLY, signal: 'DCDC_GND, 1', pin_signal: DCDC_GND1}
+ - {pin_num: L1, peripheral: SUPPLY, signal: 'DCDC_IN, 0', pin_signal: DCDC_IN0}
+ - {pin_num: L2, peripheral: SUPPLY, signal: 'DCDC_IN, 1', pin_signal: DCDC_IN1}
+ - {pin_num: K4, peripheral: SUPPLY, signal: dcdc_in_q, pin_signal: DCDC_IN_Q}
+ - {pin_num: M1, peripheral: SUPPLY, signal: 'DCDC_LP, 0', pin_signal: DCDC_LP0}
+ - {pin_num: M2, peripheral: SUPPLY, signal: 'DCDC_LP, 1', pin_signal: DCDC_LP1}
+ - {pin_num: K3, peripheral: SUPPLY, signal: dcdc_pswitch, pin_signal: DCDC_PSWITCH}
+ - {pin_num: J5, peripheral: SUPPLY, signal: dcdc_sense, pin_signal: DCDC_SENSE}
+ - {pin_num: N10, peripheral: SUPPLY, signal: gpanaio, pin_signal: GPANAIO}
+ - {pin_num: K9, peripheral: SUPPLY, signal: ngnd_kel0, pin_signal: NGND_KEL0}
+ - {pin_num: F5, peripheral: SUPPLY, signal: 'NVCC_EMC, 0', pin_signal: NVCC_EMC0}
+ - {pin_num: E6, peripheral: SUPPLY, signal: 'NVCC_EMC, 1', pin_signal: NVCC_EMC1}
+ - {pin_num: E9, peripheral: SUPPLY, signal: 'NVCC_GPIO, 0', pin_signal: NVCC_GPIO0}
+ - {pin_num: F10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 1', pin_signal: NVCC_GPIO1}
+ - {pin_num: J10, peripheral: SUPPLY, signal: 'NVCC_GPIO, 2', pin_signal: NVCC_GPIO2}
+ - {pin_num: P10, peripheral: SUPPLY, signal: nvcc_pll, pin_signal: NVCC_PLL}
+ - {pin_num: J6, peripheral: SUPPLY, signal: nvcc_sd0, pin_signal: NVCC_SD0}
+ - {pin_num: K5, peripheral: SUPPLY, signal: nvcc_sd1, pin_signal: NVCC_SD1}
+ - {pin_num: K6, peripheral: SUPPLY, signal: test_mode, pin_signal: TEST_MODE}
+ - {pin_num: N12, peripheral: SUPPLY, signal: usb_otg1_chd_b, pin_signal: USB_OTG1_CHD_B}
+ - {pin_num: M8, peripheral: SUPPLY, signal: usb_otg1_dn, pin_signal: USB_OTG1_DN}
+ - {pin_num: L8, peripheral: SUPPLY, signal: usb_otg1_dp, pin_signal: USB_OTG1_DP}
+ - {pin_num: N6, peripheral: SUPPLY, signal: usb_otg1_vbus, pin_signal: USB_OTG1_VBUS}
+ - {pin_num: N7, peripheral: SUPPLY, signal: usb_otg2_dn, pin_signal: USB_OTG2_DN}
+ - {pin_num: P7, peripheral: SUPPLY, signal: usb_otg2_dp, pin_signal: USB_OTG2_DP}
+ - {pin_num: P6, peripheral: SUPPLY, signal: usb_otg2_vbus, pin_signal: USB_OTG2_VBUS}
+ - {pin_num: P12, peripheral: SUPPLY, signal: VDD_HIGH_IN, pin_signal: VDD_HIGH_IN}
+ - {pin_num: P8, peripheral: SUPPLY, signal: VDD_HIGH_CAP, pin_signal: VDD_HIGH_CAP}
+ - {pin_num: M10, peripheral: SUPPLY, signal: VDD_SNVS_CAP, pin_signal: VDD_SNVS_CAP}
+ - {pin_num: M9, peripheral: SUPPLY, signal: VDD_SNVS_IN, pin_signal: VDD_SNVS_IN}
+ - {pin_num: F6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 0', pin_signal: VDD_SOC_IN0}
+ - {pin_num: G6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 1', pin_signal: VDD_SOC_IN1}
+ - {pin_num: H6, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 2', pin_signal: VDD_SOC_IN2}
+ - {pin_num: F7, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 3', pin_signal: VDD_SOC_IN3}
+ - {pin_num: F8, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 4', pin_signal: VDD_SOC_IN4}
+ - {pin_num: F9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 5', pin_signal: VDD_SOC_IN5}
+ - {pin_num: G9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 6', pin_signal: VDD_SOC_IN6}
+ - {pin_num: H9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 7', pin_signal: VDD_SOC_IN7}
+ - {pin_num: J9, peripheral: SUPPLY, signal: 'VDD_SOC_IN, 8', pin_signal: VDD_SOC_IN8}
+ - {pin_num: N14, peripheral: SUPPLY, signal: VDDA_ADC_3P3, pin_signal: VDDA_ADC_3P3}
+ - {pin_num: K8, peripheral: SUPPLY, signal: VDD_USB_CAP, pin_signal: VDD_USB_CAP}
+ - {pin_num: A1, peripheral: SUPPLY, signal: 'VSS, 0', pin_signal: VSS0}
+ - {pin_num: P1, peripheral: SUPPLY, signal: 'VSS, 1', pin_signal: VSS1}
+ - {pin_num: E2, peripheral: SUPPLY, signal: 'VSS, 2', pin_signal: VSS2}
+ - {pin_num: K2, peripheral: SUPPLY, signal: 'VSS, 3', pin_signal: VSS3}
+ - {pin_num: B5, peripheral: SUPPLY, signal: 'VSS, 4', pin_signal: VSS4}
+ - {pin_num: N5, peripheral: SUPPLY, signal: 'VSS, 5', pin_signal: VSS5}
+ - {pin_num: G7, peripheral: SUPPLY, signal: 'VSS, 6', pin_signal: VSS6}
+ - {pin_num: H7, peripheral: SUPPLY, signal: 'VSS, 7', pin_signal: VSS7}
+ - {pin_num: J7, peripheral: SUPPLY, signal: 'VSS, 8', pin_signal: VSS8}
+ - {pin_num: G8, peripheral: SUPPLY, signal: 'VSS, 9', pin_signal: VSS9}
+ - {pin_num: H8, peripheral: SUPPLY, signal: 'VSS, 10', pin_signal: VSS10}
+ - {pin_num: J8, peripheral: SUPPLY, signal: 'VSS, 11', pin_signal: VSS11}
+ - {pin_num: N8, peripheral: SUPPLY, signal: 'VSS, 12', pin_signal: VSS12}
+ - {pin_num: L9, peripheral: SUPPLY, signal: 'VSS, 13', pin_signal: VSS13}
+ - {pin_num: B10, peripheral: SUPPLY, signal: 'VSS, 14', pin_signal: VSS14}
+ - {pin_num: E13, peripheral: SUPPLY, signal: 'VSS, 15', pin_signal: VSS15}
+ - {pin_num: K13, peripheral: SUPPLY, signal: 'VSS, 16', pin_signal: VSS16}
+ - {pin_num: A14, peripheral: SUPPLY, signal: 'VSS, 17', pin_signal: VSS17}
+ - {pin_num: P14, peripheral: SUPPLY, signal: 'VSS, 18', pin_signal: VSS18}
+ - {pin_num: P13, peripheral: CCM, signal: CLK1_N, pin_signal: CCM_CLK1_N}
+ - {pin_num: N13, peripheral: CCM, signal: CLK1_P, pin_signal: CCM_CLK1_P}
+ - {pin_num: K7, peripheral: SNVS, signal: snvs_pmic_on_req, pin_signal: PMIC_ON_REQ}
+ - {pin_num: M6, peripheral: SRC, signal: RESET_B, pin_signal: ONOFF}
+ - {pin_num: M7, peripheral: SRC, signal: POR_B, pin_signal: POR_B}
+ - {pin_num: P9, peripheral: XTALOSC24M, signal: rtc_xtalo, pin_signal: RTC_XTALO}
+ - {pin_num: N9, peripheral: XTALOSC24M, signal: rtc_xtali, pin_signal: RTC_XTALI}
+ - {pin_num: P11, peripheral: XTALOSC24M, signal: xtali, pin_signal: XTALI}
+ - {pin_num: N11, peripheral: XTALOSC24M, signal: xtalo, pin_signal: XTALO}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSYSPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSYSPins(void) {
+ CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
+ IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ, 0U);
+#else
+ IOMUXC_SetPinMux(IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ, 0U);
+#endif
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitENETPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: L12, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_AD_B1_04}
+ - {pin_num: B14, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_B1_15}
+ - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
+ - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
+ - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
+ - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
+ - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
+ - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
+ - {pin_num: B13, peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_B1_10}
+ - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitENETPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitENETPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_ENET_MDC, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_TX_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBasicIOPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03, direction: OUTPUT}
+ - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBasicIOPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBasicIOPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+ CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+ /* GPIO configuration of BUZZER on GPIO_AD_B0_03 (pin G11) */
+ gpio_pin_config_t BUZZER_config = {
+ .direction = kGPIO_DigitalOutput,
+ .outputLogic = 0U,
+ .interruptMode = kGPIO_NoIntmode
+ };
+ /* Initialize GPIO functionality on GPIO_AD_B0_03 (pin G11) */
+ GPIO_PinInit(GPIO1, 3U, &BUZZER_config);
+
+ /* GPIO configuration of WAKEUP on WAKEUP (pin L6) */
+ gpio_pin_config_t WAKEUP_config = {
+ .direction = kGPIO_DigitalInput,
+ .outputLogic = 0U,
+ .interruptMode = kGPIO_NoIntmode
+ };
+ /* Initialize GPIO functionality on WAKEUP (pin L6) */
+ GPIO_PinInit(GPIO5, 0U, &WAKEUP_config);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitI2C1Pins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01}
+ - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitI2C1Pins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitI2C1Pins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitCAN2Pins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
+ - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitCAN2Pins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitCAN2Pins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSPDIFPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: M12, peripheral: SPDIF, signal: spdif_in, pin_signal: GPIO_AD_B1_03}
+ - {pin_num: L11, peripheral: SPDIF, signal: spdif_out, pin_signal: GPIO_AD_B1_02}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSPDIFPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitSPDIFPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_SPDIF_OUT, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_SPDIF_IN, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/pin_mux.h b/board/pin_mux.h
new file mode 100644
index 0000000..d87c119
--- /dev/null
+++ b/board/pin_mux.h
@@ -0,0 +1,246 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type */
+typedef enum _pin_mux_direction
+{
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUARTDbgPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSWDPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitFlexSPIPins(void);
+
+/* GPIO_AD_B0_05 (coord G14), USDHC1_PWR */
+/* Routed pin properties */
+#define BOARD_INITUSDPINS_USDHC1_PWR_PERIPHERAL GPIO1 /*!< Peripheral name */
+#define BOARD_INITUSDPINS_USDHC1_PWR_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITUSDPINS_USDHC1_PWR_CHANNEL 5U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO GPIO1 /*!< GPIO peripheral base pointer */
+#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN 5U /*!< GPIO pin number */
+#define BOARD_INITUSDPINS_USDHC1_PWR_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */
+#define BOARD_INITUSDPINS_USDHC1_PWR_PORT GPIO1 /*!< PORT peripheral base pointer */
+#define BOARD_INITUSDPINS_USDHC1_PWR_PIN 5U /*!< PORT pin number */
+#define BOARD_INITUSDPINS_USDHC1_PWR_PIN_MASK (1U << 5U) /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InituSDPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSDWiFiPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSEMCPins(void);
+
+/* GPIO_AD_B0_02 (coord M11), LCD_RST */
+/* Routed pin properties */
+#define BOARD_INITLCDPINS_LCD_RST_PERIPHERAL GPIO1 /*!< Peripheral name */
+#define BOARD_INITLCDPINS_LCD_RST_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITLCDPINS_LCD_RST_CHANNEL 2U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLCDPINS_LCD_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */
+#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN 2U /*!< GPIO pin number */
+#define BOARD_INITLCDPINS_LCD_RST_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */
+#define BOARD_INITLCDPINS_LCD_RST_PORT GPIO1 /*!< PORT peripheral base pointer */
+#define BOARD_INITLCDPINS_LCD_RST_PIN 2U /*!< PORT pin number */
+#define BOARD_INITLCDPINS_LCD_RST_PIN_MASK (1U << 2U) /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLCDPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCodecPins(void);
+
+/* GPIO_AD_B0_00 (coord M14), CSI_ */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_PDN_PERIPHERAL GPIO1 /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_PDN_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_PDN_CHANNEL 0U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITCSIPINS_CSI_PDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN 0U /*!< GPIO pin number */
+#define BOARD_INITCSIPINS_CSI_PDN_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
+#define BOARD_INITCSIPINS_CSI_PDN_PORT GPIO1 /*!< PORT peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_PDN_PIN 0U /*!< PORT pin number */
+#define BOARD_INITCSIPINS_CSI_PDN_PIN_MASK (1U << 0U) /*!< PORT pin mask */
+
+/* GPIO_AD_B0_01 (coord H10), CSI_RST */
+/* Routed pin properties */
+#define BOARD_INITCSIPINS_CSI_RST_PERIPHERAL GPIO1 /*!< Peripheral name */
+#define BOARD_INITCSIPINS_CSI_RST_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITCSIPINS_CSI_RST_CHANNEL 1U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITCSIPINS_CSI_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN 1U /*!< GPIO pin number */
+#define BOARD_INITCSIPINS_CSI_RST_GPIO_PIN_MASK (1U << 1U) /*!< GPIO pin mask */
+#define BOARD_INITCSIPINS_CSI_RST_PORT GPIO1 /*!< PORT peripheral base pointer */
+#define BOARD_INITCSIPINS_CSI_RST_PIN 1U /*!< PORT pin number */
+#define BOARD_INITCSIPINS_CSI_RST_PIN_MASK (1U << 1U) /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCSIPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSYSPins(void);
+
+/* GPIO_B1_07 (coord B12), LED_G */
+/* Routed pin properties */
+#define BOARD_INITENETPINS_LED_G_PERIPHERAL ENET /*!< Peripheral name */
+#define BOARD_INITENETPINS_LED_G_SIGNAL enet_tx_data /*!< Signal name */
+#define BOARD_INITENETPINS_LED_G_CHANNEL 0U /*!< Signal channel */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitENETPins(void);
+
+/* GPIO_AD_B0_03 (coord G11), BUZZER */
+/* Routed pin properties */
+#define BOARD_INITBASICIOPINS_BUZZER_PERIPHERAL GPIO1 /*!< Peripheral name */
+#define BOARD_INITBASICIOPINS_BUZZER_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITBASICIOPINS_BUZZER_CHANNEL 3U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBASICIOPINS_BUZZER_GPIO GPIO1 /*!< GPIO peripheral base pointer */
+#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN 3U /*!< GPIO pin number */
+#define BOARD_INITBASICIOPINS_BUZZER_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
+#define BOARD_INITBASICIOPINS_BUZZER_PORT GPIO1 /*!< PORT peripheral base pointer */
+#define BOARD_INITBASICIOPINS_BUZZER_PIN 3U /*!< PORT pin number */
+#define BOARD_INITBASICIOPINS_BUZZER_PIN_MASK (1U << 3U) /*!< PORT pin mask */
+
+/* WAKEUP (coord L6), WAKEUP */
+/* Routed pin properties */
+#define BOARD_INITBASICIOPINS_WAKEUP_PERIPHERAL GPIO5 /*!< Peripheral name */
+#define BOARD_INITBASICIOPINS_WAKEUP_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITBASICIOPINS_WAKEUP_CHANNEL 0U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBASICIOPINS_WAKEUP_GPIO GPIO5 /*!< GPIO peripheral base pointer */
+#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN 0U /*!< GPIO pin number */
+#define BOARD_INITBASICIOPINS_WAKEUP_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
+#define BOARD_INITBASICIOPINS_WAKEUP_PORT GPIO5 /*!< PORT peripheral base pointer */
+#define BOARD_INITBASICIOPINS_WAKEUP_PIN 0U /*!< PORT pin number */
+#define BOARD_INITBASICIOPINS_WAKEUP_PIN_MASK (1U << 0U) /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitBasicIOPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitI2C1Pins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitCAN2Pins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSPDIFPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/include/.gitkeep b/include/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/lib/.gitkeep b/lib/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/src/main.c b/src/main.c
new file mode 100644
index 0000000..4c63a63
--- /dev/null
+++ b/src/main.c
@@ -0,0 +1,24 @@
+#include "board.h"
+#include "clock_config.h"
+#include "peripherals.h"
+#include "pin_mux.h"
+
+/* Debug console */
+#include "fsl_debug_console.h"
+
+int main(void) {
+ BOARD_InitBootPins();
+ BOARD_InitBootClocks();
+ BOARD_InitBootPeripherals();
+ BOARD_ConfigMPU();
+
+ BOARD_InitDebugConsole();
+
+ CLOCK_SetMode(kCLOCK_ModeRun);
+
+ PRINTF("CPU frequency: %d\r\n", CLOCK_GetCoreSysClkFreq());
+
+ for (;;) {
+ __WFI();
+ }
+}
diff --git a/xip/fire_rt1052_pro_flexspi_nor_config.c b/xip/fire_rt1052_pro_flexspi_nor_config.c
new file mode 100644
index 0000000..7de28f0
--- /dev/null
+++ b/xip/fire_rt1052_pro_flexspi_nor_config.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fire_rt1052_pro_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t spiflash_config = {
+ .memConfig = {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+ .csHoldTime = 3U,
+ .csSetupTime = 3U,
+ .columnAddressWidth = 0U,
+ .deviceType = kFlexSpiDeviceType_SerialNOR,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
+ .sflashA1Size = 32U * 1024U * 1024U,
+ .busyOffset = 0U,
+ .busyBitPolarity = 1U,
+ .lookupTable = {
+ // Fast read quad IO (EBh) [NOR_CMD_LUT_SEQ_IDX_READ]
+ [4U * 0 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+ [4U * 0 + 1U] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xF0, DUMMY_SDR, FLEXSPI_4PAD, 0x04),
+ [4U * 0 + 2U] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
+
+ // Read SR1 (05h) [NOR_CMD_LUT_SEQ_IDX_READSTATUS]
+ [4U * 1 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x00),
+
+ // Write enable (06h) [NOR_CMD_LUT_SEQ_IDX_WRITEENABLE]
+ [4U * 3 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x00),
+
+ // Page program () [NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM]
+ [4U * 4 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+ [4U * 4 + 1U] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x00, STOP, FLEXSPI_1PAD, 0x00),
+
+ // Erase sector (20h) [NOR_CMD_LUT_SEQ_IDX_ERASESECTOR]
+ [4U * 5 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+
+ // Erase block 32kB (52h) [NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK]
+ [4U * 8 + 0U] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x52, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .blockSize = 32u * 1024u,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/xip/fire_rt1052_pro_flexspi_nor_config.h b/xip/fire_rt1052_pro_flexspi_nor_config.h
new file mode 100644
index 0000000..cde0c9b
--- /dev/null
+++ b/xip/fire_rt1052_pro_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FIRE_RT1052_PRO_FLEXSPI_NOR_CONFIG__
+#define __FIRE_RT1052_PRO_FLEXSPI_NOR_CONFIG__
+
+#include
+#include
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_100MHz = 6,
+ kFlexSpiSerialClk_133MHz = 7,
+ kFlexSpiSerialClk_166MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+ kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+ kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
+ kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
+ kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+ kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
+ kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
+ kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+ uint8_t seqId; //!< Sequence Index, valid number: 0-15
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+ kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
+ kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+ kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
+ kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
+ kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
+ kDeviceConfigCmdType_Reset, //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+ uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+ uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
+ uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+ uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
+ uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
+ uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+ //! Serial NAND, need to refer to datasheet
+ uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+ uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+ //! Generic configuration, etc.
+ uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+ //! DPI/QPI/OPI switch or reset command
+ flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+ //! sequence number, [31:16] Reserved
+ uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
+ uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+ uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+ uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
+ uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+ uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
+ uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+ //! details
+ uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
+ uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+ uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+ //! Chapter for more details
+ uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+ //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+ uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+ uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+ uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
+ uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+ uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
+ uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
+ uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+ uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+ uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
+ uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
+ uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
+ uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+ uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+ uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+ //! busy flag is 0 when flash device is busy
+ uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
+ flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+ uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/* */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
+#define NOR_CMD_INDEX_DUMMY 6 //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+ CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+ CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+ CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ * Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+ uint32_t pageSize; //!< Page size of Serial NOR
+ uint32_t sectorSize; //!< Sector size of Serial NOR
+ uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
+ uint8_t isUniformBlockSize; //!< Sector/Block size is the same
+ uint8_t reserved0[2]; //!< Reserved for future use
+ uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
+ uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
+ uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
+ uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
+ uint32_t blockSize; //!< Block size
+ uint32_t reserve2[11]; //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __LQ_VA1_FLEXSPI_NOR_CONFIG__ */