#include "peripherals.h"

#include "board.h"

QSPI_HandleTypeDef  hqspi;
SDRAM_HandleTypeDef hsdram1;

static void BOARD_SDRAM_Config(void);

void BOARD_InitBootPeripherals(void) {
    BOARD_InitQUADSPI();
}

void BOARD_InitQUADSPI(void) {
    hqspi.Instance                = QUADSPI;
    hqspi.Init.ClockPrescaler     = 1;
    hqspi.Init.FifoThreshold      = 24;
    hqspi.Init.SampleShifting     = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
    hqspi.Init.FlashSize          = 25;
    hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_6_CYCLE;
    hqspi.Init.ClockMode          = QSPI_CLOCK_MODE_0;
    hqspi.Init.DualFlash          = QSPI_DUALFLASH_ENABLE;
    if (HAL_QSPI_Init(&hqspi) != HAL_OK) {
        Error_Handler();
    }
}

void BOARD_InitFMC(void) {
    FMC_SDRAM_TimingTypeDef SdramTiming = {0};

    hsdram1.Instance                = FMC_SDRAM_DEVICE;
    hsdram1.Init.SDBank             = FMC_SDRAM_BANK2;
    hsdram1.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_9;
    hsdram1.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_13;
    hsdram1.Init.MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_32;
    hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
    hsdram1.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_2;
    hsdram1.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
    hsdram1.Init.SDClockPeriod      = FMC_SDRAM_CLOCK_PERIOD_2;
    hsdram1.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
    hsdram1.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_1;

    SdramTiming.LoadToActiveDelay    = 2;
    SdramTiming.ExitSelfRefreshDelay = 9;
    SdramTiming.SelfRefreshTime      = 6;
    SdramTiming.RowCycleDelay        = 8;
    SdramTiming.WriteRecoveryTime    = 4;
    SdramTiming.RPDelay              = 2;
    SdramTiming.RCDDelay             = 2;

    if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) {
        Error_Handler();
    }

    BOARD_SDRAM_Config();
}

static void BOARD_SDRAM_Config(void) {
    FMC_SDRAM_CommandTypeDef cmd;

    cmd.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
    cmd.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
    cmd.AutoRefreshNumber      = 1;
    cmd.ModeRegisterDefinition = 0;
    if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
        Error_Handler();
    }

    HAL_Delay(1);

    cmd.CommandMode            = FMC_SDRAM_CMD_PALL;
    cmd.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
    cmd.AutoRefreshNumber      = 1;
    cmd.ModeRegisterDefinition = 0;
    if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
        Error_Handler();
    }

    cmd.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
    cmd.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
    cmd.AutoRefreshNumber      = 8;
    cmd.ModeRegisterDefinition = 0;
    if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
        Error_Handler();
    }

    cmd.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
    cmd.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
    cmd.AutoRefreshNumber      = 1;
    cmd.ModeRegisterDefinition = 0x220UL;
    if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
        Error_Handler();
    }

    if (HAL_SDRAM_ProgramRefreshRate(&hsdram1, 900) != HAL_OK) {
        Error_Handler();
    }
}