98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
#include "peripherals.h"
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#include "board.h"
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QSPI_HandleTypeDef hqspi;
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SDRAM_HandleTypeDef hsdram1;
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static void BOARD_SDRAM_Config(void);
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void BOARD_InitBootPeripherals(void) {
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BOARD_InitQUADSPI();
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}
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void BOARD_InitQUADSPI(void) {
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hqspi.Instance = QUADSPI;
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hqspi.Init.ClockPrescaler = 1;
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hqspi.Init.FifoThreshold = 24;
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hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
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hqspi.Init.FlashSize = 25;
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hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_6_CYCLE;
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hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
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hqspi.Init.DualFlash = QSPI_DUALFLASH_ENABLE;
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if (HAL_QSPI_Init(&hqspi) != HAL_OK) {
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Error_Handler();
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}
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}
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void BOARD_InitFMC(void) {
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FMC_SDRAM_TimingTypeDef SdramTiming = {0};
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hsdram1.Instance = FMC_SDRAM_DEVICE;
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hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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SdramTiming.LoadToActiveDelay = 2;
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SdramTiming.ExitSelfRefreshDelay = 9;
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SdramTiming.SelfRefreshTime = 6;
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SdramTiming.RowCycleDelay = 8;
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SdramTiming.WriteRecoveryTime = 4;
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SdramTiming.RPDelay = 2;
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SdramTiming.RCDDelay = 2;
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if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) {
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Error_Handler();
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}
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BOARD_SDRAM_Config();
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}
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static void BOARD_SDRAM_Config(void) {
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FMC_SDRAM_CommandTypeDef cmd;
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cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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cmd.AutoRefreshNumber = 1;
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cmd.ModeRegisterDefinition = 0;
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if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
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Error_Handler();
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}
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HAL_Delay(1);
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cmd.CommandMode = FMC_SDRAM_CMD_PALL;
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cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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cmd.AutoRefreshNumber = 1;
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cmd.ModeRegisterDefinition = 0;
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if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
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Error_Handler();
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}
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cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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cmd.AutoRefreshNumber = 8;
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cmd.ModeRegisterDefinition = 0;
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if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
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Error_Handler();
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}
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cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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cmd.AutoRefreshNumber = 1;
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cmd.ModeRegisterDefinition = 0x220UL;
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if (HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000) != HAL_OK) {
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Error_Handler();
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}
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if (HAL_SDRAM_ProgramRefreshRate(&hsdram1, 900) != HAL_OK) {
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Error_Handler();
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}
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} |