parent
b4575350b1
commit
b0a500cc03
|
@ -6,8 +6,9 @@ enable_language(CXX)
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enable_language(ASM)
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# Different linker scripts
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set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/GCC/STM32H750XBHX_FLASH.ld")
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set(TARGET_LDSCRIPT_QSPI_XIP "${CMAKE_SOURCE_DIR}/GCC/STM32H750XBHX_QSPI_XIP.ld")
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set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/GCC/STM32H750XBHX_FLASH.ld")
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set(TARGET_LDSCRIPT_QSPI "${CMAKE_SOURCE_DIR}/GCC/STM32H750XBHX_QSPI.ld")
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set(TARGET_LDSCRIPT_QSPI_SDRAM "${CMAKE_SOURCE_DIR}/GCC/STM32H750XBHX_QSPI_SDRAM.ld")
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set(TARGET_SOURCES
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"GCC/startup_stm32h750xx.s"
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@ -30,15 +31,17 @@ set(TARGET_SOURCES
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c"
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c"
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c"
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c"
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c"
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"SDK/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c"
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"board/board.c"
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"board/clock_config.c"
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"board/peripherals.c"
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"board/pin_mux.c"
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"board/stm32h7xx_hal_msp.c"
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"board/stm32h7xx_it.c"
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"board/system_stm32h7xx.c"
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"src/main.c"
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"src/syscalls.c"
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"xip/fire_stm32h750_pro_xip_config.c"
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)
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@ -47,8 +50,14 @@ set(TARGET_C_DEFINES
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"USE_HAL_DRIVER"
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)
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set(TARGET_C_DEFINES_XIP
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set(TARGET_C_DEFINES_QSPI
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"XIP_BOOT_ENABLED"
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"XIP_ENABLE_SDRAM"
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)
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set(TARGET_C_DEFINES_QSPI_SDRAM
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"XIP_BOOT_ENABLED"
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"XIP_ENABLE_SDRAM"
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)
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set(TARGET_C_INCLUDES
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@ -121,22 +130,43 @@ if(DEFINED TARGET_TOOLCHAIN_SIZE)
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endif()
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# Create ELF
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add_executable("${CMAKE_PROJECT_NAME}_QSPI_XIP.elf" ${TARGET_SOURCES})
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target_compile_definitions(${CMAKE_PROJECT_NAME}_QSPI_XIP.elf PRIVATE ${TARGET_C_DEFINES_XIP})
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target_link_options("${CMAKE_PROJECT_NAME}_QSPI_XIP.elf"
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PRIVATE "-T${TARGET_LDSCRIPT_QSPI_XIP}"
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PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_QSPI_XIP.map"
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add_executable("${CMAKE_PROJECT_NAME}_QSPI.elf" ${TARGET_SOURCES})
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target_compile_definitions(${CMAKE_PROJECT_NAME}_QSPI.elf PRIVATE ${TARGET_C_DEFINES_QSPI})
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target_link_options("${CMAKE_PROJECT_NAME}_QSPI.elf"
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PRIVATE "-T${TARGET_LDSCRIPT_QSPI}"
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PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_QSPI.map"
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)
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set_property(TARGET "${CMAKE_PROJECT_NAME}_QSPI_XIP.elf" APPEND
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set_property(TARGET "${CMAKE_PROJECT_NAME}_QSPI.elf" APPEND
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PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_RAM.map"
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)
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add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_QSPI_XIP.hex"
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COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_QSPI_XIP.elf" "${CMAKE_PROJECT_NAME}_QSPI_XIP.hex"
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DEPENDS "${CMAKE_PROJECT_NAME}_QSPI_XIP.elf"
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add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_QSPI.hex"
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COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_QSPI.elf" "${CMAKE_PROJECT_NAME}_QSPI.hex"
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DEPENDS "${CMAKE_PROJECT_NAME}_QSPI.elf"
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)
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add_custom_target("${CMAKE_PROJECT_NAME}_QSPI_XIP_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_QSPI_XIP.hex")
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add_custom_target("${CMAKE_PROJECT_NAME}_QSPI_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_QSPI.hex")
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if(DEFINED TARGET_TOOLCHAIN_SIZE)
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add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_QSPI_XIP.elf" POST_BUILD
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COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_QSPI_XIP.elf"
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add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_QSPI.elf" POST_BUILD
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COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_QSPI.elf"
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)
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endif()
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# Create ELF
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add_executable("${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf" ${TARGET_SOURCES})
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target_compile_definitions(${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf PRIVATE ${TARGET_C_DEFINES_QSPI_SDRAM})
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target_link_options("${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf"
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PRIVATE "-T${TARGET_LDSCRIPT_QSPI_SDRAM}"
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PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_QSPI_SDRAM.map"
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)
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set_property(TARGET "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf" APPEND
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PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.map"
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)
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add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.hex"
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COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf" "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.hex"
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DEPENDS "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf"
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)
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add_custom_target("${CMAKE_PROJECT_NAME}_QSPI_SDRAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.hex")
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if(DEFINED TARGET_TOOLCHAIN_SIZE)
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add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf" POST_BUILD
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COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_QSPI_SDRAM.elf"
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)
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endif()
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@ -0,0 +1,187 @@
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/*
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******************************************************************************
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**
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** File : LinkerScript.ld
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**
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** Author : STM32CubeIDE
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**
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** Abstract : Linker script for STM32H7 series
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** 128Kbytes FLASH and 1056Kbytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used.
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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*****************************************************************************
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** @attention
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**
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** Copyright (c) 2022 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(SDRAM) + LENGTH(SDRAM); /* end of RAM */
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
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DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
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ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
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QSPI_CFG (rx) : ORIGIN = 0x90000000, LENGTH = 4K
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QSPI_CODE (rx) : ORIGIN = 0x90001000, LENGTH = 0x3FFF000
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SDRAM (xrw) : ORIGIN = 0xD0000000, LENGTH = 64M
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}
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/* Define output sections */
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SECTIONS
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{
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/* Instruction for bootloader */
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.xip :
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{
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. = ALIGN(4);
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KEEP(*(.xip_fcfb))
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. = ALIGN(4);
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} >QSPI_CFG
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/* The startup code goes first into FLASH */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >QSPI_CODE
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/* The program code and other data goes into FLASH */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >QSPI_CODE
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/* Constant data goes into FLASH */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >QSPI_CODE
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
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.ARM : {
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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} >QSPI_CODE
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >QSPI_CODE
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >QSPI_CODE
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >QSPI_CODE
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >SDRAM AT> QSPI_CODE
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss section */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >SDRAM
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/* User_heap_stack section, used to check that there is enough RAM left */
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._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >SDRAM
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/* Remove information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}
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Binary file not shown.
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@ -26,10 +26,23 @@ void BOARD_ConfigMPU(void) {
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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MPU_InitStruct.Number = MPU_REGION_NUMBER1;
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MPU_InitStruct.BaseAddress = 0x90000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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MPU_InitStruct.Number = MPU_REGION_NUMBER2;
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MPU_InitStruct.BaseAddress = 0xD0000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Enables the MPU */
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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}
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@ -1,7 +1,7 @@
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#ifndef BOARD_H
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#define BOARD_H
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_Noreturn void Error_Handler(void);
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void Error_Handler(void);
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void BOARD_ConfigMPU(void);
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#endif
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@ -1,64 +1,8 @@
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#include "board.h"
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#include "stm32h7xx_hal.h"
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#include "stm32h7xx_ll_rcc.h"
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static void SystemClock_Config(void);
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void BOARD_InitBootClocks(void) {
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SystemClock_Config();
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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SystemCoreClockUpdate();
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}
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static void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/** Supply configuration update enable
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*/
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
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}
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 5;
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RCC_OscInitStruct.PLL.PLLN = 160;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 |
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RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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Error_Handler();
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}
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/** Enables the Clock Security System
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*/
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HAL_RCC_EnableCSS();
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}
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@ -1,5 +1,45 @@
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#include "board.h"
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#include "peripherals.h"
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#include "board.h"
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UART_HandleTypeDef huart1;
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void BOARD_InitBootPeripherals(void) {
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BOARD_InitDebugUART();
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}
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void BOARD_InitDebugUART(void) {
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||||
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_RCC_USART1_CLK_ENABLE();
|
||||
|
||||
huart1.Instance = USART1;
|
||||
huart1.Init.BaudRate = 115200;
|
||||
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
huart1.Init.StopBits = UART_STOPBITS_1;
|
||||
huart1.Init.Parity = UART_PARITY_NONE;
|
||||
huart1.Init.Mode = UART_MODE_TX_RX;
|
||||
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
if (HAL_UART_Init(&huart1) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
|
@ -3,6 +3,9 @@
|
|||
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
extern UART_HandleTypeDef huart1;
|
||||
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
void BOARD_InitDebugUART(void);
|
||||
|
||||
#endif
|
|
@ -3,6 +3,22 @@
|
|||
#include "stm32h7xx_hal.h"
|
||||
|
||||
void BOARD_InitBootPins(void) {
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_9;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
}
|
|
@ -1,20 +1,20 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
@ -30,64 +30,64 @@ extern "C" {
|
|||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_FDCAN_MODULE_ENABLED */
|
||||
/* #define HAL_FMAC_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_COMP_MODULE_ENABLED */
|
||||
/* #define HAL_CORDIC_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_OTFDEC_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
/* #define HAL_HRTIM_MODULE_ENABLED */
|
||||
/* #define HAL_HSEM_MODULE_ENABLED */
|
||||
/* #define HAL_GFXMMU_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_OPAMP_MODULE_ENABLED */
|
||||
/* #define HAL_OSPI_MODULE_ENABLED */
|
||||
/* #define HAL_OSPI_MODULE_ENABLED */
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_SMBUS_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
/* #define HAL_RAMECC_MODULE_ENABLED */
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_FDCAN_MODULE_ENABLED
|
||||
#define HAL_FMAC_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORDIC_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_OTFDEC_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_HRTIM_MODULE_ENABLED
|
||||
#define HAL_HSEM_MODULE_ENABLED
|
||||
#define HAL_GFXMMU_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_OPAMP_MODULE_ENABLED
|
||||
#define HAL_OSPI_MODULE_ENABLED
|
||||
#define HAL_OSPI_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RAMECC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_MMC_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_SWPMI_MODULE_ENABLED */
|
||||
/* #define HAL_TIM_MODULE_ENABLED */
|
||||
/* #define HAL_UART_MODULE_ENABLED */
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||
/* #define HAL_DSI_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_MDIOS_MODULE_ENABLED */
|
||||
/* #define HAL_PSSI_MODULE_ENABLED */
|
||||
/* #define HAL_DTS_MODULE_ENABLED */
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_SWPMI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_DFSDM_MODULE_ENABLED
|
||||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_MDIOS_MODULE_ENABLED
|
||||
#define HAL_PSSI_MODULE_ENABLED
|
||||
#define HAL_DTS_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_MDMA_MODULE_ENABLED
|
||||
|
@ -101,145 +101,145 @@ extern "C" {
|
|||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
|
||||
#endif /* HSE_VALUE */
|
||||
#if !defined(HSE_VALUE)
|
||||
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
#if !defined(HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal oscillator (CSI) default value.
|
||||
* This value is the default CSI value after Reset.
|
||||
* @brief Internal oscillator (CSI) default value.
|
||||
* This value is the default CSI value after Reset.
|
||||
*/
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
#if !defined(CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
#if !defined(HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
#if !defined(LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
#if !defined(LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
#if !defined(LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz \
|
||||
The real value may vary depending on the variations \
|
||||
in voltage and temperature.*/
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
#if !defined(EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
|
||||
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
|
||||
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
|
||||
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
|
||||
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
|
||||
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
|
||||
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################### Ethernet Configuration ######################### */
|
||||
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
|
||||
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
|
||||
|
||||
#define ETH_MAC_ADDR0 (0x02UL)
|
||||
#define ETH_MAC_ADDR1 (0x00UL)
|
||||
#define ETH_MAC_ADDR2 (0x00UL)
|
||||
#define ETH_MAC_ADDR3 (0x00UL)
|
||||
#define ETH_MAC_ADDR4 (0x00UL)
|
||||
#define ETH_MAC_ADDR5 (0x00UL)
|
||||
#define ETH_MAC_ADDR0 (0x02UL)
|
||||
#define ETH_MAC_ADDR1 (0x00UL)
|
||||
#define ETH_MAC_ADDR2 (0x00UL)
|
||||
#define ETH_MAC_ADDR3 (0x00UL)
|
||||
#define ETH_MAC_ADDR4 (0x00UL)
|
||||
#define ETH_MAC_ADDR5 (0x00UL)
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
@ -487,14 +487,14 @@ extern "C" {
|
|||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
|
|
@ -1,80 +0,0 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_msp.c
|
||||
* @brief This file provides code for the MSP Initialization
|
||||
* and de-Initialization codes.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Define */
|
||||
|
||||
/* USER CODE END Define */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Macro */
|
||||
|
||||
/* USER CODE END Macro */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* External functions --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ExternalFunctions */
|
||||
|
||||
/* USER CODE END ExternalFunctions */
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
/**
|
||||
* Initializes the Global MSP.
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
/* USER CODE BEGIN MspInit 0 */
|
||||
|
||||
/* USER CODE END MspInit 0 */
|
||||
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* System interrupt init*/
|
||||
|
||||
/* USER CODE BEGIN MspInit 1 */
|
||||
|
||||
/* USER CODE END MspInit 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
|
@ -1,450 +1,116 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h7xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32h7xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock, it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h7xx.h"
|
||||
#include <math.h>
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
#include "stm32h7xx.h"
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
|
||||
/* #define DATA_IN_D2_SRAM */
|
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate the vector table
|
||||
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
|
||||
remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 64000000;
|
||||
uint32_t SystemD2Clock = 64000000;
|
||||
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the FPU setting and vector table location
|
||||
* configuration.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if defined (DATA_IN_D2_SRAM)
|
||||
__IO uint32_t tmpreg;
|
||||
#endif /* DATA_IN_D2_SRAM */
|
||||
uint32_t SystemCoreClock;
|
||||
uint32_t SystemD2Clock;
|
||||
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
void SystemInit(void) {
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
|
||||
SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
|
||||
/* Increasing the CPU frequency */
|
||||
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
|
||||
{
|
||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
|
||||
}
|
||||
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
|
||||
RCC->CR &= 0xEAF6ED7FU;
|
||||
|
||||
/* Decreasing the number of wait states because of lower CPU frequency */
|
||||
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
|
||||
{
|
||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
|
||||
}
|
||||
|
||||
#if defined(D3_SRAM_BASE)
|
||||
/* Reset D1CFGR register */
|
||||
RCC->D1CFGR = 0x00000000;
|
||||
|
||||
/* Reset D2CFGR register */
|
||||
RCC->D2CFGR = 0x00000000;
|
||||
|
||||
/* Reset D3CFGR register */
|
||||
RCC->D3CFGR = 0x00000000;
|
||||
#else
|
||||
/* Reset CDCFGR1 register */
|
||||
RCC->CDCFGR1 = 0x00000000;
|
||||
|
||||
/* Reset CDCFGR2 register */
|
||||
RCC->CDCFGR2 = 0x00000000;
|
||||
|
||||
/* Reset SRDCFGR register */
|
||||
RCC->SRDCFGR = 0x00000000;
|
||||
#endif
|
||||
/* Reset PLLCKSELR register */
|
||||
RCC->PLLCKSELR = 0x02020200;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x01FF0000;
|
||||
/* Reset PLL1DIVR register */
|
||||
RCC->PLL1DIVR = 0x01010280;
|
||||
/* Reset PLL1FRACR register */
|
||||
RCC->PLL1FRACR = 0x00000000;
|
||||
|
||||
/* Reset PLL2DIVR register */
|
||||
RCC->PLL2DIVR = 0x01010280;
|
||||
|
||||
/* Reset PLL2FRACR register */
|
||||
|
||||
RCC->PLL2FRACR = 0x00000000;
|
||||
/* Reset PLL3DIVR register */
|
||||
RCC->PLL3DIVR = 0x01010280;
|
||||
|
||||
/* Reset PLL3FRACR register */
|
||||
RCC->PLL3FRACR = 0x00000000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
#if (STM32H7_DEV_ID == 0x450UL)
|
||||
/* dual core CM7 or single core line */
|
||||
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
|
||||
{
|
||||
/* if stm32h7 revY*/
|
||||
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
|
||||
*((__IO uint32_t*)0x51008108) = 0x000000001U;
|
||||
}
|
||||
#endif /* STM32H7_DEV_ID */
|
||||
|
||||
#if defined(DATA_IN_D2_SRAM)
|
||||
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
|
||||
#if defined(RCC_AHB2ENR_D2SRAM3EN)
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
|
||||
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
|
||||
#else
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
|
||||
#endif /* RCC_AHB2ENR_D2SRAM3EN */
|
||||
|
||||
tmpreg = RCC->AHB2ENR;
|
||||
(void) tmpreg;
|
||||
#endif /* DATA_IN_D2_SRAM */
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#else
|
||||
/*
|
||||
* Disable the FMC bank1 (enabled after reset).
|
||||
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||||
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||||
*/
|
||||
FMC_Bank1_R->BTCR[0] = 0x000030D2;
|
||||
|
||||
/* Configure the Vector Table location -------------------------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#endif /*DUAL_CORE && CORE_CM4*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock , it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
|
||||
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||
uint32_t common_system_clock;
|
||||
float_t fracn1, pllvco;
|
||||
void SystemCoreClockUpdate(void) {
|
||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||
uint32_t common_system_clock;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS) {
|
||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
||||
common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
break;
|
||||
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
||||
common_system_clock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
||||
common_system_clock = CSI_VALUE;
|
||||
break;
|
||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
||||
common_system_clock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
||||
common_system_clock = HSE_VALUE;
|
||||
break;
|
||||
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||||
|
||||
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
|
||||
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
|
||||
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
|
||||
if (pllm != 0U) {
|
||||
switch (pllsource) {
|
||||
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||||
|
||||
if (pllm != 0U)
|
||||
{
|
||||
switch (pllsource)
|
||||
{
|
||||
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) *
|
||||
((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
|
||||
(float_t)1);
|
||||
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
break;
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
|
||||
((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
|
||||
(float_t)1);
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
|
||||
((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
|
||||
(float_t)1);
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) *
|
||||
((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
|
||||
(float_t)1);
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
|
||||
common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
|
||||
} else {
|
||||
common_system_clock = 0U;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
|
||||
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
}
|
||||
else
|
||||
{
|
||||
common_system_clock = 0U;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
}
|
||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||
#if defined(RCC_D1CFGR_D1CPRE)
|
||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
|
||||
|
||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||
#if defined (RCC_D1CFGR_D1CPRE)
|
||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||
SystemD2Clock =
|
||||
(common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
||||
|
||||
#else
|
||||
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
|
||||
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
|
||||
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >>
|
||||
((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
SystemCoreClock = SystemD2Clock;
|
||||
SystemCoreClock = SystemD2Clock;
|
||||
#else
|
||||
SystemCoreClock = common_system_clock;
|
||||
SystemCoreClock = common_system_clock;
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
}
|
|
@ -1,12 +1,21 @@
|
|||
def will_connect():
|
||||
info("Creating external flash region...")
|
||||
info("Creating external memory regions...")
|
||||
extFlash = FlashRegion(
|
||||
name="QSPI",
|
||||
start=0x90000000,
|
||||
length=0x04000000,
|
||||
page_size=0x200,
|
||||
sector_size=0x2000,
|
||||
access='rx',
|
||||
access="rx",
|
||||
flm="assets/FIRE_STM32H750_PRO_QSPI.FLM"
|
||||
)
|
||||
target.memory_map.add_region(extFlash)
|
||||
|
||||
extSDRAM = RamRegion(
|
||||
name="SDRAM",
|
||||
start=0xD0000000,
|
||||
length=0x04000000,
|
||||
access="rwx"
|
||||
)
|
||||
|
||||
target.memory_map.add_region(extSDRAM)
|
||||
|
|
|
@ -1,21 +1,22 @@
|
|||
#include <stdio.h>
|
||||
|
||||
/* Board */
|
||||
#include "board.h"
|
||||
#include "clock_config.h"
|
||||
#include "peripherals.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
|
||||
int main(void) {
|
||||
HAL_Init();
|
||||
|
||||
BOARD_ConfigMPU();
|
||||
|
||||
SCB_EnableICache();
|
||||
SCB_EnableDCache();
|
||||
|
||||
BOARD_InitBootClocks();
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootPeripherals();
|
||||
|
||||
printf("Hello world!\r\n");
|
||||
|
||||
for (;;) {
|
||||
HAL_Delay(500);
|
||||
}
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
#include "peripherals.h"
|
||||
|
||||
int _write(int file, char *ptr, int len) {
|
||||
HAL_UART_Transmit(&huart1, (uint8_t *)ptr, len, 1000);
|
||||
|
||||
return len;
|
||||
}
|
|
@ -3,6 +3,8 @@
|
|||
#define BOOT_HEADER_SIGNATURE_VALID 0x46434642 /* FCFB */
|
||||
#define BOOT_HEADER_CONFIG_INIT_SDRAM_Pos 0
|
||||
#define BOOT_HEADER_CONFIG_INIT_SDRAM_Msk (1 << BOOT_HEADER_CONFIG_INIT_SDRAM_Pos)
|
||||
#define BOOT_HEADER_CONFIG_KEEP_RTC_Pos 1
|
||||
#define BOOT_HEADER_CONFIG_KEEP_RTC_Msk (1 << BOOT_HEADER_CONFIG_KEEP_RTC_Msk)
|
||||
|
||||
typedef struct {
|
||||
uint32_t signature;
|
||||
|
@ -13,7 +15,11 @@ typedef struct {
|
|||
#ifdef XIP_BOOT_ENABLED
|
||||
__attribute__((section(".xip_fcfb"))) const boot_header_t boot_hdr = {
|
||||
.signature = BOOT_HEADER_SIGNATURE_VALID,
|
||||
.config = 0U,
|
||||
.base = 0x90001000UL,
|
||||
#ifdef XIP_ENABLE_SDRAM
|
||||
.config = BOOT_HEADER_CONFIG_INIT_SDRAM_Msk,
|
||||
#else
|
||||
.config = 0UL,
|
||||
#endif
|
||||
.base = 0x90001000UL,
|
||||
};
|
||||
#endif
|
Loading…
Reference in New Issue