116 lines
4.7 KiB
C
116 lines
4.7 KiB
C
#include <math.h>
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#include "stm32h7xx.h"
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uint32_t SystemCoreClock;
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uint32_t SystemD2Clock;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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void SystemInit(void) {
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
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#endif
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}
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void SystemCoreClockUpdate(void) {
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
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uint32_t common_system_clock;
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float_t fracn1, pllvco;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS) {
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
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common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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break;
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case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
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common_system_clock = CSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
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common_system_clock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
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pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
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if (pllm != 0U) {
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switch (pllsource) {
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case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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pllvco = ((float_t)hsivalue / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
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(float_t)1);
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break;
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case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
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(float_t)1);
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break;
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case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
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(float_t)1);
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break;
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default:
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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pllvco = ((float_t)hsivalue / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) +
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(float_t)1);
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break;
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}
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pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
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common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
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} else {
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common_system_clock = 0U;
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}
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break;
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default:
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common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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break;
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}
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/* Compute SystemClock frequency --------------------------------------------------*/
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#if defined(RCC_D1CFGR_D1CPRE)
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tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
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/* common_system_clock frequency : CM7 CPU frequency */
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common_system_clock >>= tmp;
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/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
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SystemD2Clock =
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(common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
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#else
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tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
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/* common_system_clock frequency : CM7 CPU frequency */
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common_system_clock >>= tmp;
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/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
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SystemD2Clock = (common_system_clock >>
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((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
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#endif
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#if defined(DUAL_CORE) && defined(CORE_CM4)
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SystemCoreClock = SystemD2Clock;
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#else
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SystemCoreClock = common_system_clock;
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#endif /* DUAL_CORE && CORE_CM4 */
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} |