/*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* * How to set up clock using clock driver functions: * * 1. Setup clock sources. * * 2. Setup voltage for the fastest of the clock outputs * * 3. Set up wait states of the flash. * * 4. Set up all dividers. * * 5. Set up all selectors to provide selected clocks. */ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v10.0 processor: LPC54102J512 package_id: LPC54102J512BD64 mcu_data: ksdk2_0 processor_version: 12.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ #include "fsl_power.h" #include "fsl_clock.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockPLL150M(); } /******************************************************************************* ******************** Configuration BOARD_BootClockIRC12M ********************** ******************************************************************************/ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockIRC12M outputs: - {id: ASYNCAPB_clock.outFreq, value: 12 MHz} - {id: FRG_clock.outFreq, value: 12 MHz} - {id: MAIN_clock.outFreq, value: 12 MHz} - {id: System_clock.outFreq, value: 12 MHz} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ /******************************************************************************* * Variables for BOARD_BootClockIRC12M configuration ******************************************************************************/ /******************************************************************************* * Code for BOARD_BootClockIRC12M configuration ******************************************************************************/ void BOARD_BootClockIRC12M(void) { /*!< Set up the clock sources */ /*!< Set up IRC */ POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */ POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */ CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ /*!< PLL is in power_down mode */ POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ /*!< Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */ Clock_SetAsyncClkDiv(1U); /*!< Set ASYNCCLKDIV divider to value 1 */ ASYNC_SYSCON->FRGCTRL = ((ASYNC_SYSCON->FRGCTRL & ~ASYNC_SYSCON_FRGCTRL_MULT_MASK) | ASYNC_SYSCON_FRGCTRL_MULT(0U)); /*!< Set FRG MULT to value 0 */ ASYNC_SYSCON->ASYNCAPBCLKCTRL |= ASYNC_SYSCON_ASYNCAPBCLKCTRL_FRG0_MASK; /*!< Enable FRG clock */ /*!< Set up clock selectors - Attach clocks to the peripheries */ CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to IRC12M */ /*!< Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKIRC12M_CORE_CLOCK; } /******************************************************************************* ******************** Configuration BOARD_BootClockPLL150M ********************* ******************************************************************************/ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockPLL150M called_from_default_init: true outputs: - {id: ASYNCAPB_clock.outFreq, value: 50 MHz} - {id: FRG_clock.outFreq, value: 50 MHz} - {id: MAIN_clock.outFreq, value: 150 MHz} - {id: SYSTICK_clock.outFreq, value: 10 MHz} - {id: System_clock.outFreq, value: 150 MHz} settings: - {id: PLL_Mode, value: Normal} - {id: ASYNC_SYSCON.ASYNCAPBCLKSELB.sel, value: SYSCON.pll_clk} - {id: ASYNC_SYSCON.ASYNCCLKDIV.scale, value: '3'} - {id: SYSCON.CLKOUTDIV.scale, value: '0', locked: true} - {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL} - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS} - {id: SYSCON.M_MULT.scale, value: '50', locked: true} - {id: SYSCON.N_DIV.scale, value: '4', locked: true} - {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO} - {id: SYSCON.SYSTICKCLKDIV.scale, value: '15', locked: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ /******************************************************************************* * Variables for BOARD_BootClockPLL150M configuration ******************************************************************************/ /******************************************************************************* * Code for BOARD_BootClockPLL150M configuration ******************************************************************************/ void BOARD_BootClockPLL150M(void) { /*!< Set up the clock sources */ /*!< Set up IRC */ POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */ POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */ CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ /*!< Set up PLL */ CLOCK_AttachClk(kIRC12M_to_SYS_PLL); /*!< Switch SYSPLLCLKSEL to IRC12M */ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL); /*!< Ensure PLL is on */ const pll_setup_t pllSetup = { .syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELI(52U) | SYSCON_SYSPLLCTRL_SELP(26U) | SYSCON_SYSPLLCTRL_DIRECTO_MASK, .syspllndec = SYSCON_SYSPLLNDEC_NDEC(2U), .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U), .syspllssctrl = {(SYSCON_SYSPLLSSCTRL0_MDEC(32597U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK),0x0U}, .pllRate = 150000000U, .flags = PLL_SETUPFLAG_WAITLOCK }; CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */ POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ /*!< Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 15U, false); /*!< Set SYSTICKCLKDIV divider to value 15 */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */ Clock_SetAsyncClkDiv(3U); /*!< Set ASYNCCLKDIV divider to value 3 */ ASYNC_SYSCON->FRGCTRL = ((ASYNC_SYSCON->FRGCTRL & ~ASYNC_SYSCON_FRGCTRL_MULT_MASK) | ASYNC_SYSCON_FRGCTRL_MULT(0U)); /*!< Set FRG MULT to value 0 */ ASYNC_SYSCON->ASYNCAPBCLKCTRL |= ASYNC_SYSCON_ASYNCAPBCLKCTRL_FRG0_MASK; /*!< Enable FRG clock */ /*!< Set up clock selectors - Attach clocks to the peripheries */ CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL_OUT */ CLOCK_AttachClk(kSYS_PLL_OUT_to_ASYNC_APB); /*!< Switch ASYNC_APB to SYS_PLL_OUT */ /*!< Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; }