175 lines
8.7 KiB
C
175 lines
8.7 KiB
C
/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to set up clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Setup voltage for the fastest of the clock outputs
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*
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* 3. Set up wait states of the flash.
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*
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* 4. Set up all dividers.
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*
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* 5. Set up all selectors to provide selected clocks.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v10.0
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processor: LPC54102J512
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package_id: LPC54102J512BD64
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mcu_data: ksdk2_0
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processor_version: 12.0.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockIRC12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockIRC12M
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 12 MHz}
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- {id: FRG_clock.outFreq, value: 12 MHz}
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- {id: MAIN_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockIRC12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockIRC12M configuration
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******************************************************************************/
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void BOARD_BootClockIRC12M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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/*!< PLL is in power_down mode */
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POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */
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Clock_SetAsyncClkDiv(1U); /*!< Set ASYNCCLKDIV divider to value 1 */
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ASYNC_SYSCON->FRGCTRL = ((ASYNC_SYSCON->FRGCTRL & ~ASYNC_SYSCON_FRGCTRL_MULT_MASK) | ASYNC_SYSCON_FRGCTRL_MULT(0U)); /*!< Set FRG MULT to value 0 */
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ASYNC_SYSCON->ASYNCAPBCLKCTRL |= ASYNC_SYSCON_ASYNCAPBCLKCTRL_FRG0_MASK; /*!< Enable FRG clock */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to IRC12M */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKIRC12M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL150M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL150M
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called_from_default_init: true
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 50 MHz}
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- {id: FRG_clock.outFreq, value: 50 MHz}
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- {id: MAIN_clock.outFreq, value: 150 MHz}
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- {id: SYSTICK_clock.outFreq, value: 10 MHz}
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- {id: System_clock.outFreq, value: 150 MHz}
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settings:
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- {id: PLL_Mode, value: Normal}
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- {id: ASYNC_SYSCON.ASYNCAPBCLKSELB.sel, value: SYSCON.pll_clk}
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- {id: ASYNC_SYSCON.ASYNCCLKDIV.scale, value: '3'}
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- {id: SYSCON.CLKOUTDIV.scale, value: '0', locked: true}
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- {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '50', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '4', locked: true}
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- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
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- {id: SYSCON.SYSTICKCLKDIV.scale, value: '15', locked: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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void BOARD_BootClockPLL150M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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/*!< Set up PLL */
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CLOCK_AttachClk(kIRC12M_to_SYS_PLL); /*!< Switch SYSPLLCLKSEL to IRC12M */
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POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL); /*!< Ensure PLL is on */
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const pll_setup_t pllSetup = {
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.syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELI(52U) | SYSCON_SYSPLLCTRL_SELP(26U) | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
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.syspllndec = SYSCON_SYSPLLNDEC_NDEC(2U),
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.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U),
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.syspllssctrl = {(SYSCON_SYSPLLSSCTRL0_MDEC(32597U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK),0x0U},
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.pllRate = 150000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
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POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 15U, false); /*!< Set SYSTICKCLKDIV divider to value 15 */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */
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Clock_SetAsyncClkDiv(3U); /*!< Set ASYNCCLKDIV divider to value 3 */
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ASYNC_SYSCON->FRGCTRL = ((ASYNC_SYSCON->FRGCTRL & ~ASYNC_SYSCON_FRGCTRL_MULT_MASK) | ASYNC_SYSCON_FRGCTRL_MULT(0U)); /*!< Set FRG MULT to value 0 */
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ASYNC_SYSCON->ASYNCAPBCLKCTRL |= ASYNC_SYSCON_ASYNCAPBCLKCTRL_FRG0_MASK; /*!< Enable FRG clock */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL_OUT */
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CLOCK_AttachClk(kSYS_PLL_OUT_to_ASYNC_APB); /*!< Switch ASYNC_APB to SYS_PLL_OUT */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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}
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