47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/*
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* Copyright 2017-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include "fsl_common.h"
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#include "clock_config.h"
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#include "board.h"
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#include "fsl_debug_console.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Clock rate on the CLKIN pin */
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const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* Initialize debug console. */
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status_t BOARD_InitDebugConsole(void)
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{
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status_t result;
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/* attach 12 MHz clock to USART0 (debug console) */
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CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
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RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
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result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE,
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BOARD_DEBUG_UART_CLK_FREQ);
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assert(kStatus_Success == result);
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return result;
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}
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status_t BOARD_InitDebugConsole_Core1(void)
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{
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status_t result;
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/* attach 12 MHz clock to USART2 (debug console) */
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CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
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RESET_PeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
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result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1,
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BOARD_DEBUG_UART_TYPE_CORE1, BOARD_DEBUG_UART_CLK_FREQ_CORE1);
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assert(kStatus_Success == result);
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return result;
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}
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