diff --git a/CMakeLists.txt b/CMakeLists.txt index eb0cdfa..559d86c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -60,6 +60,7 @@ set(TARGET_SOURCES "board/clock_config.c" "board/peripherals.c" "board/pin_mux.c" + "src/app_nh_impl.c" "src/main.c" ) diff --git a/LPCXpresso55S69.mex b/LPCXpresso55S69.mex index c0fcd22..1a4009a 100644 --- a/LPCXpresso55S69.mex +++ b/LPCXpresso55S69.mex @@ -534,12 +534,17 @@ true + + + true + + true - + true @@ -549,16 +554,22 @@ - - + - + - + + + + + + + + diff --git a/board/pin_mux.c b/board/pin_mux.c index 0efec84..f8f08d2 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -23,6 +23,7 @@ pin_labels: #include "fsl_common.h" #include "fsl_gpio.h" #include "fsl_iocon.h" +#include "fsl_inputmux.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -859,9 +860,9 @@ BOARD_InitMikroEPins: - {pin_num: '59', peripheral: FLEXCOMM8, signal: HS_SPI_SSEL1, pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4} - {pin_num: '61', peripheral: FLEXCOMM8, signal: HS_SPI_SCK, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} - {pin_num: '60', peripheral: FLEXCOMM8, signal: HS_SPI_MOSI, pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26} - - {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6} - - {pin_num: '31', peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, direction: INPUT} - - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: ESP_DRDY, direction: INPUT} + - {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6, mode: pullUp} + - {pin_num: '31', peripheral: PINT, signal: 'PINT, 0', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, direction: INPUT, mode: inactive} + - {pin_num: '64', peripheral: PINT, signal: 'PINT, 1', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: ESP_DRDY, direction: INPUT, mode: inactive} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -875,25 +876,14 @@ BOARD_InitMikroEPins: /* Function assigned for the Cortex-M33 (Core #0) */ void BOARD_InitMikroEPins(void) { + /* Enables the clock for the Input Mux.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_InputMux); /* Enables the clock for the I/O controller.: Enable Clock. */ CLOCK_EnableClock(kCLOCK_Iocon); - - /* Enables the clock for the GPIO1 module */ - CLOCK_EnableClock(kCLOCK_Gpio1); - - gpio_pin_config_t ESP_HS_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO1_5 (pin 31) */ - GPIO_PinInit(BOARD_INITMIKROEPINS_ESP_HS_GPIO, BOARD_INITMIKROEPINS_ESP_HS_PORT, BOARD_INITMIKROEPINS_ESP_HS_PIN, &ESP_HS_config); - - gpio_pin_config_t ESP_DRDY_config = { - .pinDirection = kGPIO_DigitalInput, - .outputLogic = 0U - }; - /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ - GPIO_PinInit(BOARD_INITMIKROEPINS_ESP_DRDY_GPIO, BOARD_INITMIKROEPINS_ESP_DRDY_PORT, BOARD_INITMIKROEPINS_ESP_DRDY_PIN, &ESP_DRDY_config); + /* PIO1_5 is selected for PINT input 0 */ + INPUTMUX_AttachSignal(INPUTMUX, 0U, kINPUTMUX_GpioPort1Pin5ToPintsel); + /* PIO1_18 is selected for PINT input 1 */ + INPUTMUX_AttachSignal(INPUTMUX, 1U, kINPUTMUX_GpioPort1Pin18ToPintsel); IOCON->PIO[0][26] = ((IOCON->PIO[0][26] & /* Mask bits to zero which are setting */ @@ -923,12 +913,17 @@ void BOARD_InitMikroEPins(void) IOCON->PIO[1][18] = ((IOCON->PIO[1][18] & /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Selects pin function. * : PORT118 (pin 64) is configured as PIO1_18. */ | IOCON_PIO_FUNC(PIO1_18_FUNC_ALT0) + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). */ + | IOCON_PIO_MODE(PIO1_18_MODE_INACTIVE) + /* Select Digital mode. * : Enable Digital mode. * Digital input is enabled. */ @@ -949,12 +944,17 @@ void BOARD_InitMikroEPins(void) IOCON->PIO[1][3] = ((IOCON->PIO[1][3] & /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Selects pin function. * : PORT13 (pin 62) is configured as HS_SPI_MISO. */ | IOCON_PIO_FUNC(PIO1_3_FUNC_ALT6) + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_3_MODE_PULL_UP) + /* Select Digital mode. * : Enable Digital mode. * Digital input is enabled. */ @@ -962,12 +962,17 @@ void BOARD_InitMikroEPins(void) IOCON->PIO[1][5] = ((IOCON->PIO[1][5] & /* Mask bits to zero which are setting */ - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Selects pin function. * : PORT15 (pin 31) is configured as PIO1_5. */ | IOCON_PIO_FUNC(PIO1_5_FUNC_ALT0) + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). */ + | IOCON_PIO_MODE(PIO1_5_MODE_INACTIVE) + /* Select Digital mode. * : Enable Digital mode. * Digital input is enabled. */ diff --git a/board/pin_mux.h b/board/pin_mux.h index 819c5bc..98e0430 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -444,6 +444,13 @@ void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0 /*! * @brief Selects pin function.: Alternative connection 0. */ #define PIO1_18_FUNC_ALT0 0x00u +/*! + * @brief + * Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). + */ +#define PIO1_18_MODE_INACTIVE 0x00u /*! * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ #define PIO1_1_DIGIMODE_DIGITAL 0x01u @@ -462,19 +469,25 @@ void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0 /*! * @brief Selects pin function.: Alternative connection 6. */ #define PIO1_3_FUNC_ALT6 0x06u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_3_MODE_PULL_UP 0x02u /*! * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ #define PIO1_5_DIGIMODE_DIGITAL 0x01u /*! * @brief Selects pin function.: Alternative connection 0. */ #define PIO1_5_FUNC_ALT0 0x00u +/*! + * @brief + * Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). + */ +#define PIO1_5_MODE_INACTIVE 0x00u /*! @name PIO1_5 (number 31), P17[17]/P24[1]/PIO1_5_GPIO_ARD @{ */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITMIKROEPINS_ESP_HS_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define BOARD_INITMIKROEPINS_ESP_HS_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ #define BOARD_INITMIKROEPINS_ESP_HS_PORT 1U /*!<@brief PORT peripheral base pointer */ #define BOARD_INITMIKROEPINS_ESP_HS_PIN 5U /*!<@brief PORT pin number */ #define BOARD_INITMIKROEPINS_ESP_HS_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ @@ -482,10 +495,6 @@ void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0 /*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO @{ */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITMIKROEPINS_ESP_DRDY_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ -#define BOARD_INITMIKROEPINS_ESP_DRDY_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ #define BOARD_INITMIKROEPINS_ESP_DRDY_PORT 1U /*!<@brief PORT peripheral base pointer */ #define BOARD_INITMIKROEPINS_ESP_DRDY_PIN 18U /*!<@brief PORT pin number */ #define BOARD_INITMIKROEPINS_ESP_DRDY_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ diff --git a/include/app_nh_impl.h b/include/app_nh_impl.h new file mode 100644 index 0000000..f0de93e --- /dev/null +++ b/include/app_nh_impl.h @@ -0,0 +1,9 @@ +#ifndef APP_NH_IMPL_H +#define APP_NH_IMPL_H + +#include "nh_shared_if.h" +#include "nh_ctrl_api.h" + +int app_nh_impl_init(void); + +#endif // APP_NH_IMPL_H diff --git a/lib/esp_nano_hosted b/lib/esp_nano_hosted index 35f33ad..a628889 160000 --- a/lib/esp_nano_hosted +++ b/lib/esp_nano_hosted @@ -1 +1 @@ -Subproject commit 35f33adb70379a456f5223c25defbd36fd7b256e +Subproject commit a628889e74f306b82a1d3fe0e0df75158ab53fbd diff --git a/src/app_nh_impl.c b/src/app_nh_impl.c new file mode 100644 index 0000000..01f94f2 --- /dev/null +++ b/src/app_nh_impl.c @@ -0,0 +1,351 @@ +/* Board */ +#include "board.h" +#include "clock_config.h" +#include "pin_mux.h" + +/* FreeRTOS */ +/* clang-format off */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +/* clang-format on */ + +/* SDK drivers */ +#include "fsl_gpio.h" +#include "fsl_pint.h" +#include "fsl_spi.h" + +/* Debug Console */ +#include "fsl_debug_console.h" + +/* Private */ +#include "app_nh_impl.h" + +static int app_nh_impl_spi_init(void); +static int app_nh_impl_pin_init(void); + +static inline bool app_nh_impl_is_isr(void); + +static void app_nh_impl_drdy_callback(pint_pin_int_t pintr, uint32_t pmatch_status); +static void app_nh_impl_hs_callback(pint_pin_int_t pintr, uint32_t pmatch_status); + +static nh_ret_t app_nh_impl_ops_xfer(void *handle, uint8_t *tx_data, uint8_t *rx_data, uint32_t len); +static nh_ret_t app_nh_impl_ops_drdy_read(void *handle, bool *rdy); +static void app_nh_impl_cb_event(void *handle, uint8_t *payload); + +static nh_ret_t app_nh_impl_buf_allocate(void *handle, uint8_t **buf, uint32_t size); +static nh_ret_t app_nh_impl_buf_free(void *handle, uint8_t *buf); + +static nh_ret_t app_nh_impl_semaphore_create(void *handle, nh_osa_semaphore_t *sem); +static nh_ret_t app_nh_impl_semaphore_take(void *handle, nh_osa_semaphore_t sem, uint32_t timeout_msec); +static nh_ret_t app_nh_impl_semaphore_give(void *handle, nh_osa_semaphore_t sem); +static nh_ret_t app_nh_impl_semaphore_destroy(void *handle, nh_osa_semaphore_t sem); + +static nh_ret_t app_nh_impl_queue_create(void *handle, nh_osa_queue_t *queue, uint32_t item_size, uint32_t max_length); +static nh_ret_t app_nh_impl_queue_enqueue(void *handle, nh_osa_queue_t queue, void *item, uint32_t timeout_msec); +static nh_ret_t app_nh_impl_queue_dequeue(void *handle, nh_osa_queue_t queue, void *item, uint32_t timeout_msec); +static nh_ret_t app_impl_queue_destroy(void *handle, nh_osa_queue_t queue); + +static void app_nh_impl_shared_if_task(void *parameters); +static void app_nh_impl_ctrl_task(void *parameters); + +static nh_osa_t s_nh_osa = { + .buf_allocate = app_nh_impl_buf_allocate, + .buf_free = app_nh_impl_buf_free, + + .sem_create = app_nh_impl_semaphore_create, + .sem_give = app_nh_impl_semaphore_give, + .sem_take = app_nh_impl_semaphore_take, + .sem_destroy = app_nh_impl_semaphore_destroy, + + .queue_create = app_nh_impl_queue_create, + .queue_enqueue = app_nh_impl_queue_enqueue, + .queue_dequeue = app_nh_impl_queue_dequeue, + .queue_destroy = app_impl_queue_destroy, +}; + +static nh_shared_if_t s_nh_shared_if = { + .osa = &s_nh_osa, + .ops = + { + .xfer = app_nh_impl_ops_xfer, + .drdy_read = app_nh_impl_ops_drdy_read, + }, + .cb = + { + .event = app_nh_impl_cb_event, + }, +}; + +static nh_ctrl_api_t s_nh_ctrl_api = { + .osa = &s_nh_osa, + .shared_if = &s_nh_shared_if, +}; + +int app_nh_impl_init(void) { + if (app_nh_impl_pin_init() != 0) { + return -1; + } + + if (app_nh_impl_spi_init() != 0) { + return -2; + } + + if (nh_shared_if_init(&s_nh_shared_if) != NH_RET_SUCCESS) { + return -3; + } + + if (xTaskCreate(app_nh_impl_shared_if_task, "NH_SHARED_IF", 1024, &s_nh_shared_if, 2, NULL) != pdPASS) { + return -4; + } + + if (nh_ctrl_api_init(&s_nh_ctrl_api) != NH_RET_SUCCESS) { + return -5; + } + + if (xTaskCreate(app_nh_impl_ctrl_task, "NH_CTRL", 512, &s_nh_ctrl_api, 2, NULL) != pdPASS) { + return -6; + } + + return 0; +} + +static int app_nh_impl_spi_init(void) { + spi_master_config_t cfg; + + /* Main Clock to SPI */ + CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI); + + SPI_MasterGetDefaultConfig(&cfg); + + cfg.baudRate_Bps = 20000000UL; + cfg.sselNum = kSPI_Ssel1; + cfg.phase = kSPI_ClockPhaseSecondEdge; /* SPI Mode 1 */ + + if (SPI_MasterInit(SPI8, &cfg, CLOCK_GetHsLspiClkFreq()) != kStatus_Success) { + return -1; + } + + return 0; +} + +static int app_nh_impl_pin_init(void) { + /* Configure pin interrupt */ + + PINT_Init(PINT); + + PINT_PinInterruptConfig(PINT, kPINT_PinInt0, kPINT_PinIntEnableRiseEdge, app_nh_impl_hs_callback); + PINT_EnableCallbackByIndex(PINT, kPINT_PinInt1); + + PINT_PinInterruptConfig(PINT, kPINT_PinInt1, kPINT_PinIntEnableRiseEdge, app_nh_impl_drdy_callback); + PINT_EnableCallbackByIndex(PINT, kPINT_PinInt1); + + EnableIRQ(PIN_INT0_IRQn); + NVIC_SetPriority(PIN_INT0_IRQn, 5); + + EnableIRQ(PIN_INT1_IRQn); + NVIC_SetPriority(PIN_INT1_IRQn, 5); + + return 0; +} + +static inline bool app_nh_impl_is_isr(void) { + if (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) { + /* We are in ISR... */ + return true; + } + + return false; +} + +static void app_nh_impl_drdy_callback(pint_pin_int_t pintr, uint32_t pmatch_status) { + /* If there's a packet to be received by host, the DRDY is set high. */ + if (GPIO_PinRead(GPIO, BOARD_INITMIKROEPINS_ESP_HS_PORT, BOARD_INITMIKROEPINS_ESP_HS_PIN)) { + nh_shared_if_inject_data_ready(&s_nh_shared_if); + } +} + +static void app_nh_impl_hs_callback(pint_pin_int_t pintr, uint32_t pmatch_status) { + /* If the DRDY is high when HS rises, there's another packet waiting... */ + if (GPIO_PinRead(GPIO, BOARD_INITMIKROEPINS_ESP_DRDY_PORT, BOARD_INITMIKROEPINS_ESP_DRDY_PIN)) { + nh_shared_if_inject_data_ready(&s_nh_shared_if); + } +} + +static nh_ret_t app_nh_impl_ops_drdy_read(void *handle, bool *rdy) { + if (GPIO_PinRead(GPIO, BOARD_INITMIKROEPINS_ESP_DRDY_PORT, BOARD_INITMIKROEPINS_ESP_DRDY_PIN)) { + *rdy = true; + } else { + *rdy = false; + } + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_ops_xfer(void *handle, uint8_t *tx_data, uint8_t *rx_data, uint32_t len) { + spi_transfer_t xfer = { + .txData = tx_data, + .rxData = rx_data, + .dataSize = len, + .configFlags = kSPI_FrameAssert, + }; + + if (SPI_MasterTransferBlocking(SPI8, &xfer) != kStatus_Success) { + return NH_RET_FAIL; + } + + return NH_RET_SUCCESS; +} + +static void app_nh_impl_cb_event(void *handle, uint8_t *payload) { + PRINTF("Received event from ESP..\r\n"); +} + +static nh_ret_t app_nh_impl_buf_allocate(void *handle, uint8_t **buf, uint32_t size) { + *buf = pvPortMalloc(size); + if (*buf == NULL) { + return NH_RET_FAIL; + } + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_buf_free(void *handle, uint8_t *buf) { + vPortFree(buf); + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_semaphore_create(void *handle, nh_osa_semaphore_t *sem) { + *sem = xSemaphoreCreateBinary(); + if (*sem == NULL) { + return NH_RET_FAIL; + } + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_semaphore_take(void *handle, nh_osa_semaphore_t sem, uint32_t timeout_msec) { + nh_ret_t ret = NH_RET_SUCCESS; + if (app_nh_impl_is_isr()) { + if (timeout_msec != 0) { + /* Block in ISR is not permitted */ + return NH_RET_FAIL; + } + + BaseType_t higher_prio_task_woken = pdFALSE; + if (xSemaphoreTakeFromISR(sem, &higher_prio_task_woken) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + + portYIELD_FROM_ISR(higher_prio_task_woken); + + } else { + if (xSemaphoreTake(sem, pdMS_TO_TICKS(timeout_msec)) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + } + return ret; +} + +static nh_ret_t app_nh_impl_semaphore_give(void *handle, nh_osa_semaphore_t sem) { + nh_ret_t ret = NH_RET_SUCCESS; + + if (app_nh_impl_is_isr()) { + BaseType_t higher_prio_task_woken = pdFALSE; + if (xSemaphoreGiveFromISR(sem, &higher_prio_task_woken) != pdPASS) { + ret = NH_RET_FAIL; + } + + portYIELD_FROM_ISR(higher_prio_task_woken); + } else { + if (xSemaphoreGive(sem) != pdPASS) { + ret = NH_RET_FAIL; + } + } + + return ret; +} + +static nh_ret_t app_nh_impl_semaphore_destroy(void *handle, nh_osa_semaphore_t sem) { + vSemaphoreDelete(sem); + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_queue_create(void *handle, nh_osa_queue_t *queue, uint32_t item_size, uint32_t max_length) { + *queue = xQueueCreate(max_length, item_size); + if (*queue == NULL) { + return NH_RET_FAIL; + } + + return NH_RET_SUCCESS; +} + +static nh_ret_t app_nh_impl_queue_enqueue(void *handle, nh_osa_queue_t queue, void *item, uint32_t timeout_msec) { + nh_ret_t ret = NH_RET_SUCCESS; + + if (app_nh_impl_is_isr()) { + if (timeout_msec != 0) { + return NH_RET_FAIL; + } + + BaseType_t higher_prio_task_woken = pdFALSE; + if (xQueueSendFromISR(queue, item, &higher_prio_task_woken) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + + portYIELD_FROM_ISR(higher_prio_task_woken); + } else { + if (xQueueSend(queue, item, pdMS_TO_TICKS(timeout_msec)) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + } + + return ret; +} + +static nh_ret_t app_nh_impl_queue_dequeue(void *handle, nh_osa_queue_t queue, void *item, uint32_t timeout_msec) { + nh_ret_t ret = NH_RET_SUCCESS; + + if (app_nh_impl_is_isr()) { + if (timeout_msec != 0) { + return NH_RET_FAIL; + } + + BaseType_t higher_prio_task_woken = pdFALSE; + if (xQueueReceiveFromISR(queue, item, &higher_prio_task_woken) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + + portYIELD_FROM_ISR(higher_prio_task_woken); + } else { + if (xQueueReceive(queue, item, pdMS_TO_TICKS(timeout_msec)) != pdPASS) { + ret = NH_RET_TIMEOUT; + } + } + + return ret; +} + +static nh_ret_t app_impl_queue_destroy(void *handle, nh_osa_queue_t queue) { + vQueueDelete(queue); + + return NH_RET_SUCCESS; +} + +static void app_nh_impl_shared_if_task(void *parameters) { + for (;;) { + nh_shared_if_task(&s_nh_shared_if); + } + + vTaskDelete(NULL); +} + +static void app_nh_impl_ctrl_task(void *parameters) { + for (;;) { + nh_ctrl_api_task(&s_nh_ctrl_api); + } + + vTaskDelete(NULL); +} \ No newline at end of file diff --git a/src/main.c b/src/main.c index 2ca91f5..06f0f95 100644 --- a/src/main.c +++ b/src/main.c @@ -11,6 +11,9 @@ #include "FreeRTOS.h" #include "task.h" +/* Private */ +#include "app_nh_impl.h" + static void initialization_task(void *params); int main(void) { @@ -41,6 +44,9 @@ static void initialization_task(void *params) { PRINTF("Initialization task running...\r\n"); /* Do initialization stuff here, since the scheduler is running now. */ + if(app_nh_impl_init() != 0) { + PRINTF("Failed to init nano_hosted\r\n"); + } vTaskDelete(NULL); } \ No newline at end of file