diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..eb964b4 --- /dev/null +++ b/.clang-format @@ -0,0 +1,12 @@ +BasedOnStyle: Google +IndentWidth: 4 +AlignConsecutiveMacros: AcrossEmptyLines +AlignConsecutiveDeclarations: Consecutive +AlignConsecutiveAssignments: AcrossEmptyLinesAndComments +AllowShortFunctionsOnASingleLine: None +BreakBeforeBraces: Custom +BraceWrapping: + AfterEnum: false + AfterStruct: false + SplitEmptyFunction: false +ColumnLimit: 120 \ No newline at end of file diff --git a/.gitmodules b/.gitmodules index 01dbdb2..921aec9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,9 @@ [submodule "SDK"] path = SDK url = https://git.minori.work/Embedded_SDK/MCUXpresso_LPC55S69.git +[submodule "lib/esp_hosted/hosted"] + path = lib/esp_hosted/hosted + url = https://github.com/espressif/esp-hosted.git +[submodule "lib/freertos"] + path = lib/freertos + url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 0251e8f..2cbb4d8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,6 @@ cmake_minimum_required(VERSION 3.10) -project(lpcxpresso_55s69_template) +project(lpcxpresso_55s69_esp_hosted) enable_language(CXX) enable_language(ASM) @@ -67,6 +67,7 @@ set(TARGET_C_DEFINES "CPU_LPC55S69JBD100_cm33_core0" "FFR_INCLUDE=\"fsl_iap_ffr.h\"" "MCUXPRESSO_SDK" + "SDK_OS_FREE_RTOS" "SERIAL_PORT_TYPE_UART=1" "__STARTUP_CLEAR_BSS" ) @@ -86,13 +87,16 @@ set(TARGET_C_INCLUDES # Shared libraries linked with application set(TARGET_LIBS "c" + "esp_hosted" + "freertos_kernel" + "fro_calib_hardabi" "m" "nosys" ) # Shared library and linker script search paths set(TARGET_LIB_DIRECTORIES - + "SDK/devices/LPC55S69/gcc" ) # Conditional flags @@ -113,6 +117,16 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp") set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections") +# Submodules +set(ESP_HOSTED_PORT_INCLUDES "${CMAKE_SOURCE_DIR}/lib/esp_hosted/nxp/include" CACHE STRING "") +add_subdirectory(lib/esp_hosted) + +add_library(freertos_config INTERFACE) +target_include_directories(freertos_config SYSTEM INTERFACE include) +set(FREERTOS_PORT "GCC_ARM_CM33_NTZ_NONSECURE" CACHE STRING "") +set(FREERTOS_HEAP "4" CACHE STRING "") +add_subdirectory(lib/freertos) + # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) include_directories(${TARGET_C_INCLUDES}) diff --git a/LPCXpresso55S69.mex b/LPCXpresso55S69.mex index 5bc9c26..c0fcd22 100644 --- a/LPCXpresso55S69.mex +++ b/LPCXpresso55S69.mex @@ -27,6 +27,10 @@ 12.0.0 + + + + @@ -290,6 +294,7 @@ + @@ -516,6 +521,48 @@ + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + diff --git a/SDK b/SDK new file mode 160000 index 0000000..4426225 --- /dev/null +++ b/SDK @@ -0,0 +1 @@ +Subproject commit 442622515005ffb9fd32e59d3fbd470f0f67550b diff --git a/board/pin_mux.c b/board/pin_mux.c index 1c8f15c..0efec84 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -13,6 +13,9 @@ package_id: LPC55S69JBD100 mcu_data: ksdk2_0 processor_version: 12.0.0 board: LPCXpresso55S69 +pin_labels: +- {pin_num: '31', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, label: 'P17[17]/P24[1]/PIO1_5_GPIO_ARD', identifier: ESP_HS} +- {pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, label: 'S2/P18[16]/P24[2]/WAKE/GPIO', identifier: S2;ESP_DRDY} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -32,6 +35,7 @@ void BOARD_InitBootPins(void) { BOARD_InitDEBUG_UARTPins(); BOARD_InitPins_Core0(); + BOARD_InitMikroEPins(); } /* clang-format off */ @@ -443,7 +447,7 @@ BOARD_InitBUTTONsPins: - pin_list: - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} - - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard, + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: S2, direction: INPUT, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} @@ -845,6 +849,130 @@ void BOARD_InitACCELPins(void) /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); } + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitMikroEPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '59', peripheral: FLEXCOMM8, signal: HS_SPI_SSEL1, pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4} + - {pin_num: '61', peripheral: FLEXCOMM8, signal: HS_SPI_SCK, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} + - {pin_num: '60', peripheral: FLEXCOMM8, signal: HS_SPI_MOSI, pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26} + - {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6} + - {pin_num: '31', peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, direction: INPUT} + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: ESP_DRDY, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitMikroEPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitMikroEPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ESP_HS_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_5 (pin 31) */ + GPIO_PinInit(BOARD_INITMIKROEPINS_ESP_HS_GPIO, BOARD_INITMIKROEPINS_ESP_HS_PORT, BOARD_INITMIKROEPINS_ESP_HS_PIN, &ESP_HS_config); + + gpio_pin_config_t ESP_DRDY_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITMIKROEPINS_ESP_DRDY_GPIO, BOARD_INITMIKROEPINS_ESP_DRDY_PORT, BOARD_INITMIKROEPINS_ESP_DRDY_PIN, &ESP_DRDY_config); + + IOCON->PIO[0][26] = ((IOCON->PIO[0][26] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT026 (pin 60) is configured as HS_SPI_MOSI. */ + | IOCON_PIO_FUNC(0x09u) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_26_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][1] = ((IOCON->PIO[1][1] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT11 (pin 59) is configured as HS_SPI_SSEL1. */ + | IOCON_PIO_FUNC(PIO1_1_FUNC_ALT5) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_1_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][18] = ((IOCON->PIO[1][18] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT118 (pin 64) is configured as PIO1_18. */ + | IOCON_PIO_FUNC(PIO1_18_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_18_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][2] = ((IOCON->PIO[1][2] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT12 (pin 61) is configured as HS_SPI_SCK. */ + | IOCON_PIO_FUNC(PIO1_2_FUNC_ALT6) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][3] = ((IOCON->PIO[1][3] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT13 (pin 62) is configured as HS_SPI_MISO. */ + | IOCON_PIO_FUNC(PIO1_3_FUNC_ALT6) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_3_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][5] = ((IOCON->PIO[1][5] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT15 (pin 31) is configured as PIO1_5. */ + | IOCON_PIO_FUNC(PIO1_5_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_5_DIGIMODE_DIGITAL)); +} /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/board/pin_mux.h b/board/pin_mux.h index 1678fa9..819c5bc 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -435,6 +435,68 @@ void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_26_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_18_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_18_FUNC_ALT0 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_1_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 5. */ +#define PIO1_1_FUNC_ALT5 0x05u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_2_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 6. */ +#define PIO1_2_FUNC_ALT6 0x06u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_3_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 6. */ +#define PIO1_3_FUNC_ALT6 0x06u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_5_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_5_FUNC_ALT0 0x00u + +/*! @name PIO1_5 (number 31), P17[17]/P24[1]/PIO1_5_GPIO_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITMIKROEPINS_ESP_HS_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITMIKROEPINS_ESP_HS_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITMIKROEPINS_ESP_HS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITMIKROEPINS_ESP_HS_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITMIKROEPINS_ESP_HS_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITMIKROEPINS_ESP_DRDY_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITMIKROEPINS_ESP_DRDY_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +#define BOARD_INITMIKROEPINS_ESP_DRDY_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITMIKROEPINS_ESP_DRDY_PIN 18U /*!<@brief PORT pin number */ +#define BOARD_INITMIKROEPINS_ESP_DRDY_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitMikroEPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + #if defined(__cplusplus) } #endif diff --git a/include/FreeRTOSConfig.h b/include/FreeRTOSConfig.h new file mode 100644 index 0000000..6bfeaed --- /dev/null +++ b/include/FreeRTOSConfig.h @@ -0,0 +1,166 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 1 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(64 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 8 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/lib/esp_hosted/CMakeLists.txt b/lib/esp_hosted/CMakeLists.txt new file mode 100644 index 0000000..316c49a --- /dev/null +++ b/lib/esp_hosted/CMakeLists.txt @@ -0,0 +1,35 @@ +cmake_minimum_required(VERSION 3.10) + +project(esp_hosted) + +if(NOT DEFINED ESP_HOSTED_PORT_INCLUDES) + message(FATAL_ERROR "Variable ESP_HOSTED_PORT_INCLUDES is not defined.") +endif() + +set(ESP_HOSTED_SOURCES + "hosted/esp_hosted_fg/common/protobuf-c/protobuf-c/protobuf-c.c" + "hosted/esp_hosted_fg/common/esp_hosted_config.pb-c.c" + "hosted/esp_hosted_fg/host/components/src/esp_queue.c" + "hosted/esp_hosted_fg/host/control_lib/src/ctrl_api.c" + "hosted/esp_hosted_fg/host/control_lib/src/ctrl_core.c" + "hosted/esp_hosted_fg/host/virtual_serial_if/src/serial_if.c" +) + +set(ESP_HOSTED_INCLUDES + "hosted/esp_hosted_fg/common/include" + "hosted/esp_hosted_fg/common/protobuf-c" + "hosted/esp_hosted_fg/host/control_lib/include" + "hosted/esp_hosted_fg/host/components/include" + "hosted/esp_hosted_fg/host/control_lib/src/include" + "hosted/esp_hosted_fg/host/virtual_serial_if/include" + ${ESP_HOSTED_PORT_INCLUDES} +) + +set(ESP_HOSTED_INCLUDES_PRIVATE +) + +add_library(${PROJECT_NAME} ${ESP_HOSTED_SOURCES}) +target_include_directories(${PROJECT_NAME} + PUBLIC ${ESP_HOSTED_INCLUDES} + PRIVATE ${ESP_HOSTED_INCLUDES_PRIVATE} +) \ No newline at end of file diff --git a/lib/esp_hosted/hosted b/lib/esp_hosted/hosted new file mode 160000 index 0000000..16dece6 --- /dev/null +++ b/lib/esp_hosted/hosted @@ -0,0 +1 @@ +Subproject commit 16dece6639c378324f460f1f0f5dc9cb1c248541 diff --git a/lib/esp_hosted/nxp/include/common.h b/lib/esp_hosted/nxp/include/common.h new file mode 100644 index 0000000..ff69f67 --- /dev/null +++ b/lib/esp_hosted/nxp/include/common.h @@ -0,0 +1,6 @@ +#ifndef ESP_HOSTED_NXP_COMMON_H +#define ESP_HOSTED_NXP_COMMON_H + +int min(int x, int y); + +#endif /* ESP_HOSTED_NXP_COMMON_H */ \ No newline at end of file diff --git a/lib/esp_hosted/nxp/include/platform_wrapper.h b/lib/esp_hosted/nxp/include/platform_wrapper.h new file mode 100644 index 0000000..e9f33fa --- /dev/null +++ b/lib/esp_hosted/nxp/include/platform_wrapper.h @@ -0,0 +1,16 @@ +#ifndef PLATFORM_WRAPPER_H +#define PLATFORM_WRAPPER_H + +#define PLATFORM_NO_SYS 1 + +#define CTRL__TIMER_ONESHOT (0) + +#define HOSTED_SEM_BLOCKING (-1) + +#define mem_free(x) hosted_free(x) + +void* hosted_malloc(size_t size); +void* hosted_calloc(size_t blk_no, size_t size); +void hosted_free(void* ptr); + +#endif \ No newline at end of file diff --git a/lib/freertos b/lib/freertos new file mode 160000 index 0000000..6d65558 --- /dev/null +++ b/lib/freertos @@ -0,0 +1 @@ +Subproject commit 6d65558ba01141d7c50ff6f93a4054cc5f16940e diff --git a/src/main.c b/src/main.c index 21245ea..2ca91f5 100644 --- a/src/main.c +++ b/src/main.c @@ -1,10 +1,18 @@ +/* Board */ #include "board.h" #include "clock_config.h" #include "peripherals.h" #include "pin_mux.h" +/* Debug Console */ #include "fsl_debug_console.h" +/* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" + +static void initialization_task(void *params); + int main(void) { BOARD_InitBootPins(); BOARD_BootClockFROHF96M(); @@ -14,7 +22,25 @@ int main(void) { PRINTF("Hello world!!\r\n"); - for(;;) { + if (xTaskCreate(initialization_task, "INIT", 2048, NULL, 2, NULL) != pdPASS) { + PRINTF("Failed to create initialization task...\r\n"); + + goto dead_loop; + } + + vTaskStartScheduler(); + +dead_loop: + /* We should never reach here. */ + for (;;) { __WFI(); } +} + +static void initialization_task(void *params) { + PRINTF("Initialization task running...\r\n"); + + /* Do initialization stuff here, since the scheduler is running now. */ + + vTaskDelete(NULL); } \ No newline at end of file