diff --git a/.gitmodules b/.gitmodules index 01dbdb2..f491663 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "SDK"] path = SDK url = https://git.minori.work/Embedded_SDK/MCUXpresso_LPC55S69.git +[submodule "lib/lcd"] + path = lib/lcd + url = https://git.minori.work/Embedded_Drivers/epd-spi.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 96c4342..4ca3e96 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,6 @@ cmake_minimum_required(VERSION 3.10) -project(lpcxpresso_55s69_template) +project(lpcxpresso_55s69_lcd) enable_language(CXX) enable_language(ASM) @@ -60,6 +60,7 @@ set(TARGET_SOURCES "board/clock_config.c" "board/peripherals.c" "board/pin_mux.c" + "src/epd_impl.c" "src/main.c" ) @@ -88,6 +89,7 @@ set(TARGET_LIBS "c" "m" "nosys" + "epd-spi" ) # Shared library and linker script search paths @@ -116,6 +118,7 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${TARGET_CFLAGS_HARDWARE} -Wall - set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} ${CMAKE_C_FLAGS} -x assembler-with-cpp") set(CMAKE_EXE_LINKER_FLAGS "-specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments") +add_subdirectory(lib/lcd) # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) diff --git a/LPCXpresso55S69.mex b/LPCXpresso55S69.mex index d0fd199..186d25d 100644 --- a/LPCXpresso55S69.mex +++ b/LPCXpresso55S69.mex @@ -1,5 +1,5 @@ - + LPC55S69 LPC55S69JBD100 @@ -20,13 +20,18 @@ false - + - 11.0.1 + 12.0.0 + + + + + @@ -516,15 +521,63 @@ + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - 11.0.1 + 12.0.0 @@ -541,6 +594,16 @@ true + + + true + + + + + true + + true @@ -573,6 +636,16 @@ true + + + true + + + + + true + + true @@ -630,6 +703,16 @@ true + + + true + + + + + true + + true @@ -693,6 +776,16 @@ true + + + true + + + + + true + + true @@ -720,6 +813,83 @@ + false + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + true @@ -732,18 +902,56 @@ + + + + true + + + + + 2.1.0 + + + - 11.0.1 + 12.0.0 - + + + + true + + + + + true + + + + + true + + + + + true + + + + + 0 + + + @@ -790,6 +998,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SDK b/SDK new file mode 160000 index 0000000..4426225 --- /dev/null +++ b/SDK @@ -0,0 +1 @@ +Subproject commit 442622515005ffb9fd32e59d3fbd470f0f67550b diff --git a/board/clock_config.c b/board/clock_config.c index 1595dbb..d589cea 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -17,11 +17,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v9.0 +product: Clocks v10.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 board: LPCXpresso55S69 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ @@ -37,15 +37,13 @@ board: LPCXpresso55S69 /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { - BOARD_BootClockPLL150M(); + BOARD_BootClockPLL150M_PMODSPI(); } /******************************************************************************* @@ -217,7 +215,6 @@ void BOARD_BootClockPLL100M(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockPLL150M -called_from_default_init: true outputs: - {id: System_clock.outFreq, value: 150 MHz} settings: @@ -284,3 +281,89 @@ void BOARD_BootClockPLL150M(void) #endif } +/******************************************************************************* + **************** Configuration BOARD_BootClockPLL150M_PMODSPI ***************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M_PMODSPI +called_from_default_init: true +outputs: +- {id: FXCOM3_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL3_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M_PMODSPI configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M_PMODSPI configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M_PMODSPI(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_PMODSPI_CORE_CLOCK; +#endif +} + diff --git a/board/clock_config.h b/board/clock_config.h index 69a7bc6..b364e3e 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -136,5 +136,31 @@ void BOARD_BootClockPLL150M(void); } #endif /* __cplusplus*/ +/******************************************************************************* + **************** Configuration BOARD_BootClockPLL150M_PMODSPI ***************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M_PMODSPI configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_PMODSPI_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M_PMODSPI configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M_PMODSPI(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + #endif /* _CLOCK_CONFIG_H_ */ diff --git a/board/peripherals.c b/board/peripherals.c index 439049f..acca1aa 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -10,7 +10,7 @@ product: Peripherals v11.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 board: LPCXpresso55S69 functionalGroups: - name: BOARD_InitPeripherals_cm33_core0 @@ -80,12 +80,75 @@ instance: static void NVIC_init(void) { } */ +/*********************************************************************************************************************** + * FLEXCOMM3 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'FLEXCOMM3' +- type: 'flexcomm_spi' +- mode: 'SPI_Polling' +- custom_name_enabled: 'false' +- type_id: 'flexcomm_spi_481dadba00035f986f31ed9ac95af181' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM3' +- config_sets: + - fsl_spi: + - spi_mode: 'kSPI_Master' + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'BOARD_BootClockPLL150M_PMODSPI' + - spi_master_config: + - enableLoopback: 'false' + - enableMaster: 'true' + - polarity: 'kSPI_ClockPolarityActiveHigh' + - phase: 'kSPI_ClockPhaseFirstEdge' + - direction: 'kSPI_MsbFirst' + - baudRate_Bps: '16000000' + - dataWidth: 'kSPI_Data8Bits' + - sselNum: 'kSPI_Ssel0' + - sselPol_set: '' + - txWatermark: 'kSPI_TxFifo0' + - rxWatermark: 'kSPI_RxFifo1' + - delayConfig: + - preDelay: '0' + - postDelay: '0' + - frameDelay: '0' + - transferDelay: '0' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const spi_master_config_t FLEXCOMM3_config = { + .enableLoopback = false, + .enableMaster = true, + .polarity = kSPI_ClockPolarityActiveHigh, + .phase = kSPI_ClockPhaseFirstEdge, + .direction = kSPI_MsbFirst, + .baudRate_Bps = 16000000UL, + .dataWidth = kSPI_Data8Bits, + .sselNum = kSPI_Ssel0, + .sselPol = kSPI_SpolActiveAllLow, + .txWatermark = kSPI_TxFifo0, + .rxWatermark = kSPI_RxFifo1, + .delayConfig = { + .preDelay = 0U, + .postDelay = 0U, + .frameDelay = 0U, + .transferDelay = 0U + } +}; + +static void FLEXCOMM3_init(void) { + /* Initialization function */ + SPI_MasterInit(FLEXCOMM3_PERIPHERAL, &FLEXCOMM3_config, FLEXCOMM3_CLOCK_SOURCE); +} + /*********************************************************************************************************************** * Initialization functions **********************************************************************************************************************/ void BOARD_InitPeripherals_cm33_core0(void) { /* Initialize components */ + FLEXCOMM3_init(); } /*********************************************************************************************************************** diff --git a/board/peripherals.h b/board/peripherals.h index 358d8de..32dfb2a 100644 --- a/board/peripherals.h +++ b/board/peripherals.h @@ -10,11 +10,27 @@ * Included files **********************************************************************************************************************/ #include "fsl_common.h" +#include "fsl_spi.h" #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* BOARD_InitPeripherals_cm33_core0 defines for FLEXCOMM3 */ +/* Definition of peripheral ID */ +#define FLEXCOMM3_PERIPHERAL ((SPI_Type *)FLEXCOMM3) +/* Definition of the clock source frequency */ +#define FLEXCOMM3_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const spi_master_config_t FLEXCOMM3_config; + /*********************************************************************************************************************** * Initialization functions **********************************************************************************************************************/ diff --git a/board/pin_mux.c b/board/pin_mux.c index bdfead3..9687c1f 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -7,12 +7,16 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v11.0 +product: Pins v12.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 board: LPCXpresso55S69 +pin_labels: +- {pin_num: '81', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, label: 'U6[11]/P20[5]/FC3_SPI_MISO', identifier: LCD_DC} +- {pin_num: '86', pin_signal: PIO0_4/FC4_SCK/CT_INP12/SCT_GPI4/FC3_CTS_SDA_SSEL0/SECURE_GPIO0_4, label: 'U3[14]/P20[1]/FC3_SPI_SSEL0', identifier: LCD_CS} +- {pin_num: '41', pin_signal: PIO1_22/SD0_CMD/CTIMER2_MAT3/SCT_GPI5/FC4_SSEL3/PLU_OUT4, label: 'P20[4]/PLU_OUT4/GPIO', identifier: LCS_RST;LCD_RST} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -32,6 +36,7 @@ void BOARD_InitBootPins(void) { BOARD_InitDEBUG_UARTPins(); BOARD_InitPins_Core0(); + BOARD_InitPMODPins(); } /* clang-format off */ @@ -845,6 +850,127 @@ void BOARD_InitACCELPins(void) /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); } + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPMODPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '86', peripheral: GPIO, signal: 'PIO0, 4', pin_signal: PIO0_4/FC4_SCK/CT_INP12/SCT_GPI4/FC3_CTS_SDA_SSEL0/SECURE_GPIO0_4, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: '81', peripheral: GPIO, signal: 'PIO0, 2', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: '41', peripheral: GPIO, signal: 'PIO1, 22', pin_signal: PIO1_22/SD0_CMD/CTIMER2_MAT3/SCT_GPI5/FC4_SSEL3/PLU_OUT4, identifier: LCD_RST, direction: OUTPUT, + gpio_init_state: 'true'} + - {pin_num: '83', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3} + - {pin_num: '89', peripheral: FLEXCOMM3, signal: SCK, pin_signal: PIO0_6/FC3_SCK/CT_INP13/CTIMER4_MAT0/SCT_GPI6/SECURE_GPIO0_6} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPMODPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPMODPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t LCD_DC_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_2 (pin 81) */ + GPIO_PinInit(BOARD_INITPMODPINS_LCD_DC_GPIO, BOARD_INITPMODPINS_LCD_DC_PORT, BOARD_INITPMODPINS_LCD_DC_PIN, &LCD_DC_config); + + gpio_pin_config_t LCD_CS_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_4 (pin 86) */ + GPIO_PinInit(BOARD_INITPMODPINS_LCD_CS_GPIO, BOARD_INITPMODPINS_LCD_CS_PORT, BOARD_INITPMODPINS_LCD_CS_PIN, &LCD_CS_config); + + gpio_pin_config_t LCD_RST_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_22 (pin 41) */ + GPIO_PinInit(BOARD_INITPMODPINS_LCD_RST_GPIO, BOARD_INITPMODPINS_LCD_RST_PORT, BOARD_INITPMODPINS_LCD_RST_PIN, &LCD_RST_config); + + IOCON->PIO[0][2] = ((IOCON->PIO[0][2] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT02 (pin 81) is configured as PIO0_2. */ + | IOCON_PIO_FUNC(PIO0_2_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_2_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][3] = ((IOCON->PIO[0][3] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT03 (pin 83) is configured as FC3_RXD_SDA_MOSI_DATA. */ + | IOCON_PIO_FUNC(PIO0_3_FUNC_ALT1) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_3_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][4] = ((IOCON->PIO[0][4] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT04 (pin 86) is configured as PIO0_4. */ + | IOCON_PIO_FUNC(PIO0_4_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_4_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][6] = ((IOCON->PIO[0][6] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT06 (pin 89) is configured as FC3_SCK. */ + | IOCON_PIO_FUNC(PIO0_6_FUNC_ALT1) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_6_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][22] = ((IOCON->PIO[1][22] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT122 (pin 41) is configured as PIO1_22. */ + | IOCON_PIO_FUNC(PIO1_22_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_22_DIGIMODE_DIGITAL)); +} /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/board/pin_mux.h b/board/pin_mux.h index 1678fa9..8af90d0 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -435,6 +435,76 @@ void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_2_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO0_2_FUNC_ALT0 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_3_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO0_3_FUNC_ALT1 0x01u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_4_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO0_4_FUNC_ALT0 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_6_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO0_6_FUNC_ALT1 0x01u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_22_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_22_FUNC_ALT0 0x00u + +/*! @name PIO0_4 (number 86), U3[14]/P20[1]/FC3_SPI_SSEL0 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPMODPINS_LCD_CS_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_CS_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */ +#define BOARD_INITPMODPINS_LCD_CS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_CS_PIN 4U /*!<@brief PORT pin number */ +#define BOARD_INITPMODPINS_LCD_CS_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_2 (number 81), U6[11]/P20[5]/FC3_SPI_MISO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPMODPINS_LCD_DC_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_DC_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */ +#define BOARD_INITPMODPINS_LCD_DC_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_DC_PIN 2U /*!<@brief PORT pin number */ +#define BOARD_INITPMODPINS_LCD_DC_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_22 (number 41), P20[4]/PLU_OUT4/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPMODPINS_LCD_RST_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_RST_GPIO_PIN_MASK (1U << 22U) /*!<@brief GPIO pin mask */ +#define BOARD_INITPMODPINS_LCD_RST_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITPMODPINS_LCD_RST_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITPMODPINS_LCD_RST_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPMODPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + #if defined(__cplusplus) } #endif diff --git a/lib/lcd b/lib/lcd new file mode 160000 index 0000000..40bef05 --- /dev/null +++ b/lib/lcd @@ -0,0 +1 @@ +Subproject commit 40bef05c632b9e9699b827cf6fded712325bfdec diff --git a/src/epd_impl.c b/src/epd_impl.c new file mode 100644 index 0000000..92e4171 --- /dev/null +++ b/src/epd_impl.c @@ -0,0 +1,73 @@ +#include "epd-spi/panel/lcd_zjy350c4001.h" +#include "fsl_flexcomm.h" +#include "fsl_gpio.h" +#include "fsl_spi.h" +#include "pin_mux.h" + +#define DMA_TRANSFER 0 + +#define LCD_SPI SPI3 +#define SET_GPIO(x, v) \ + GPIO_PinWrite(BOARD_INITPMODPINS_LCD_##x##_GPIO, BOARD_INITPMODPINS_LCD_##x##_PORT, \ + BOARD_INITPMODPINS_LCD_##x##_PIN, v) + +void lcd_impl_init(void) { + SET_GPIO(CS, 1U); + SET_GPIO(DC, 1U); + SET_GPIO(RST, 1U); +} + +epd_ret_t lcd_impl_write_cmd(void *handle, uint8_t *cmd, uint32_t len) { + SET_GPIO(DC, 0U); + SET_GPIO(CS, 0U); + + spi_transfer_t xfer = { + .txData = cmd, + .rxData = NULL, + .dataSize = 1U, + .configFlags = kSPI_FrameAssert, + }; + + SPI_MasterTransferBlocking(LCD_SPI, &xfer); + + if (len > 1) { + SET_GPIO(DC, 1U); + + xfer.txData = &cmd[1]; + xfer.dataSize = len - 1; + + SPI_MasterTransferBlocking(LCD_SPI, &xfer); + } + + SET_GPIO(CS, 1U); + + return EPD_OK; +} + +epd_ret_t lcd_impl_write_data(void *handle, uint8_t *data, uint32_t len) { + SET_GPIO(DC, 1U); + SET_GPIO(CS, 0U); + + spi_transfer_t xfer = { + .txData = data, + .rxData = NULL, + .dataSize = len, + .configFlags = kSPI_FrameAssert, + }; + + SPI_MasterTransferBlocking(LCD_SPI, &xfer); + + SET_GPIO(CS, 1U); + + return EPD_OK; +} + +epd_ret_t lcd_impl_reset(void *handle) { + SET_GPIO(RST, 0U); + SDK_DelayAtLeastUs(50 * 1000, CLOCK_GetCoreSysClkFreq()); + + SET_GPIO(RST, 1U); + SDK_DelayAtLeastUs(50 * 1000, CLOCK_GetCoreSysClkFreq()); + + return EPD_OK; +} diff --git a/src/main.c b/src/main.c index 21245ea..cde3cca 100644 --- a/src/main.c +++ b/src/main.c @@ -3,8 +3,35 @@ #include "peripherals.h" #include "pin_mux.h" +/* DebugConsole */ #include "fsl_debug_console.h" +/* LCD */ +#include "epd-spi/panel/lcd_zjy350c4001.h" + +void lcd_impl_init(void); +epd_ret_t lcd_impl_write_cmd(void *handle, uint8_t *cmd, uint32_t len); +epd_ret_t lcd_impl_write_data(void *handle, uint8_t *data, uint32_t len); +epd_ret_t lcd_impl_reset(void *handle); + +static lcd_zjy350c4001_t s_lcd = { + .user_data = NULL, + .config = + { + .direction = LCD_ZJY350C4001_DIR_0, + .pix_fmt = LCD_ZJY350C4001_RGB565, + .bgr_mode = 1, + .inversion = 1, + }, + .cb = + { + .backlight_cb = NULL, + .write_command_cb = lcd_impl_write_cmd, + .write_data_cb = lcd_impl_write_data, + .reset_cb = lcd_impl_reset, + }, +}; + int main(void) { BOARD_InitBootPins(); BOARD_BootClockFROHF96M(); @@ -14,7 +41,11 @@ int main(void) { PRINTF("Hello world!!\r\n"); - for(;;) { + lcd_impl_init(); + + lcd_zjy350c4001_init(&s_lcd); + + for (;;) { __WFI(); } } \ No newline at end of file