diff --git a/.gitmodules b/.gitmodules index 01dbdb2..73435ed 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "SDK"] path = SDK url = https://git.minori.work/Embedded_SDK/MCUXpresso_LPC55S69.git +[submodule "lib/mruby"] + path = lib/mruby + url = https://git.minori.work/Embedded_Projects/MRuby_MCUXpresso.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 0251e8f..d32a982 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -6,7 +6,7 @@ enable_language(CXX) enable_language(ASM) # Different linker scripts -set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/LPC55S69/gcc/LPC55S69_cm33_core0_flash.ld") +set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/app_flash.ld") set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/SDK/devices/LPC55S69/gcc/LPC55S69_cm33_core0_ram.ld") set(TARGET_SOURCES @@ -85,6 +85,7 @@ set(TARGET_C_INCLUDES # Shared libraries linked with application set(TARGET_LIBS + "mruby_mcux" "c" "m" "nosys" @@ -92,7 +93,7 @@ set(TARGET_LIBS # Shared library and linker script search paths set(TARGET_LIB_DIRECTORIES - + "${CMAKE_SOURCE_DIR}/SDK/devices/LPC55S69/gcc" ) # Conditional flags @@ -113,6 +114,9 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp") set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections") +set(MRUBY_MCUX_TARGET "lpc55s69") +add_subdirectory(lib/mruby) + # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) include_directories(${TARGET_C_INCLUDES}) diff --git a/LPCXpresso55S69.mex b/LPCXpresso55S69.mex index 5bc9c26..e307a5c 100644 --- a/LPCXpresso55S69.mex +++ b/LPCXpresso55S69.mex @@ -20,13 +20,13 @@ false - + - 12.0.0 + 13.0.1 @@ -518,13 +518,13 @@ - + - 12.0.0 + 13.0.1 @@ -771,13 +771,13 @@ - + - 12.0.0 + 13.0.1 @@ -789,7 +789,7 @@ - + diff --git a/SDK b/SDK new file mode 160000 index 0000000..3969019 --- /dev/null +++ b/SDK @@ -0,0 +1 @@ +Subproject commit 3969019d6a43b0b76c8227cbd5b9640047c41c0d diff --git a/app_flash.ld b/app_flash.ld new file mode 100644 index 0000000..15400e4 --- /dev/null +++ b/app_flash.ld @@ -0,0 +1,4 @@ +__stack_size__ = 0x4000; +__heap_size__ = 0x8000; + +INCLUDE LPC55S69_cm33_core0_flash.ld \ No newline at end of file diff --git a/board/clock_config.c b/board/clock_config.c index 5f21ddd..31e680f 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -17,11 +17,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v10.0 +product: Clocks v11.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 13.0.1 board: LPCXpresso55S69 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ diff --git a/board/clock_config.h b/board/clock_config.h index 69a7bc6..1d765ee 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -41,6 +41,42 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL + /******************************************************************************* * API for BOARD_BootClockFRO12M configuration ******************************************************************************/ @@ -67,6 +103,42 @@ void BOARD_BootClockFRO12M(void); #define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK0UL +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL + /******************************************************************************* * API for BOARD_BootClockFROHF96M configuration ******************************************************************************/ @@ -93,6 +165,42 @@ void BOARD_BootClockFROHF96M(void); #define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL + /******************************************************************************* * API for BOARD_BootClockPLL100M configuration ******************************************************************************/ @@ -119,6 +227,42 @@ void BOARD_BootClockPLL100M(void); #define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 150000000UL +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL + /******************************************************************************* * API for BOARD_BootClockPLL150M configuration ******************************************************************************/ diff --git a/board/peripherals.c b/board/peripherals.c index 2628636..ebcd6ea 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -6,11 +6,11 @@ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Peripherals v11.0 +product: Peripherals v12.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 13.0.1 board: LPCXpresso55S69 functionalGroups: - name: BOARD_InitPeripherals_cm33_core0 diff --git a/board/pin_mux.c b/board/pin_mux.c index 1c8f15c..23645fd 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -7,11 +7,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v12.0 +product: Pins v13.0 processor: LPC55S69 package_id: LPC55S69JBD100 mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 13.0.1 board: LPCXpresso55S69 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ diff --git a/lib/mruby b/lib/mruby new file mode 160000 index 0000000..d31acdb --- /dev/null +++ b/lib/mruby @@ -0,0 +1 @@ +Subproject commit d31acdb6fa8e857bb6de4a0bbb630c14dac25e00 diff --git a/src/main.c b/src/main.c index 21245ea..3358c51 100644 --- a/src/main.c +++ b/src/main.c @@ -1,3 +1,5 @@ +#include + #include "board.h" #include "clock_config.h" #include "peripherals.h" @@ -5,6 +7,9 @@ #include "fsl_debug_console.h" +#include "mruby.h" +#include "mruby/compile.h" + int main(void) { BOARD_InitBootPins(); BOARD_BootClockFROHF96M(); @@ -12,7 +17,14 @@ int main(void) { BOARD_InitDebugConsole(); - PRINTF("Hello world!!\r\n"); + mrb_state* mrb = mrb_open(); + mrbc_context *cxt = mrbc_context_new(mrb); + + PRINTF("MRuby Version: %s\r\n", MRUBY_RUBY_VERSION); + + mrbc_cleanup_local_variables(mrb, cxt); + mrbc_context_free(mrb, cxt); + mrb_close(mrb); for(;;) { __WFI();