329 lines
12 KiB
C
329 lines
12 KiB
C
#include <stdio.h>
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/* Board */
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#include "board.h"
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/* SDK drivers */
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#include "fsl_ctimer.h"
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#include "fsl_gpio.h"
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#include "fsl_iocon.h"
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#include "fsl_power.h"
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/* Gem private */
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#include "machine-pwm/src/pwm.h"
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/**
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* LPC55S69 has 5 CTimers, each with 4 Match channels, each channel can route up to 2 pins
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* Total: 40 PWM capable pins (at most)
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* Actual: 30 pins (shared).
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* Match channel 3 is special, normally it will be used as period channel
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* TODO: Find a way to utilize channel 3 as normal PWM outputs
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*/
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#define PWM_IMPL_INST_COUNT 5
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#define PWM_IMPL_INST_CH 4
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/* FIXME: A reasonable clock for PWM resolution, could be determined dynamically. */
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#define PWM_IMPL_REASONABLE_CLK (10000000UL) /* 10MHz */
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#define PWM_IMPL_MR_RL_MASK \
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(CTIMER_MCR_MR0RL_MASK | CTIMER_MCR_MR1RL_MASK | CTIMER_MCR_MR2RL_MASK | CTIMER_MCR_MR3RL_MASK)
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/* Timer channel ID fields */
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#define PWM_IMPL_CT_OFFSET_Pos 0
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#define PWM_IMPL_CT_OFFSET_Msk (1U << PWM_IMPL_CT_OFFSET_Pos)
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#define PWM_IMPL_CT_CH_Pos 1
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#define PWM_IMPL_CT_CH_Msk (3U << PWM_IMPL_CT_CH_Pos)
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#define PWM_IMPL_CT_INST_Pos 3
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#define PWM_IMPL_CT_INST_Msk (0x1FU << PWM_IMPL_CT_INST_Pos)
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#define PWM_IMPL_CT_OFFSET(x) ((x & PWM_IMPL_CT_OFFSET_Msk) >> PWM_IMPL_CT_OFFSET_Pos)
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#define PWM_IMPL_CT_CH(x) ((x & PWM_IMPL_CT_CH_Msk) >> PWM_IMPL_CT_CH_Pos)
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#define PWM_IMPL_CT_INST(x) ((x & PWM_IMPL_CT_INST_Msk) >> PWM_IMPL_CT_INST_Pos)
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/* Pin ID fields */
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#define PWM_IMPL_PIN_ID_Pos 0
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#define PWM_IMPL_PIN_ID_Msk (0x1FU << PWM_IMPL_PIN_ID_Pos)
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#define PWM_IMPL_PIN_PORT_Pos 5
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#define PWM_IMPL_PIN_PORT_Msk (7U << PWM_IMPL_PIN_PORT_Pos)
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#define PWM_IMPL_PIN_FUNC_Pos 8
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#define PWM_IMPL_PIN_FUNC_Msk (0x0FU << PWM_IMPL_PIN_FUNC_Pos)
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#define PWM_IMPL_PIN_VALID_Pos 31
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#define PWM_IMPL_PIN_VALID_Msk (1U << PWM_IMPL_PIN_VALID_Pos)
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#define PWM_IMPL_PIN_PORT(x) ((x & PWM_IMPL_PIN_PORT_Msk) >> PWM_IMPL_PIN_PORT_Pos)
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#define PWM_IMPL_PIN_ID(x) ((x & PWM_IMPL_PIN_ID_Msk) >> PWM_IMPL_PIN_ID_Pos)
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#define PWM_IMPL_PIN_FUNC(x) ((x & PWM_IMPL_PIN_FUNC_Msk) >> PWM_IMPL_PIN_FUNC_Pos)
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#define PWM_IMPL_PIN_VALID(x) ((x & PWM_IMPL_PIN_VALID_Msk) >> PWM_IMPL_PIN_VALID_Pos)
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#define PWM_IMPL_PIN(port, id, func) \
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(((port << PWM_IMPL_PIN_PORT_Pos) & PWM_IMPL_PIN_PORT_Msk) | ((id << PWM_IMPL_PIN_ID_Pos) & PWM_IMPL_PIN_ID_Msk) | \
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((func << PWM_IMPL_PIN_FUNC_Pos) & PWM_IMPL_PIN_FUNC_Msk) | PWM_IMPL_PIN_VALID_Msk)
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static uint32_t const s_pwm_channel_map[PWM_IMPL_INST_COUNT][PWM_IMPL_INST_CH * 2] = {
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{
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PWM_IMPL_PIN(0, 0, 3), PWM_IMPL_PIN(0, 30, 3), // CT0MAT0, Channel ID: 0, 1
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PWM_IMPL_PIN(0, 3, 2), PWM_IMPL_PIN(0, 31, 3), // CT0MAT1, Channel ID: 2, 3
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PWM_IMPL_PIN(0, 19, 3), PWM_IMPL_PIN(1, 31, 3), // CT0MAT2, Channel ID: 4, 5
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0x00000000UL, 0x00000000UL, // CT0MAT3, Channel ID: 6, 7
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},
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{
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PWM_IMPL_PIN(0, 18, 3), PWM_IMPL_PIN(1, 10, 3), // CT1MAT0, Channel ID: 8, 9
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PWM_IMPL_PIN(0, 20, 2), PWM_IMPL_PIN(1, 12, 3), // CT1MAT1, Channel ID: 10, 11
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PWM_IMPL_PIN(0, 23, 2), PWM_IMPL_PIN(1, 14, 3), // CT1MAT2, Channel ID: 12, 13
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0x00000000UL, 0x00000000UL, // CT1MAT3, Channel ID: 14, 15
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},
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{
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PWM_IMPL_PIN(0, 10, 3), PWM_IMPL_PIN(1, 5, 3), // CT2MAT0, Channel ID: 16, 17
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PWM_IMPL_PIN(1, 4, 3), PWM_IMPL_PIN(1, 6, 3), // CT2MAT1, Channel ID: 18, 19
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PWM_IMPL_PIN(0, 11, 2), PWM_IMPL_PIN(1, 7, 3), // CT2MAT2, Channel ID: 20, 21
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0x00000000UL, 0x00000000UL, // CT2MAT3, Channel ID: 22, 23
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},
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{
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PWM_IMPL_PIN(0, 5, 3), 0x00000000UL, // CT3MAT0, Channel ID: 24, 25
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PWM_IMPL_PIN(1, 19, 3), 0x00000000UL, // CT3MAT1, Channel ID: 26, 27
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PWM_IMPL_PIN(0, 27, 3), PWM_IMPL_PIN(1, 21, 3), // CT3MAT2, Channel ID: 28, 29
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0x00000000UL, 0x00000000UL, // CT3MAT3, Channel ID: 30, 31
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},
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{
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PWM_IMPL_PIN(0, 6, 3), 0x00000000UL, // CT4MAT0, Channel ID: 32, 33
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0x00000000UL, 0x00000000UL, // CT4MAT1, Channel ID: 34, 35
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0x00000000UL, 0x00000000UL, // CT4MAT2, Channel ID: 36, 37
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0x00000000UL, 0x00000000UL, // CT4MAT3, Channel ID: 38, 39
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},
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};
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static clock_attach_id_t const s_pwm_clk_attach_list[] = {
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kMAIN_CLK_to_CTIMER0, kMAIN_CLK_to_CTIMER1, kMAIN_CLK_to_CTIMER2, kMAIN_CLK_to_CTIMER3, kMAIN_CLK_to_CTIMER4,
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};
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static CTIMER_Type *const s_pwm_ct_list[] = {
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CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4,
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};
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static IRQn_Type const s_pwm_irq_list[] = {
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CTIMER0_IRQn,
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CTIMER1_IRQn,
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CTIMER2_IRQn,
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CTIMER3_IRQn,
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};
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static bool mrb_machine_pwm_ctimer_in_use(uint8_t ctimer_id) {
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/* Determine whether CTIMERx is in use:
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* 1: Check module power down status
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* 2: Check module enable and counter running status
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* 3: Check MATCH output settings and enable status (by MATCH action)
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*/
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clock_attach_id_t ct_att_id = s_pwm_clk_attach_list[ctimer_id];
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const CTIMER_Type *ct_inst = s_pwm_ct_list[ctimer_id];
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/* Check if the clock is configured by us */
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if (ct_att_id != CLOCK_GetClockAttachId(ct_att_id)) {
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return false;
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}
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/* Check if this CTIMER is enabled */
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if ((ct_inst->TCR & CTIMER_TCR_CEN_MASK) == 0) {
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return false;
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}
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/* Check if Match channel 3 is configured as reset. */
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/* TODO: Find a way to utilize channel 3 as normal PWM outputs */
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if ((ct_inst->MCR & CTIMER_MCR_MR3R_MASK) == 0) {
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return false;
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}
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/* Check if any PWM outputs are enabled */
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/* TODO: Find a way to utilize channel 3 as normal PWM outputs */
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if ((ct_inst->PWMC & (CTIMER_PWMC_PWMEN0_MASK | CTIMER_PWMC_PWMEN1_MASK | CTIMER_PWMC_PWMEN2_MASK)) == 0) {
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return false;
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}
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return true;
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}
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int mrb_machine_pwm_impl_init(uint32_t channel, machine_pwm_config_t *config) {
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uint8_t ctimer_id = PWM_IMPL_CT_INST(channel);
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uint8_t ctimer_mat = PWM_IMPL_CT_CH(channel);
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uint8_t ctimer_off = PWM_IMPL_CT_OFFSET(channel);
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/* Sanity checks */
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if ((ctimer_id >= PWM_IMPL_INST_COUNT) || (ctimer_mat >= PWM_IMPL_INST_CH)) {
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return -1;
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}
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uint32_t ctimer_pin = s_pwm_channel_map[ctimer_id][ctimer_mat * 2 + ctimer_off];
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CTIMER_Type *ctimer_inst = s_pwm_ct_list[ctimer_id];
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/* Check valid bit to see if there really is a pin for this channel */
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if (PWM_IMPL_PIN_VALID(ctimer_pin) == 0) {
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return -2;
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}
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if (!mrb_machine_pwm_ctimer_in_use(ctimer_id)) {
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/* CTimer is not in use, initialize timer */
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/* Disable interrupt for CTx */
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DisableIRQ(s_pwm_irq_list[ctimer_id]);
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CLOCK_AttachClk(s_pwm_clk_attach_list[ctimer_id]);
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ctimer_config_t ct_cfg;
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CTIMER_GetDefaultConfig(&ct_cfg);
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ct_cfg.prescale = CLOCK_GetCTimerClkFreq(ctimer_id) / PWM_IMPL_REASONABLE_CLK;
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CTIMER_Init(ctimer_inst, &ct_cfg);
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CTIMER_EnableResetMatchChannel(ctimer_inst, kCTIMER_Match_3, true);
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ctimer_inst->MR[3] = 0x00000000UL;
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ctimer_inst->MCR |= (CTIMER_MCR_MR3RL_MASK);
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CTIMER_StartTimer(ctimer_inst);
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}
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/* Calculate new reload value */
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uint32_t rl_match_old = ctimer_inst->MR[3];
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uint32_t rl_match_new = (PWM_IMPL_REASONABLE_CLK / config->freq);
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uint32_t ch_enabled = ctimer_inst->MCR & PWM_IMPL_MR_RL_MASK;
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/* Do not sync channels while we are fiddling with shadow registers */
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ctimer_inst->MCR &= ~(PWM_IMPL_MR_RL_MASK);
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/* Update period channel */
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ctimer_inst->MSR[3] = rl_match_new;
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/* To disable PWM output: Write MRx to 0xFFFFFFFF, to enable, enable reload from shadow. */
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for (uint8_t i = 0; i < 3; i++) {
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if (ctimer_inst->PWMC & (1 << i)) {
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uint32_t new_duty = (uint32_t)((uint64_t)ctimer_inst->MSR[i] * rl_match_new / rl_match_old);
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ctimer_inst->MSR[i] = new_duty;
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}
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}
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/* New channel */
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ctimer_inst->MSR[ctimer_mat] = rl_match_new - ((config->duty * rl_match_new) / 65536);
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/* Start sync MRx values with shadow registers */
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ctimer_inst->MCR |= ch_enabled | (1U << (CTIMER_MCR_MR0RL_SHIFT + ctimer_mat));
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/* From now on, the pin will be controlled by MATx PWM */
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ctimer_inst->PWMC |= (1 << ctimer_mat);
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/* Function is retrieved from const array. */
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uint32_t iocon_mode = IOCON_PIO_SLEW(0) | IOCON_DIGITAL_EN | IOCON_PIO_FUNC(PWM_IMPL_PIN_FUNC(ctimer_pin));
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/* Setup pin */
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IOCON_PinMuxSet(IOCON, PWM_IMPL_PIN_PORT(ctimer_pin), PWM_IMPL_PIN_ID(ctimer_pin), iocon_mode);
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return 0;
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}
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int mrb_machine_pwm_impl_output_set(uint32_t channel, bool enable) {
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uint8_t ctimer_id = PWM_IMPL_CT_INST(channel);
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uint8_t ctimer_mat = PWM_IMPL_CT_CH(channel);
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uint8_t ctimer_off = PWM_IMPL_CT_OFFSET(channel);
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/* Sanity checks */
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if ((ctimer_id >= PWM_IMPL_INST_COUNT) || (ctimer_mat >= PWM_IMPL_INST_CH)) {
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return -1;
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}
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uint32_t ctimer_pin = s_pwm_channel_map[ctimer_id][ctimer_mat * 2 + ctimer_off];
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CTIMER_Type *ctimer_inst = s_pwm_ct_list[ctimer_id];
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/* Check valid bit to see if there really is a pin for this channel */
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if (PWM_IMPL_PIN_VALID(ctimer_pin) == 0) {
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return -2;
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}
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if (enable) {
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ctimer_inst->MCR |= (1 << (CTIMER_MCR_MR0RL_SHIFT + ctimer_mat));
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} else {
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ctimer_inst->MCR &= ~(1 << (CTIMER_MCR_MR0RL_SHIFT + ctimer_mat));
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ctimer_inst->MR[ctimer_mat] = 0xFFFFFFFFUL;
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}
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return 0;
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}
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bool mrb_machine_pwm_impl_output_get(uint32_t channel) {
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uint8_t ctimer_id = PWM_IMPL_CT_INST(channel);
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uint8_t ctimer_mat = PWM_IMPL_CT_CH(channel);
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uint8_t ctimer_off = PWM_IMPL_CT_OFFSET(channel);
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/* Sanity checks */
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if ((ctimer_id >= PWM_IMPL_INST_COUNT) || (ctimer_mat >= PWM_IMPL_INST_CH)) {
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return false;
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}
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uint32_t ctimer_pin = s_pwm_channel_map[ctimer_id][ctimer_off];
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CTIMER_Type *ctimer_inst = s_pwm_ct_list[ctimer_id];
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/* Check valid bit to see if there really is a pin for this channel */
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if (PWM_IMPL_PIN_VALID(ctimer_pin) == 0) {
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return false;
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}
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if (ctimer_inst->MCR & (1 << (CTIMER_MCR_MR0RL_SHIFT + ctimer_mat))) {
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return true;
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} else {
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return false;
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}
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}
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int mrb_machine_pwm_impl_duty_set(uint32_t channel, uint16_t duty) {
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uint8_t ctimer_id = PWM_IMPL_CT_INST(channel);
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uint8_t ctimer_mat = PWM_IMPL_CT_CH(channel);
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uint8_t ctimer_off = PWM_IMPL_CT_OFFSET(channel);
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/* Sanity checks */
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if ((ctimer_id >= PWM_IMPL_INST_COUNT) || (ctimer_mat >= PWM_IMPL_INST_CH)) {
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return -1;
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}
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uint32_t ctimer_pin = s_pwm_channel_map[ctimer_id][ctimer_off];
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CTIMER_Type *ctimer_inst = s_pwm_ct_list[ctimer_id];
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/* Check valid bit to see if there really is a pin for this channel */
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if (PWM_IMPL_PIN_VALID(ctimer_pin) == 0) {
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return -2;
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}
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ctimer_inst->MSR[ctimer_mat] = ctimer_inst->MSR[3] - ((uint32_t)duty * ctimer_inst->MSR[3] / 65536);
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return 0;
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}
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uint16_t mrb_machine_pwm_impl_duty_get(uint32_t channel) {
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uint8_t ctimer_id = PWM_IMPL_CT_INST(channel);
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uint8_t ctimer_mat = PWM_IMPL_CT_CH(channel);
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uint8_t ctimer_off = PWM_IMPL_CT_OFFSET(channel);
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/* Sanity checks */
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if ((ctimer_id >= PWM_IMPL_INST_COUNT) || (ctimer_mat >= PWM_IMPL_INST_CH)) {
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return 0;
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}
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uint32_t ctimer_pin = s_pwm_channel_map[ctimer_id][ctimer_off];
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CTIMER_Type *ctimer_inst = s_pwm_ct_list[ctimer_id];
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/* Check valid bit to see if there really is a pin for this channel */
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if (PWM_IMPL_PIN_VALID(ctimer_pin) == 0) {
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return 0;
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}
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uint16_t duty = ctimer_inst->MSR[ctimer_mat] * 65536 / ctimer_inst->MSR[3];
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return duty;
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} |