2022-04-08 17:19:15 +00:00
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to set up clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Set up wait states of the flash.
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*
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* 3. Set up all dividers.
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*
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* 4. Set up all selectors to provide selected clocks.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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2022-12-22 14:33:40 +00:00
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product: Clocks v10.0
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2022-04-08 17:19:15 +00:00
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processor: LPC55S69
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package_id: LPC55S69JBD100
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mcu_data: ksdk2_0
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2022-12-22 14:33:40 +00:00
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processor_version: 12.0.0
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2022-04-08 17:19:15 +00:00
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board: LPCXpresso55S69
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: System_clock.outFreq, value: 12 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF96M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF96M
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outputs:
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- {id: System_clock.outFreq, value: 96 MHz}
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settings:
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- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
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sources:
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- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF96M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL100M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL100M
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outputs:
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- {id: System_clock.outFreq, value: 100 MHz}
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settings:
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- {id: PLL0_Mode, value: Normal}
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- {id: ENABLE_CLKIN_ENA, value: Enabled}
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- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
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- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
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- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
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- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
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- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
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sources:
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- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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void BOARD_BootClockPLL100M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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/*!< Configure XTAL32M */
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POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
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POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
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CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
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ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
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POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
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POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
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POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
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const pll_setup_t pll0Setup = {
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.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
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.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
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.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
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.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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.pllRate = 100000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL150M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL150M
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called_from_default_init: true
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outputs:
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- {id: System_clock.outFreq, value: 150 MHz}
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settings:
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- {id: PLL0_Mode, value: Normal}
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- {id: ENABLE_CLKIN_ENA, value: Enabled}
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- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
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- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
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- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
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- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
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- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
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sources:
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- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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void BOARD_BootClockPLL150M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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/*!< Configure XTAL32M */
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POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
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POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
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CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
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ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
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POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
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POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
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POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
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const pll_setup_t pll0Setup = {
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.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
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.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
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.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
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.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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.pllRate = 150000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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#endif
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}
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