diff --git a/CMakeLists.txt b/CMakeLists.txt index 4baa9ce..474f177 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -102,13 +102,17 @@ set(TARGET_SOURCES set(TARGET_C_DEFINES "CPU_MIMXRT1052DVL6B" "MCUXPRESSO_SDK" + "PRINTF_ADVANCED_ENABLE=1" + "PRINTF_FLOAT_ENABLE=1" "SERIAL_PORT_TYPE_UART" "__STARTUP_CLEAR_BSS" "__STARTUP_INITIALIZE_NONCACHEDATA" ) set(TARGET_C_DEFINES_XIP + "SKIP_SYSCLK_INIT" "XIP_BOOT_HEADER_ENABLE=1" + "XIP_BOOT_HEADER_DCD_ENABLE=1" "XIP_EXTERNAL_FLASH=1" ) @@ -137,9 +141,6 @@ set(TARGET_LIB_DIRECTORIES ) -# Device specific settings, goes to CFLAGS and LDFLAGS -set(TARGET_CFLAGS_HARDWARE "-mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard") - # Conditional flags # DEBUG set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0 -g") @@ -153,10 +154,10 @@ set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto") set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto") # Final compiler flags -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_CFLAGS_HARDWARE} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${TARGET_CFLAGS_HARDWARE} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections") -set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} ${CMAKE_C_FLAGS} -x assembler-with-cpp") -set(CMAKE_EXE_LINKER_FLAGS "-specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections") +set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections") # Shared sources, includes and definitions add_compile_definitions(${TARGET_C_DEFINES}) @@ -183,6 +184,11 @@ add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH.hex" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.elf" ) add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.hex") +if(DEFINED TARGET_TOOLCHAIN_SIZE) +add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD + COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH.elf" +) +endif() # Create ELF add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${TARGET_SOURCES}) @@ -198,3 +204,8 @@ add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex" DEPENDS "${CMAKE_PROJECT_NAME}_RAM.elf" ) add_custom_target("${CMAKE_PROJECT_NAME}_RAM_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_RAM.hex") +if(DEFINED TARGET_TOOLCHAIN_SIZE) +add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_RAM.elf" POST_BUILD + COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_RAM.elf" +) +endif() diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex index 9549be6..5d18086 100644 --- a/MIMXRT1052xxxxB.mex +++ b/MIMXRT1052xxxxB.mex @@ -1,5 +1,5 @@ - + MIMXRT1052xxxxB MIMXRT1052DVL6B @@ -23,7 +23,7 @@ - 12.0.0 + 12.0.1 @@ -159,45 +159,320 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -411,12 +686,54 @@ - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -502,7 +819,7 @@ - 12.0.0 + 12.0.1 @@ -580,12 +897,10 @@ - - @@ -597,7 +912,7 @@ - false + true @@ -664,15 +979,12 @@ - - - - + @@ -681,7 +993,7 @@ - true + false @@ -766,14 +1078,143 @@ - 12.0.0 + 12.0.1 c_array - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -783,7 +1224,7 @@ - 12.0.0 + 12.0.1 diff --git a/SDK b/SDK index f208e92..ded8674 160000 --- a/SDK +++ b/SDK @@ -1 +1 @@ -Subproject commit f208e9228edc85ff9b477a8589b99453bb621c0b +Subproject commit ded867438906eef783e00cf1effe5328c658cfc3 diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake index ab16b40..a9ef74e 100644 --- a/arm-none-eabi.cmake +++ b/arm-none-eabi.cmake @@ -1,10 +1,17 @@ -set(CMAKE_C_COMPILER arm-none-eabi-gcc) -set(CMAKE_CXX_COMPILER arm-none-eabi-g++) - -# Make CMake happy about those compilers -set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") - # Poor old Windows... if(WIN32) set(CMAKE_SYSTEM_NAME "Generic") -endif() \ No newline at end of file +endif() + +set(CMAKE_C_COMPILER arm-none-eabi-gcc) +set(CMAKE_CXX_COMPILER arm-none-eabi-g++) + +# Optionally set size binary name, for elf section size reporting. +set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size) + +set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16") +set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16") +set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments") + +# Make CMake happy about those compilers +set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") diff --git a/board/clock_config.c b/board/clock_config.c index 211269f..b6e061a 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -19,7 +19,7 @@ product: Clocks v10.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 12.0.1 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -38,7 +38,7 @@ processor_version: 12.0.0 ******************************************************************************/ void BOARD_InitBootClocks(void) { - Board_BootClockPLL480MHz(); + Board_BootClockPLL600MHz(); } /******************************************************************************* @@ -47,6 +47,7 @@ void BOARD_InitBootClocks(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: Board_BootClockPLL600MHz +called_from_default_init: true outputs: - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} @@ -85,12 +86,10 @@ outputs: - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '1'} - {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '30'} - {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} -- {id: CCM.SEMC_PODF.scale, value: '3', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} @@ -437,7 +436,6 @@ void Board_BootClockPLL600MHz(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: Board_BootClockPLL480MHz -called_from_default_init: true outputs: - {id: AHB_CLK_ROOT.outFreq, value: 480 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} @@ -476,15 +474,12 @@ outputs: - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '1'} - {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '30'} - {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} -- {id: CCM.SEMC_PODF.scale, value: '3', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40'} - {id: CCM_ANALOG.PLL2.denom, value: '1'} - {id: CCM_ANALOG.PLL2.num, value: '0'} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} diff --git a/board/dcd.c b/board/dcd.c index d3bf9dc..3b3c654 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -24,7 +24,7 @@ product: DCDx v3.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 12.0.1 output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ @@ -33,9 +33,269 @@ const uint8_t dcd_data[] = { /* Tag */ 0xD2, /* Image Length */ - 0x00, 0x04, + 0x04, 0x08, /* Version */ - 0x41 + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-112, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x84, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4, comment: 'PLL2: 528MHz, ON' */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4, comment: 'SEMC: 133MHz, FlexSPI: 133MHz' */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40, + /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.91, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.92, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.94, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.98, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.99, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.100, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.101, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.102, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.103, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.104, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.105, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.106, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.107, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.108, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.109, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.110, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.111, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ diff --git a/board/peripherals.c b/board/peripherals.c index 2007c30..95cc2f5 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -10,7 +10,7 @@ product: Peripherals v11.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 12.0.1 functionalGroups: - name: BOARD_InitPeripherals UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830 diff --git a/board/pin_mux.c b/board/pin_mux.c index 2395fc1..4759ede 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -10,7 +10,7 @@ product: Pins v12.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 12.0.0 +processor_version: 12.0.1 pin_labels: - {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B} - {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G} @@ -140,45 +140,47 @@ void BOARD_InitLEDPins(void) { BOARD_InitSEMCPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00} - - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01} - - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02} - - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03} - - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04} - - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05} - - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06} - - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07} - - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30} - - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31} - - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32} - - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33} - - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35} - - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34} - - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36} - - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37} - - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09} - - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10} - - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11} - - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12} - - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13} - - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14} - - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15} - - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16} - - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17} - - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18} - - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23} - - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19} - - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20} - - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21} - - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22} - - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08} - - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38} - - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26} - - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27} - - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29} - - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25} - - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24} - - {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39} + - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00, hysteresis_enable: Enable, pull_keeper_select: Keeper, speed: MHZ_200, drive_strength: R0_7, + slew_rate: Fast} + - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27, hysteresis_enable: Enable, pull_keeper_select: Keeper, speed: MHZ_200, drive_strength: R0_7, + slew_rate: Fast} + - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -294,6 +296,109 @@ void BOARD_InitSEMCPins(void) { #endif IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U); +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0x0110F9U); +#endif + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0x0110F9U); +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0x0110F9U); +#endif + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0x0110F9U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0x0110F9U); } @@ -448,12 +553,12 @@ void BOARD_InitSDPins(void) { BOARD_InitFlexSPIPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} - - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} - - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} - - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} - - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} - - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -496,6 +601,36 @@ void BOARD_InitFlexSPIPins(void) { #else IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); #endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x0110F9U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0x0110F9U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x0110F9U); +#endif }