From 733eaad9f8d64111e33cfda24d8cfa109ae64f07 Mon Sep 17 00:00:00 2001 From: imi415 Date: Fri, 26 Aug 2022 23:34:28 +0800 Subject: [PATCH] Updated clock options and LED GPIO groups. --- MIMXRT1052xxxxB.mex | 203 ++++++-- board/board.c | 200 ------- board/board.h | 83 +-- board/clock_config.c | 1181 ++++++++++++++++++++++++++++-------------- board/clock_config.h | 305 +++++++---- board/dcd.c | 2 +- board/peripherals.c | 2 +- board/pin_mux.c | 53 +- board/pin_mux.h | 63 ++- src/main.c | 6 +- 10 files changed, 1205 insertions(+), 893 deletions(-) diff --git a/MIMXRT1052xxxxB.mex b/MIMXRT1052xxxxB.mex index e71b6b5..ade940d 100644 --- a/MIMXRT1052xxxxB.mex +++ b/MIMXRT1052xxxxB.mex @@ -1,5 +1,5 @@ - + MIMXRT1052xxxxB MIMXRT1052DVL6B @@ -17,22 +17,22 @@ false - + - 11.0.1 - + 12.0.0 + - + Configures pin routing and optionally pin electrical features. true @@ -40,22 +40,17 @@ true - + true - + true - - - true - - - + true @@ -64,6 +59,33 @@ + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + @@ -88,45 +110,45 @@ - + - 11.0.1 + 12.0.0 - + - + true - + INPUT - + true - + OUTPUT - + true - + true @@ -134,7 +156,7 @@ - + @@ -143,16 +165,16 @@ - - - - + + + + - - + + - + @@ -164,39 +186,53 @@ - + - + - - + + + + + + + + + + + + + + + + false - + - + true - + INPUT - + true - + OUTPUT @@ -204,7 +240,7 @@ - + @@ -216,11 +252,11 @@ - + - + @@ -245,12 +281,12 @@ - + - + @@ -261,6 +297,81 @@ true + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + @@ -269,7 +380,7 @@ - 11.0.1 + 12.0.0 c_array @@ -286,7 +397,7 @@ - 11.0.1 + 12.0.0 diff --git a/board/board.c b/board/board.c index 1330b5f..4a5d727 100644 --- a/board/board.c +++ b/board/board.c @@ -8,9 +8,6 @@ #include "fsl_common.h" #include "fsl_debug_console.h" #include "board.h" -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -#include "fsl_lpi2c.h" -#endif /* SDK_I2C_BASED_COMPONENT_USED */ #include "fsl_iomuxc.h" /******************************************************************************* * Variables @@ -47,203 +44,6 @@ void BOARD_InitDebugConsole(void) DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); } -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) -{ - lpi2c_master_config_t lpi2cConfig = {0}; - - /* - * lpi2cConfig.debugEnable = false; - * lpi2cConfig.ignoreAck = false; - * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; - * lpi2cConfig.baudRate_Hz = 100000U; - * lpi2cConfig.busIdleTimeout_ns = 0; - * lpi2cConfig.pinLowTimeout_ns = 0; - * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; - * lpi2cConfig.sclGlitchFilterWidth_ns = 0; - */ - LPI2C_MasterGetDefaultConfig(&lpi2cConfig); - LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); -} - -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Read; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize) -{ - status_t status; - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = NULL; - xfer.dataSize = 0; - - status = LPI2C_MasterTransferBlocking(base, &xfer); - - if (kStatus_Success == status) - { - xfer.subaddressSize = 0; - xfer.direction = kLPI2C_Read; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - status = LPI2C_MasterTransferBlocking(base, &xfer); - } - - return status; -} - -void BOARD_Accel_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ); -} - -status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff) -{ - uint8_t data = (uint8_t)txBuff; - - return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1); -} - -status_t BOARD_Accel_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize); -} - -void BOARD_Codec_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); -} - -status_t BOARD_Codec_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Codec_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); -} - -void BOARD_Camera_I2C_Init(void) -{ - CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT); - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER); - BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ); -} - -status_t BOARD_Camera_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Camera_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, - rxBuffSize); -} - -status_t BOARD_Camera_I2C_SendSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Camera_I2C_ReceiveSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, - rxBuffSize); -} - -status_t BOARD_Touch_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Touch_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); -} -#endif /* SDK_I2C_BASED_COMPONENT_USED */ - /* MPU configuration. */ void BOARD_ConfigMPU(void) { diff --git a/board/board.h b/board/board.h index 1c28655..2bc096f 100644 --- a/board/board.h +++ b/board/board.h @@ -17,7 +17,7 @@ * Definitions ******************************************************************************/ /*! @brief The board name */ -#define BOARD_NAME "IMXRT1050-EVKB" +#define BOARD_NAME "LQ-RT1052SYS-VA1" /* The UART to use for debug messages. */ #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart @@ -75,26 +75,8 @@ #define BOARD_USB_PHY_TXCAL45DP (0x06U) #define BOARD_USB_PHY_TXCAL45DM (0x06U) -#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn) -#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn) -#define BOARD_ARDUINO_I2C_INDEX (1) - #define BOARD_HAS_SDCARD (1U) -/* @Brief Board accelerator sensor configuration */ -#define BOARD_ACCEL_I2C_BASEADDR LPI2C1 -/* Select USB1 PLL (480 MHz) as LPI2C's clock source */ -#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U) -/* Clock divider for LPI2C clock source */ -#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U) -#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U)) - -#define BOARD_CODEC_I2C_BASEADDR LPI2C1 -#define BOARD_CODEC_I2C_INSTANCE 1U -#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U) -#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U) -#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U) - /* @Brief Board CAMERA configuration */ #define BOARD_CAMERA_I2C_BASEADDR LPI2C1 #define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U) @@ -109,19 +91,6 @@ #define BOARD_CAMERA_PWDN_GPIO GPIO1 #define BOARD_CAMERA_PWDN_PIN 4 -/* @Brief Board touch panel configuration */ -#define BOARD_TOUCH_I2C_BASEADDR LPI2C1 -#define BOARD_TOUCH_RST_GPIO GPIO1 -#define BOARD_TOUCH_RST_PIN 2 -#define BOARD_TOUCH_INT_GPIO GPIO1 -#define BOARD_TOUCH_INT_PIN 11 - -/* @Brief Board Bluetooth HCI UART configuration */ -#define BOARD_BT_UART_BASEADDR LPUART3 -#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() -#define BOARD_BT_UART_IRQ LPUART3_IRQn -#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler - #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -134,56 +103,6 @@ uint32_t BOARD_DebugConsoleSrcFreq(void); void BOARD_InitDebugConsole(void); void BOARD_ConfigMPU(void); -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz); -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize); -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize); -status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize); -status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize); -void BOARD_Accel_I2C_Init(void); -status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff); -status_t BOARD_Accel_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); -void BOARD_Codec_I2C_Init(void); -status_t BOARD_Codec_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); -status_t BOARD_Codec_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); -void BOARD_Camera_I2C_Init(void); -status_t BOARD_Camera_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); -status_t BOARD_Camera_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); - -status_t BOARD_Camera_I2C_SendSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); -status_t BOARD_Camera_I2C_ReceiveSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); -status_t BOARD_Touch_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); -status_t BOARD_Touch_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); -#endif /* SDK_I2C_BASED_COMPONENT_USED */ #if defined(__cplusplus) } diff --git a/board/clock_config.c b/board/clock_config.c index 326ab07..211269f 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v9.0 +product: Clocks v10.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -32,400 +32,23 @@ processor_version: 11.0.1 /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { - Board_BootClock600MHz(); + Board_BootClockPLL480MHz(); } /******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** + ******************* Configuration Board_BootClockPLL600MHz ******************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration -name: BOARD_BootClockRUN +name: Board_BootClockPLL600MHz outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 12 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 3 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 3 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} -- {id: LVDS1_CLK.outFreq, value: 24 MHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 3 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 4 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} -settings: -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 98, /* PLL loop divider, Fout = Fin * 49 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = - { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 2); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* Bypass for ARM PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - /* Bypass System PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - -/******************************************************************************* - ******************** Configuration Board_BootClock600MHz ********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: Board_BootClock600MHz -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} @@ -435,15 +58,15 @@ outputs: - {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} - {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 4 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 4 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} - {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.056 GHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 4 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 5 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} - {id: SAI1_MCLK1.outFreq, value: 3 MHz} @@ -465,12 +88,12 @@ settings: - {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '1'} - {id: CCM.LPSPI_PODF.scale, value: '5'} -- {id: CCM.PERCLK_PODF.scale, value: '33'} +- {id: CCM.PERCLK_PODF.scale, value: '30'} - {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} - {id: CCM.SEMC_PODF.scale, value: '3', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '44', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} - {id: CCM_ANALOG.PLL2.denom, value: '1'} - {id: CCM_ANALOG.PLL2.num, value: '0'} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} @@ -481,21 +104,21 @@ settings: * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* - * Variables for Board_BootClock600MHz configuration + * Variables for Board_BootClockPLL600MHz configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_Board_BootClock600MHz = +const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz = { - .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_sys_pll_config_t sysPllConfig_Board_BootClock600MHz = +const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -const clock_enet_pll_config_t enetPllConfig_Board_BootClock600MHz = +const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz = { .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ @@ -503,9 +126,9 @@ const clock_enet_pll_config_t enetPllConfig_Board_BootClock600MHz = .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* - * Code for Board_BootClock600MHz configuration + * Code for Board_BootClockPLL600MHz configuration ******************************************************************************/ -void Board_BootClock600MHz(void) +void Board_BootClockPLL600MHz(void) { /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; @@ -524,6 +147,12 @@ void Board_BootClock600MHz(void) /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ @@ -545,7 +174,7 @@ void Board_BootClock600MHz(void) CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 32); + CLOCK_SetDiv(kCLOCK_PerclkDiv, 29); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ @@ -692,7 +321,7 @@ void Board_BootClock600MHz(void) /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_Board_BootClock600MHz); + CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL600MHz); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ @@ -701,7 +330,7 @@ void Board_BootClock600MHz(void) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." #endif /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_Board_BootClock600MHz); + CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL600MHz); /* Init System pfd0. */ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); /* Init System pfd1. */ @@ -740,7 +369,7 @@ void Board_BootClock600MHz(void) /* Enable Video PLL output. */ CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_Board_BootClock600MHz); + CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL600MHz); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* DeInit Usb2 PLL. */ @@ -799,6 +428,754 @@ void Board_BootClock600MHz(void) /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCK600MHZ_CORE_CLOCK; + SystemCoreClock = BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration Board_BootClockPLL480MHz ******************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: Board_BootClockPLL480MHz +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 480 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 4 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 4 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 120 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 960 MHz} +- {id: MQS_MCLK.outFreq, value: 3 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 4 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI1_MCLK1.outFreq, value: 3 MHz} +- {id: SAI1_MCLK2.outFreq, value: 3 MHz} +- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI2_MCLK1.outFreq, value: 3 MHz} +- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI3_MCLK1.outFreq, value: 3 MHz} +- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 132 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 88 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '1'} +- {id: CCM.LPSPI_PODF.scale, value: '5'} +- {id: CCM.PERCLK_PODF.scale, value: '30'} +- {id: CCM.SEMC_CLK_SEL.sel, value: CCM.SEMC_ALT_CLK_SEL} +- {id: CCM.SEMC_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '40', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for Board_BootClockPLL480MHz configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz = + { + .loopDivider = 80, /* PLL loop divider, Fout = Fin * 40 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz = + { + .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for Board_BootClockPLL480MHz configuration + ******************************************************************************/ +void Board_BootClockPLL480MHz(void) +{ + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 29); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 2); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 1); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_Board_BootClockPLL480MHz); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_Board_BootClockPLL480MHz); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* DeInit Usb1 PLL. */ + CLOCK_DeinitUsb1Pll(); + /* Bypass Usb1 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); + /* Enable Usb1 PLL output. */ + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_Board_BootClockPLL480MHz); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockXT24MHz ********************* + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockXT24MHz +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 6 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 6 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 6 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} +- {id: LVDS1_CLK.outFreq, value: 24 MHz} +- {id: MQS_MCLK.outFreq, value: 3 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 6 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI1_MCLK1.outFreq, value: 3 MHz} +- {id: SAI1_MCLK2.outFreq, value: 3 MHz} +- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI2_MCLK1.outFreq, value: 3 MHz} +- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI3_MCLK1.outFreq, value: 3 MHz} +- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} +settings: +- {id: CCM.ARM_PODF.scale, value: '1'} +- {id: CCM.FLEXSPI_PODF.scale, value: '1'} +- {id: CCM.SEMC_PODF.scale, value: '1'} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_SYS_POWERDOWN_CFG, value: 'Yes'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockXT24MHz configuration + ******************************************************************************/ +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz = + { + .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockXT24MHz configuration + ******************************************************************************/ +void BOARD_BootClockXT24MHz(void) +{ + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 0); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 0); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* DeInit ARM PLL. */ + CLOCK_DeinitArmPll(); + /* Bypass ARM PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1); + /* Enable ARM PLL output. */ + CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK; + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* DeInit System PLL. */ + CLOCK_DeinitSysPll(); + /* Bypass System PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); + /* Enable System PLL output. */ + CCM_ANALOG->PLL_SYS |= CCM_ANALOG_PLL_SYS_ENABLE_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* DeInit Usb1 PLL. */ + CLOCK_DeinitUsb1Pll(); + /* Bypass Usb1 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); + /* Enable Usb1 PLL output. */ + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockXT24MHz); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK; } diff --git a/board/clock_config.h b/board/clock_config.h index 4a44a97..379e02f 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -28,73 +28,73 @@ void BOARD_InitBootClocks(void); #endif /* __cplusplus*/ /******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** + ******************* Configuration Board_BootClockPLL600MHz ******************** ******************************************************************************/ /******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration + * Definitions for Board_BootClockPLL600MHz configuration ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 3000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 3000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. +/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration. */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. +extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz; +/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration. */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. +extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz; +/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration. */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; +extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz; /******************************************************************************* - * API for BOARD_BootClockRUN configuration + * API for Board_BootClockPLL600MHz configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { @@ -104,80 +104,80 @@ extern "C" { * @brief This function executes configuration of clocks. * */ -void BOARD_BootClockRUN(void); +void Board_BootClockPLL600MHz(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ /******************************************************************************* - ******************** Configuration Board_BootClock600MHz ********************** + ******************* Configuration Board_BootClockPLL480MHz ******************** ******************************************************************************/ /******************************************************************************* - * Definitions for Board_BootClock600MHz configuration + * Definitions for Board_BootClockPLL480MHz configuration ******************************************************************************/ -#define BOARD_BOOTCLOCK600MHZ_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ +#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCK600MHZ_AHB_CLK_ROOT 528000000UL -#define BOARD_BOOTCLOCK600MHZ_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCK600MHZ_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCK600MHZ_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_CLK_1M 1000000UL -#define BOARD_BOOTCLOCK600MHZ_CLK_24M 24000000UL -#define BOARD_BOOTCLOCK600MHZ_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCK600MHZ_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCK600MHZ_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCK600MHZ_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCK600MHZ_FLEXIO2_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCK600MHZ_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCK600MHZ_GPT1_IPG_CLK_HIGHFREQ 4000000UL -#define BOARD_BOOTCLOCK600MHZ_GPT2_IPG_CLK_HIGHFREQ 4000000UL -#define BOARD_BOOTCLOCK600MHZ_IPG_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCK600MHZ_LCDIF_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCK600MHZ_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCK600MHZ_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCK600MHZ_LVDS1_CLK 1056000000UL -#define BOARD_BOOTCLOCK600MHZ_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCK600MHZ_PERCLK_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCK600MHZ_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCK600MHZ_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCK600MHZ_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCK600MHZ_SEMC_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCK600MHZ_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCK600MHZ_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCK600MHZ_TRACE_CLK_ROOT 88000000UL -#define BOARD_BOOTCLOCK600MHZ_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCK600MHZ_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCK600MHZ_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCK600MHZ_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL -/*! @brief Arm PLL set for Board_BootClock600MHz configuration. +/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration. */ -extern const clock_arm_pll_config_t armPllConfig_Board_BootClock600MHz; -/*! @brief Sys PLL for Board_BootClock600MHz configuration. +extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz; +/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration. */ -extern const clock_sys_pll_config_t sysPllConfig_Board_BootClock600MHz; -/*! @brief Enet PLL set for Board_BootClock600MHz configuration. +extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz; +/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration. */ -extern const clock_enet_pll_config_t enetPllConfig_Board_BootClock600MHz; +extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz; /******************************************************************************* - * API for Board_BootClock600MHz configuration + * API for Board_BootClockPLL480MHz configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { @@ -187,7 +187,84 @@ extern "C" { * @brief This function executes configuration of clocks. * */ -void Board_BootClock600MHz(void); +void Board_BootClockPLL480MHz(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockXT24MHz ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockXT24MHz configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL +#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL +#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL +#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL +#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL + +/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz; + +/******************************************************************************* + * API for BOARD_BootClockXT24MHz configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockXT24MHz(void); #if defined(__cplusplus) } diff --git a/board/dcd.c b/board/dcd.c index 52583c3..d3bf9dc 100644 --- a/board/dcd.c +++ b/board/dcd.c @@ -24,7 +24,7 @@ product: DCDx v3.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ diff --git a/board/peripherals.c b/board/peripherals.c index f9f07f1..2007c30 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -10,7 +10,7 @@ product: Peripherals v11.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 functionalGroups: - name: BOARD_InitPeripherals UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830 diff --git a/board/pin_mux.c b/board/pin_mux.c index fbe95b3..097d74b 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v11.0 +product: Pins v12.0 processor: MIMXRT1052xxxxB package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 -processor_version: 11.0.1 +processor_version: 12.0.0 pin_labels: - {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B} - {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G} @@ -30,16 +30,47 @@ pin_labels: * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { - BOARD_InitPins(); + BOARD_InitDbgConsolePins(); + BOARD_InitLEDPins(); } /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: +BOARD_InitDbgConsolePins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12} - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDbgConsolePins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDbgConsolePins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); +#endif +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: - {pin_num: C7, peripheral: GPIO3, signal: 'gpio_io, 27', pin_signal: GPIO_EMC_41, identifier: LED_B, direction: OUTPUT, gpio_init_state: 'true'} - {pin_num: B12, peripheral: GPIO2, signal: 'gpio_io, 23', pin_signal: GPIO_B1_07, direction: OUTPUT, gpio_init_state: 'true'} - {pin_num: A7, peripheral: GPIO3, signal: 'gpio_io, 26', pin_signal: GPIO_EMC_40, identifier: LED_R, direction: OUTPUT, gpio_init_state: 'true'} @@ -48,11 +79,11 @@ BOARD_InitPins: /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitPins + * Function Name : BOARD_InitLEDPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { +void BOARD_InitLEDPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* GPIO configuration of LED_G on GPIO_B1_07 (pin B12) */ @@ -82,16 +113,6 @@ void BOARD_InitPins(void) { /* Initialize GPIO functionality on GPIO_EMC_41 (pin C7) */ GPIO_PinInit(GPIO3, 27U, &LED_B_config); -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); -#endif IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_GPIO2_IO23, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_GPIO3_IO26, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_GPIO3_IO27, 0U); diff --git a/board/pin_mux.h b/board/pin_mux.h index a33c138..c9b2e96 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -37,54 +37,61 @@ extern "C" { */ void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDbgConsolePins(void); + /* GPIO_EMC_41 (coord C7), LED_B */ /* Routed pin properties */ -#define BOARD_INITPINS_LED_B_PERIPHERAL GPIO3 /*!< Peripheral name */ -#define BOARD_INITPINS_LED_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPINS_LED_B_CHANNEL 27U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LED_B_PERIPHERAL GPIO3 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LED_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LED_B_CHANNEL 27U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPINS_LED_B_GPIO GPIO3 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPINS_LED_B_GPIO_PIN 27U /*!< GPIO pin number */ -#define BOARD_INITPINS_LED_B_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */ -#define BOARD_INITPINS_LED_B_PORT GPIO3 /*!< PORT peripheral base pointer */ -#define BOARD_INITPINS_LED_B_PIN 27U /*!< PORT pin number */ -#define BOARD_INITPINS_LED_B_PIN_MASK (1U << 27U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LED_B_GPIO GPIO3 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_B_GPIO_PIN 27U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LED_B_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LED_B_PORT GPIO3 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_B_PIN 27U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LED_B_PIN_MASK (1U << 27U) /*!< PORT pin mask */ /* GPIO_B1_07 (coord B12), LED_G */ /* Routed pin properties */ -#define BOARD_INITPINS_LED_G_PERIPHERAL GPIO2 /*!< Peripheral name */ -#define BOARD_INITPINS_LED_G_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPINS_LED_G_CHANNEL 23U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LED_G_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LED_G_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LED_G_CHANNEL 23U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPINS_LED_G_GPIO GPIO2 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPINS_LED_G_GPIO_PIN 23U /*!< GPIO pin number */ -#define BOARD_INITPINS_LED_G_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */ -#define BOARD_INITPINS_LED_G_PORT GPIO2 /*!< PORT peripheral base pointer */ -#define BOARD_INITPINS_LED_G_PIN 23U /*!< PORT pin number */ -#define BOARD_INITPINS_LED_G_PIN_MASK (1U << 23U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LED_G_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_G_GPIO_PIN 23U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LED_G_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LED_G_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_G_PIN 23U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LED_G_PIN_MASK (1U << 23U) /*!< PORT pin mask */ /* GPIO_EMC_40 (coord A7), LED_R */ /* Routed pin properties */ -#define BOARD_INITPINS_LED_R_PERIPHERAL GPIO3 /*!< Peripheral name */ -#define BOARD_INITPINS_LED_R_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPINS_LED_R_CHANNEL 26U /*!< Signal channel */ +#define BOARD_INITLEDPINS_LED_R_PERIPHERAL GPIO3 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_LED_R_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLEDPINS_LED_R_CHANNEL 26U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPINS_LED_R_GPIO GPIO3 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPINS_LED_R_GPIO_PIN 26U /*!< GPIO pin number */ -#define BOARD_INITPINS_LED_R_GPIO_PIN_MASK (1U << 26U) /*!< GPIO pin mask */ -#define BOARD_INITPINS_LED_R_PORT GPIO3 /*!< PORT peripheral base pointer */ -#define BOARD_INITPINS_LED_R_PIN 26U /*!< PORT pin number */ -#define BOARD_INITPINS_LED_R_PIN_MASK (1U << 26U) /*!< PORT pin mask */ +#define BOARD_INITLEDPINS_LED_R_GPIO GPIO3 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_R_GPIO_PIN 26U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_LED_R_GPIO_PIN_MASK (1U << 26U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_LED_R_PORT GPIO3 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_R_PIN 26U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_LED_R_PIN_MASK (1U << 26U) /*!< PORT pin mask */ /*! * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InitPins(void); +void BOARD_InitLEDPins(void); #if defined(__cplusplus) } diff --git a/src/main.c b/src/main.c index 957f80c..35a194d 100644 --- a/src/main.c +++ b/src/main.c @@ -15,9 +15,9 @@ int main(void) { CLOCK_SetMode(kCLOCK_ModeRun); - GPIO_WritePinOutput(BOARD_INITPINS_LED_R_GPIO, BOARD_INITPINS_LED_R_PIN, 0U); - GPIO_WritePinOutput(BOARD_INITPINS_LED_G_GPIO, BOARD_INITPINS_LED_G_PIN, 0U); - GPIO_WritePinOutput(BOARD_INITPINS_LED_B_GPIO, BOARD_INITPINS_LED_B_PIN, 0U); + GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_R_GPIO, BOARD_INITLEDPINS_LED_R_PIN, 0U); + GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_G_GPIO, BOARD_INITLEDPINS_LED_G_PIN, 0U); + GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_B_GPIO, BOARD_INITLEDPINS_LED_B_PIN, 0U); for (;;) { __WFI();