From 62556a4edebc8ed147846569dda81d6dacb5bdc9 Mon Sep 17 00:00:00 2001 From: imi415 Date: Fri, 20 May 2022 17:40:56 +0800 Subject: [PATCH] Added ENET0 pinmux. --- MK60DN512xxx10.mex | 15 +++++++++++++++ board/pin_mux.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++ board/pin_mux.h | 1 + 3 files changed, 63 insertions(+) diff --git a/MK60DN512xxx10.mex b/MK60DN512xxx10.mex index 1da80ee..a3fc0db 100644 --- a/MK60DN512xxx10.mex +++ b/MK60DN512xxx10.mex @@ -47,6 +47,11 @@ true + + + true + + true @@ -112,6 +117,16 @@ + + + + + + + + + + diff --git a/board/pin_mux.c b/board/pin_mux.c index 4a89ccd..a114204 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -84,6 +84,16 @@ BOARD_InitPins: - {pin_num: '77', peripheral: FB, signal: 'A, 27', pin_signal: PTA26/MII0_TXD3/FB_A27} - {pin_num: '123', peripheral: FB, signal: CS5_TSIZ1_BE23_16_BLS15_8, pin_signal: PTC16/CAN1_RX/UART3_RX/ENET0_1588_TMR0/FB_CS5_b/FB_TSIZ1/FB_BE23_16_b} - {pin_num: '124', peripheral: FB, signal: CS4_TSIZ0_BE31_24_BLS7_0, pin_signal: PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_b} + - {pin_num: '82', peripheral: ENET, signal: RMII_MDC, pin_signal: ADC0_SE9/ADC1_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHB} + - {pin_num: '81', peripheral: ENET, signal: RMII_MDIO, pin_signal: ADC0_SE8/ADC1_SE8/TSI0_CH0/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHA} + - {pin_num: '68', peripheral: ENET, signal: RMII_TXD0, pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1} + - {pin_num: '69', peripheral: ENET, signal: RMII_TXD1, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK} + - {pin_num: '55', peripheral: ENET, signal: RMII_RXER, pin_signal: PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b} + - {pin_num: '65', peripheral: ENET, signal: RMII_RXD0, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2S0_TX_FS/FTM1_QD_PHB} + - {pin_num: '64', peripheral: ENET, signal: RMII_RXD1, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2S0_TXD0/FTM1_QD_PHA} + - {pin_num: '66', peripheral: ENET, signal: RMII_CRS_DV, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2S0_RX_BCLK/I2S0_TXD1} + - {pin_num: '67', peripheral: ENET, signal: rmii_txen, pin_signal: PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0} + - {pin_num: '72', peripheral: ENET, signal: RMII_CLKIN, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -112,12 +122,42 @@ void BOARD_InitPins(void) /* Initialize GPIO functionality on pin PTA6 (pin 58) */ GPIO_PinInit(BOARD_INITPINS_BUZZER_GPIO, BOARD_INITPINS_BUZZER_PIN, &BUZZER_config); + /* PORTA12 (pin 64) is configured as RMII0_RXD1 */ + PORT_SetPinMux(PORTA, 12U, kPORT_MuxAlt4); + + /* PORTA13 (pin 65) is configured as RMII0_RXD0 */ + PORT_SetPinMux(PORTA, 13U, kPORT_MuxAlt4); + + /* PORTA14 (pin 66) is configured as RMII0_CRS_DV */ + PORT_SetPinMux(PORTA, 14U, kPORT_MuxAlt4); + + /* PORTA15 (pin 67) is configured as RMII0_TXEN */ + PORT_SetPinMux(PORTA, 15U, kPORT_MuxAlt4); + + /* PORTA16 (pin 68) is configured as RMII0_TXD0 */ + PORT_SetPinMux(PORTA, 16U, kPORT_MuxAlt4); + + /* PORTA17 (pin 69) is configured as RMII0_TXD1 */ + PORT_SetPinMux(PORTA, 17U, kPORT_MuxAlt4); + + /* PORTA18 (pin 72) is configured as EXTAL0 */ + PORT_SetPinMux(PORTA, 18U, kPORT_PinDisabledOrAnalog); + /* PORTA26 (pin 77) is configured as FB_A27 */ PORT_SetPinMux(PORTA, 26U, kPORT_MuxAlt6); + /* PORTA5 (pin 55) is configured as RMII0_RXER */ + PORT_SetPinMux(PORTA, 5U, kPORT_MuxAlt4); + /* PORTA6 (pin 58) is configured as PTA6 */ PORT_SetPinMux(BOARD_INITPINS_BUZZER_PORT, BOARD_INITPINS_BUZZER_PIN, kPORT_MuxAsGpio); + /* PORTB0 (pin 81) is configured as RMII0_MDIO */ + PORT_SetPinMux(PORTB, 0U, kPORT_MuxAlt4); + + /* PORTB1 (pin 82) is configured as RMII0_MDC */ + PORT_SetPinMux(PORTB, 1U, kPORT_MuxAlt4); + /* PORTB10 (pin 91) is configured as FB_AD19 */ PORT_SetPinMux(PORTB, 10U, kPORT_MuxAlt5); @@ -244,6 +284,13 @@ void BOARD_InitPins(void) /* PORTD9 (pin 138) is configured as FB_A17 */ PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt6); + SIM->SOPT2 = ((SIM->SOPT2 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT2_RMIISRC_MASK))) + + /* RMII clock source select: EXTAL clock. */ + | SIM_SOPT2_RMIISRC(SOPT2_RMIISRC_EXTAL)); + SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) diff --git a/board/pin_mux.h b/board/pin_mux.h index e95bb9d..c594838 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -25,6 +25,7 @@ extern "C" { */ void BOARD_InitBootPins(void); +#define SOPT2_RMIISRC_EXTAL 0x00u /*!<@brief RMII clock source select: EXTAL clock */ #define SOPT5_UART0RXSRC_UART_RX 0x00u /*!<@brief UART 0 receive data source select: UART0_RX pin */ #define SOPT5_UART0TXSRC_UART_TX 0x00u /*!<@brief UART 0 transmit data source select: UART0_TX pin */