diff --git a/MK60DN512xxx10.mex b/MK60DN512xxx10.mex
index 372a5b9..1da80ee 100644
--- a/MK60DN512xxx10.mex
+++ b/MK60DN512xxx10.mex
@@ -42,6 +42,11 @@
true
+
+
+ true
+
+
true
@@ -66,6 +71,47 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -162,6 +208,18 @@
+
+
+
+ true
+
+
+
+
+ 2.0.2
+
+
+
@@ -173,7 +231,263 @@
-
+
+
+
+ 0
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
@@ -181,6 +495,73 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ checkSignals_FB_A
+ checkSignals_FB_AD
+ checkSignal_FB_OE
+ checkSignal_FB_RW
+ checkSignal_FB_CS0
+ checkSignalGroup1
+ checkSignalGroup2
+ checkSignalGroup3
+
+
+
+
diff --git a/board/peripherals.c b/board/peripherals.c
index b21cd2e..b37c6d3 100644
--- a/board/peripherals.c
+++ b/board/peripherals.c
@@ -76,12 +76,131 @@ instance:
static void NVIC_init(void) {
} */
+/***********************************************************************************************************************
+ * FB initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'FB'
+- type: 'flexbus'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'flexbus_c0f98ce230f06c38b26b546b16ee96cc'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'FB'
+- config_sets:
+ - fsl_flexbus:
+ - clockSource: 'FunctionClock'
+ - clockSourceFreq: 'BOARD_BootClockRUN'
+ - flexbus_configs:
+ - 0:
+ - enableChipConfiguration: 'true'
+ - initChip: 'true'
+ - chip: 'FB_CS0'
+ - chipUserName: 'LCD'
+ - chipBaseAddress: '0x70000000'
+ - chipBaseAddressMask: 'mask_0x0FFF'
+ - byteEnableMode: 'false'
+ - autoAcknowledge: 'true'
+ - extendTransferAddress: 'false'
+ - byteLaneShift: 'kFLEXBUS_NotShifted'
+ - portSize: 'kFLEXBUS_1Byte'
+ - writeAddressHold: 'kFLEXBUS_Hold1Cycle'
+ - readAddressHold: 'kFLEXBUS_Hold1Or0Cycles'
+ - addressSetup: 'kFLEXBUS_FirstRisingEdge'
+ - waitStates: '0'
+ - burstWrite: 'false'
+ - burstRead: 'false'
+ - writeProtect: 'false'
+ - 1:
+ - enableChipConfiguration: 'true'
+ - initChip: 'true'
+ - chip: 'FB_CS1'
+ - chipUserName: 'SRAM'
+ - chipBaseAddress: '0x60000000'
+ - chipBaseAddressMask: 'mask_0x0007'
+ - byteEnableMode: 'true'
+ - autoAcknowledge: 'true'
+ - extendTransferAddress: 'false'
+ - byteLaneShift: 'kFLEXBUS_NotShifted'
+ - portSize: 'kFLEXBUS_2Bytes'
+ - writeAddressHold: 'kFLEXBUS_Hold1Cycle'
+ - readAddressHold: 'kFLEXBUS_Hold1Or0Cycles'
+ - addressSetup: 'kFLEXBUS_FirstRisingEdge'
+ - waitStates: '1'
+ - burstWrite: 'false'
+ - burstRead: 'false'
+ - writeProtect: 'false'
+ - groupsMultiplexControl:
+ - group1MultiplexControl: 'kFLEXBUS_MultiplexGroup1_FB_CS1'
+ - group2MultiplexControl: 'kFLEXBUS_MultiplexGroup2_FB_BE_31_24'
+ - group3MultiplexControl: 'kFLEXBUS_MultiplexGroup3_FB_BE_23_16'
+ - group4MultiplexControl: 'kFLEXBUS_MultiplexGroup4_FB_TBST'
+ - group5MultiplexControl: 'kFLEXBUS_MultiplexGroup5_FB_TA'
+ - checkSignalsPins: 'checkSignals_FB_A checkSignals_FB_AD checkSignal_FB_OE checkSignal_FB_RW checkSignal_FB_CS0 checkSignalGroup1 checkSignalGroup2 checkSignalGroup3'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+flexbus_config_t FB_LCD_config = {
+ .chip = 0,
+ .chipBaseAddress = 0x70000000UL,
+ .chipBaseAddressMask = 0x0FFFU,
+ .byteEnableMode = false,
+ .autoAcknowledge = true,
+ .extendTransferAddress = false,
+ .byteLaneShift = kFLEXBUS_NotShifted,
+ .portSize = kFLEXBUS_1Byte,
+ .writeAddressHold = kFLEXBUS_Hold1Cycle,
+ .readAddressHold = kFLEXBUS_Hold1Or0Cycles,
+ .addressSetup = kFLEXBUS_FirstRisingEdge,
+ .waitStates = 0U,
+ .secondaryWaitStates = false,
+ .burstWrite = false,
+ .burstRead = false,
+ .writeProtect = false,
+ .group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_CS1,
+ .group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_BE_31_24,
+ .group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_BE_23_16,
+ .group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST,
+ .group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA
+};
+flexbus_config_t FB_SRAM_config = {
+ .chip = 1,
+ .chipBaseAddress = 0x60000000UL,
+ .chipBaseAddressMask = 0x0007U,
+ .byteEnableMode = true,
+ .autoAcknowledge = true,
+ .extendTransferAddress = false,
+ .byteLaneShift = kFLEXBUS_NotShifted,
+ .portSize = kFLEXBUS_2Bytes,
+ .writeAddressHold = kFLEXBUS_Hold1Cycle,
+ .readAddressHold = kFLEXBUS_Hold1Or0Cycles,
+ .addressSetup = kFLEXBUS_FirstRisingEdge,
+ .waitStates = 1U,
+ .secondaryWaitStates = false,
+ .burstWrite = false,
+ .burstRead = false,
+ .writeProtect = false,
+ .group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_CS1,
+ .group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_BE_31_24,
+ .group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_BE_23_16,
+ .group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST,
+ .group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA
+};
+
+static void FB_init(void) {
+ /* FlexBus initialization */
+ FLEXBUS_Init(FB_PERIPHERAL, &FB_LCD_config);
+ FLEXBUS_Init(FB_PERIPHERAL, &FB_SRAM_config);
+}
+
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
/* Initialize components */
+ FB_init();
}
/***********************************************************************************************************************
diff --git a/board/peripherals.h b/board/peripherals.h
index 2a75809..7778516 100644
--- a/board/peripherals.h
+++ b/board/peripherals.h
@@ -10,11 +10,27 @@
* Included files
**********************************************************************************************************************/
#include "fsl_common.h"
+#include "fsl_flexbus.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals functional group */
+/* Definition of peripheral ID */
+#define FB_PERIPHERAL FB
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+/* FlexBus configuration structure for LCD */
+extern flexbus_config_t FB_LCD_config;
+/* FlexBus configuration structure for SRAM */
+extern flexbus_config_t FB_SRAM_config;
+
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
diff --git a/board/pin_mux.c b/board/pin_mux.c
index 3f9703b..4a89ccd 100644
--- a/board/pin_mux.c
+++ b/board/pin_mux.c
@@ -43,6 +43,47 @@ BOARD_InitPins:
- {pin_num: '136', peripheral: UART0, signal: TX, pin_signal: PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1}
- {pin_num: '133', peripheral: UART0, signal: RX, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0}
- {pin_num: '58', peripheral: GPIOA, signal: 'GPIO, 6', pin_signal: PTA6/FTM0_CH3/TRACE_CLKOUT, direction: OUTPUT}
+ - {pin_num: '132', peripheral: FB, signal: 'AD, 1', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/UART0_COL_b/FTM0_CH5/FB_AD1/EWM_OUT_b}
+ - {pin_num: '131', peripheral: FB, signal: 'AD, 2', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN}
+ - {pin_num: '130', peripheral: FB, signal: 'AD, 3', pin_signal: PTD3/SPI0_SIN/UART2_TX/FB_AD3}
+ - {pin_num: '129', peripheral: FB, signal: 'AD, 4', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FB_AD4}
+ - {pin_num: '115', peripheral: FB, signal: 'AD, 5', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/I2S0_RX_FS/FB_AD5}
+ - {pin_num: '114', peripheral: FB, signal: 'AD, 6', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/I2S0_RX_BCLK/FB_AD6/FTM2_FLT0}
+ - {pin_num: '113', peripheral: FB, signal: 'AD, 7', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/I2S0_MCLK/FB_AD7}
+ - {pin_num: '112', peripheral: FB, signal: 'AD, 8', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS/FB_AD8}
+ - {pin_num: '111', peripheral: FB, signal: 'AD, 9', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK}
+ - {pin_num: '110', peripheral: FB, signal: 'AD, 10', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT}
+ - {pin_num: '109', peripheral: FB, signal: 'AD, 11', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT}
+ - {pin_num: '105', peripheral: FB, signal: 'AD, 12', pin_signal: ADC0_SE4b/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/I2S0_TX_FS}
+ - {pin_num: '104', peripheral: FB, signal: 'AD, 13', pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/I2S0_TXD0}
+ - {pin_num: '103', peripheral: FB, signal: 'AD, 14', pin_signal: ADC0_SE14/TSI0_CH13/PTC0/SPI0_PCS4/PDB0_EXTRG/FB_AD14/I2S0_TXD1}
+ - {pin_num: '97', peripheral: FB, signal: 'AD, 15', pin_signal: TSI0_CH11/PTB18/CAN0_TX/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/FTM2_QD_PHA}
+ - {pin_num: '137', peripheral: FB, signal: 'A, 16', pin_signal: PTD8/I2C0_SCL/UART5_RX/FB_A16}
+ - {pin_num: '138', peripheral: FB, signal: 'A, 17', pin_signal: PTD9/I2C0_SDA/UART5_TX/FB_A17}
+ - {pin_num: '139', peripheral: FB, signal: 'A, 18', pin_signal: PTD10/UART5_RTS_b/FB_A18}
+ - {pin_num: '96', peripheral: FB, signal: 'AD, 16', pin_signal: TSI0_CH10/PTB17/SPI1_SIN/UART0_TX/FB_AD16/EWM_OUT_b}
+ - {pin_num: '95', peripheral: FB, signal: 'AD, 17', pin_signal: TSI0_CH9/PTB16/SPI1_SOUT/UART0_RX/FB_AD17/EWM_IN}
+ - {pin_num: '92', peripheral: FB, signal: 'AD, 18', pin_signal: ADC1_SE15/PTB11/SPI1_SCK/UART3_TX/FB_AD18/FTM0_FLT2}
+ - {pin_num: '91', peripheral: FB, signal: 'AD, 19', pin_signal: ADC1_SE14/PTB10/SPI1_PCS0/UART3_RX/FB_AD19/FTM0_FLT1}
+ - {pin_num: '90', peripheral: FB, signal: 'AD, 20', pin_signal: PTB9/SPI1_PCS1/UART3_CTS_b/FB_AD20}
+ - {pin_num: '89', peripheral: FB, signal: 'AD, 21', pin_signal: PTB8/UART3_RTS_b/FB_AD21}
+ - {pin_num: '88', peripheral: FB, signal: 'AD, 22', pin_signal: ADC1_SE13/PTB7/FB_AD22}
+ - {pin_num: '87', peripheral: FB, signal: 'AD, 23', pin_signal: ADC1_SE12/PTB6/FB_AD23}
+ - {pin_num: '120', peripheral: FB, signal: 'AD, 24', pin_signal: PTC15/UART4_TX/FB_AD24}
+ - {pin_num: '119', peripheral: FB, signal: 'AD, 25', pin_signal: PTC14/UART4_RX/FB_AD25}
+ - {pin_num: '117', peripheral: FB, signal: 'AD, 27', pin_signal: PTC12/UART4_RTS_b/FB_AD27}
+ - {pin_num: '118', peripheral: FB, signal: 'AD, 26', pin_signal: PTC13/UART4_CTS_b/FB_AD26}
+ - {pin_num: '102', peripheral: FB, signal: 'AD, 28', pin_signal: PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28}
+ - {pin_num: '101', peripheral: FB, signal: 'AD, 29', pin_signal: PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT}
+ - {pin_num: '100', peripheral: FB, signal: 'AD, 30', pin_signal: PTB21/SPI2_SCK/FB_AD30/CMP1_OUT}
+ - {pin_num: '99', peripheral: FB, signal: 'AD, 31', pin_signal: PTB20/SPI2_PCS0/FB_AD31/CMP0_OUT}
+ - {pin_num: '127', peripheral: FB, signal: ALE_CS1_TS, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FB_ALE/FB_CS1_b/FB_TS_b}
+ - {pin_num: '128', peripheral: FB, signal: CS0, pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FB_CS0_b}
+ - {pin_num: '116', peripheral: FB, signal: RW, pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/I2S0_RXD1/FB_RW_b}
+ - {pin_num: '98', peripheral: FB, signal: OE, pin_signal: TSI0_CH12/PTB19/CAN0_RX/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB}
+ - {pin_num: '77', peripheral: FB, signal: 'A, 27', pin_signal: PTA26/MII0_TXD3/FB_A27}
+ - {pin_num: '123', peripheral: FB, signal: CS5_TSIZ1_BE23_16_BLS15_8, pin_signal: PTC16/CAN1_RX/UART3_RX/ENET0_1588_TMR0/FB_CS5_b/FB_TSIZ1/FB_BE23_16_b}
+ - {pin_num: '124', peripheral: FB, signal: CS4_TSIZ0_BE31_24_BLS7_0, pin_signal: PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_b}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
@@ -57,6 +98,10 @@ void BOARD_InitPins(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
+ /* Port B Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortB);
+ /* Port C Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortC);
/* Port D Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortD);
@@ -67,15 +112,138 @@ void BOARD_InitPins(void)
/* Initialize GPIO functionality on pin PTA6 (pin 58) */
GPIO_PinInit(BOARD_INITPINS_BUZZER_GPIO, BOARD_INITPINS_BUZZER_PIN, &BUZZER_config);
+ /* PORTA26 (pin 77) is configured as FB_A27 */
+ PORT_SetPinMux(PORTA, 26U, kPORT_MuxAlt6);
+
/* PORTA6 (pin 58) is configured as PTA6 */
PORT_SetPinMux(BOARD_INITPINS_BUZZER_PORT, BOARD_INITPINS_BUZZER_PIN, kPORT_MuxAsGpio);
+ /* PORTB10 (pin 91) is configured as FB_AD19 */
+ PORT_SetPinMux(PORTB, 10U, kPORT_MuxAlt5);
+
+ /* PORTB11 (pin 92) is configured as FB_AD18 */
+ PORT_SetPinMux(PORTB, 11U, kPORT_MuxAlt5);
+
+ /* PORTB16 (pin 95) is configured as FB_AD17 */
+ PORT_SetPinMux(PORTB, 16U, kPORT_MuxAlt5);
+
+ /* PORTB17 (pin 96) is configured as FB_AD16 */
+ PORT_SetPinMux(PORTB, 17U, kPORT_MuxAlt5);
+
+ /* PORTB18 (pin 97) is configured as FB_AD15 */
+ PORT_SetPinMux(PORTB, 18U, kPORT_MuxAlt5);
+
+ /* PORTB19 (pin 98) is configured as FB_OE_b */
+ PORT_SetPinMux(PORTB, 19U, kPORT_MuxAlt5);
+
+ /* PORTB20 (pin 99) is configured as FB_AD31 */
+ PORT_SetPinMux(PORTB, 20U, kPORT_MuxAlt5);
+
+ /* PORTB21 (pin 100) is configured as FB_AD30 */
+ PORT_SetPinMux(PORTB, 21U, kPORT_MuxAlt5);
+
+ /* PORTB22 (pin 101) is configured as FB_AD29 */
+ PORT_SetPinMux(PORTB, 22U, kPORT_MuxAlt5);
+
+ /* PORTB23 (pin 102) is configured as FB_AD28 */
+ PORT_SetPinMux(PORTB, 23U, kPORT_MuxAlt5);
+
+ /* PORTB6 (pin 87) is configured as FB_AD23 */
+ PORT_SetPinMux(PORTB, 6U, kPORT_MuxAlt5);
+
+ /* PORTB7 (pin 88) is configured as FB_AD22 */
+ PORT_SetPinMux(PORTB, 7U, kPORT_MuxAlt5);
+
+ /* PORTB8 (pin 89) is configured as FB_AD21 */
+ PORT_SetPinMux(PORTB, 8U, kPORT_MuxAlt5);
+
+ /* PORTB9 (pin 90) is configured as FB_AD20 */
+ PORT_SetPinMux(PORTB, 9U, kPORT_MuxAlt5);
+
+ /* PORTC0 (pin 103) is configured as FB_AD14 */
+ PORT_SetPinMux(PORTC, 0U, kPORT_MuxAlt5);
+
+ /* PORTC1 (pin 104) is configured as FB_AD13 */
+ PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt5);
+
+ /* PORTC10 (pin 115) is configured as FB_AD5 */
+ PORT_SetPinMux(PORTC, 10U, kPORT_MuxAlt5);
+
+ /* PORTC11 (pin 116) is configured as FB_RW_b */
+ PORT_SetPinMux(PORTC, 11U, kPORT_MuxAlt5);
+
+ /* PORTC12 (pin 117) is configured as FB_AD27 */
+ PORT_SetPinMux(PORTC, 12U, kPORT_MuxAlt5);
+
+ /* PORTC13 (pin 118) is configured as FB_AD26 */
+ PORT_SetPinMux(PORTC, 13U, kPORT_MuxAlt5);
+
+ /* PORTC14 (pin 119) is configured as FB_AD25 */
+ PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt5);
+
+ /* PORTC15 (pin 120) is configured as FB_AD24 */
+ PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt5);
+
+ /* PORTC16 (pin 123) is configured as FB_CS5_b */
+ PORT_SetPinMux(PORTC, 16U, kPORT_MuxAlt5);
+
+ /* PORTC17 (pin 124) is configured as FB_CS4_b */
+ PORT_SetPinMux(PORTC, 17U, kPORT_MuxAlt5);
+
+ /* PORTC2 (pin 105) is configured as FB_AD12 */
+ PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt5);
+
+ /* PORTC4 (pin 109) is configured as FB_AD11 */
+ PORT_SetPinMux(PORTC, 4U, kPORT_MuxAlt5);
+
+ /* PORTC5 (pin 110) is configured as FB_AD10 */
+ PORT_SetPinMux(PORTC, 5U, kPORT_MuxAlt5);
+
+ /* PORTC6 (pin 111) is configured as FB_AD9 */
+ PORT_SetPinMux(PORTC, 6U, kPORT_MuxAlt5);
+
+ /* PORTC7 (pin 112) is configured as FB_AD8 */
+ PORT_SetPinMux(PORTC, 7U, kPORT_MuxAlt5);
+
+ /* PORTC8 (pin 113) is configured as FB_AD7 */
+ PORT_SetPinMux(PORTC, 8U, kPORT_MuxAlt5);
+
+ /* PORTC9 (pin 114) is configured as FB_AD6 */
+ PORT_SetPinMux(PORTC, 9U, kPORT_MuxAlt5);
+
+ /* PORTD0 (pin 127) is configured as FB_CS1_b */
+ PORT_SetPinMux(PORTD, 0U, kPORT_MuxAlt5);
+
+ /* PORTD1 (pin 128) is configured as FB_CS0_b */
+ PORT_SetPinMux(PORTD, 1U, kPORT_MuxAlt5);
+
+ /* PORTD10 (pin 139) is configured as FB_A18 */
+ PORT_SetPinMux(PORTD, 10U, kPORT_MuxAlt6);
+
+ /* PORTD2 (pin 129) is configured as FB_AD4 */
+ PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt5);
+
+ /* PORTD3 (pin 130) is configured as FB_AD3 */
+ PORT_SetPinMux(PORTD, 3U, kPORT_MuxAlt5);
+
+ /* PORTD4 (pin 131) is configured as FB_AD2 */
+ PORT_SetPinMux(PORTD, 4U, kPORT_MuxAlt5);
+
+ /* PORTD5 (pin 132) is configured as FB_AD1 */
+ PORT_SetPinMux(PORTD, 5U, kPORT_MuxAlt5);
+
/* PORTD6 (pin 133) is configured as UART0_RX */
PORT_SetPinMux(PORTD, 6U, kPORT_MuxAlt3);
/* PORTD7 (pin 136) is configured as UART0_TX */
PORT_SetPinMux(PORTD, 7U, kPORT_MuxAlt3);
+ /* PORTD8 (pin 137) is configured as FB_A16 */
+ PORT_SetPinMux(PORTD, 8U, kPORT_MuxAlt6);
+
+ /* PORTD9 (pin 138) is configured as FB_A17 */
+ PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt6);
+
SIM->SOPT5 = ((SIM->SOPT5 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))
diff --git a/include/system_utilities.h b/include/system_utilities.h
new file mode 100644
index 0000000..ecdcad3
--- /dev/null
+++ b/include/system_utilities.h
@@ -0,0 +1,7 @@
+#ifndef SYSTEM_UTILITIES_H
+#define SYSTEM_UTILITIES_H
+
+void print_hardware(void);
+void sram_test(void);
+
+#endif
\ No newline at end of file
diff --git a/src/main.c b/src/main.c
index 5a5028e..3fa1aa0 100644
--- a/src/main.c
+++ b/src/main.c
@@ -2,11 +2,10 @@
#include "clock_config.h"
#include "peripherals.h"
#include "pin_mux.h"
+#include "system_utilities.h"
#include "fsl_debug_console.h"
-void print_hardware(void);
-
int main(void) {
BOARD_InitBootPins();
BOARD_BootClockRUN();
@@ -15,6 +14,7 @@ int main(void) {
BOARD_InitDebugConsole();
print_hardware();
+ sram_test();
for (;;) {
__WFI();
diff --git a/src/system_utilities.c b/src/system_utilities.c
index d94d7f8..01ede5f 100644
--- a/src/system_utilities.c
+++ b/src/system_utilities.c
@@ -5,6 +5,9 @@
#include "fsl_debug_console.h"
+#define SRAM_BASE (0x60000000)
+#define SRAM_SIZE (512 * 1024)
+
void print_hardware(void) {
uint32_t kinetis_revid = (SIM->SDID & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT;
uint32_t kinetis_family = (SIM->SDID & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT;
@@ -93,4 +96,22 @@ void print_hardware(void) {
}
PRINTF("This is %s with Rev. (Mask Set): %s, %s pins.\r\n", family_str, rev_str, pin_str);
+}
+
+void sram_test(void) {
+ PRINTF("SRAM write... ");
+ for(uint32_t i = SRAM_BASE; i < SRAM_BASE + SRAM_SIZE; i += 4) {
+ *(volatile uint32_t *)i = i;
+ }
+
+ PRINTF("done, SRAM read... ");
+
+ for(uint32_t i = SRAM_BASE; i < SRAM_BASE + SRAM_SIZE; i += 4) {
+ if(*(volatile uint32_t *)i != i) {
+ PRINTF("error.\r\n");
+ return;
+ }
+ }
+
+ PRINTF("done.\r\n");
}
\ No newline at end of file