/*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* * How to setup clock using clock driver functions: * * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock * and flash clock are in allowed range during clock mode switch. * * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. * * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and * internal reference clock(MCGIRCLK). Follow the steps to setup: * * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. * * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig * explicitly to setup MCGIRCLK. * * 3). Don't need to configure FLL explicitly, because if target mode is FLL * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, * if the target mode is not FLL mode, the FLL is disabled. * * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. * * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. */ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v9.0 processor: MK60DN512xxx10 package_id: MK60DN512VLQ10 mcu_data: ksdk2_0 processor_version: 11.0.1 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ #include "fsl_rtc.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ #define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */ #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ #define RTC_OSC_CAP_LOAD_12PF 0x1800U /*!< RTC oscillator capacity load: 12pF */ #define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ #define SIM_ENET_RMII_CLK_SEL_EXTAL_CLK 0U /*!< SDHC clock select: Core/system clock */ #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ #define SIM_SDHC_CLK_SEL_OSCERCLK_CLK 2U /*!< SDHC clock select: OSCERCLK clock */ /******************************************************************************* * Variables ******************************************************************************/ /* System clock frequency. */ extern uint32_t SystemCoreClock; /******************************************************************************* * Code ******************************************************************************/ /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetRtcClock * Description : This function is used to configuring RTC clock including * enabling RTC oscillator. * Param capLoad : RTC oscillator capacity load * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals * *END**************************************************************************/ static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) { /* RTC clock gate enable */ CLOCK_EnableClock(kCLOCK_Rtc0); if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ /* Set the specified capacitor configuration for the RTC oscillator */ RTC_SetOscCapLoad(RTC, capLoad); /* Enable the RTC 32KHz oscillator */ RTC->CR |= RTC_CR_OSCE_MASK; } /* Output to other peripherals */ if (enableOutPeriph) { RTC->CR &= ~RTC_CR_CLKO_MASK; } else { RTC->CR |= RTC_CR_CLKO_MASK; } /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); /* Set RTC_TSR if there is fault value in RTC */ if (RTC->SR & RTC_SR_TIF_MASK) { RTC -> TSR = RTC -> TSR; } /* RTC clock gate disable */ CLOCK_DisableClock(kCLOCK_Rtc0); } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetFllExtRefDiv * Description : Configure FLL external reference divider (FRDIV). * Param frdiv : The value to set FRDIV. * *END**************************************************************************/ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) { MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); } /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockRUN(); } /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockRUN called_from_default_init: true outputs: - {id: Bus_clock.outFreq, value: 50 MHz} - {id: Core_clock.outFreq, value: 100 MHz} - {id: Flash_clock.outFreq, value: 25 MHz} - {id: FlexBus_clock.outFreq, value: 50 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGFFCLK.outFreq, value: 39.0625 kHz} - {id: OSCERCLK.outFreq, value: 50 MHz} - {id: RMIICLK.outFreq, value: 50 MHz} - {id: SDHCCLK.outFreq, value: 50 MHz} - {id: System_clock.outFreq, value: 100 MHz} settings: - {id: MCGMode, value: PEE} - {id: MCG.FLL_mul.scale, value: '640', locked: true} - {id: MCG.FRDIV.scale, value: '1280'} - {id: MCG.IREFS.sel, value: MCG.FRDIV} - {id: MCG.PLLS.sel, value: MCG.PLL} - {id: MCG.PRDIV.scale, value: '13', locked: true} - {id: MCG.VDIV.scale, value: '26', locked: true} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: OSC_CR_ERCLKEN_CFG, value: Enabled} - {id: RMIISrcConfig, value: 'yes'} - {id: RTC_CR_OSCE_CFG, value: Enabled} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC12PF} - {id: SDHCClkConfig, value: 'yes'} - {id: SIM.OUTDIV1.scale, value: '1', locked: true} - {id: SIM.OUTDIV2.scale, value: '2'} - {id: SIM.OUTDIV3.scale, value: '2'} - {id: SIM.OUTDIV4.scale, value: '4'} - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK} sources: - {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true} - {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockRUN = { .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ .frdiv = 0x6U, /* FLL reference clock divider: divided by 1280 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .prdiv = 0xcU, /* PLL Reference divider: divided by 13 */ .vdiv = 0x2U, /* VCO divider: multiplied by 26 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ .clkdiv1 = 0x1130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { .freq = 50000000U, /* Oscillator frequency: 50000000Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ } }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Configure RTC clock including enabling RTC oscillator. */ CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); /* Initializes OSC0 according to board configuration. */ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); /* Configure FLL external reference divider (FRDIV). */ CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); /* Set MCG to PEE mode. */ CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockRUN.pll0Config); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; /* Set RMII clock source. */ CLOCK_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_EXTAL_CLK); /* Set SDHC clock source. */ CLOCK_SetSdhc0Clock(SIM_SDHC_CLK_SEL_OSCERCLK_CLK); }