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Landzo_K60Z_WebServer/board/pin_mux.c

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v11.0
processor: MK60DN512xxx10
package_id: MK60DN512VLQ10
mcu_data: ksdk2_0
processor_version: 11.0.1
pin_labels:
- {pin_num: '58', pin_signal: PTA6/FTM0_CH3/TRACE_CLKOUT, label: BUZZER, identifier: BUZZER}
- {pin_num: '106', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK, label: TFT_BL, identifier: TFT_BL}
- {pin_num: '126', pin_signal: PTC19/UART3_CTS_b/ENET0_1588_TMR3/FB_CS3_b/FB_BE7_0_b/FB_TA_b, label: TFT_RESET, identifier: TFT_RESET}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '136', peripheral: UART0, signal: TX, pin_signal: PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1}
- {pin_num: '133', peripheral: UART0, signal: RX, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0}
- {pin_num: '58', peripheral: GPIOA, signal: 'GPIO, 6', pin_signal: PTA6/FTM0_CH3/TRACE_CLKOUT, direction: OUTPUT}
- {pin_num: '132', peripheral: FB, signal: 'AD, 1', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/UART0_COL_b/FTM0_CH5/FB_AD1/EWM_OUT_b}
- {pin_num: '131', peripheral: FB, signal: 'AD, 2', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN}
- {pin_num: '130', peripheral: FB, signal: 'AD, 3', pin_signal: PTD3/SPI0_SIN/UART2_TX/FB_AD3}
- {pin_num: '129', peripheral: FB, signal: 'AD, 4', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FB_AD4}
- {pin_num: '115', peripheral: FB, signal: 'AD, 5', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/I2S0_RX_FS/FB_AD5}
- {pin_num: '114', peripheral: FB, signal: 'AD, 6', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/I2S0_RX_BCLK/FB_AD6/FTM2_FLT0}
- {pin_num: '113', peripheral: FB, signal: 'AD, 7', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/I2S0_MCLK/FB_AD7}
- {pin_num: '112', peripheral: FB, signal: 'AD, 8', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS/FB_AD8}
- {pin_num: '111', peripheral: FB, signal: 'AD, 9', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK}
- {pin_num: '110', peripheral: FB, signal: 'AD, 10', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT}
- {pin_num: '109', peripheral: FB, signal: 'AD, 11', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT}
- {pin_num: '105', peripheral: FB, signal: 'AD, 12', pin_signal: ADC0_SE4b/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/I2S0_TX_FS}
- {pin_num: '104', peripheral: FB, signal: 'AD, 13', pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/I2S0_TXD0}
- {pin_num: '103', peripheral: FB, signal: 'AD, 14', pin_signal: ADC0_SE14/TSI0_CH13/PTC0/SPI0_PCS4/PDB0_EXTRG/FB_AD14/I2S0_TXD1}
- {pin_num: '97', peripheral: FB, signal: 'AD, 15', pin_signal: TSI0_CH11/PTB18/CAN0_TX/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/FTM2_QD_PHA}
- {pin_num: '137', peripheral: FB, signal: 'A, 16', pin_signal: PTD8/I2C0_SCL/UART5_RX/FB_A16}
- {pin_num: '138', peripheral: FB, signal: 'A, 17', pin_signal: PTD9/I2C0_SDA/UART5_TX/FB_A17}
- {pin_num: '139', peripheral: FB, signal: 'A, 18', pin_signal: PTD10/UART5_RTS_b/FB_A18}
- {pin_num: '96', peripheral: FB, signal: 'AD, 16', pin_signal: TSI0_CH10/PTB17/SPI1_SIN/UART0_TX/FB_AD16/EWM_OUT_b}
- {pin_num: '95', peripheral: FB, signal: 'AD, 17', pin_signal: TSI0_CH9/PTB16/SPI1_SOUT/UART0_RX/FB_AD17/EWM_IN}
- {pin_num: '92', peripheral: FB, signal: 'AD, 18', pin_signal: ADC1_SE15/PTB11/SPI1_SCK/UART3_TX/FB_AD18/FTM0_FLT2}
- {pin_num: '91', peripheral: FB, signal: 'AD, 19', pin_signal: ADC1_SE14/PTB10/SPI1_PCS0/UART3_RX/FB_AD19/FTM0_FLT1}
- {pin_num: '90', peripheral: FB, signal: 'AD, 20', pin_signal: PTB9/SPI1_PCS1/UART3_CTS_b/FB_AD20}
- {pin_num: '89', peripheral: FB, signal: 'AD, 21', pin_signal: PTB8/UART3_RTS_b/FB_AD21}
- {pin_num: '88', peripheral: FB, signal: 'AD, 22', pin_signal: ADC1_SE13/PTB7/FB_AD22}
- {pin_num: '87', peripheral: FB, signal: 'AD, 23', pin_signal: ADC1_SE12/PTB6/FB_AD23}
- {pin_num: '120', peripheral: FB, signal: 'AD, 24', pin_signal: PTC15/UART4_TX/FB_AD24}
- {pin_num: '119', peripheral: FB, signal: 'AD, 25', pin_signal: PTC14/UART4_RX/FB_AD25}
- {pin_num: '117', peripheral: FB, signal: 'AD, 27', pin_signal: PTC12/UART4_RTS_b/FB_AD27}
- {pin_num: '118', peripheral: FB, signal: 'AD, 26', pin_signal: PTC13/UART4_CTS_b/FB_AD26}
- {pin_num: '102', peripheral: FB, signal: 'AD, 28', pin_signal: PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28}
- {pin_num: '101', peripheral: FB, signal: 'AD, 29', pin_signal: PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT}
- {pin_num: '100', peripheral: FB, signal: 'AD, 30', pin_signal: PTB21/SPI2_SCK/FB_AD30/CMP1_OUT}
- {pin_num: '99', peripheral: FB, signal: 'AD, 31', pin_signal: PTB20/SPI2_PCS0/FB_AD31/CMP0_OUT}
- {pin_num: '127', peripheral: FB, signal: ALE_CS1_TS, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FB_ALE/FB_CS1_b/FB_TS_b}
- {pin_num: '128', peripheral: FB, signal: CS0, pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FB_CS0_b}
- {pin_num: '116', peripheral: FB, signal: RW, pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/I2S0_RXD1/FB_RW_b}
- {pin_num: '98', peripheral: FB, signal: OE, pin_signal: TSI0_CH12/PTB19/CAN0_RX/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB}
- {pin_num: '77', peripheral: FB, signal: 'A, 27', pin_signal: PTA26/MII0_TXD3/FB_A27}
- {pin_num: '123', peripheral: FB, signal: CS5_TSIZ1_BE23_16_BLS15_8, pin_signal: PTC16/CAN1_RX/UART3_RX/ENET0_1588_TMR0/FB_CS5_b/FB_TSIZ1/FB_BE23_16_b}
- {pin_num: '124', peripheral: FB, signal: CS4_TSIZ0_BE31_24_BLS7_0, pin_signal: PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_b}
- {pin_num: '66', peripheral: ENET, signal: RMII_CRS_DV, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2S0_RX_BCLK/I2S0_TXD1}
- {pin_num: '82', peripheral: ENET, signal: RMII_MDC, pin_signal: ADC0_SE9/ADC1_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHB}
- {pin_num: '81', peripheral: ENET, signal: RMII_MDIO, pin_signal: ADC0_SE8/ADC1_SE8/TSI0_CH0/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHA}
- {pin_num: '65', peripheral: ENET, signal: RMII_RXD0, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2S0_TX_FS/FTM1_QD_PHB}
- {pin_num: '64', peripheral: ENET, signal: RMII_RXD1, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2S0_TXD0/FTM1_QD_PHA}
- {pin_num: '55', peripheral: ENET, signal: RMII_RXER, pin_signal: PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b}
- {pin_num: '68', peripheral: ENET, signal: RMII_TXD0, pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1}
- {pin_num: '69', peripheral: ENET, signal: RMII_TXD1, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK}
- {pin_num: '67', peripheral: ENET, signal: rmii_txen, pin_signal: PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0}
- {pin_num: '72', peripheral: ENET, signal: RMII_CLKIN, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0}
- {pin_num: '4', peripheral: SDHC, signal: CMD, pin_signal: ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SDHC0_CMD/SPI1_SOUT, pull_select: up, pull_enable: enable}
- {pin_num: '2', peripheral: SDHC, signal: 'D, 0', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/SDHC0_D0/I2C1_SCL/SPI1_SIN, pull_select: up, pull_enable: enable}
- {pin_num: '1', peripheral: SDHC, signal: 'D, 1', pin_signal: ADC1_SE4a/PTE0/SPI1_PCS1/UART1_TX/SDHC0_D1/I2C1_SDA/RTC_CLKOUT, pull_select: up, pull_enable: enable}
- {pin_num: '7', peripheral: SDHC, signal: 'D, 3', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/UART3_TX/SDHC0_D3, pull_select: up, pull_enable: enable}
- {pin_num: '8', peripheral: SDHC, signal: 'D, 2', pin_signal: PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2, pull_select: up, pull_enable: enable}
- {pin_num: '3', peripheral: SDHC, signal: DCLK, pin_signal: ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b/SDHC0_DCLK, pull_select: up, pull_enable: enable}
- {pin_num: '106', peripheral: GPIOC, signal: 'GPIO, 3', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: '126', peripheral: GPIOC, signal: 'GPIO, 19', pin_signal: PTC19/UART3_CTS_b/ENET0_1588_TMR3/FB_CS3_b/FB_BE7_0_b/FB_TA_b, direction: OUTPUT, gpio_init_state: 'true'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
/* Port B Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortB);
/* Port C Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC);
/* Port D Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortD);
/* Port E Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortE);
gpio_pin_config_t BUZZER_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 0U
};
/* Initialize GPIO functionality on pin PTA6 (pin 58) */
GPIO_PinInit(BOARD_INITPINS_BUZZER_GPIO, BOARD_INITPINS_BUZZER_PIN, &BUZZER_config);
gpio_pin_config_t TFT_BL_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PTC3 (pin 106) */
GPIO_PinInit(BOARD_INITPINS_TFT_BL_GPIO, BOARD_INITPINS_TFT_BL_PIN, &TFT_BL_config);
gpio_pin_config_t TFT_RESET_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PTC19 (pin 126) */
GPIO_PinInit(BOARD_INITPINS_TFT_RESET_GPIO, BOARD_INITPINS_TFT_RESET_PIN, &TFT_RESET_config);
/* PORTA12 (pin 64) is configured as RMII0_RXD1 */
PORT_SetPinMux(PORTA, 12U, kPORT_MuxAlt4);
/* PORTA13 (pin 65) is configured as RMII0_RXD0 */
PORT_SetPinMux(PORTA, 13U, kPORT_MuxAlt4);
/* PORTA14 (pin 66) is configured as RMII0_CRS_DV */
PORT_SetPinMux(PORTA, 14U, kPORT_MuxAlt4);
/* PORTA15 (pin 67) is configured as RMII0_TXEN */
PORT_SetPinMux(PORTA, 15U, kPORT_MuxAlt4);
/* PORTA16 (pin 68) is configured as RMII0_TXD0 */
PORT_SetPinMux(PORTA, 16U, kPORT_MuxAlt4);
/* PORTA17 (pin 69) is configured as RMII0_TXD1 */
PORT_SetPinMux(PORTA, 17U, kPORT_MuxAlt4);
/* PORTA18 (pin 72) is configured as EXTAL0 */
PORT_SetPinMux(PORTA, 18U, kPORT_PinDisabledOrAnalog);
/* PORTA26 (pin 77) is configured as FB_A27 */
PORT_SetPinMux(PORTA, 26U, kPORT_MuxAlt6);
/* PORTA5 (pin 55) is configured as RMII0_RXER */
PORT_SetPinMux(PORTA, 5U, kPORT_MuxAlt4);
/* PORTA6 (pin 58) is configured as PTA6 */
PORT_SetPinMux(BOARD_INITPINS_BUZZER_PORT, BOARD_INITPINS_BUZZER_PIN, kPORT_MuxAsGpio);
/* PORTB0 (pin 81) is configured as RMII0_MDIO */
PORT_SetPinMux(PORTB, 0U, kPORT_MuxAlt4);
/* PORTB1 (pin 82) is configured as RMII0_MDC */
PORT_SetPinMux(PORTB, 1U, kPORT_MuxAlt4);
/* PORTB10 (pin 91) is configured as FB_AD19 */
PORT_SetPinMux(PORTB, 10U, kPORT_MuxAlt5);
/* PORTB11 (pin 92) is configured as FB_AD18 */
PORT_SetPinMux(PORTB, 11U, kPORT_MuxAlt5);
/* PORTB16 (pin 95) is configured as FB_AD17 */
PORT_SetPinMux(PORTB, 16U, kPORT_MuxAlt5);
/* PORTB17 (pin 96) is configured as FB_AD16 */
PORT_SetPinMux(PORTB, 17U, kPORT_MuxAlt5);
/* PORTB18 (pin 97) is configured as FB_AD15 */
PORT_SetPinMux(PORTB, 18U, kPORT_MuxAlt5);
/* PORTB19 (pin 98) is configured as FB_OE_b */
PORT_SetPinMux(PORTB, 19U, kPORT_MuxAlt5);
/* PORTB20 (pin 99) is configured as FB_AD31 */
PORT_SetPinMux(PORTB, 20U, kPORT_MuxAlt5);
/* PORTB21 (pin 100) is configured as FB_AD30 */
PORT_SetPinMux(PORTB, 21U, kPORT_MuxAlt5);
/* PORTB22 (pin 101) is configured as FB_AD29 */
PORT_SetPinMux(PORTB, 22U, kPORT_MuxAlt5);
/* PORTB23 (pin 102) is configured as FB_AD28 */
PORT_SetPinMux(PORTB, 23U, kPORT_MuxAlt5);
/* PORTB6 (pin 87) is configured as FB_AD23 */
PORT_SetPinMux(PORTB, 6U, kPORT_MuxAlt5);
/* PORTB7 (pin 88) is configured as FB_AD22 */
PORT_SetPinMux(PORTB, 7U, kPORT_MuxAlt5);
/* PORTB8 (pin 89) is configured as FB_AD21 */
PORT_SetPinMux(PORTB, 8U, kPORT_MuxAlt5);
/* PORTB9 (pin 90) is configured as FB_AD20 */
PORT_SetPinMux(PORTB, 9U, kPORT_MuxAlt5);
/* PORTC0 (pin 103) is configured as FB_AD14 */
PORT_SetPinMux(PORTC, 0U, kPORT_MuxAlt5);
/* PORTC1 (pin 104) is configured as FB_AD13 */
PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt5);
/* PORTC10 (pin 115) is configured as FB_AD5 */
PORT_SetPinMux(PORTC, 10U, kPORT_MuxAlt5);
/* PORTC11 (pin 116) is configured as FB_RW_b */
PORT_SetPinMux(PORTC, 11U, kPORT_MuxAlt5);
/* PORTC12 (pin 117) is configured as FB_AD27 */
PORT_SetPinMux(PORTC, 12U, kPORT_MuxAlt5);
/* PORTC13 (pin 118) is configured as FB_AD26 */
PORT_SetPinMux(PORTC, 13U, kPORT_MuxAlt5);
/* PORTC14 (pin 119) is configured as FB_AD25 */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt5);
/* PORTC15 (pin 120) is configured as FB_AD24 */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt5);
/* PORTC16 (pin 123) is configured as FB_CS5_b */
PORT_SetPinMux(PORTC, 16U, kPORT_MuxAlt5);
/* PORTC17 (pin 124) is configured as FB_CS4_b */
PORT_SetPinMux(PORTC, 17U, kPORT_MuxAlt5);
/* PORTC19 (pin 126) is configured as PTC19 */
PORT_SetPinMux(BOARD_INITPINS_TFT_RESET_PORT, BOARD_INITPINS_TFT_RESET_PIN, kPORT_MuxAsGpio);
/* PORTC2 (pin 105) is configured as FB_AD12 */
PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt5);
/* PORTC3 (pin 106) is configured as PTC3 */
PORT_SetPinMux(BOARD_INITPINS_TFT_BL_PORT, BOARD_INITPINS_TFT_BL_PIN, kPORT_MuxAsGpio);
/* PORTC4 (pin 109) is configured as FB_AD11 */
PORT_SetPinMux(PORTC, 4U, kPORT_MuxAlt5);
/* PORTC5 (pin 110) is configured as FB_AD10 */
PORT_SetPinMux(PORTC, 5U, kPORT_MuxAlt5);
/* PORTC6 (pin 111) is configured as FB_AD9 */
PORT_SetPinMux(PORTC, 6U, kPORT_MuxAlt5);
/* PORTC7 (pin 112) is configured as FB_AD8 */
PORT_SetPinMux(PORTC, 7U, kPORT_MuxAlt5);
/* PORTC8 (pin 113) is configured as FB_AD7 */
PORT_SetPinMux(PORTC, 8U, kPORT_MuxAlt5);
/* PORTC9 (pin 114) is configured as FB_AD6 */
PORT_SetPinMux(PORTC, 9U, kPORT_MuxAlt5);
/* PORTD0 (pin 127) is configured as FB_CS1_b */
PORT_SetPinMux(PORTD, 0U, kPORT_MuxAlt5);
/* PORTD1 (pin 128) is configured as FB_CS0_b */
PORT_SetPinMux(PORTD, 1U, kPORT_MuxAlt5);
/* PORTD10 (pin 139) is configured as FB_A18 */
PORT_SetPinMux(PORTD, 10U, kPORT_MuxAlt6);
/* PORTD2 (pin 129) is configured as FB_AD4 */
PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt5);
/* PORTD3 (pin 130) is configured as FB_AD3 */
PORT_SetPinMux(PORTD, 3U, kPORT_MuxAlt5);
/* PORTD4 (pin 131) is configured as FB_AD2 */
PORT_SetPinMux(PORTD, 4U, kPORT_MuxAlt5);
/* PORTD5 (pin 132) is configured as FB_AD1 */
PORT_SetPinMux(PORTD, 5U, kPORT_MuxAlt5);
/* PORTD6 (pin 133) is configured as UART0_RX */
PORT_SetPinMux(PORTD, 6U, kPORT_MuxAlt3);
/* PORTD7 (pin 136) is configured as UART0_TX */
PORT_SetPinMux(PORTD, 7U, kPORT_MuxAlt3);
/* PORTD8 (pin 137) is configured as FB_A16 */
PORT_SetPinMux(PORTD, 8U, kPORT_MuxAlt6);
/* PORTD9 (pin 138) is configured as FB_A17 */
PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt6);
/* PORTE0 (pin 1) is configured as SDHC0_D1 */
PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt4);
PORTE->PCR[0] = ((PORTE->PCR[0] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
/* PORTE1 (pin 2) is configured as SDHC0_D0 */
PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt4);
PORTE->PCR[1] = ((PORTE->PCR[1] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
/* PORTE2 (pin 3) is configured as SDHC0_DCLK */
PORT_SetPinMux(PORTE, 2U, kPORT_MuxAlt4);
PORTE->PCR[2] = ((PORTE->PCR[2] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
/* PORTE3 (pin 4) is configured as SDHC0_CMD */
PORT_SetPinMux(PORTE, 3U, kPORT_MuxAlt4);
PORTE->PCR[3] = ((PORTE->PCR[3] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
/* PORTE4 (pin 7) is configured as SDHC0_D3 */
PORT_SetPinMux(PORTE, 4U, kPORT_MuxAlt4);
PORTE->PCR[4] = ((PORTE->PCR[4] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
/* PORTE5 (pin 8) is configured as SDHC0_D2 */
PORT_SetPinMux(PORTE, 5U, kPORT_MuxAlt4);
PORTE->PCR[5] = ((PORTE->PCR[5] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding Port Pull Enable Register field is set. */
| (uint32_t)(kPORT_PullUp));
SIM->SOPT2 = ((SIM->SOPT2 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT2_RMIISRC_MASK)))
/* RMII clock source select: EXTAL clock. */
| SIM_SOPT2_RMIISRC(SOPT2_RMIISRC_EXTAL));
SIM->SOPT5 = ((SIM->SOPT5 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))
/* UART 0 transmit data source select: UART0_TX pin. */
| SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)
/* UART 0 receive data source select: UART0_RX pin. */
| SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX));
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
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