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N32WB031_Template
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Initial commit. 

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2023-10-20 23:07:55 +08:00
commit a6cad506de
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
11 changed files with 721 additions and 0 deletions
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BasedOnStyle: Google
IndentWidth: 4
AlignConsecutiveMacros: Consecutive
AlignConsecutiveDeclarations: Consecutive
AlignConsecutiveAssignments: Consecutive
AllowShortFunctionsOnASingleLine: None
BreakBeforeBraces: Custom
BraceWrapping:
AfterEnum: false
AfterStruct: false
SplitEmptyFunction: false
ColumnLimit: 120

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/cmake-build-*
/build
/board/*.bak
/.vscode

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[submodule "SDK"]
path = SDK
url = https://git.minori.work/Embedded_SDK/N32WB031_SDK.git

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cmake_minimum_required(VERSION 3.10)
project(n32wb03x_template)
enable_language(CXX)
enable_language(ASM)
# Different linker scripts
set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/gcc/n32wb03x_FLASH.ld")
set(TARGET_SOURCES
"SDK/firmware/n32wb03x_std_periph_driver/src/misc.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_adc.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_crc.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_dma.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_exti.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_gpio.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_i2c.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_iwdg.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_keyscan.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_lpuart.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_pwr.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_qflash.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_rcc.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_rtc.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_spi.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_tim.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_usart.c"
"SDK/firmware/n32wb03x_std_periph_driver/src/n32wb03x_wwdg.c"
"board/n32wb03x_it.c"
"board/system_n32wb03x.c"
"SDK/gcc/startup_n32wb03x.S"
"src/main.c"
)
set(TARGET_C_DEFINES
"N32WB03X"
"USE_STDPERIPH_DRIVER"
)
set(TARGET_C_INCLUDES
"SDK/firmware/CMSIS/core"
"SDK/firmware/CMSIS/device"
"SDK/firmware/n32wb03x_std_periph_driver/inc"
"board"
"include"
)
# Shared libraries linked with application
set(TARGET_LIBS
"c"
"m"
"nosys"
)
# Shared library and linker script search paths
set(TARGET_LIB_DIRECTORIES
)
# Conditional flags
# DEBUG
set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0 -g")
set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0 -g")
set(CMAKE_ASM_FLAGS_DEBUG "-DDEBUG -O0 -g")
# RELEASE
set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto")
# Final compiler flags
set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -ffreestanding -fdata-sections -ffunction-sections")
set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections")
# Shared sources, includes and definitions
add_compile_definitions(${TARGET_C_DEFINES})
include_directories(${TARGET_C_INCLUDES})
link_directories(${TARGET_LIB_DIRECTORIES})
link_libraries(${TARGET_LIBS})
# Main targets are added here
# Create ELF
add_executable("${CMAKE_PROJECT_NAME}_FLASH.elf" ${TARGET_SOURCES})
target_compile_definitions("${CMAKE_PROJECT_NAME}_FLASH.elf"
PRIVATE ${TARGET_C_DEFINES_XIP}
)
target_link_options("${CMAKE_PROJECT_NAME}_FLASH.elf"
PRIVATE "-T${TARGET_LDSCRIPT_FLASH}"
PRIVATE "-Wl,--Map=${CMAKE_PROJECT_NAME}_FLASH.map"
)
set_property(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" APPEND
PROPERTY ADDITIONAL_CLEAN_FILES "${CMAKE_PROJECT_NAME}_FLASH.map"
)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH.hex"
COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLASH.elf" "${CMAKE_PROJECT_NAME}_FLASH.hex"
DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.elf"
)
add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.hex")
if(DEFINED TARGET_TOOLCHAIN_SIZE)
add_custom_command(TARGET "${CMAKE_PROJECT_NAME}_FLASH.elf" POST_BUILD
COMMAND ${TARGET_TOOLCHAIN_SIZE} "${CMAKE_PROJECT_NAME}_FLASH.elf"
)
endif()

1
SDK Submodule

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Subproject commit 0e0fa208b6f44c1bf0e0598493a0d71987414a9f

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arm-none-eabi.cmake Normal file
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# Poor old Windows...
if(WIN32)
set(CMAKE_SYSTEM_NAME "Generic")
endif()
set(CMAKE_C_COMPILER arm-none-eabi-gcc)
set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
# Optionally set size binary name, for elf section size reporting.
set(TARGET_TOOLCHAIN_SIZE arm-none-eabi-size)
set(CMAKE_C_FLAGS_INIT "-mcpu=cortex-m0plus -mthumb -mfloat-abi=soft")
set(CMAKE_CXX_FLAGS_INIT "-mcpu=cortex-m0plus -mthumb -mfloat-abi=soft")
set(CMAKE_EXE_LINKER_FLAGS_INIT "-specs=nano.specs -specs=nosys.specs -Wl,--print-memory-usage -Wl,--no-warn-rwx-segments")
# Make CMake happy about those compilers
set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY")

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32wb03x_it.c
* @author Nations Firmware Team
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#include "n32wb03x_it.h"
/** @addtogroup N32WB03X_StdPeriph_Template
* @{
*/
/******************************************************************************/
/* Cortex-M0 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles PendSV_Handler exception.
*/
void PendSV_Handler(void)
{
}
/*******************************************************************************/
/* N32WB03X Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_n32wb03x.S). */
/*******************************************************************************/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32wb03x_it.h
* @author Nations Firmware Team
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32WB03X_IT_H__
#define __N32WB03X_IT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32wb03x.h"
void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32WB03X_IT_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file system_n32wb03x.c
* @author Nations Firmware Team
* @version v1.0.2
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#include "n32wb03x.h"
#include "string.h"
/* Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your
device's maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume
that:
- HSI is configer as 64M and used to driverd the system clock.
- External 32MHz crystal use for Bluetooth RF system only.
- If Bluetooth stack is enable, we should select the LSI or LSE when configer
the Bluetooth stack only.
*/
#define SYSCLK_USE_HSI 1
#define SYSCLK_USE_HSE 0
#ifndef SYSCLK_FREQ
#define SYSCLK_FREQ HSI_VALUE
#endif
/*
* SYSCLK_SRC *
** SYSCLK_USE_HSI **
** SYSCLK_USE_HSE **
*/
#ifndef SYSCLK_SRC
#define SYSCLK_SRC SYSCLK_USE_HSI
#endif
#define TRIM_STORE_ADDR 0x1000
#define TRIM_READ_CMD_CODE_LEN 0x140
#define TRIM_READ_CMD_CODE_CRC 0x3aa0
const unsigned char TRIM_READ_CMD_CODE[] ={
0x40,0xba,0x70,0x47,0xc0,0xba,0x70,0x47,0x01,0x38,0xfd,0xd1,0x70,0x47,0x00,0x00,
0xf7,0xb5,0x03,0x25,0xad,0x06,0x28,0x6a,0x82,0xb0,0x16,0x46,0x0c,0x46,0x40,0x08,
0x40,0x00,0x28,0x62,0x28,0x6a,0x02,0x21,0x08,0x43,0x28,0x62,0x28,0x6a,0x80,0x07,
0xfc,0xd4,0x66,0x20,0x68,0x60,0x01,0x27,0x2f,0x61,0xa8,0x6a,0xc0,0x05,0xfc,0xd5,
0x99,0x20,0x68,0x60,0x2f,0x61,0xa8,0x6a,0xc0,0x05,0xfc,0xd5,0xff,0x20,0x91,0x30,
0xff,0xf7,0xda,0xff,0xff,0x23,0x01,0x33,0xab,0x62,0x68,0x46,0xef,0x60,0x35,0x21,
0x69,0x60,0x2f,0x61,0xa9,0x6a,0xc9,0x05,0xfc,0xd5,0xab,0x62,0xa9,0x69,0xef,0x60,
0xc9,0xb2,0x05,0x22,0x6a,0x60,0x2f,0x61,0xaa,0x6a,0xd2,0x05,0xfc,0xd5,0xab,0x62,
0xaa,0x69,0x09,0x02,0xd2,0xb2,0x11,0x43,0x01,0x80,0xc8,0x07,0x02,0xd0,0x03,0x20,
0x05,0xb0,0xf0,0xbd,0xab,0x62,0x68,0x69,0xff,0x21,0x08,0x31,0x88,0x43,0x68,0x61,
0x68,0x69,0xc9,0x1e,0x08,0x43,0x68,0x61,0x02,0x98,0x00,0x02,0x48,0x30,0x68,0x60,
0x08,0x20,0xa8,0x60,0xee,0x60,0x2f,0x61,0xa8,0x6a,0xc0,0x05,0xfc,0xd5,0xff,0x20,
0x01,0x30,0xa8,0x62,0x00,0x23,0xf6,0x1c,0xb0,0x08,0x0e,0xd0,0xb2,0x08,0x11,0x48,
0x00,0x68,0x99,0x00,0x60,0x54,0x06,0x0a,0x09,0x19,0x4e,0x70,0x06,0x0c,0x00,0x0e,
0x8e,0x70,0x5b,0x1c,0xc8,0x70,0x9a,0x42,0xf1,0xd8,0xff,0x20,0x01,0x30,0xa8,0x62,
0x68,0x69,0xff,0x21,0x08,0x31,0x88,0x43,0x68,0x61,0x68,0x69,0x38,0x43,0x68,0x61,
0x28,0x6a,0x80,0x08,0x80,0x00,0x28,0x62,0x28,0x6a,0x38,0x43,0x28,0x62,0x00,0x20,
0x05,0xb0,0xf0,0xbd,0x80,0x00,0x00,0x0c,0x03,0x20,0x80,0x06,0x41,0x69,0xff,0x22,
0x08,0x32,0x91,0x43,0x41,0x61,0x42,0x69,0x01,0x21,0x0a,0x43,0x42,0x61,0x02,0x6a,
0x92,0x08,0x92,0x00,0x02,0x62,0x02,0x6a,0x0a,0x43,0x02,0x62,0x70,0x47,0x00,0x00,
};
typedef uint32_t (*trim_read_cmd_func_t)(uint32_t,uint8_t*,uint32_t);
trim_stored_t trim_stored;
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
static void RCC_HsiCalib(uint32_t systemfreq);
void SystemTrimValueRead(uint8_t* p_data,uint32_t byte_length)
{
uint32_t ramcode[TRIM_READ_CMD_CODE_LEN/4 +1 ];
trim_read_cmd_func_t trim_read_cmd_func = (trim_read_cmd_func_t)((uint8_t*)&ramcode[0] + 0x11);
memcpy((void*)ramcode,(const void*)TRIM_READ_CMD_CODE,TRIM_READ_CMD_CODE_LEN);
(*trim_read_cmd_func)(TRIM_STORE_ADDR, p_data, byte_length);
}
trim_stored_t* SystemTrimValueGet(void)
{
//read the trim value if not in RAM yet
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
SystemTrimValueRead((uint8_t*)&trim_stored,sizeof(trim_stored));
}
//check again if read trim value sucessful
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
return NULL;
}else{
return &trim_stored;
}
}
uint8_t* SystemGetUUID(void)
{
//read the trim value if not in RAM yet
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
SystemTrimValueRead((uint8_t*)&trim_stored,sizeof(trim_stored));
}
//check again if read trim value sucessful
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
return NULL;
}else{
return trim_stored.flash_uuid;
}
}
uint8_t* SystemGetMacAddr(void)
{
//read the trim value if not in RAM yet
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
SystemTrimValueRead((uint8_t*)&trim_stored,sizeof(trim_stored));
}
//check again if read trim value sucessful
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
return NULL;
}else{
return &trim_stored.flash_uuid[5];
}
}
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
*/
void SystemInit(void)
{
uint32_t tmp;
RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR; // PWR enable
PWR->VTOR_REG = 0x81000000; //set irq vtor to flash address
*(uint32_t*)0x40007014 = 0x0000080F;
*(uint32_t*)0x40007020 = 0x00020018;
*(uint32_t*)0x40011000 &= ~0xC000;
SystemTrimValueRead((uint8_t*)&trim_stored,sizeof(trim_stored));
/* check otp has been write */
if(trim_stored.stote_rc64m_trim_value == 0xFFFFFFFF || trim_stored.stote_rc64m_trim_value == 0)
{
RCC->CFG |= RCC_CFG_HSISRC_DIV1; // USE HSI as system clock
RCC->CFG &= ~RCC_CFG_APB1PRES;
RCC->CFG |= RCC_HCLK_DIV2; //APB1 = HCLK/2, APB1 max is 32M
/* Calib from HSE */
RCC_HsiCalib(SYSCLK_FREQ);
}
else
{
tmp = (PWR->reserved4)&(~0X1F);
tmp |= (trim_stored.stote_bg_vtrim_value)&0X1F;
PWR->reserved4 = tmp;
if(SYSCLK_FREQ == 64000000)
{
RCC->CTRL &= ~0x8000;// Set HSI as 64M
/* Configures LSI trim */
tmp = RCC->CTRL & ~(0x7F << 8); // TRIM 8-14 bit
RCC->CTRL = tmp|(trim_stored.stote_rc64m_trim_value << 8);// clear and set TRIM value
RCC->CFG |= RCC_CFG_HSISRC_DIV1; // USE HSI as system clock
RCC->CFG &= ~RCC_CFG_APB1PRES;
RCC->CFG |= RCC_HCLK_DIV2; //APB1 = HCLK/2, APB1 max is 32M
}
// else if(SYSCLK_FREQ == 96000000)
// {
// RCC->CTRL |= 0x8000; // Set HSI as 96M
// /* Configures LSI trim */
// tmp = RCC->CTRL & ~(0x7F << 8); // TRIM 8-14 bit
// RCC->CTRL = tmp|(trim_stored.stote_rc96m_trim_value << 8);// clear and set TRIM value
//
// RCC->CFG |= RCC_CFG_HSISRC_DIV1; // USE HSI as system clock
// tmp = RCC->CFG & ~RCC_CFG_APB1PRES;
// RCC->CFG |= RCC_HCLK_DIV4; //APB1 = HCLK/4, APB1 max is 32M
//
// tmp = RCC->CFG & ~RCC_CFG_APB2PRES;
// RCC->CFG |= RCC_HCLK_DIV4<<3; //APB2 = HCLK/2, APB1 max is 64M
// }
/* Configures LSI trim */
RCC->LSCTRL &= ~RCC_LSCTRL_LSTTRIM;
RCC->LSCTRL |= trim_stored.stote_rc32768_trim_value << 8;
}
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or
* configure other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any
* configuration based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*/
void SystemCoreClockUpdate(void)
{
SystemCoreClock = HSI_VALUE;
}
/**
* @brief dealy cycles.
*/
__attribute__((naked)) void system_delay_cycles(uint32_t i)
{
asm volatile(
"sub r0, #1\n"
"bne system_delay_cycles\n"
"bx lr"
);
}
/**
* @brief Dealy 10 us
*/
void system_delay_n_10us(uint32_t value)
{
system_delay_cycles(107*value);
}
/**
* @brief Enable the HSI and calibration it.
*/
static void RCC_HsiCalib(uint32_t systemfreq)
{
uint32_t g_hsi_accuracy = 0;
uint32_t g_timeoutcnt = 1000;
uint32_t g_cal_hsi_cnt_value = 1024;
uint32_t delta =0;
uint32_t min = 0;
uint32_t max = 127; //32M TRIM 8-14 bit
uint32_t mid = (RCC->CTRL >> 8) & 0x7F;
uint16_t count_value = 0;
uint32_t hsi_timeoutcnt = 0;
uint8_t tmp_trim;
if(systemfreq == 64000000)
{
RCC->CTRL &= ~0x8000;
g_cal_hsi_cnt_value = 2048; //for 64M
}
else
{
RCC->CTRL |= 0x8000;
g_cal_hsi_cnt_value = 3072; //for 96M
}
do{
uint32_t tmp = RCC->CTRL & ~(0x7F << 8); //32M TRIM 8-14 bit
RCC->CTRL = tmp| (mid << 8); // clear and set TRIM value //and start to cnt
system_delay_cycles(5); // delay scape
while(1)
{
system_delay_cycles(1);
if((RCC->OSCFCSR & 0x02))
{
break;
}
if(hsi_timeoutcnt++ > g_timeoutcnt)
{
break;
}
}
count_value = RCC->OSCFCHSICNT; //ready cnt value
if(count_value > g_cal_hsi_cnt_value)
{
delta = count_value - g_cal_hsi_cnt_value;
}
else
{
delta = g_cal_hsi_cnt_value - count_value;
}
if(count_value >= g_cal_hsi_cnt_value)
{
max = mid;
}
else
{
min = mid;
}
tmp_trim = (min + max)/2;
if(tmp_trim == mid ) //0 and 127 if not used
{
break;
}
mid = tmp_trim;
}while(delta > g_hsi_accuracy);
RCC->CFG &= ~1;
while((RCC->CFG & (1<<2)));
}

31
pyocd_user.py Normal file
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def will_connect(board):
# Use "cortex_m" as target, remove the following default regions:
old_region = target.memory_map.get_first_matching_region(name="Code")
target.memory_map.remove_region(old_region)
old_region = target.memory_map.get_first_matching_region(name="SRAM")
target.memory_map.remove_region(old_region)
old_region = target.memory_map.get_first_matching_region(name="RAM1")
target.memory_map.remove_region(old_region)
old_region = target.memory_map.get_first_matching_region(name="RAM2")
target.memory_map.remove_region(old_region)
flash = FlashRegion(
name="FLASH",
start=0x01000000,
length=0x00040000,
are_erased_sectors_readable=False, # Never seen that usage for something other than LPC5500 ...
flm="SDK/utilities/N32WB03x.FLM"
)
ram = RamRegion(
name="SRAM",
start=0x20000000,
length=0x0000C000
)
target.memory_map.add_region(ram)
target.memory_map.add_region(flash)

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src/main.c Normal file
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#include "n32wb03x.h"
#include "n32wb03x_gpio.h"
static volatile uint32_t uwTick = 0U;
static void HAL_Delay(uint32_t msec);
int main(void) {
SysTick_Config(SystemCoreClock / 1000);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitType led;
led.Pin = GPIO_PIN_0;
led.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
led.GPIO_Speed = GPIO_SPEED_LOW;
led.GPIO_Current = GPIO_DC_12MA;
led.GPIO_Pull = GPIO_NO_PULL;
led.GPIO_Alternate = GPIO_AF0;
GPIO_InitPeripheral(GPIOB, &led);
led.Pin = GPIO_PIN_6;
GPIO_InitPeripheral(GPIOA, &led);
GPIO_TogglePin(GPIOB, GPIO_PIN_0);
for (;;) {
GPIO_TogglePin(GPIOB, GPIO_PIN_0);
GPIO_TogglePin(GPIOA, GPIO_PIN_6);
HAL_Delay(500);
}
}
static void HAL_Delay(uint32_t msec) {
uint32_t t_start = uwTick;
while (uwTick - t_start < msec) {
__WFI();
}
}
void SysTick_Handler(void) {
uwTick++;
}