Fixed SysTick clock source and debug server script.

run_debugserver.sh

@@ -14,7 +14,7 @@ run_openocd_jlink() {
 run_pyocd() {
 	echo "Note: pyOCD uses low level DAP APIs provided by J-LINK," \
 		"speed settings and other functions may not available."
-	pyocd gdbserver -t stm32h750vbtx -f 4m --persist
+	pyocd gdbserver -t nuc220le3an -f 4m --persist
 }
 
 case $1 in

src/main.c

@@ -58,9 +58,13 @@ static void system_clock_config(void) {
      * Clear the latch manually after clock changes.
      */
     SYS_UnlockReg();
-    CLK->CLKSEL0 = CLK_CLKSEL0_STCLK_S_HCLK | CLK_CLKSEL0_HCLK_S_PLL; /* SysTick and HCLK */
+    CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL; /* HCLK */
     SYS_LockReg();
 
+    SysTick->CTRL &= ~(SysTick_CTRL_CLKSOURCE_Msk); /* SysTick */
+    SysTick->CTRL |= CLK_CLKSEL0_STCLK_S_HCLK;
+
+
     CLK->CLKSEL1 = 0xFFFFFFFF; /* Reset value */
     CLK->CLKSEL1 &= ~CLK_CLKSEL1_SPI0_S_Msk;
     CLK->CLKSEL1 |= CLK_CLKSEL1_SPI0_S_HCLK;