From ff9f140a9b42df4ab4d998852953ed6937550a35 Mon Sep 17 00:00:00 2001 From: imi415 Date: Fri, 18 Feb 2022 16:00:01 +0800 Subject: [PATCH] Initial commit. --- .clang-format | 11 + .gitignore | 6 + .../CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 46999 bytes BSP/CMSIS/Include/arm_common_tables.h | 37 + BSP/CMSIS/Include/arm_math.h | 7556 +++++++++++ BSP/CMSIS/Include/core_cm0.h | 673 + BSP/CMSIS/Include/core_cm0plus.h | 778 ++ BSP/CMSIS/Include/core_cm3.h | 1612 +++ BSP/CMSIS/Include/core_cm4.h | 1757 +++ BSP/CMSIS/Include/core_cm4_simd.h | 649 + BSP/CMSIS/Include/core_cmFunc.h | 620 + BSP/CMSIS/Include/core_cmInstr.h | 624 + BSP/CMSIS/Include/core_sc000.h | 798 ++ BSP/CMSIS/Include/core_sc300.h | 1583 +++ BSP/CMSIS/index.html | 14 + .../NUC200Series/Include/NUC200Series.h | 11030 ++++++++++++++++ .../Include/system_NUC200Series.h | 66 + .../Source/ARM/startup_NUC200Series.s | 410 + .../NUC200Series/Source/GCC/_syscalls.c | 1168 ++ .../NUC200Series/Source/GCC/gcc_arm.ld | 195 + .../NUC200Series/Source/GCC/semihosting.h | 116 + .../Source/GCC/startup_NUC200Series.S | 316 + .../Source/IAR/startup_NUC200Series.s | 184 + .../NUC200Series/Source/system_NUC200Series.c | 75 + BSP/README.md | 58 + BSP/SmartcardLib/Include/sclib.h | 307 + BSP/SmartcardLib/SmartCardLib.lib | Bin 0 -> 40904 bytes BSP/SmartcardLib/SmartCardLib_IAR.a | Bin 0 -> 40200 bytes BSP/SmartcardLib/SmartCardLib_Keil.lib | Bin 0 -> 42080 bytes BSP/SmartcardLib/libsmartcard.a | Bin 0 -> 118192 bytes BSP/StdDriver/inc/acmp.h | 163 + BSP/StdDriver/inc/adc.h | 362 + BSP/StdDriver/inc/clk.h | 561 + BSP/StdDriver/inc/crc.h | 160 + BSP/StdDriver/inc/fmc.h | 456 + BSP/StdDriver/inc/gpio.h | 441 + BSP/StdDriver/inc/i2c.h | 206 + BSP/StdDriver/inc/i2s.h | 300 + BSP/StdDriver/inc/pdma.h | 197 + BSP/StdDriver/inc/ps2.h | 250 + BSP/StdDriver/inc/pwm.h | 237 + BSP/StdDriver/inc/rtc.h | 258 + BSP/StdDriver/inc/sc.h | 275 + BSP/StdDriver/inc/spi.h | 392 + BSP/StdDriver/inc/sys.h | 1462 ++ BSP/StdDriver/inc/timer.h | 394 + BSP/StdDriver/inc/uart.h | 460 + BSP/StdDriver/inc/usbd.h | 668 + BSP/StdDriver/inc/wdt.h | 201 + BSP/StdDriver/inc/wwdt.h | 145 + BSP/StdDriver/src/acmp.c | 83 + BSP/StdDriver/src/adc.c | 165 + BSP/StdDriver/src/clk.c | 749 ++ BSP/StdDriver/src/crc.c | 102 + BSP/StdDriver/src/fmc.c | 282 + BSP/StdDriver/src/gpio.c | 100 + BSP/StdDriver/src/i2c.c | 389 + BSP/StdDriver/src/i2s.c | 204 + BSP/StdDriver/src/pdma.c | 284 + BSP/StdDriver/src/ps2.c | 201 + BSP/StdDriver/src/pwm.c | 672 + BSP/StdDriver/src/retarget.c | 760 ++ BSP/StdDriver/src/rtc.c | 786 ++ BSP/StdDriver/src/sc.c | 280 + BSP/StdDriver/src/spi.c | 638 + BSP/StdDriver/src/sys.c | 206 + BSP/StdDriver/src/timer.c | 269 + BSP/StdDriver/src/uart.c | 495 + BSP/StdDriver/src/usbd.c | 689 + BSP/StdDriver/src/wdt.c | 71 + BSP/StdDriver/src/wwdt.c | 72 + CMakeLists.txt | 117 + arm-none-eabi.cmake | 4 + run_debugserver.sh | 38 + src/main.c | 8 + 75 files changed, 45895 insertions(+) create mode 100644 .clang-format create mode 100644 .gitignore create mode 100644 BSP/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf create mode 100644 BSP/CMSIS/Include/arm_common_tables.h create mode 100644 BSP/CMSIS/Include/arm_math.h create mode 100644 BSP/CMSIS/Include/core_cm0.h create mode 100644 BSP/CMSIS/Include/core_cm0plus.h create mode 100644 BSP/CMSIS/Include/core_cm3.h create mode 100644 BSP/CMSIS/Include/core_cm4.h create mode 100644 BSP/CMSIS/Include/core_cm4_simd.h create mode 100644 BSP/CMSIS/Include/core_cmFunc.h create mode 100644 BSP/CMSIS/Include/core_cmInstr.h create mode 100644 BSP/CMSIS/Include/core_sc000.h create mode 100644 BSP/CMSIS/Include/core_sc300.h create mode 100644 BSP/CMSIS/index.html create mode 100644 BSP/Device/Nuvoton/NUC200Series/Include/NUC200Series.h create mode 100644 BSP/Device/Nuvoton/NUC200Series/Include/system_NUC200Series.h create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/ARM/startup_NUC200Series.s create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/GCC/_syscalls.c create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/GCC/gcc_arm.ld create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/GCC/semihosting.h create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/GCC/startup_NUC200Series.S create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/IAR/startup_NUC200Series.s create mode 100644 BSP/Device/Nuvoton/NUC200Series/Source/system_NUC200Series.c create mode 100644 BSP/README.md create mode 100644 BSP/SmartcardLib/Include/sclib.h create mode 100644 BSP/SmartcardLib/SmartCardLib.lib create mode 100644 BSP/SmartcardLib/SmartCardLib_IAR.a create mode 100644 BSP/SmartcardLib/SmartCardLib_Keil.lib create mode 100644 BSP/SmartcardLib/libsmartcard.a create mode 100644 BSP/StdDriver/inc/acmp.h create mode 100644 BSP/StdDriver/inc/adc.h create mode 100644 BSP/StdDriver/inc/clk.h create mode 100644 BSP/StdDriver/inc/crc.h create mode 100644 BSP/StdDriver/inc/fmc.h create mode 100644 BSP/StdDriver/inc/gpio.h create mode 100644 BSP/StdDriver/inc/i2c.h create mode 100644 BSP/StdDriver/inc/i2s.h create mode 100644 BSP/StdDriver/inc/pdma.h create mode 100644 BSP/StdDriver/inc/ps2.h create mode 100644 BSP/StdDriver/inc/pwm.h create mode 100644 BSP/StdDriver/inc/rtc.h create mode 100644 BSP/StdDriver/inc/sc.h create mode 100644 BSP/StdDriver/inc/spi.h create mode 100644 BSP/StdDriver/inc/sys.h create mode 100644 BSP/StdDriver/inc/timer.h create mode 100644 BSP/StdDriver/inc/uart.h create mode 100644 BSP/StdDriver/inc/usbd.h create mode 100644 BSP/StdDriver/inc/wdt.h create mode 100644 BSP/StdDriver/inc/wwdt.h create mode 100644 BSP/StdDriver/src/acmp.c create mode 100644 BSP/StdDriver/src/adc.c create mode 100644 BSP/StdDriver/src/clk.c create mode 100644 BSP/StdDriver/src/crc.c create mode 100644 BSP/StdDriver/src/fmc.c create mode 100644 BSP/StdDriver/src/gpio.c create mode 100644 BSP/StdDriver/src/i2c.c create mode 100644 BSP/StdDriver/src/i2s.c create mode 100644 BSP/StdDriver/src/pdma.c create mode 100644 BSP/StdDriver/src/ps2.c create mode 100644 BSP/StdDriver/src/pwm.c create mode 100644 BSP/StdDriver/src/retarget.c create mode 100644 BSP/StdDriver/src/rtc.c create mode 100644 BSP/StdDriver/src/sc.c create mode 100644 BSP/StdDriver/src/spi.c create mode 100644 BSP/StdDriver/src/sys.c create mode 100644 BSP/StdDriver/src/timer.c create mode 100644 BSP/StdDriver/src/uart.c create mode 100644 BSP/StdDriver/src/usbd.c create mode 100644 BSP/StdDriver/src/wdt.c create mode 100644 BSP/StdDriver/src/wwdt.c create mode 100644 CMakeLists.txt create mode 100644 arm-none-eabi.cmake create mode 100755 run_debugserver.sh create mode 100644 src/main.c diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..7427375 --- /dev/null +++ b/.clang-format @@ -0,0 +1,11 @@ +BasedOnStyle: Google +IndentWidth: 4 +AlignConsecutiveMacros: AcrossEmptyLines +AlignConsecutiveDeclarations: true +AlignConsecutiveAssignments: true +BreakBeforeBraces: Custom +BraceWrapping: + AfterEnum: false + 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QQc9AHn2Sr@P=oA$0ObL?h5!Hn literal 0 HcmV?d00001 diff --git a/BSP/CMSIS/Include/arm_common_tables.h b/BSP/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000..dd9526a --- /dev/null +++ b/BSP/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 14/04/08 10:21a $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef[6144]; +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/BSP/CMSIS/Include/arm_math.h b/BSP/CMSIS/Include/arm_math.h new file mode 100644 index 0000000..c270566 --- /dev/null +++ b/BSP/CMSIS/Include/arm_math.h @@ -0,0 +1,7556 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * $Date: 14/04/08 10:21a $Revision: V1.1.0 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.1.0 2012/02/15 + * Updated with more optimizations, bug fixes and minor API changes. + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.23. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined (__GNUC__) + #define __SIMD32(addr) (*( int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr)) +#else + #define __SIMD32(addr) (*(__packed int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr)) +#endif + + #define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && defined ( __TASKING__ ) +/* No need to redefine __CLZ */ +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) ) + + __STATIC_INLINE uint32_t __CLZ(q31_t data); + + + __STATIC_INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the f32 FFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the f32 IFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen 1/fftLenfth + * @return none. + */ + + void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + +#ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + +#else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + +#endif + +#ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc); + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #elif (__FPU_USED == 1) && defined ( __TMS_740 ) + *pOut = __builtin_sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/BSP/CMSIS/Include/core_cm0.h b/BSP/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..42db361 --- /dev/null +++ b/BSP/CMSIS/Include/core_cm0.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 13. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** @addtogroup CMSIS_Definitions CMSIS + @{ +*/ + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +/*@}*/ /* end of group CMSIS_Definitions */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_cm0plus.h b/BSP/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..cf92fb7 --- /dev/null +++ b/BSP/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,778 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_cm3.h b/BSP/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..db1716a --- /dev/null +++ b/BSP/CMSIS/Include/core_cm3.h @@ -0,0 +1,1612 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_cm4.h b/BSP/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..024302e --- /dev/null +++ b/BSP/CMSIS/Include/core_cm4.h @@ -0,0 +1,1757 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_cm4_simd.h b/BSP/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 0000000..b514007 --- /dev/null +++ b/BSP/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,649 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_cmFunc.h b/BSP/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..b370cc9 --- /dev/null +++ b/BSP/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + +/** @addtogroup CMSIS_Definitions CMSIS + @{ +*/ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +/*@}*/ /* end of group CMSIS_Definitions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/BSP/CMSIS/Include/core_cmInstr.h b/BSP/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..88ac672 --- /dev/null +++ b/BSP/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,624 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + +/** @addtogroup CMSIS_Definitions CMSIS + @{ +*/ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +/*@}*/ /* end of group CMSIS_Definitions */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/BSP/CMSIS/Include/core_sc000.h b/BSP/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9d874b7 --- /dev/null +++ b/BSP/CMSIS/Include/core_sc000.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/Include/core_sc300.h b/BSP/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..1dd2f12 --- /dev/null +++ b/BSP/CMSIS/Include/core_sc300.h @@ -0,0 +1,1583 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/BSP/CMSIS/index.html b/BSP/CMSIS/index.html new file mode 100644 index 0000000..3d57a19 --- /dev/null +++ b/BSP/CMSIS/index.html @@ -0,0 +1,14 @@ + + + +Redirect to the CMSIS main page after 0 seconds + + + + + + +If the automatic redirection is failing, click open CMSIS Documentation. + + + diff --git a/BSP/Device/Nuvoton/NUC200Series/Include/NUC200Series.h b/BSP/Device/Nuvoton/NUC200Series/Include/NUC200Series.h new file mode 100644 index 0000000..4a314e9 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Include/NUC200Series.h @@ -0,0 +1,11030 @@ +/**************************************************************************//** + * @file NUC200Series.h + * @version V3.0 + * $Revision: 75 $ + * $Date: 17/05/26 10:58a $ + * @brief NUC200 Series Peripheral Access Layer Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + + + +/** + \mainpage Introduction + * + * + * This user manual describes the usage of NUC200 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Copyright Notice + * + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + */ + +#ifndef __NUC200Series_H__ +#define __NUC200Series_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== +*/ + +/** @addtogroup CMSIS Device Definitions for CMSIS + Interrupt Number Definition and Configurations for CMSIS + @{ +*/ + +/** + * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible. + */ + +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M0 System Tick Interrupt */ + + /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ + BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */ + WDT_IRQn = 1, /*!< Watch Dog Timer Interrupt */ + EINT0_IRQn = 2, /*!< EINT0 Interrupt */ + EINT1_IRQn = 3, /*!< EINT1 Interrupt */ + GPAB_IRQn = 4, /*!< GPIO_PA/PB Interrupt */ + GPCDEF_IRQn = 5, /*!< GPIO_PC/PD/PE/PF Interrupt */ + PWMA_IRQn = 6, /*!< PWMA Interrupt */ + PWMB_IRQn = 7, /*!< PWMB Interrupt */ + TMR0_IRQn = 8, /*!< TIMER0 Interrupt */ + TMR1_IRQn = 9, /*!< TIMER1 Interrupt */ + TMR2_IRQn = 10, /*!< TIMER2 Interrupt */ + TMR3_IRQn = 11, /*!< TIMER3 Interrupt */ + UART02_IRQn = 12, /*!< UART0/UART2 Interrupt */ + UART1_IRQn = 13, /*!< UART1 Interrupt */ + SPI0_IRQn = 14, /*!< SPI0 Interrupt */ + SPI1_IRQn = 15, /*!< SPI1 Interrupt */ + SPI2_IRQn = 16, /*!< SPI2 Interrupt */ + SPI3_IRQn = 17, /*!< SPI3 Interrupt */ + I2C0_IRQn = 18, /*!< I2C0 Interrupt */ + I2C1_IRQn = 19, /*!< I2C1 Interrupt */ + CAN0_IRQn = 20, /*!< CAN0 Interrupt */ + CAN1_IRQn = 21, /*!< CAN1 Interrupt */ + SC012_IRQn = 22, /*!< SC0/SC1/SC2 Interrupt */ + USBD_IRQn = 23, /*!< USB device Interrupt */ + PS2_IRQn = 24, /*!< PS/2 device Interrupt */ + ACMP_IRQn = 25, /*!< ACMP0 Interrupt */ + PDMA_IRQn = 26, /*!< PDMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + PWRWU_IRQn = 28, /*!< Power Down Wake Up Interrupt */ + ADC_IRQn = 29, /*!< ADC Interrupt */ + IRC_IRQn = 30, /*!< IRC TRIM Interrupt */ + RTC_IRQn = 31 /*!< RTC Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +/*@}*/ /* end of group CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_NUC200Series.h" /* NUC200 System */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + +/*-------------------------------- Device Specific Peripheral registers structures ---------------------*/ +/** @addtogroup REGISTER Control Register + Peripheral Control Registers + @{ + */ + +/*---------------------- Analog Comparator Controller -------------------------*/ +/** + @addtogroup ACMP Analog Comparator Controller (ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + + + +typedef struct +{ + + +/** + * @var ACMP_T::CMPCR + * Offset: 0x00 Analog Comparator 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CMPEN |Comparator Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[1] |CMPIE |Comparator Interrupt Enable + * | | |0 = Interrupt function + * | | |Disabled. + * | | |1 = Interrupt function + * | | |Enabled. + * |[2] |CMP_HYSEN |Comparator Hysteresis Enable + * | | |0 = Hysteresis function Disabled (Default). + * | | |1 = Hysteresis function + * | | |Enabled. + * |[4] |CMPCN |Comparator Negative Input Selection + * | | |0 = The source of the negative comparator input is from ACMPn_N pin (n = 0, 1). + * | | |1 = Internal band-gap reference voltage is selected as the source + * | | | of negative comparator input. + + * @var ACMP_T::CMPSR + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CMPF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware whenever the comparator 0 output changes state. + * | | |This will cause an interrupt if CMPCR0[1] is set to 1. + * | | |Write 1 to clear this bit to 0. + * |[1] |CMPF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware whenever the comparator 1 output changes state. + * | | |This will cause an interrupt if CMPCR1[1] is set to 1. + * | | |Write 1 to clear this bit to 0. + * |[2] |CO0 |Comparator 0 Output + * | | |Synchronized to the APB clock to allow reading by software. + * | | |Cleared when the comparator 0 is disabled (CMPCR0[0] = 0). + * |[3] |CO1 |Comparator 1 Output + * | | |Synchronized to the APB clock to allow reading by software. + * | | |Cleared when the comparator 1 is disabled (CMPCR1[0] = 0). + */ + + __IO uint32_t CMPCR[2]; /* Offset: 0x00 Analog Comparator 0 Control Register */ + __IO uint32_t CMPSR; /* Offset: 0x04 Analog Comparator 1 Control Register */ + +} ACMP_T; + + + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + + +/* CMPCR Bit Field Definitions */ +#define ACMP_CMPCR_CMPCN_Pos 4 /*!< ACMP_T::CMPCR: CMPCN Position */ +#define ACMP_CMPCR_CMPCN_Msk (1ul << ACMP_CMPCR_CMPCN_Pos) /*!< ACMP_T::CMPCR: CMPCN Mask */ + +#define ACMP_CMPCR_CMP_HYSEN_Pos 2 /*!< ACMP_T::CMPCR: CMP_HYSEN Position */ +#define ACMP_CMPCR_CMP_HYSEN_Msk (1ul << ACMP_CMPCR_CMP_HYSEN_Pos) /*!< ACMP_T::CMPCR: CMP_HYSEN Mask */ + +#define ACMP_CMPCR_CMPIE_Pos 1 /*!< ACMP_T::CMPCR: CMPIE Position */ +#define ACMP_CMPCR_CMPIE_Msk (1ul << ACMP_CMPCR_CMPIE_Pos) /*!< ACMP_T::CMPCR: CMPIE Mask */ + +#define ACMP_CMPCR_CMPEN_Pos 0 /*!< ACMP_T::CMPCR: CMPEN Position */ +#define ACMP_CMPCR_CMPEN_Msk (1ul << ACMP_CMPCR_CMPEN_Pos) /*!< ACMP_T::CMPCR: CMPEN Mask */ + +/* CMPSR Bit Field Definitions */ +#define ACMP_CMPSR_CO1_Pos 3 /*!< ACMP_T::CMPSR: CO1 Position */ +#define ACMP_CMPSR_CO1_Msk (1ul << ACMP_CMPSR_CO1_Pos) /*!< ACMP_T::CMPSR: CO1 Mask */ + +#define ACMP_CMPSR_CO0_Pos 2 /*!< ACMP_T::CMPSR: CO0 Position */ +#define ACMP_CMPSR_CO0_Msk (1ul << ACMP_CMPSR_CO0_Pos) /*!< ACMP_T::CMPSR: CO0 Mask */ + +#define ACMP_CMPSR_CMPF1_Pos 1 /*!< ACMP_T::CMPSR: CMPF1 Position */ +#define ACMP_CMPSR_CMPF1_Msk (1ul << ACMP_CMPSR_CMPF1_Pos) /*!< ACMP_T::CMPSR: CMPF1 Mask */ + +#define ACMP_CMPSR_CMPF0_Pos 0 /*!< ACMP_T::CMPSR: CMPF0 Position */ +#define ACMP_CMPSR_CMPF0_Msk (1ul << ACMP_CMPSR_CMPF0_Pos) /*!< ACMP_T::CMPSR: CMPF0 Mask */ + +/*@}*/ /* end of group ACMP_CONST */ +/*@}*/ /* end of group ACMP */ + + + + +/*----------------------------- ADC Controller -------------------------------*/ +/** @addtogroup ADC Analog to Digital Converter (ADC) + Memory Mapped Structure for ADC Controller + @{ + */ + + +typedef struct +{ + + + +/** + * @var ADC_T::ADDR + * Offset: 0x00-0x1C ADC Data Register x + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RSLT |A/D Conversion Result + * | | |This field contains conversion result of ADC. + * | | |When DMOF bit (ADCR[31]) set to 0, 12-bit ADC conversion result with unsigned format will be + * | | |filled in RSLT (ADDRx[11:0], x=0~7) and zero will be filled in RSLT (ADDRx[15:12], x=0~7). + * | | |When DMOF bit (ADCR[31]) set to 1, 12-bit ADC conversion result with 2'complement format + * | | |will be filled in RSLT(ADDRx[11:0], x=0~7) and signed bits to will be filled in RSLT + * | | |(ADDRx[15:12], x=0~7). + * |[16] |OVERRUN |Overrun Flag + * | | |0 = Data in RSLT (ADDRx[15:0], x=0~7) is recent conversion result. + * | | |1 = Data in RSLT (ADDRx[15:0], x=0~7) is overwritten. + * | | |If converted data in RSLT has not been read before new conversion result is loaded to this + * | | |register, OVERRUN is set to 1 and previous conversion result is gone. + * | | |It is cleared by hardware after ADDR register is read. + * | | |This is a read only bit. + * |[17] |VALID |Valid Flag + * | | |0 = Data in RSLT bits (ADDRx[15:0], x=0~7) is not valid. + * | | |1 = Data in RSLT bits (ADDRx[15:0], x=0~7) is valid. + * | | |This bit is set to 1 when corresponding channel analog input conversion is completed and + * | | |cleared by hardware after ADDR register is read. + * | | |This is a read only bit + * @var ADC_T::ADCR + * Offset: 0x20 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADEN |A/D Converter Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |Before starting A/D conversion function, this bit should be set to 1. + * | | |Clear it to 0 to disable A/D converter analog circuit for saving power consumption. + * |[1] |ADIE |A/D Interrupt Enable + * | | |0 = A/D interrupt function Disabled. + * | | |1 = A/D interrupt function Enabled. + * | | |A/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1. + * |[3:2] |ADMD |A/D Converter Operation Mode + * | | |00 = Single conversion. + * | | |01 = Reserved. + * | | |10 = Single-cycle scan. + * | | |11 = Continuous scan. + * | | |When changing the operation mode, software should disable ADST bit (ADCR[11]) firstly. + * |[5:4] |TRGS |Hardware Trigger Source + * | | |00 = A/D conversion is started by external STADC pin. + * | | |11 = A/D conversion is started by PWM Center-aligned trigger. + * | | |Others = Reserved. + * | | |Software should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS. + * |[7:6] |TRGCOND |External Trigger Condition + * | | |These two bits decide external pin STADC trigger event is level or edge. + * | | |The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at + * | | |high and low state for edge trigger. + * | | |00 = Low level. + * | | |01 = High level. + * | | |10 = Falling edge. + * | | |11 = Rising edge. + * |[8] |TRGEN |Hardware Trigger Enable + * | | |Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM + * | | |Center-aligned trigger). + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |ADC hardware trigger function is only supported in single-cycle scan mode. + * | | |If hardware trigger mode, the ADST bit (ADCR[11]) can be set to 1 by the selected hardware + * | | |trigger source. + * |[9] |PTEN |PDMA Transfer Enable + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer in ADDR 0~7 Enabled. + * | | |When A/D conversion is completed, the converted data is loaded into ADDR 0~7, software can + * | | |enable this bit to generate a PDMA data transfer request. + * | | |When PTEN=1, software must set ADIE=0 (ADCR[1]) to disable interrupt. + * |[10] |DIFFEN |Differential Input Mode Enable + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * | | |Differential input Paired Channel + * | | |Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus + * | | |is the analog input; Vminus is the inverted analog input. + * | | |In differential input mode, only the even number of the two corresponding channels needs to + * | | |be enabled in ADCHER. + * | | |The conversion result will be placed to the corresponding data register of the enabled + * | | |channel. + * |[11] |ADST |A/D Conversion Start + * | | |0 = Conversion stops and A/D converter enter idle state. + * | | |1 = Conversion starts. + * | | |ADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and + * | | |external pin STADC. + * | | |ADST will be cleared to 0 by hardware automatically at the ends of single mode and + * | | |single-cycle scan mode. + * | | |In continuous scan mode, A/D conversion is continuously performed until software writes 0 to + * | | |this bit or chip reset. + * |[31] |DMOF |A/D Differential Input Mode Output Format + * | | |0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format. + * | | |1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement + * | | |format. + * @var ADC_T::ADCHER + * Offset: 0x24 ADC Channel Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CHEN |Analog Input Channel Enable + * | | |Set CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. + * | | |If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled. + * | | |0 = ADC input channel Disabled. + * | | |1 = ADC input channel Enabled. + * |[9:8] |PRESEL |Analog Input Channel 7 Select + * | | |00 = External analog input. + * | | |01 = Internal band-gap voltage. + * | | |10 = Internal temperature sensor. + * | | |11 = Reserved. + * | | |Note: + * | | |When software select the band-gap voltage as the analog input source of ADC channel 7, ADC + * | | |clock rate needs to be limited to slower than 300 kHz. + * @var ADC_T::ADCMPR + * Offset: 0x28 ADC Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CMPEN |Compare Enable + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * | | |Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified + * | | |channel conversion result when converted data is loaded into ADDR register. + * |[1] |CMPIE |Compare Interrupt Enable + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND + * | | |(ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, + * | | |in the meanwhile, if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is + * | | |generated. + * |[2] |CMPCOND |Compare Condition + * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the + * | | |12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one. + * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or + * | | |equal to the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8])+1), the + * | | |CMPF0/1 bit (ADSR[1]/[2]) will be set. + * |[5:3] |CMPCH |Compare Channel Selection + * | | |000 = Channel 0 conversion result is selected to be compared. + * | | |001 = Channel 1 conversion result is selected to be compared. + * | | |010 = Channel 2 conversion result is selected to be compared. + * | | |011 = Channel 3 conversion result is selected to be compared. + * | | |100 = Channel 4 conversion result is selected to be compared. + * | | |101 = Channel 5 conversion result is selected to be compared. + * | | |110 = Channel 6 conversion result is selected to be compared. + * | | |111 = Channel 7 conversion result is selected to be compared. + * |[11:8] |CMPMATCNT |Compare Match Count + * | | |When the specified A/D channel analog conversion result matches the compare condition + * | | |defined by CMPCOND (ADCMPR0/1[2]), the internal match counter will increase 1. + * | | |When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) +1), the CMPF0/1 + * | | |bit (ADSR[1]/[2]) will be set. + * |[27:16] |CMPD |Comparison Data + * | | |The 12-bit data is used to compare with conversion result of specified channel. + * | | |When DMOF bit (ADCR[31]) is set to 0, ADC comparator compares CMPD with conversion result + * | | |with unsigned format. + * | | |CMPD should be filled in unsigned format. + * | | |When DMOF bit (ADCR[31]) is set to 1, ADC comparator compares CMPD with conversion result + * | | |with 2'complement format. + * | | |CMPD should be filled in 2'complement format. + * @var ADC_T::ADSR + * Offset: 0x30 ADC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADF |A/D Conversion End Flag + * | | |A status flag that indicates the end of A/D conversion. + * | | |ADF is set to 1 at these two conditions: + * | | |1. When A/D conversion ends in Single mode. + * | | |2. When A/D conversion ends on all specified channels in Scan mode. + * | | |This flag can be cleared by writing 1 to itself. + * |[1] |CMPF0 |Compare Flag + * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this + * | | |bit is set to 1. + * | | |And it is cleared by writing 1 to self. + * | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting. + * | | |1 = Conversion result in ADDR meets ADCMPR0 setting. + * |[2] |CMPF1 |Compare Flag + * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this + * | | |bit is set to 1. + * | | |And it is cleared by writing 1 to self. + * | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting. + * | | |1 = Conversion result in ADDR meets ADCMPR1 setting. + * |[3] |BUSY |BUSY/IDLE + * | | |0 = A/D converter is in idle state. + * | | |1 = A/D converter is busy at conversion. + * | | |This bit is mirror of as ADST bit (ADCR[11]). + * | | |It is read only. + * |[6:4] |CHANNEL |Current Conversion Channel + * | | |This field reflects the current conversion channel when BUSY = 1 (ADSR[3]). + * | | |When BUSY = 0, it shows the number of the next converted channel. + * | | |It is read only. + * |[15:8] |VALID |Data Valid Flag + * | | |It is a mirror of VALID bit (ADDR0~7[17]). + * | | |It is read only. + * |[23:16] |OVERRUN |Overrun Flag + * | | |It is a mirror to OVERRUN bit (ADDR0~7[16]). + * | | |It is read only. + * @var ADC_T::ADPDMA + * Offset: 0x40 ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |AD_PDMA |ADC PDMA Current Transfer Data Register + * | | |When PDMA transferring, read this register can monitor current PDMA transfer data. + * | | |Current PDMA transfer data is the content of ADDR0 ~ ADDR7. + * | | |This is a read only register. + */ + + __I uint32_t ADDR[8]; /* Offset: 0x00-0x1C ADC Data Register x */ + __IO uint32_t ADCR; /* Offset: 0x20 ADC Control Register */ + __IO uint32_t ADCHER; /* Offset: 0x24 ADC Channel Enable Register */ + __IO uint32_t ADCMPR[2]; /* Offset: 0x28 ADC Compare Register x */ + __IO uint32_t ADSR; /* Offset: 0x30 ADC Status Register */ + __I uint32_t RESERVE0[3]; + __I uint32_t ADPDMA; /* Offset: 0x40 ADC PDMA Current Transfer Data Register */ + +} ADC_T; + + + +/** + @addtogroup ADC_CONST ADC Bit Field Definition + Constant Definitions for ADC Controller +@{ */ + +/* ADDR Bit Field Definitions */ +#define ADC_ADDR_VALID_Pos 17 /*!< ADC_T::ADDR: VALID Position */ +#define ADC_ADDR_VALID_Msk (1ul << ADC_ADDR_VALID_Pos) /*!< ADC_T::ADDR: VALID Mask */ + +#define ADC_ADDR_OVERRUN_Pos 16 /*!< ADC_T::ADDR: OVERRUN Position */ +#define ADC_ADDR_OVERRUN_Msk (1ul << ADC_ADDR_OVERRUN_Pos) /*!< ADC_T::ADDR: OVERRUN Mask */ + +#define ADC_ADDR_RSLT_Pos 0 /*!< ADC_T::ADDR: RSLT Position */ +#define ADC_ADDR_RSLT_Msk (0xFFFFul << ADC_ADDR_RSLT_Pos) /*!< ADC_T::ADDR: RSLT Mask */ + +/* ADCR Bit Field Definitions */ +#define ADC_ADCR_DMOF_Pos 31 /*!< ADC_T::ADCR: DMOF Position */ +#define ADC_ADCR_DMOF_Msk (1ul << ADC_ADCR_DMOF_Pos) /*!< ADC_T::ADCR: DMOF Mask */ + +#define ADC_ADCR_ADST_Pos 11 /*!< ADC_T::ADCR: ADST Position */ +#define ADC_ADCR_ADST_Msk (1ul << ADC_ADCR_ADST_Pos) /*!< ADC_T::ADCR: ADST Mask */ + +#define ADC_ADCR_DIFFEN_Pos 10 /*!< ADC_T::ADCR: DIFFEN Position */ +#define ADC_ADCR_DIFFEN_Msk (1ul << ADC_ADCR_DIFFEN_Pos) /*!< ADC_T::ADCR: DIFFEN Mask */ + +#define ADC_ADCR_PTEN_Pos 9 /*!< ADC_T::ADCR: PTEN Position */ +#define ADC_ADCR_PTEN_Msk (1ul << ADC_ADCR_PTEN_Pos) /*!< ADC_T::ADCR: PTEN Mask */ + +#define ADC_ADCR_TRGEN_Pos 8 /*!< ADC_T::ADCR: TRGEN Position */ +#define ADC_ADCR_TRGEN_Msk (1ul << ADC_ADCR_TRGEN_Pos) /*!< ADC_T::ADCR: TRGEN Mask */ + +#define ADC_ADCR_TRGCOND_Pos 6 /*!< ADC_T::ADCR: TRGCOND Position */ +#define ADC_ADCR_TRGCOND_Msk (3ul << ADC_ADCR_TRGCOND_Pos) /*!< ADC_T::ADCR: TRGCOND Mask */ + +#define ADC_ADCR_TRGS_Pos 4 /*!< ADC_T::ADCR: TRGS Position */ +#define ADC_ADCR_TRGS_Msk (3ul << ADC_ADCR_TRGS_Pos) /*!< ADC_T::ADCR: TRGS Mask */ + +#define ADC_ADCR_ADMD_Pos 2 /*!< ADC_T::ADCR: ADMD Position */ +#define ADC_ADCR_ADMD_Msk (3ul << ADC_ADCR_ADMD_Pos) /*!< ADC_T::ADCR: ADMD Mask */ + +#define ADC_ADCR_ADIE_Pos 1 /*!< ADC_T::ADCR: ADIE Position */ +#define ADC_ADCR_ADIE_Msk (1ul << ADC_ADCR_ADIE_Pos) /*!< ADC_T::ADCR: ADIE Mask */ + +#define ADC_ADCR_ADEN_Pos 0 /*!< ADC_T::ADCR: ADEN Position */ +#define ADC_ADCR_ADEN_Msk (1ul << ADC_ADCR_ADEN_Pos) /*!< ADC_T::ADCR: ADEN Mask */ + +/* ADCHER Bit Field Definitions */ +#define ADC_ADCHER_PRESEL_Pos 8 /*!< ADC_T::ADCHER: PRESEL Position */ +#define ADC_ADCHER_PRESEL_Msk (3ul << ADC_ADCHER_PRESEL_Pos) /*!< ADC_T::ADCHER: PRESEL Mask */ + +#define ADC_ADCHER_CHEN_Pos 0 /*!< ADC_T::ADCHER: CHEN Position */ +#define ADC_ADCHER_CHEN_Msk (0xFFul << ADC_ADCHER_CHEN_Pos) /*!< ADC_T::ADCHER: CHEN Mask */ + +/* ADCMPR Bit Field Definitions */ +#define ADC_ADCMPR_CMPD_Pos 16 /*!< ADC_T::ADCMPR: CMPD Position */ +#define ADC_ADCMPR_CMPD_Msk (0xFFFul << ADC_ADCMPR_CMPD_Pos) /*!< ADC_T::ADCMPR: CMPD Mask */ + +#define ADC_ADCMPR_CMPMATCNT_Pos 8 /*!< ADC_T::ADCMPR: CMPMATCNT Position */ +#define ADC_ADCMPR_CMPMATCNT_Msk (0xFul << ADC_ADCMPR_CMPMATCNT_Pos) /*!< ADC_T::ADCMPR: CMPMATCNT Mask */ + +#define ADC_ADCMPR_CMPCH_Pos 3 /*!< ADC_T::ADCMPR: CMPCH Position */ +#define ADC_ADCMPR_CMPCH_Msk (7ul << ADC_ADCMPR_CMPCH_Pos) /*!< ADC_T::ADCMPR: CMPCH Mask */ + +#define ADC_ADCMPR_CMPCOND_Pos 2 /*!< ADC_T::ADCMPR: CMPCOND Position */ +#define ADC_ADCMPR_CMPCOND_Msk (1ul << ADC_ADCMPR_CMPCOND_Pos) /*!< ADC_T::ADCMPR: CMPCOND Mask */ + +#define ADC_ADCMPR_CMPIE_Pos 1 /*!< ADC_T::ADCMPR: CMPIE Position */ +#define ADC_ADCMPR_CMPIE_Msk (1ul << ADC_ADCMPR_CMPIE_Pos) /*!< ADC_T::ADCMPR: CMPIE Mask */ + +#define ADC_ADCMPR_CMPEN_Pos 0 /*!< ADC_T::ADCMPR: CMPEN Position */ +#define ADC_ADCMPR_CMPEN_Msk (1ul << ADC_ADCMPR_CMPEN_Pos) /*!< ADC_T::ADCMPR: CMPEN Mask */ + +/* ADSR Bit Field Definitions */ +#define ADC_ADSR_OVERRUN_Pos 16 /*!< ADC_T::ADSR: OVERRUN Position */ +#define ADC_ADSR_OVERRUN_Msk (0xFFul << ADC_ADSR_OVERRUN_Pos) /*!< ADC_T::ADSR: OVERRUN Mask */ + +#define ADC_ADSR_VALID_Pos 8 /*!< ADC_T::ADSR: VALID Position */ +#define ADC_ADSR_VALID_Msk (0xFFul << ADC_ADSR_VALID_Pos) /*!< ADC_T::ADSR: VALID Mask */ + +#define ADC_ADSR_CHANNEL_Pos 4 /*!< ADC_T::ADSR: CHANNEL Position */ +#define ADC_ADSR_CHANNEL_Msk (7ul << ADC_ADSR_CHANNEL_Pos) /*!< ADC_T::ADSR: CHANNEL Mask */ + +#define ADC_ADSR_BUSY_Pos 3 /*!< ADC_T::ADSR: BUSY Position */ +#define ADC_ADSR_BUSY_Msk (1ul << ADC_ADSR_BUSY_Pos) /*!< ADC_T::ADSR: BUSY Mask */ + +#define ADC_ADSR_CMPF1_Pos 2 /*!< ADC_T::ADSR: CMPF1 Position */ +#define ADC_ADSR_CMPF1_Msk (1ul << ADC_ADSR_CMPF1_Pos) /*!< ADC_T::ADSR: CMPF1 Mask */ + +#define ADC_ADSR_CMPF0_Pos 1 /*!< ADC_T::ADSR: CMPF0 Position */ +#define ADC_ADSR_CMPF0_Msk (1ul << ADC_ADSR_CMPF0_Pos) /*!< ADC_T::ADSR: CMPF0 Mask */ + +#define ADC_ADSR_ADF_Pos 0 /*!< ADC_T::ADSR: ADF Position */ +#define ADC_ADSR_ADF_Msk (1ul << ADC_ADSR_ADF_Pos) /*!< ADC_T::ADSR: ADF Mask */ + +/* ADPDMA Bit Field Definitions */ +#define ADC_ADPDMA_AD_PDMA_Pos 0 /*!< ADC_T::ADPDMA: AD_PDMA Position */ +#define ADC_ADPDMA_AD_PDMA_Msk (0x3FFFFul << ADC_ADPDMA_AD_PDMA_Pos) /*!< ADC_T::ADPDMA: AD_PDMA Mask */ + +/*@}*/ /* end of group ADC_CONST */ +/*@}*/ /* end of group ADC */ + + + +/*---------------------------- Clock Controller ------------------------------*/ +/** @addtogroup CLK System Clock Controller (CLK) + Memory Mapped Structure for System Clock Controller + @{ + */ + + +typedef struct +{ + + + +/** + * @var CLK_T::PWRCON + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XTL12M_EN |External 4~24 MHz High Speed Crystal Enable (HXT) Control (Write Protect) + * | | |The bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]). + * | | |When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically. + * | | |0 = External 4~24 MHz high speed crystal oscillator (HXT) Disabled. + * | | |1 = External 4~24 MHz high speed crystal oscillator (HXT) Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[1] |XTL32K_EN |External 32.768 KHz Low Speed Crystal Enable (LXT) Control (Write Protect) + * | | |0 = External 32.768 kHz low speed crystal oscillator (LXT) Disabled. + * | | |1 = External 32.768 kHz low speed crystal oscillator (LXT) Enabled (Normal operation). + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[2] |OSC22M_EN |Internal 22.1184 MHz High Speed Oscillator (HIRC) Enable Control (Write Protect) + * | | |0 = Internal 22.1184 MHz high speed oscillator (HIRC) Disabled. + * | | |1 = Internal 22.1184 MHz high speed oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[3] |OSC10K_EN |Internal 10 KHz Low Speed Oscillator (LIRC) Enable Control (Write Protect) + * | | |0 = Internal 10 kHz low speed oscillator (LIRC) Disabled. + * | | |1 = Internal 10 kHz low speed oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[4] |PD_WU_DLY |Wake-up Delay Counter Enable Control (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator. + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[5] |PD_WU_INT_EN|Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. + * | | |Note2: This bit is write protected bit. Refer to the REGWRPROT register. + * |[6] |PD_WU_STS |Power-Down Mode Wake-Up Interrupt Status + * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. + * | | |The flag is set if the GPIO, USB, UART, WDT, I2C, TIMER, ACMP, BOD or RTC wake-up occurred. + * | | |Write 1 to clear the bit to 0. + * | | |Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. + * |[7] |PWR_DOWN_EN|System Power-Down Enable Bit (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior willdepends on the PD_WAIT_CPU bit. + * | | |(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set. + * | | |(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. (recommend) + * | | |When chip wakes up from Power-down mode, this bit is cleared by hardware. + * | | |User needs to set this bit again for next Power-down. + * | | |In Power-down mode, external 4~24 MHz high speed crystal oscillator and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, + * | | |but the external 32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not controlled by Power-down mode. + * | | |In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low speed crystal oscillator or the internal 10 kHz low speed oscillator. + * | | |0 = Chip operating normally or chip in Idle mode because of WFI command. + * | | |1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[8] |PD_WAIT_CPU|This Bit Control The Power-Down Entry Condition (Write Protect) + * | | |0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1. + * | | |1 = Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMA_EN |PDMA Controller Clock Enable Control + * | | |0 = PDMA peripheral clock Disabled. + * | | |1 = PDMA peripheral clock Enabled. + * |[2] |ISP_EN |Flash ISP Controller Clock Enable Control + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * @var CLK_T::APBCLK + * Offset: 0x08 APB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDT_EN |Watchdog Timer Clock Enable Control (Write Protect) + * | | |0 = Watchdog Timer clock Disabled. + * | | |1 = Watchdog Timer clock Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[1] |RTC_EN |Real-Time-Clock APB Interface Clock Enable Control + * | | |This bit is used to control the RTC APB clock only. The RTC clock source is from the external 32.768 kHz low speed crystal. + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0_EN |Timer0 Clock Enable Control + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1_EN |Timer1 Clock Enable Control + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2_EN |Timer2 Clock Enable Control + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3_EN |Timer3 Clock Enable Control + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |FDIV_EN |Frequency Divider Output Clock Enable Control + * | | |0 = FDIV clock Disabled. + * | | |1 = FDIV clock Enabled. + * |[8] |I2C0_EN |I2C0 Clock Enable Control + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1_EN |I2C1 Clock Enable Control + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[12] |SPI0_EN |SPI0 Clock Enable Control + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[13] |SPI1_EN |SPI1 Clock Enable Control + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[14] |SPI2_EN |SPI2 Clock Enable Control + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[15] |SPI3_EN |SPI3 Clock Enable Control + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[16] |UART0_EN |UART0 Clock Enable Control + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1_EN |UART1 Clock Enable Control + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2_EN |UART2 Clock Enable Control + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[20] |PWM01_EN |PWM_01 Clock Enable Control + * | | |0 = PWM01 clock Disabled. + * | | |1 = PWM01 clock Enabled. + * |[21] |PWM23_EN |PWM_23 Clock Enable Control + * | | |0 = PWM23 clock Disabled. + * | | |1 = PWM23 clock Enabled. + * |[22] |PWM45_EN |PWM_45 Clock Enable Control + * | | |0 = PWM45 clock Disabled. + * | | |1 = PWM45 clock Enabled. + * |[23] |PWM67_EN |PWM_67 Clock Enable Control + * | | |0 = PWM67 clock Disabled. + * | | |1 = PWM67 clock Enabled. + * |[27] |USBD_EN |USB 2.0 FS Device Controller Clock Enable Control + * | | |0 = USB clock Disabled. + * | | |1 = USB clock Enabled. + * |[28] |ADC_EN |Analog-Digital-Converter (ADC) Clock Enable Control + * | | |0 = ADC clock Disabled. + * | | |1 = ADC clock Enabled. + * |[29] |I2S_EN |I2S Clock Enable Control + * | | |0 = I2S clock Disabled. + * | | |1 = I2S clock Enabled. + * |[30] |ACMP_EN |Analog Comparator Clock Enable Control + * | | |0 = Analog Comparator clock Disabled. + * | | |1 = Analog Comparator clock Enabled. + * |[31] |PS2_EN |PS/2 Clock Enable Control + * | | |0 = PS/2 clock Disabled. + * | | |1 = PS/2 clock Enabled. + * @var CLK_T::CLKSTATUS + * Offset: 0x0C Clock status monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XTL12M_STB|External 4~24 MHz High Speed Crystal (HXT) Clock Source Stable Flag (Read Only) + * | | |0 = External 4~24 MHz high speed crystal clock (HXT) is not stable or disabled. + * | | |1 = External 4~24 MHz high speed crystal clock (HXT) is stable and enabled. + * |[1] |XTL32K_STB|External 32.768 KHz Low Speed Crystal (LXT) Clock Source Stable Flag(Read Only) + * | | |0 = External 32.768 kHz low speed crystal (LXT) clock is not stable or disabled. + * | | |1 = External 32.768 kHz low speed crystal (LXT) clock is stable and enabled. + * |[2] |PLL_STB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable in normal mode. + * |[3] |OSC10K_STB|Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only) + * | | |0 = Internal 10 kHz low speed oscillator clock (LIRC) is not stable or disabled. + * | | |1 = Internal 10 kHz low speed oscillator clock (LIRC) is stable and enabled. + * |[4] |OSC22M_STB|Internal 22.1184 MHz High Speed Oscillator (HIRC) Clock Source Stable Flag (Read Only) + * | | |0 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is not stable or disabled. + * | | |1 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is stable and enabled. + * |[7] |CLK_SW_FAIL|Clock Switching Fail Flag + * | | |0 = Clock switching success. + * | | |1 = Clock switching failed. + * | | |This bit is updated when software switches system clock source. + * | | |If switch target clock is stable, this bit will be set to 0. + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |Write 1 to clear the bit to 0. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLK_S |HCLK Clock Source Selection (Write Protect) + * | | |1. Before clock switching, the related clock sources (both pre-select and new-select) must be turn on. + * | | |2. The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. + * | | |000 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |010 = Clock source from PLL clock. + * | | |011 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |Note: These bits are write protected bit. Refer to the REGWRPROT register. + * |[5:3] |STCLK_S |Cortex-M0 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CSR[2] = 1, SysTick clock source is from HCLK. + * | | |If SYST_CSR[2] = 0, SysTick clock source is defined by STCLK_S(CLKSEL0[5:3]). + * | | |000 = Clock source from external 4~24 MHz high speed crystal clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal clock. + * | | |010 = Clock source from external 4~24 MHz high speed crystal clock/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock/2. + * | | |Note1: These bits are write protected bit. Refer to the REGWRPROT register. + * | | |Note2: if SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDT_S |Watchdog Timer Clock Source Select (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK/2048 clock. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |Note: These bits are write protected bit. Refer to the REGWRPROT register. + * |[3:2] |ADC_S |ADC Clock Source Select + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[4] |SPI0_S |SPI0 Clock Source Selection + * | | |0 = Clock source from PLL clock. + * | | |1 = Clock source from HCLK. + * |[5] |SPI1_S |SPI1 Clock Source Selection + * | | |0 = Clock source from PLL clock. + * | | |1 = Clock source from HCLK. + * |[6] |SPI2_S |SPI2 Clock Source Selection + * | | |0 = Clock source from PLL clock. + * | | |1 = Clock source from HCLK. + * |[7] |SPI3_S |SPI3 Clock Source Selection + * | | |0 = Clock source from PLL clock. + * | | |1 = Clock source from HCLK. + * |[10:8] |TMR0_S |TIMER0 Clock Source Selection + * | | |000 = Clock source from external 4~24 MHz high speed crystal clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal clock. + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from external trigger. + * | | |101 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |Others = Reserved. + * |[14:12] |TMR1_S |TIMER1 Clock Source Selection + * | | |000 = Clock source from external 4~24 MHz high speed crystal clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal clock. + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from external trigger. + * | | |101 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |Others = Reserved. + * |[18:16] |TMR2_S |TIMER2 Clock Source Selection + * | | |000 = Clock source from external 4~24 MHz high speed crystal clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal clock. + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from external trigger. + * | | |101 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |Others = Reserved. + * |[22:20] |TMR3_S |TIMER3 Clock Source Selection + * | | |000 = Clock source from external 4~24 MHz high speed crystal clock. + * | | |001 = Clock source from external 32.768 kHz low speed crystal clock. + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from external trigger. + * | | |101 = Clock source from internal 10 kHz low speed oscillator clock. + * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |Others = Reserved. + * |[25:24] |UART_S |UART Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[29:28] |PWM01_S |PWM0 And PWM1 Clock Source Selection + * | | |PWM0 and PWM1 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). + * | | |If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[31:30] |PWM23_S |PWM2 And PWM3 Clock Source Selection + * | | |PWM2 and PWM3 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). + * | | |If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * @var CLK_T::CLKDIV + * Offset: 0x18 Clock Divider Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLK_N |HCLK Clock Divide Number From HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1). + * |[7:4] |USB_N |USB Clock Divide Number From PLL Clock + * | | |USB clock frequency = (PLL frequency) / (USB_N + 1). + * |[11:8] |UART_N |UART Clock Divide Number From UART Clock Source + * | | |UART clock frequency = (UART clock source frequency) / (UART_N + 1). + * |[23:16] |ADC_N |ADC Clock Divide Number From ADC Clock Source + * | | |ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1). + * @var CLK_T::CLKSEL2 + * Offset: 0x1C Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |I2S_S |I2S Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[3:2] |FRQDIV_S |Clock Divider Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[5:4] |PWM45_S |PWM4 And PWM5 Clock Source Selection + * | | |PWM4 and PWM5 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]). + * | | |If PWM45_S_E = 0, the clock source of PWM4 and PWM5 defined by PWM45_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM45_S_E = 1, the clock source of PWM4 and PWM5 defined by PWM45_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[7:6] |PWM67_S |PWM6 And PWM7 Clock Source Selection + * | | |PWM6 and PWM7 used the sameclock source; both of them used the same prescaler. + * | | |The clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]). + * | | |If PWM67_S_E = 0, the clock source of PWM6 and PWM7 defined by PWM67_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM67_S_E = 1, the clock source of PWM6 and PWM7 defined by PWM67_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[8] |PWM01_S_E |PWM0 And PWM1 Clock Source Selection Extend + * | | |PWM0 and PWM1 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). + * | | |If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[9] |PWM23_S_E |PWM2 And PWM3 Clock Source Selection Extend + * | | |PWM2 and PWM3 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). + * | | |If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S listbelow: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[10] |PWM45_S_E |PWM4 And PWM5 Clock Source Selection Extend + * | | |PWM4 and PWM5 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]). + * | | |If PWM45_S_E = 0, the clock source of PWM4 and PWM5 defined by PWM45_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM45_S_E = 1, the clock source of PWM4 and PWM5 defined by PWM45_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[11] |PWM67_S_E |PWM6 And PWM7 Clock Source Selection Extend + * | | |PWM6 and PWM7 used the same clock source; both of them used the same prescaler. + * | | |The clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]). + * | | |If PWM67_S_E = 0, the peripheral clock source of PWM6 and PWM7 defined by PWM67_S list below: + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from external 32.768 kHz low speed crystal oscillator clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * | | |If PWM67_S_E = 1, the clock source of PWM6 and PWM7 defined by PWM67_S list below: + * | | |00 = Reserved. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * |[17:16] |WWDT_S |Window Watchdog Timer Clock Source Selection + * | | |10 = Clock source from HCLK/2048 clock. + * | | |11 = Clock source from internal 10 kHz low speed oscillator clock. + * @var CLK_T::PLLCON + * Offset: 0x20 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FB_DV |PLL Feedback Divider Control Bits + * | | |Refer to the PLL formulas. + * |[13:9] |IN_DV |PLL Input Divider Control Bits + * | | |Refer to the PLL formulas. + * |[15:14] |OUT_DV |PLL Output Divider Control Bits + * | | |Refer to the PLL formulas. + * |[16] |PD |Power-Down Mode + * | | |If the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too. + * | | |0 = PLL is in Normal mode. + * | | |1 = PLL is in Power-down mode (default). + * |[17] |BP |PLL Bypass Control + * | | |0 = PLL is in Normal mode (default). + * | | |1 = PLL clock output is same as PLL source clock input. + * |[18] |OE |PLL OE (FOUT Enable) Control + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * |[19] |PLL_SRC |PLL Source Clock Selection + * | | |0 = PLL source clock from external 4~24 MHz high speed crystal. + * | | |1 = PLL source clock from internal 22.1184 MHz high speed oscillator. + * @var CLK_T::FRQDIV + * Offset: 0x24 Frequency Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FSEL |Divider Output Frequency Selection Bits + * | | |The formula of output frequency is Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FSEL[3:0]. + * |[4] |DIVIDER_EN|Frequency Divider Enable Bit + * | | |0 = Frequency Divider function Disabled. + * | | |1 = Frequency Divider function Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x30 APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0_EN |SC0 Clock Enable Control + * | | |0 = SC0 Clock Disabled. + * | | |1 = SC0 Clock Enabled. + * |[1] |SC1_EN |SC1 Clock Enable Control + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2_EN |SC2 Clock Enable Control + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * @var CLK_T::CLKSEL3 + * Offset: 0x34 Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0_S |SC0 Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[3:2] |SC1_S |SC1 Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * |[5:4] |SC2_S |SC2 Clock Source Selection + * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = HCLK. + * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock. + * @var CLK_T::CLKDIV1 + * Offset: 0x38 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0_N |SC0 Clock Divide Number From SC0 Clock Source + * | | |The SC0 clock frequency = (SC0 clock source frequency) / (SC0_N + 1). + * |[15:8] |SC1_N |SC1 Clock Divide Number From SC1 Clock Source + * | | |The SC1 clock frequency = (SC1 clock source frequency) / (SC1_N + 1). + * |[23:16] |SC2_N |SC2 Clock Divide Number From SC2 Clock Source + * | | |The SC2 clock frequency = (SC2 clock source frequency) / (SC2_N + 1). + */ + + __IO uint32_t PWRCON; /* Offset: 0x00 System Power-down Control Register */ + __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK; /* Offset: 0x08 APB Devices Clock Enable Control Register */ + __IO uint32_t CLKSTATUS; /* Offset: 0x0C Clock status monitor Register */ + __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */ + __IO uint32_t CLKDIV; /* Offset: 0x18 Clock Divider Number Register */ + __IO uint32_t CLKSEL2; /* Offset: 0x1C Clock Source Select Control Register 2 */ + __IO uint32_t PLLCON; /* Offset: 0x20 PLL Control Register */ + __IO uint32_t FRQDIV; /* Offset: 0x24 Frequency Divider Control Register */ + __IO uint32_t RESERVE[2]; + __IO uint32_t APBCLK1; /* Offset: 0x30 APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL3; /* Offset: 0x34 Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV1; /* Offset: 0x38 Clock Divider Number Register 1 */ + +} CLK_T; + + + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +/* CLK PWRCON Bit Field Definitions */ +#define CLK_PWRCON_PD_WAIT_CPU_Pos 8 /*!< CLK_T::PWRCON: PD_WAIT_CPU Position */ +#define CLK_PWRCON_PD_WAIT_CPU_Msk (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) /*!< CLK_T::PWRCON: PD_WAIT_CPU Mask */ + +#define CLK_PWRCON_PWR_DOWN_EN_Pos 7 /*!< CLK_T::PWRCON: PWR_DOWN_EN Position */ +#define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) /*!< CLK_T::PWRCON: PWR_DOWN_EN Mask */ + +#define CLK_PWRCON_PD_WU_STS_Pos 6 /*!< CLK_T::PWRCON: PD_WU_STS Position */ +#define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos) /*!< CLK_T::PWRCON: PD_WU_STS Mask */ + +#define CLK_PWRCON_PD_WU_INT_EN_Pos 5 /*!< CLK_T::PWRCON: PD_WU_INT_EN Position */ +#define CLK_PWRCON_PD_WU_INT_EN_Msk (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) /*!< CLK_T::PWRCON: PD_WU_INT_EN Mask */ + +#define CLK_PWRCON_PD_WU_DLY_Pos 4 /*!< CLK_T::PWRCON: PD_WU_DLY Position */ +#define CLK_PWRCON_PD_WU_DLY_Msk (1ul << CLK_PWRCON_PD_WU_DLY_Pos) /*!< CLK_T::PWRCON: PD_WU_DLY Mask */ + +#define CLK_PWRCON_OSC10K_EN_Pos 3 /*!< CLK_T::PWRCON: OSC10K_EN Position */ +#define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) /*!< CLK_T::PWRCON: OSC10K_EN Mask */ +#define CLK_PWRCON_IRC10K_EN_Pos 3 /*!< CLK_T::PWRCON: IRC10K_EN Position */ +#define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_IRC10K_EN_Pos) /*!< CLK_T::PWRCON: IRC10K_EN Mask */ + +#define CLK_PWRCON_OSC22M_EN_Pos 2 /*!< CLK_T::PWRCON: OSC22M_EN Position */ +#define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) /*!< CLK_T::PWRCON: OSC22M_EN Mask */ +#define CLK_PWRCON_IRC22M_EN_Pos 2 /*!< CLK_T::PWRCON: IRC22M_EN Position */ +#define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_IRC22M_EN_Pos) /*!< CLK_T::PWRCON: IRC22M_EN Mask */ + +#define CLK_PWRCON_XTL32K_EN_Pos 1 /*!< CLK_T::PWRCON: XTL32K_EN Position */ +#define CLK_PWRCON_XTL32K_EN_Msk (1ul << CLK_PWRCON_XTL32K_EN_Pos) /*!< CLK_T::PWRCON: XTL32K_EN Mask */ + +#define CLK_PWRCON_XTL12M_EN_Pos 0 /*!< CLK_T::PWRCON: XTL12M_EN Position */ +#define CLK_PWRCON_XTL12M_EN_Msk (1ul << CLK_PWRCON_XTL12M_EN_Pos) /*!< CLK_T::PWRCON: XTL12M_EN Mask */ + +/* CLK AHBCLK Bit Field Definitions */ +#define CLK_AHBCLK_ISP_EN_Pos 2 /*!< CLK_T::AHBCLK: ISP_EN Position */ +#define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos) /*!< CLK_T::AHBCLK: ISP_EN Mask */ + +#define CLK_AHBCLK_PDMA_EN_Pos 1 /*!< CLK_T::AHBCLK: PDMA_EN Position */ +#define CLK_AHBCLK_PDMA_EN_Msk (1ul << CLK_AHBCLK_PDMA_EN_Pos) /*!< CLK_T::AHBCLK: PDMA_EN Mask */ + +/* CLK APBCLK Bit Field Definitions */ +#define CLK_APBCLK_PS2_EN_Pos 31 /*!< CLK_T::APBCLK: PS2_EN Position */ +#define CLK_APBCLK_PS2_EN_Msk (1ul << CLK_APBCLK_PS2_EN_Pos) /*!< CLK_T::APBCLK: PS2_EN Mask */ + +#define CLK_APBCLK_ACMP_EN_Pos 30 /*!< CLK_T::APBCLK: ACMP_EN Position */ +#define CLK_APBCLK_ACMP_EN_Msk (1ul << CLK_APBCLK_ACMP_EN_Pos) /*!< CLK_T::APBCLK: ACMP_EN Mask */ + +#define CLK_APBCLK_I2S_EN_Pos 29 /*!< CLK_T::APBCLK: I2S_EN Position */ +#define CLK_APBCLK_I2S_EN_Msk (1ul << CLK_APBCLK_I2S_EN_Pos) /*!< CLK_T::APBCLK: I2S_EN Mask */ + +#define CLK_APBCLK_ADC_EN_Pos 28 /*!< CLK_T::APBCLK: ADC_EN Position */ +#define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos) /*!< CLK_T::APBCLK: ADC_EN Mask */ + +#define CLK_APBCLK_USBD_EN_Pos 27 /*!< CLK_T::APBCLK: USBD_EN Position */ +#define CLK_APBCLK_USBD_EN_Msk (1ul << CLK_APBCLK_USBD_EN_Pos) /*!< CLK_T::APBCLK: USBD_EN Mask */ + +#define CLK_APBCLK_PWM67_EN_Pos 23 /*!< CLK_T::APBCLK: PWM67_EN Position */ +#define CLK_APBCLK_PWM67_EN_Msk (1ul << CLK_APBCLK_PWM67_EN_Pos) /*!< CLK_T::APBCLK: PWM67_EN Mask */ + +#define CLK_APBCLK_PWM45_EN_Pos 22 /*!< CLK_T::APBCLK: PWM45_EN Position */ +#define CLK_APBCLK_PWM45_EN_Msk (1ul << CLK_APBCLK_PWM45_EN_Pos) /*!< CLK_T::APBCLK: PWM45_EN Mask */ + +#define CLK_APBCLK_PWM23_EN_Pos 21 /*!< CLK_T::APBCLK: PWM23_EN Position */ +#define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos) /*!< CLK_T::APBCLK: PWM23_EN Mask */ + +#define CLK_APBCLK_PWM01_EN_Pos 20 /*!< CLK_T::APBCLK: PWM01_EN Position */ +#define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos) /*!< CLK_T::APBCLK: PWM01_EN Mask */ + +#define CLK_APBCLK_UART2_EN_Pos 18 /*!< CLK_T::APBCLK: UART2_EN Position */ +#define CLK_APBCLK_UART2_EN_Msk (1ul << CLK_APBCLK_UART2_EN_Pos) /*!< CLK_T::APBCLK: UART2_EN Mask */ + +#define CLK_APBCLK_UART1_EN_Pos 17 /*!< CLK_T::APBCLK: UART1_EN Position */ +#define CLK_APBCLK_UART1_EN_Msk (1ul << CLK_APBCLK_UART1_EN_Pos) /*!< CLK_T::APBCLK: UART1_EN Mask */ + +#define CLK_APBCLK_UART0_EN_Pos 16 /*!< CLK_T::APBCLK: UART0_EN Position */ +#define CLK_APBCLK_UART0_EN_Msk (1ul << CLK_APBCLK_UART0_EN_Pos) /*!< CLK_T::APBCLK: UART0_EN Mask */ + +#define CLK_APBCLK_SPI3_EN_Pos 15 /*!< CLK_T::APBCLK: SPI3_EN Position */ +#define CLK_APBCLK_SPI3_EN_Msk (1ul << CLK_APBCLK_SPI3_EN_Pos) /*!< CLK_T::APBCLK: SPI3_EN Mask */ + +#define CLK_APBCLK_SPI2_EN_Pos 14 /*!< CLK_T::APBCLK: SPI2_EN Position */ +#define CLK_APBCLK_SPI2_EN_Msk (1ul << CLK_APBCLK_SPI2_EN_Pos) /*!< CLK_T::APBCLK: SPI2_EN Mask */ + +#define CLK_APBCLK_SPI1_EN_Pos 13 /*!< CLK_T::APBCLK: SPI1_EN Position */ +#define CLK_APBCLK_SPI1_EN_Msk (1ul << CLK_APBCLK_SPI1_EN_Pos) /*!< CLK_T::APBCLK: SPI1_EN Mask */ + +#define CLK_APBCLK_SPI0_EN_Pos 12 /*!< CLK_T::APBCLK: SPI0_EN Position */ +#define CLK_APBCLK_SPI0_EN_Msk (1ul << CLK_APBCLK_SPI0_EN_Pos) /*!< CLK_T::APBCLK: SPI0_EN Mask */ + +#define CLK_APBCLK_I2C1_EN_Pos 9 /*!< CLK_T::APBCLK: I2C1_EN Position */ +#define CLK_APBCLK_I2C1_EN_Msk (1ul << CLK_APBCLK_I2C1_EN_Pos) /*!< CLK_T::APBCLK: I2C1_EN Mask */ + +#define CLK_APBCLK_I2C0_EN_Pos 8 /*!< CLK_T::APBCLK: I2C0_EN_ Position */ +#define CLK_APBCLK_I2C0_EN_Msk (1ul << CLK_APBCLK_I2C0_EN_Pos) /*!< CLK_T::APBCLK: I2C0_EN_ Mask */ + +#define CLK_APBCLK_FDIV_EN_Pos 6 /*!< CLK_T::APBCLK: FDIV_EN Position */ +#define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos) /*!< CLK_T::APBCLK: FDIV_EN Mask */ + +#define CLK_APBCLK_TMR3_EN_Pos 5 /*!< CLK_T::APBCLK: TMR3_EN Position */ +#define CLK_APBCLK_TMR3_EN_Msk (1ul << CLK_APBCLK_TMR3_EN_Pos) /*!< CLK_T::APBCLK: TMR3_EN Mask */ + +#define CLK_APBCLK_TMR2_EN_Pos 4 /*!< CLK_T::APBCLK: TMR2_EN Position */ +#define CLK_APBCLK_TMR2_EN_Msk (1ul << CLK_APBCLK_TMR2_EN_Pos) /*!< CLK_T::APBCLK: TMR2_EN Mask */ + +#define CLK_APBCLK_TMR1_EN_Pos 3 /*!< CLK_T::APBCLK: TMR1_EN Position */ +#define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos) /*!< CLK_T::APBCLK: TMR1_EN Mask */ + +#define CLK_APBCLK_TMR0_EN_Pos 2 /*!< CLK_T::APBCLK: TMR0_EN Position */ +#define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos) /*!< CLK_T::APBCLK: TMR0_EN Mask */ + +#define CLK_APBCLK_RTC_EN_Pos 1 /*!< CLK_T::APBCLK: RTC_EN Position */ +#define CLK_APBCLK_RTC_EN_Msk (1ul << CLK_APBCLK_RTC_EN_Pos) /*!< CLK_T::APBCLK: RTC_EN Mask */ + +#define CLK_APBCLK_WDT_EN_Pos 0 /*!< CLK_T::APBCLK: WDT_EN Position */ +#define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos) /*!< CLK_T::APBCLK: WDT_EN Mask */ + +/* CLK APBCLK1 Bit Field Definitions */ +#define CLK_APBCLK1_SC2_EN_Pos 2 /*!< CLK_T::APBCLK1: SC2_EN Position */ +#define CLK_APBCLK1_SC2_EN_Msk (1ul << CLK_APBCLK1_SC2_EN_Pos) /*!< CLK_T::APBCLK1: SC2_EN Mask */ + +#define CLK_APBCLK1_SC1_EN_Pos 1 /*!< CLK_T::APBCLK1: SC1_EN Position */ +#define CLK_APBCLK1_SC1_EN_Msk (1ul << CLK_APBCLK1_SC1_EN_Pos) /*!< CLK_T::APBCLK1: SC1_EN Mask */ + +#define CLK_APBCLK1_SC0_EN_Pos 0 /*!< CLK_T::APBCLK1: SC0_EN Position */ +#define CLK_APBCLK1_SC0_EN_Msk (1ul << CLK_APBCLK1_SC0_EN_Pos) /*!< CLK_T::APBCLK1: SC0_EN Mask */ + +/* CLK CLKSTATUS Bit Field Definitions */ +#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7 /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Position */ +#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Mask */ + +#define CLK_CLKSTATUS_OSC22M_STB_Pos 4 /*!< CLK_T::CLKSTATUS: OSC22M_STB Position */ +#define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) /*!< CLK_T::CLKSTATUS: OSC22M_STB Mask */ +#define CLK_CLKSTATUS_IRC22M_STB_Pos 4 /*!< CLK_T::CLKSTATUS: IRC22M_STB Position */ +#define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) /*!< CLK_T::CLKSTATUS: IRC22M_STB Mask */ + +#define CLK_CLKSTATUS_OSC10K_STB_Pos 3 /*!< CLK_T::CLKSTATUS: OSC10K_STB Position */ +#define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) /*!< CLK_T::CLKSTATUS: OSC10K_STB Mask */ +#define CLK_CLKSTATUS_IRC10K_STB_Pos 3 /*!< CLK_T::CLKSTATUS: IRC10K_STB Position */ +#define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) /*!< CLK_T::CLKSTATUS: IRC10K_STB Mask */ + +#define CLK_CLKSTATUS_PLL_STB_Pos 2 /*!< CLK_T::CLKSTATUS: PLL_STB Position */ +#define CLK_CLKSTATUS_PLL_STB_Msk (1ul << CLK_CLKSTATUS_PLL_STB_Pos) /*!< CLK_T::CLKSTATUS: PLL_STB Mask */ + +#define CLK_CLKSTATUS_XTL32K_STB_Pos 1 /*!< CLK_T::CLKSTATUS: XTL32K_STB Position */ +#define CLK_CLKSTATUS_XTL32K_STB_Msk (1ul << CLK_CLKSTATUS_XTL32K_STB_Pos) /*!< CLK_T::CLKSTATUS: XTL32K_STB Mask */ + +#define CLK_CLKSTATUS_XTL12M_STB_Pos 0 /*!< CLK_T::CLKSTATUS: XTL12M_STB Position */ +#define CLK_CLKSTATUS_XTL12M_STB_Msk (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) /*!< CLK_T::CLKSTATUS: XTL12M_STB Mask */ + +/* CLK CLKSEL0 Bit Field Definitions */ +#define CLK_CLKSEL0_STCLK_S_Pos 3 /*!< CLK_T::CLKSEL0: STCLK_S Position */ +#define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos) /*!< CLK_T::CLKSEL0: STCLK_S Mask */ + +#define CLK_CLKSEL0_HCLK_S_Pos 0 /*!< CLK_T::CLKSEL0: HCLK_S Position */ +#define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos) /*!< CLK_T::CLKSEL0: HCLK_S Mask */ + +/* CLK CLKSEL1 Bit Field Definitions */ +#define CLK_CLKSEL1_PWM23_S_Pos 30 /*!< CLK_T::CLKSEL1: PWM23_S Position */ +#define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos) /*!< CLK_T::CLKSEL1: PWM23_S Mask */ + +#define CLK_CLKSEL1_PWM01_S_Pos 28 /*!< CLK_T::CLKSEL1: PWM01_S Position */ +#define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos) /*!< CLK_T::CLKSEL1: PWM01_S Mask */ + +#define CLK_CLKSEL1_UART_S_Pos 24 /*!< CLK_T::CLKSEL1: UART_S Position */ +#define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos) /*!< CLK_T::CLKSEL1: UART_S Mask */ + +#define CLK_CLKSEL1_TMR3_S_Pos 20 /*!< CLK_T::CLKSEL1: TMR3_S Position */ +#define CLK_CLKSEL1_TMR3_S_Msk (7ul << CLK_CLKSEL1_TMR3_S_Pos) /*!< CLK_T::CLKSEL1: TMR3_S Mask */ + +#define CLK_CLKSEL1_TMR2_S_Pos 16 /*!< CLK_T::CLKSEL1: TMR2_S Position */ +#define CLK_CLKSEL1_TMR2_S_Msk (7ul << CLK_CLKSEL1_TMR2_S_Pos) /*!< CLK_T::CLKSEL1: TMR2_S Mask */ + +#define CLK_CLKSEL1_TMR1_S_Pos 12 /*!< CLK_T::CLKSEL1: TMR1_S Position */ +#define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos) /*!< CLK_T::CLKSEL1: TMR1_S Mask */ + +#define CLK_CLKSEL1_TMR0_S_Pos 8 /*!< CLK_T::CLKSEL1: TMR0_S Position */ +#define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos) /*!< CLK_T::CLKSEL1: TMR0_S Mask */ + +#define CLK_CLKSEL1_SPI3_S_Pos 7 /*!< CLK_T::CLKSEL1: SPI3_S Position */ +#define CLK_CLKSEL1_SPI3_S_Msk (1ul << CLK_CLKSEL1_SPI3_S_Pos) /*!< CLK_T::CLKSEL1: SPI3_S Mask */ + +#define CLK_CLKSEL1_SPI2_S_Pos 6 /*!< CLK_T::CLKSEL1: SPI2_S Position */ +#define CLK_CLKSEL1_SPI2_S_Msk (1ul << CLK_CLKSEL1_SPI2_S_Pos) /*!< CLK_T::CLKSEL1: SPI2_S Mask */ + +#define CLK_CLKSEL1_SPI1_S_Pos 5 /*!< CLK_T::CLKSEL1: SPI1_S Position */ +#define CLK_CLKSEL1_SPI1_S_Msk (1ul << CLK_CLKSEL1_SPI1_S_Pos) /*!< CLK_T::CLKSEL1: SPI1_S Mask */ + +#define CLK_CLKSEL1_SPI0_S_Pos 4 /*!< CLK_T::CLKSEL1: SPI0_S Position */ +#define CLK_CLKSEL1_SPI0_S_Msk (1ul << CLK_CLKSEL1_SPI0_S_Pos) /*!< CLK_T::CLKSEL1: SPI0_S Mask */ + +#define CLK_CLKSEL1_ADC_S_Pos 2 /*!< CLK_T::CLKSEL1: ADC_S Position */ +#define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos) /*!< CLK_T::CLKSEL1: ADC_S Mask */ + +#define CLK_CLKSEL1_WDT_S_Pos 0 /*!< CLK_T::CLKSEL1: WDT_S Position */ +#define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos) /*!< CLK_T::CLKSEL1: WDT_S Mask */ + +/* CLK CLKSEL2 Bit Field Definitions */ +#define CLK_CLKSEL2_WWDT_S_Pos 16 /*!< CLK_T::CLKSEL2: WWDT_S Position */ +#define CLK_CLKSEL2_WWDT_S_Msk (3ul << CLK_CLKSEL2_WWDT_S_Pos) /*!< CLK_T::CLKSEL2: WWDT_S Mask */ + +#define CLK_CLKSEL2_PWM67_S_E_Pos 11 /*!< CLK_T::CLKSEL2: PWM67_S_E Position */ +#define CLK_CLKSEL2_PWM67_S_E_Msk (1ul << CLK_CLKSEL2_PWM67_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM67_S_E Mask */ +#define CLK_CLKSEL2_PWM67_S_EXT_Pos 11 /*!< CLK_T::CLKSEL2: PWM67_S_E Position */ +#define CLK_CLKSEL2_PWM67_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM67_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM67_S_E Mask */ + +#define CLK_CLKSEL2_PWM45_S_E_Pos 10 /*!< CLK_T::CLKSEL2: PWM45_S_E Position */ +#define CLK_CLKSEL2_PWM45_S_E_Msk (1ul << CLK_CLKSEL2_PWM45_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM45_S_E Mask */ +#define CLK_CLKSEL2_PWM45_S_EXT_Pos 10 /*!< CLK_T::CLKSEL2: PWM45_S_EXT Position */ +#define CLK_CLKSEL2_PWM45_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM45_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM45_S_EXT Mask */ + +#define CLK_CLKSEL2_PWM23_S_E_Pos 9 /*!< CLK_T::CLKSEL2: PWM23_S_E Position */ +#define CLK_CLKSEL2_PWM23_S_E_Msk (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM23_S_E Mask */ +#define CLK_CLKSEL2_PWM23_S_EXT_Pos 9 /*!< CLK_T::CLKSEL2: PWM23_S_EXT Position */ +#define CLK_CLKSEL2_PWM23_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM23_S_EXT Mask */ + +#define CLK_CLKSEL2_PWM01_S_E_Pos 8 /*!< CLK_T::CLKSEL2: PWM01_S_E Position */ +#define CLK_CLKSEL2_PWM01_S_E_Msk (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM01_S_E Mask */ +#define CLK_CLKSEL2_PWM01_S_EXT_Pos 8 /*!< CLK_T::CLKSEL2: PWM01_S_EXT Position */ +#define CLK_CLKSEL2_PWM01_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM01_S_EXT Mask */ + +#define CLK_CLKSEL2_PWM67_S_Pos 6 /*!< CLK_T::CLKSEL2: PWM67_S_ Position */ +#define CLK_CLKSEL2_PWM67_S_Msk (3ul << CLK_CLKSEL2_PWM67_S_Pos) /*!< CLK_T::CLKSEL2: PWM67_S_ Mask */ + +#define CLK_CLKSEL2_PWM45_S_Pos 4 /*!< CLK_T::CLKSEL2: PWM45_S Position */ +#define CLK_CLKSEL2_PWM45_S_Msk (3ul << CLK_CLKSEL2_PWM45_S_Pos) /*!< CLK_T::CLKSEL2: PWM45_S Mask */ + +#define CLK_CLKSEL2_FRQDIV_S_Pos 2 /*!< CLK_T::CLKSEL2: FRQDIV_S Position */ +#define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) /*!< CLK_T::CLKSEL2: FRQDIV_S Mask */ + +#define CLK_CLKSEL2_I2S_S_Pos 0 /*!< CLK_T::CLKSEL2: I2S_S Position */ +#define CLK_CLKSEL2_I2S_S_Msk (3ul << CLK_CLKSEL2_I2S_S_Pos) /*!< CLK_T::CLKSEL2: I2S_S Mask */ + +/* CLK CLKSEL3 Bit Field Definitions */ +#define CLK_CLKSEL3_SC2_S_Pos 4 /*!< CLK_T::CLKSEL3: SC2_S Position */ +#define CLK_CLKSEL3_SC2_S_Msk (3ul << CLK_CLKSEL3_SC2_S_Pos) /*!< CLK_T::CLKSEL3: SC2_S Mask */ + +#define CLK_CLKSEL3_SC1_S_Pos 2 /*!< CLK_T::CLKSEL3: SC1_S Position */ +#define CLK_CLKSEL3_SC1_S_Msk (3ul << CLK_CLKSEL3_SC1_S_Pos) /*!< CLK_T::CLKSEL3: SC1_S Mask */ + +#define CLK_CLKSEL3_SC0_S_Pos 0 /*!< CLK_T::CLKSEL3: SC0_S Position */ +#define CLK_CLKSEL3_SC0_S_Msk (3ul << CLK_CLKSEL3_SC0_S_Pos) /*!< CLK_T::CLKSEL3: SC0_S Mask */ + +/* CLK CLKDIV Bit Field Definitions */ +#define CLK_CLKDIV_ADC_N_Pos 16 /*!< CLK_T::CLKDIV: ADC_N Position */ +#define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos) /*!< CLK_T::CLKDIV: ADC_N Mask */ + +#define CLK_CLKDIV_UART_N_Pos 8 /*!< CLK_T::CLKDIV: UART_N Position */ +#define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos) /*!< CLK_T::CLKDIV: UART_N Mask */ + +#define CLK_CLKDIV_USB_N_Pos 4 /*!< CLK_T::CLKDIV: USB_N Position */ +#define CLK_CLKDIV_USB_N_Msk (0xFul << CLK_CLKDIV_USB_N_Pos) /*!< CLK_T::CLKDIV: USB_N Mask */ + +#define CLK_CLKDIV_HCLK_N_Pos 0 /*!< CLK_T::CLKDIV: HCLK_N Position */ +#define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos) /*!< CLK_T::CLKDIV: HCLK_N Mask */ + +/* CLK CLKDIV1 Bit Field Definitions */ +#define CLK_CLKDIV1_SC2_N_Pos 16 /*!< CLK_T::CLKDIV: SC2_N Position */ +#define CLK_CLKDIV1_SC2_N_Msk (0xFFul << CLK_CLKDIV1_SC2_N_Pos) /*!< CLK_T::CLKDIV: SC2_N Mask */ + +#define CLK_CLKDIV1_SC1_N_Pos 8 /*!< CLK_T::CLKDIV: SC1_N Position */ +#define CLK_CLKDIV1_SC1_N_Msk (0xFFul << CLK_CLKDIV1_SC1_N_Pos) /*!< CLK_T::CLKDIV: SC1_N Mask */ + +#define CLK_CLKDIV1_SC0_N_Pos 0 /*!< CLK_T::CLKDIV: SC0_N Position */ +#define CLK_CLKDIV1_SC0_N_Msk (0xFFul << CLK_CLKDIV1_SC0_N_Pos) /*!< CLK_T::CLKDIV: SC0_N Mask */ + +/* CLK PLLCON Bit Field Definitions */ +#define CLK_PLLCON_PLL_SRC_Pos 19 /*!< CLK_T::PLLCON: PLL_SRC Position */ +#define CLK_PLLCON_PLL_SRC_Msk (1ul << CLK_PLLCON_PLL_SRC_Pos) /*!< CLK_T::PLLCON: PLL_SRC Mask */ + +#define CLK_PLLCON_OE_Pos 18 /*!< CLK_T::PLLCON: PLL_SRC Position */ +#define CLK_PLLCON_OE_Msk (1ul << CLK_PLLCON_OE_Pos) /*!< CLK_T::PLLCON: PLL_SRC Mask */ + +#define CLK_PLLCON_BP_Pos 17 /*!< CLK_T::PLLCON: OE Position */ +#define CLK_PLLCON_BP_Msk (1ul << CLK_PLLCON_BP_Pos) /*!< CLK_T::PLLCON: OE Mask */ + +#define CLK_PLLCON_PD_Pos 16 /*!< CLK_T::PLLCON: PD Position */ +#define CLK_PLLCON_PD_Msk (1ul << CLK_PLLCON_PD_Pos) /*!< CLK_T::PLLCON: PD Mask */ + +#define CLK_PLLCON_OUT_DV_Pos 14 /*!< CLK_T::PLLCON: OUT_DV Position */ +#define CLK_PLLCON_OUT_DV_Msk (3ul << CLK_PLLCON_OUT_DV_Pos) /*!< CLK_T::PLLCON: OUT_DV Mask */ + +#define CLK_PLLCON_IN_DV_Pos 9 /*!< CLK_T::PLLCON: IN_DV Position */ +#define CLK_PLLCON_IN_DV_Msk (0x1Ful << CLK_PLLCON_IN_DV_Pos) /*!< CLK_T::PLLCON: IN_DV Mask */ + +#define CLK_PLLCON_FB_DV_Pos 0 /*!< CLK_T::PLLCON: FB_DV Position */ +#define CLK_PLLCON_FB_DV_Msk (0x1FFul << CLK_PLLCON_FB_DV_Pos) /*!< CLK_T::PLLCON: FB_DV Mask */ + +/* CLK FRQDIV Bit Field Definitions */ +#define CLK_FRQDIV_DIVIDER_EN_Pos 4 /*!< CLK_T::FRQDIV: DIVIDER_EN Position */ +#define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) /*!< CLK_T::FRQDIV: DIVIDER_EN Mask */ + +#define CLK_FRQDIV_FSEL_Pos 0 /*!< CLK_T::FRQDIV: FRQDIV_FSEL Position */ +#define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos) /*!< CLK_T::FRQDIV: FRQDIV_FSEL Mask */ + +/*@}*/ /* end of group CLK_CONST */ +/*@}*/ /* end of group CLK */ + + + +/*----------------------------- Cyclic Redundancy Check (CRC) Controller -----------------------------*/ +/** @addtogroup CRC Cyclic Redundancy Check Controller (CRC) + Memory Mapped Structure for Cyclic Redundancy Check + @{ + */ + + +typedef struct +{ + + +/** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCCEN |CRC Channel Enable + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * | | |Note1: When operating in CRC DMA mode (TRIG_EN (CRC_CTL[23]) = 1), if user clears this bit, + * | | |the DMA operation will be continuous until all CRC DMA operation is done, and the TRIG_EN + * | | |(CRC_CTL[23]) bit will keep 1until all CRC DMA operation done. + * | | |But in this case, the CRC_BLKD_IF (CRC_DMAISR[1])flag will inactive, user can read CRC + * | | |checksum result only if TRIG_EN (CRC_CTL[23]) clears to 0. + * | | |Note2: When operating in CRC DMA mode (TRIG_EN (CRC_CTL[23]) = 1), if user wants to stop the + * | | |transfer immediately, user can write 1 to CRC_RST (CRC_CTL [1]) bit to stop the + * | | |transmission. + * |[1] |CRC_RST |CRC Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal CRC state machine and internal buffer. + * | | |The others contents of CRC_CTL register will not be cleared. + * | | |This bit will be cleared automatically. + * | | |Note: When operated in CPU PIO mode, setting this bit will reload the initial seed value + * | | |(CRC_SEED register). + * |[23] |TRIG_EN |Trigger Enable + * | | |This bit is used to trigger the CRC DMA transfer. + * | | |0 = No effect. + * | | |1 = CRC DMA data read or write transfer Enabled. + * | | |Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not + * | | |fill in any data in CRC_WDATA register. + * | | |Note2: When CRC DMA transfer completed, this bit will be cleared automatically. + * | | |Note3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be + * | | |stopped. + * | | |Software must reset all DMA channel before trigger DMA again. + * |[24] |WDATA_RVS |Write Data Order Reverse + * | | |This bit is used to enable the bit order reverse function for write data value in CRC_WDATA + * | | |register. + * | | |0 = Bit order reverse for CRC write data in Disabled. + * | | |1 = Bit order reverse for CRC write data in Enabled (per byre). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is + * | | |0x55DD33BB + * |[25] |CHECKSUM_RVS|Checksum Reverse + * | | |This bit is used to enable the bit order reverse function for write data value in + * | | |CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is + * | | |0x74F0DEBB + * |[26] |WDATA_COM |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_WDATA + * | | |register. + * | | |0 = 1's complement for CRC write data in Disabled. + * | | |1 = 1's complement for CRC write data in Enabled. + * |[27] |CHECKSUM_COM|Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM + * | | |register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |1 = 1's complement for CRC checksum Enabled. + * |[29:28] |CPU_WDLEN |CPU Write Data Length + * | | |This field indicates the CPU write data length only when operating in CPU PIO mode. + * | | |00 = The write data length is 8-bit mode. + * | | |01 = The write data length is 16-bit mode. + * | | |10 = The write data length is 32-bit mode. + * | | |11 = Reserved. + * | | |Note1: This field is only valid when operating in CPU PIO mode. + * | | |Note2: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is + * | | |only CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in + * | | |CRC_WDATA register is only CRC_WDATA [15:0]. + * |[31:30] |CRC_MODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial Mode. + * | | |01 = CRC-8 Polynomial Mode. + * | | |10 = CRC-16 Polynomial Mode. + * | | |11 = CRC-32 Polynomial Mode. + * @var CRC_T::DMASAR + * Offset: 0x04 CRC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRC_DMASAR|CRC DMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of CRC DMA. + * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR). + * | | |Note: The source address must be word alignment + * @var CRC_T::DMABCR + * Offset: 0x0C CRC DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRC_DMABCR|CRC DMA Transfer Byte Count Register + * | | |This field indicates a 16-bit total transfer byte count number of CRC DMA + * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR). + * @var CRC_T::DMACSAR + * Offset: 0x14 CRC DMA Current Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRC_DMACSAR|CRC DMA Current Source Address Register (Read Only) + * | | |This field indicates the current source address where the CRC DMA transfer just occurs. + * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR). + * @var CRC_T::DMACBCR + * Offset: 0x1C CRC DMA Current Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRC_DMACBCR|CRC DMA Current Remained Byte Count Register (Read Only) + * | | |This field indicates the current remained byte count of CRC DMA. + * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR). + * | | |Note: Setting CRC_RST (CRC_CTL[1]) bit to 1 will clear this register value. + * @var CRC_T::DMAIER + * Offset: 0x20 CRC DMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRC_TABORT_IE|CRC DMA Read/Write Target Abort Interrupt Enable + * | | |Enable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF + * | | |(CRC_DMAISR[0]) bit is set to 1. + * | | |0 = Target abort interrupt generation Disabled during CRC DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during CRC DMA transfer. + * |[1] |CRC_BLKD_IE|CRC DMA Block Transfer Done Interrupt Enable + * | | |Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF + * | | |(CRC_DMAISR[1]) bit is set to 1. + * | | |0 = Interrupt generator Disabled when CRC DMA transfer done. + * | | |1 = Interrupt generator Enabled when CRC DMA transfer done. + * @var CRC_T::DMAISR + * Offset: 0x24 CRC DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRC_TABORT_IF|CRC DMA Read/Write Target Abort Interrupt Flag + * | | |This bit indicates that CRC bus has error or not during CRC DMA transfer. + * | | |0 = No bus error response received during CRC DMA transfer. + * | | |1 = Bus error response received during CRC DMA transfer. + * | | |It is cleared by writing 1 to it through software. + * | | |Note: The bit filed indicate bus master received error response or not. + * | | |If bus master received error response, it means that CRC transfer target abort is happened. + * | | |DMA will stop transfer and respond this event to software then CRC state machine goes to + * | | |IDLE state. + * | | |When target abort occurred, software must reset DMA before transfer those data again. + * |[1] |CRC_BLKD_IF|CRC DMA Block Transfer Done Interrupt Flag + * | | |This bit indicates that CRC DMA transfer has finished or not. + * | | |0 = Not finished if TRIG_EN (CRC_CTL[23]) bit has enabled. + * | | |1 = CRC transfer done if TRIG_EN (CRC_CTL[23]) bit has enabled. + * | | |It is cleared by writing 1 to it through software. + * | | |(When CRC DMA transfer done, TRIG_EN (CRC_CTL[23]) bit will be cleared automatically) + * @var CRC_T::WDATA + * Offset: 0x80 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRC_WDATA |CRC Write Data Register + * | | |When operating in CPU PIO mode, software can write data to this field to perform CRC + * | | |operation. + * | | |When operating in DMA mode, this field indicates the DMA read data from memory and cannot be + * | | |written. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only + * | | |CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_WDATA + * | | |register is only CRC_WDATA [15:0]. + * @var CRC_T::SEED + * Offset: 0x84 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRC_SEED |CRC Seed Register + * | | |This field indicates the CRC seed value. + * @var CRC_T::CHECKSUM + * Offset: 0x88 CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRC_CHECKSUM|CRC Checksum Register + * | | |This fields indicates the CRC checksum result + */ + + __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */ + __IO uint32_t DMASAR; /* Offset: 0x04 CRC DMA Source Address Register */ + __I uint32_t RESERVED0; + __IO uint32_t DMABCR ; /* Offset: 0x0C CRC DMA Transfer Byte Count Register */ + __I uint32_t RESERVED1; + __I uint32_t DMACSAR; /* Offset: 0x14 CRC DMA Current Source Address Register */ + __I uint32_t RESERVED2; + __I uint32_t DMACBCR; /* Offset: 0x1C CRC DMA Current Transfer Byte Count Register */ + __IO uint32_t DMAIER ; /* Offset: 0x20 CRC DMA Interrupt Enable Register */ + __IO uint32_t DMAISR; /* Offset: 0x24 CRC DMA Interrupt Status Register */ + __I uint32_t RESERVED3[22]; + __IO uint32_t WDATA; /* Offset: 0x80 CRC Write Data Register */ + __IO uint32_t SEED; /* Offset: 0x84 CRC Seed Register */ + __I uint32_t CHECKSUM; /* Offset: 0x88 CRC Checksum Register */ + +} CRC_T; + + + + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +/* CRC CTL Bit Field Definitions */ +#define CRC_CTL_CRC_MODE_Pos 30 /*!< CRC_T::CTL: CRC_MODE Position */ +#define CRC_CTL_CRC_MODE_Msk (0x3ul << CRC_CTL_CRC_MODE_Pos) /*!< CRC_T::CTL: CRC_MODE Mask */ + +#define CRC_CTL_CPU_WDLEN_Pos 28 /*!< CRC_T::CTL: CPU_WDLEN Position */ +#define CRC_CTL_CPU_WDLEN_Msk (0x3ul << CRC_CTL_CPU_WDLEN_Pos) /*!< CRC_T::CTL: CPU_WDLEN Mask */ + +#define CRC_CTL_CHECKSUM_COM_Pos 27 /*!< CRC_T::CTL: CHECKSUM_COM Position */ +#define CRC_CTL_CHECKSUM_COM_Msk (1ul << CRC_CTL_CHECKSUM_COM_Pos) /*!< CRC_T::CTL: CHECKSUM_COM Mask */ + +#define CRC_CTL_WDATA_COM_Pos 26 /*!< CRC_T::CTL: WDATA_COM Position */ +#define CRC_CTL_WDATA_COM_Msk (1ul << CRC_CTL_WDATA_COM_Pos) /*!< CRC_T::CTL: WDATA_COM Mask */ + +#define CRC_CTL_CHECKSUM_RVS_Pos 25 /*!< CRC_T::CTL: CHECKSUM_RVS Position */ +#define CRC_CTL_CHECKSUM_RVS_Msk (1ul << CRC_CTL_CHECKSUM_RVS_Pos) /*!< CRC_T::CTL: CHECKSUM_RVS Mask */ + +#define CRC_CTL_WDATA_RVS_Pos 24 /*!< CRC_T::CTL: WDATA_RVS Position */ +#define CRC_CTL_WDATA_RVS_Msk (1ul << CRC_CTL_WDATA_RVS_Pos) /*!< CRC_T::CTL: WDATA_RVS Mask */ + +#define CRC_CTL_TRIG_EN_Pos 23 /*!< CRC_T::CTL: TRIG_EN Position */ +#define CRC_CTL_TRIG_EN_Msk (1ul << CRC_CTL_TRIG_EN_Pos) /*!< CRC_T::CTL: TRIG_EN Mask */ + +#define CRC_CTL_CRC_RST_Pos 1 /*!< CRC_T::CTL: CRC_RST Position */ +#define CRC_CTL_CRC_RST_Msk (1ul << CRC_CTL_CRC_RST_Pos) /*!< CRC_T::CTL: CRC_RST Mask */ + +#define CRC_CTL_CRCCEN_Pos 0 /*!< CRC_T::CTL: CRCCEN Position */ +#define CRC_CTL_CRCCEN_Msk (1ul << CRC_CTL_CRCCEN_Pos) /*!< CRC_T::CTL: CRCCEN Mask */ + +/* CRC DMASAR Bit Field Definitions */ +#define CRC_DMASAR_CRC_DMASAR_Pos 0 /*!< CRC_T::DMASAR: CRC_DMASAR Position */ +#define CRC_DMASAR_CRC_DMASAR_Msk (0xFFFFFFFFul << CRC_DMASAR_CRC_DMASAR_Pos) /*!< CRC_T::DMASAR: CRC_DMASAR Mask */ + +/* CRC DMABCR Bit Field Definitions */ +#define CRC_DMABCR_CRC_DMABCR_Pos 0 /*!< CRC_T::DMABCR: CRC_DMABCR Position */ +#define CRC_DMABCR_CRC_DMABCR_Msk (0xFFFFul << CRC_DMABCR_CRC_DMABCR_Pos) /*!< CRC_T::DMABCR: CRC_DMABCR Mask */ + +/* CRC DMACSAR Bit Field Definitions */ +#define CRC_DMACSAR_CRC_DMACSAR_Pos 0 /*!< CRC_T::DMACSAR: CRC_DMACSAR Position */ +#define CRC_DMACSAR_CRC_DMACSAR_Msk (0xFFFFFFFFul << CRC_DMACSAR_CRC_DMACSAR_Pos) /*!< CRC_T::DMACSAR: CRC_DMACSAR Mask */ + +/* CRC DMACBCR Bit Field Definitions */ +#define CRC_DMACBCR_CRC_DMACBCR_Pos 0 /*!< CRC_T::DMACBCR: DMACBCR Position */ +#define CRC_DMACBCR_CRC_DMACBCR_Msk (0xFFFFul << CRC_DMACBCR_CRC_DMACBCR_Pos) /*!< CRC_T::DMACBCR: DMACBCR Mask */ + +/* CRC DMAIER Bit Field Definitions */ +#define CRC_DMAIER_CRC_BLKD_IE_Pos 1 /*!< CRC_T::DMAIER: CRC_BLKD_IE Position */ +#define CRC_DMAIER_CRC_BLKD_IE_Msk (1ul << CRC_DMAIER_CRC_BLKD_IE_Pos) /*!< CRC_T::DMAIER: CRC_BLKD_IE Mask */ + +#define CRC_DMAIER_CRC_TABORT_IE_Pos 0 /*!< CRC_T::DMAIER: CRC_TABORT_IE Position */ +#define CRC_DMAIER_CRC_TABORT_IE_Msk (1ul << CRC_DMAIER_CRC_TABORT_IE_Pos) /*!< CRC_T::DMAIER: CRC_TABORT_IE Mask */ + +/* CRC DMAISR Bit Field Definitions */ +#define CRC_DMAISR_CRC_BLKD_IF_Pos 1 /*!< CRC_T::DMAISR: CRC_BLKD_IF Position */ +#define CRC_DMAISR_CRC_BLKD_IF_Msk (1ul << CRC_DMAISR_CRC_BLKD_IF_Pos) /*!< CRC_T::DMAISR: CRC_BLKD_IF Mask */ + +#define CRC_DMAISR_CRC_TABORT_IF_Pos 0 /*!< CRC_T::DMAISR: CRC_TABORT_IF Position */ +#define CRC_DMAISR_CRC_TABORT_IF_Msk (1ul << CRC_DMAISR_CRC_TABORT_IF_Pos) /*!< CRC_T::DMAISR: CRC_TABORT_IF Mask */ + +/* CRC WDATA Bit Field Definitions */ +#define CRC_WDATA_CRC_WDATA_Pos 0 /*!< CRC_T::WDATA: CRC_WDATA Position */ +#define CRC_WDATA_CRC_WDATA_Msk (0xFFFFFFFFul << CRC_WDATA_CRC_WDATA_Pos) /*!< CRC_T::WDATA: CRC_WDATA Mask */ + +/* CRC SEED Bit Field Definitions */ +#define CRC_SEED_CRC_SEED_Pos 0 /*!< CRC_T::SEED: CRC_SEED Position */ +#define CRC_SEED_CRC_SEED_Msk (0xFFFFFFFFul << CRC_SEED_CRC_SEED_Pos) /*!< CRC_T::SEED: CRC_SEED Mask */ + +/* CRC CHECKSUM Bit Field Definitions */ +#define CRC_CHECKSUM_CRC_CHECKSUM_Pos 0 /*!< CRC_T::CHECKSUM: CRC_CHECKSUM Position */ +#define CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xFFFFFFFFul << CRC_CHECKSUM_CRC_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CRC_CHECKSUM Mask */ +/*@}*/ /* end of group CRC_CONST */ +/*@}*/ /* end of group CRC */ + + + +/*---------------------- External Bus Interface Controller -------------------------*/ +/** + @addtogroup EBI External Bus Interface Controller (EBI) + Memory Mapped Structure for EBI Controller +@{ */ + + + +typedef struct +{ + + +/** + * @var EBI_T::EBICON + * Offset: 0x00 EBI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ExtEN |EBI Enable + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function is disabled + * | | |1 = EBI function is enabled + * |[1] |ExtBW16 |EBI data width 16 bit + * | | |This bit defines if the data bus is 8-bit or 16-bit. + * | | |0 = EBI data width is 8 bit + * | | |1 = EBI data width is 16 bit + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock is controlled by MCLKDIV. + * | | |000 = HCLK/1 + * | | |001 = HCLK/2 + * | | |010 = HCLK/4 + * | | |011 = HCLK/8 + * | | |100 = HCLK/16 + * | | |101 = HCKL/32 + * | | |11X = default + * | | |Notice: Default value of output clock is HCLK/1 + * |[18:16] |ExttALE |Expand Time of ALE + * | | |The ALE width (tALE) to latch the address can be controlled by ExttALE. + * | | |tALE = (ExttALE + 1) * MCLK + * @var EBI_T::EXTIME + * Offset: 0x04 EBI Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |ExttACC |EBI Data Access Time + * | | |ExttACC define data access time (tACC). + * | | |tACC = (ExttACC + 1) * MCLK + * |[10:8] |ExttAHD |EBI Data Access Hold Time + * | | |ExttAHD define data access hold time (tAHD). + * | | |tAHD = (ExttAHD + 1) * MCLK + * |[15:12] |ExtIW2X |Idle State Cycle After Write + * | | |When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not + * | | |zero. + * | | |Idle state cycle = (ExtIW2X * MCLK) + * |[27:24] |ExtIR2R |Idle State Cycle Between Read-Read + * | | |When read action is finish and next action is going to read, idle state is inserted and nCS + * | | |return + * | | |to high if ExtIR2R is not zero. + * | | |Idle state cycle = (ExtIR2R * MCLK) + * @var EBI_T::EBICON2 + * Offset: 0x08 External Bus Interface General Control Register 2 + * --------------------------------------------------------------------------------------------------- + */ + + __IO uint32_t EBICON; /* Offset: 0x00 EBI Control Register */ + __IO uint32_t EXTIME; /* Offset: 0x04 EBI Timing Control Register */ + __IO uint32_t EBICON2; /* Offset: 0x08 External Bus Interface General Control Register 2 */ + +} EBI_T; + + + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +/* EBI EBICON Bit Field Definitions */ +#define EBI_EBICON_ExttALE_Pos 16 /*!< EBI_T::EBICON: ExttALE Position */ +#define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos) /*!< EBI_T::EBICON: ExttALE Mask */ + +#define EBI_EBICON_MCLKDIV_Pos 8 /*!< EBI_T::EBICON: MCLKDIV Position */ +#define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos) /*!< EBI_T::EBICON: MCLKDIV Mask */ + +#define EBI_EBICON_ExtBW16_Pos 1 /*!< EBI_T::EBICON: ExtBW16 Position */ +#define EBI_EBICON_ExtBW16_Msk (1ul << EBI_EBICON_ExtBW16_Pos) /*!< EBI_T::EBICON: ExtBW16 Mask */ + +#define EBI_EBICON_ExtEN_Pos 0 /*!< EBI_T::EBICON: ExtEN Position */ +#define EBI_EBICON_ExtEN_Msk (1ul << EBI_EBICON_ExtEN_Pos) /*!< EBI_T::EBICON: ExtEN Mask */ + +/* EBI EXTIME Bit Field Definitions */ +#define EBI_EXTIME_ExtIR2R_Pos 24 /*!< EBI_T::EXTIME: ExtIR2R Position */ +#define EBI_EXTIME_ExtIR2R_Msk (0xFul << EBI_EXTIME_ExtIR2R_Pos) /*!< EBI_T::EXTIME: ExtIR2R Mask */ + +#define EBI_EXTIME_ExtIW2X_Pos 12 /*!< EBI_T::EXTIME: ExtIW2X Position */ +#define EBI_EXTIME_ExtIW2X_Msk (0xFul << EBI_EXTIME_ExtIW2X_Pos) /*!< EBI_T::EXTIME: ExtIW2X Mask */ + +#define EBI_EXTIME_ExttAHD_Pos 8 /*!< EBI_T::EXTIME: ExttAHD Position */ +#define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos) /*!< EBI_T::EXTIME: ExttAHD Mask */ + +#define EBI_EXTIME_ExttACC_Pos 3 /*!< EBI_T::EXTIME: ExttACC Position */ +#define EBI_EXTIME_ExttACC_Msk (0x1Ful << EBI_EXTIME_ExttACC_Pos) /*!< EBI_T::EXTIME: ExttACC Mask */ + +/* EBI EBICON2 Bit Field Definitions */ +#define EBI_EBICON2_WAHD_OFF_Pos 2 /*!< EBI_T::EBICON2: WAHD_OFF Position */ +#define EBI_EBICON2_WAHD_OFF_Msk (1ul << EBI_EBICON2_WAHD_OFF_Pos) /*!< EBI_T::EBICON2: WAHD_OFF Mask */ + +#define EBI_EBICON2_RAHD_OFF_Pos 1 /*!< EBI_T::EBICON2: RAHD_OFF Position */ +#define EBI_EBICON2_RAHD_OFF_Msk (1ul << EBI_EBICON2_RAHD_OFF_Pos) /*!< EBI_T::EBICON2: RAHD_OFF Mask */ + +#define EBI_EBICON2_WBUFF_EN_Pos 0 /*!< EBI_T::EBICON2: WBUFF_EN Position */ +#define EBI_EBICON2_WBUFF_EN_Msk (1ul << EBI_EBICON2_WBUFF_EN_Pos) /*!< EBI_T::EBICON2: WBUFF_EN Mask */ +/*@}*/ /* end of group EBI_CONST */ +/*@}*/ /* end of group EBI */ + + + +/*---------------------- Flash Memory Controller -------------------------*/ +/** + @addtogroup FMC Flash Memory Controller (FMC) + Memory Mapped Structure for FMC Controller +@{ */ + + +typedef struct +{ + + +/** + * @var FMC_T::ISPCON + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable + * | | |This bit is protected bit. ISP function enable bit. Set this bit to enable ISP function. + * | | |1 = Enable ISP function + * | | |0 = Disable ISP function + * |[1] |BS |Boot Select + * | | |This bit is protected bit. Set/clear this bit to select next booting from LDROM/APROM, + * | | |respectively. This bit also functions as MCU booting status flag, which can be used to check + * | | |where + * | | |MCU booted from. This bit is initiated with the inverted value of CBS in Config0 after + * | | |power- + * | | |on reset; It keeps the same value at other reset. + * | | |1 = boot from LDROM + * | | |0 = boot from APROM + * |[4] |CFGUEN |Config Update Enable + * | | |Writing this bit to 1 enables s/w to update Config value by ISP procedure regardless of + * | | |program + * | | |code is running in APROM or LDROM. + * | | |1 = Config update enable + * | | |0 = Config update disable + * |[5] |LDUEN |LDROM Update Enable + * | | |LDROM update enable bit. + * | | |1 = LDROM can be updated when the MCU runs in APROM. + * | | |0 = LDROM cannot be updated + * |[6] |ISPFF |ISP Fail Flag + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself. + * | | |(2) LDROM writes to itself. + * | | |(3) Destination address is illegal, such as over an available range. + * | | |Write 1 to clear. + * |[7] |SWRST |Software Reset + * | | |Writing 1 to this bit to start software reset. + * | | |It is cleared by hardware after reset is finished. + * |[10:8] |PT |Flash Program Time + * | | |000 = 40 us + * | | |001 = 45 us + * | | |010 = 50 us + * | | |011 = 55 us + * | | |100 = 20 us + * | | |101 = 25 us + * | | |110 = 30 us + * | | |111 = 35 us + * |[14:12] |ET |Flash Erase Time + * | | |000 = 20 ms (default) + * | | |001 = 25 ms + * | | |010 = 30 ms + * | | |011 = 35 ms + * | | |100 = 3 ms + * | | |101 = 5 ms + * | | |110 = 10 ms + * | | |111 = 15 ms + * @var FMC_T::ISPADR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADR |ISP Address + * | | |NuMicro M051 series equips with a maximum 16kx32 embedded flash, it supports word program + * | | |only. ISPARD[1:0] must be kept 2'b00 for ISP operation. + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation + * | | |Read data from this register after ISP read operation + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FOEN_FCEN_FCTRL|ISP Command + * | | |ISP command table is shown below: + * | | |Operation Mode, FOEN, FCEN, FCTRL[3:0] + * | | |Read , 0, 0, 0000 + * | | |Program , 1, 0, 0001 + * | | |Page Erase , 1, 0, 0010 + * @var FMC_T::ISPTRG + * Offset: 0x10 IISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP start trigger + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically + * | | |when ISP + * | | |operation is finish. + * | | |1 = ISP is on going + * | | |0 = ISP done + * @var FMC_T::DFBADR + * Offset: 0x14 Data Flash Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DFBA |Data Flash Base Address + * | | |This register indicates data flash start address. + * | | |It is a read only register. + * | | |For 8/16/32/64kB flash memory device, the data flash size is 4kB and it start address is + * | | |fixed at + * | | |0x01F000 by hardware internally. + * @var FMC_T::FATCON + * Offset: 0x18 Flash Access Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FPSEN |Flash Power Save Enable + * | | |If CPU clock is slower than 24 MHz, then s/w can enable flash power saving function. + * | | |1 = Enable flash power saving + * | | |0 = Disable flash power saving + * |[3:1] |FATS |Flash Access Time Window Select + * | | |These bits are used to decide flash sense amplifier active duration. + * | | |000 = 40 ns + * | | |001 = 50 ns + * | | |010 = 60 ns + * | | |011 = 70 ns + * | | |100 = 80 ns + * | | |101 = 90 ns + * | | |110 = 100 ns + * | | |111 = Reserved + * |[4] |L_SPEED |Flash Low Speed Mode Enable + * | | |1 = Flash access always no wait state (zero wait state) + * | | |0 = Insert wait state while Flash access discontinued address. + * | | |Note: Set this bit only when HCLK <= 25MHz. If HCLK > 25MHz, CPU will fetch wrong + * | | |code and cause fail result. + * @var FMC_T::ISPSTA + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware + * | | |automatically when ISP operation is finished. + * | | |0 = ISP operation finished. + * | | |1 = ISP operation progressed. + * | | |Note: This bit is the same as ISPTRG bit0 + * |[2:1] |CBS |Chip Boot Selection (Read Only) + * | | |This is a mirror of CBS in Config0. + * |[6] |ISPFF |ISP Fail Flag (Write-protection Bit) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself. + * | | |(2) LDROM writes to itself. + * | | |(3) CONFIG is erased/programmed when CFGUEN is set to 0 + * | | |(4) Destination address is illegal, such as over an available range. + * |[20:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |The current flash address space 0x0000_0000~0x0000_01FF is mapping to the address + * | | |{VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF} + */ + + __IO uint32_t ISPCON; /* Offset: 0x00 ISP Control Register */ + __IO uint32_t ISPADR; /* Offset: 0x04 ISP Address Register */ + __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */ + __IO uint32_t ISPCMD; /* Offset: 0x0C ISP Command Register */ + __IO uint32_t ISPTRG; /* Offset: 0x10 IISP Trigger Control Register */ + __I uint32_t DFBADR; /* Offset: 0x14 Data Flash Base Address Register */ + __IO uint32_t FATCON; /* Offset: 0x18 Flash Access Time Control Register */ + __I uint32_t RESERVED[9]; + __IO uint32_t ISPSTA; /* Offset: 0x40 ISP Status Register */ + +} FMC_T; + + + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +/* FMC ISPCON Bit Field Definitions */ +#define FMC_ISPCON_ET_Pos 12 /*!< FMC_T::ISPCON: ET Position */ +#define FMC_ISPCON_ET_Msk (7ul << FMC_ISPCON_ET_Pos) /*!< FMC_T::ISPCON: ET Mask */ + +#define FMC_ISPCON_PT_Pos 8 /*!< FMC_T::ISPCON: PT Position */ +#define FMC_ISPCON_PT_Msk (7ul << FMC_ISPCON_PT_Pos) /*!< FMC_T::ISPCON: PT Mask */ + +#define FMC_ISPCON_ISPFF_Pos 6 /*!< FMC_T::ISPCON: ISPFF Position */ +#define FMC_ISPCON_ISPFF_Msk (1ul << FMC_ISPCON_ISPFF_Pos) /*!< FMC_T::ISPCON: ISPFF Mask */ + +#define FMC_ISPCON_LDUEN_Pos 5 /*!< FMC_T::ISPCON: LDUEN Position */ +#define FMC_ISPCON_LDUEN_Msk (1ul << FMC_ISPCON_LDUEN_Pos) /*!< FMC_T::ISPCON: LDUEN Mask */ + +#define FMC_ISPCON_CFGUEN_Pos 4 /*!< FMC_T::ISPCON: CFGUEN Position */ +#define FMC_ISPCON_CFGUEN_Msk (1ul << FMC_ISPCON_CFGUEN_Pos) /*!< FMC_T::ISPCON: CFGUEN Mask */ + +#define FMC_ISPCON_APUEN_Pos 3 /*!< FMC_T::ISPCON: APUEN Position */ +#define FMC_ISPCON_APUEN_Msk (1ul << FMC_ISPCON_APUEN_Pos) /*!< FMC_T::ISPCON: APUEN Mask */ + +#define FMC_ISPCON_BS_Pos 1 /*!< FMC_T::ISPCON: BS Position */ +#define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) /*!< FMC_T::ISPCON: BS Mask */ + +#define FMC_ISPCON_ISPEN_Pos 0 /*!< FMC_T::ISPCON: ISPEN Position */ +#define FMC_ISPCON_ISPEN_Msk (1ul << FMC_ISPCON_ISPEN_Pos) /*!< FMC_T::ISPCON: ISPEN Mask */ + +/* FMC ISPADR Bit Field Definitions */ +#define FMC_ISPADR_ISPADR_Pos 0 /*!< FMC_T::ISPADR: ISPADR Position */ +#define FMC_ISPADR_ISPADR_Msk (0xFFFFFFFFul << FMC_ISPADR_ISPADR_Pos) /*!< FMC_T::ISPADR: ISPADR Mask */ + +/* FMC ISPADR Bit Field Definitions */ +#define FMC_ISPDAT_ISPDAT_Pos 0 /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xFFFFFFFFul << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +/* FMC ISPCMD Bit Field Definitions */ +#define FMC_ISPCMD_FOEN_Pos 5 /*!< FMC_T::ISPCMD: FOEN Position */ +#define FMC_ISPCMD_FOEN_Msk (1ul << FMC_ISPCMD_FOEN_Pos) /*!< FMC_T::ISPCMD: FOEN Mask */ + +#define FMC_ISPCMD_FCEN_Pos 4 /*!< FMC_T::ISPCMD: FCEN Position */ +#define FMC_ISPCMD_FCEN_Msk (1ul << FMC_ISPCMD_FCEN_Pos) /*!< FMC_T::ISPCMD: FCEN Mask */ + +#define FMC_ISPCMD_FCTRL_Pos 0 /*!< FMC_T::ISPCMD: FCTRL Position */ +#define FMC_ISPCMD_FCTRL_Msk (0xFul << FMC_ISPCMD_FCTRL_Pos) /*!< FMC_T::ISPCMD: FCTRL Mask */ + +/* FMC ISPTRG Bit Field Definitions */ +#define FMC_ISPTRG_ISPGO_Pos 0 /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +/* FMC DFBADR Bit Field Definitions */ +#define FMC_DFBADR_DFBA_Pos 0 /*!< FMC_T::DFBADR: DFBA Position */ +#define FMC_DFBADR_DFBA_Msk (0xFFFFFFFFul << FMC_DFBADR_DFBA_Pos) /*!< FMC_T::DFBADR: DFBA Mask */ + +/* FMC FATCON Bit Field Definitions */ +#define FMC_FATCON_FOMSEL1_Pos 6 /*!< FMC_T::FATCON: FOMSEL1 Position */ +#define FMC_FATCON_FOMSEL1_Msk (1ul << FMC_FATCON_FOMSEL1_Pos) /*!< FMC_T::FATCON: FOMSEL1 Mask */ + +#define FMC_FATCON_FOMSEL0_Pos 4 /*!< FMC_T::FATCON: FOMSEL0 Position */ +#define FMC_FATCON_FOMSEL0_Msk (1ul << FMC_FATCON_FOMSEL0_Pos) /*!< FMC_T::FATCON: FOMSEL0 Mask */ + +#define FMC_FATCON_FATS_Pos 1 /*!< FMC_T::FATCON: FATS Position */ +#define FMC_FATCON_FATS_Msk (7ul << FMC_FATCON_FATS_Pos) /*!< FMC_T::FATCON: FATS Mask */ + +#define FMC_FATCON_FPSEN_Pos 0 /*!< FMC_T::FATCON: FPSEN Position */ +#define FMC_FATCON_FPSEN_Msk (1ul << FMC_FATCON_FPSEN_Pos) /*!< FMC_T::FATCON: FPSEN Mask */ + + +#define FMC_ISPSTA_ISPGO_Pos 0 /*!< FMC_T::ISPSTA: ISPGO Position */ +#define FMC_ISPSTA_ISPGO_Msk (1ul << FMC_ISPSTA_ISPGO_Pos) /*!< FMC_T::ISPSTA: ISPGO Mask */ + +#define FMC_ISPSTA_CBS_Pos 1 /*!< FMC_T::ISPSTA: CBS Position */ +#define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) /*!< FMC_T::ISPSTA: CBS Mask */ + +#define FMC_ISPSTA_ISPFF_Pos 6 /*!< FMC_T::ISPSTA: ISPFF Position */ +#define FMC_ISPSTA_ISPFF_Msk (0x3ul << FMC_ISPSTA_ISPFF_Pos) /*!< FMC_T::ISPSTA: ISPFF Mask */ + +#define FMC_ISPSTA_VECMAP_Pos 9 /*!< FMC_T::ISPSTA: VECMAP Position */ +#define FMC_ISPSTA_VECMAP_Msk (0xFFFul << FMC_ISPSTA_VECMAP_Pos) /*!< FMC_T::ISPSTA: VECMAP Mask */ +/*@}*/ /* end of group FMC_CONST */ +/*@}*/ /* end of group FMC */ + + + + +/*---------------------- General Purpose Input/Output Controller -------------------------*/ +/** + @addtogroup GPIO General Purpose Input/Output Controller (GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + +/** + * @var GPIO_T::PMD + * Offset: 0x00 GPIO Port [A/B/C/D/E/F] Pin I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PMDn |GPIOx I/O Pin[n] Mode Control + * | | |Determine each I/O mode of GPIOx pins. + * | | |00 = GPIO port [n] pin is in Input mode. + * | | |01 = GPIO port [n] pin is in Push-pull Output mode. + * | | |10 = GPIO port [n] pin is in Open-drain Output mode. + * | | |11 = GPIO port [n] pin is in Quasi-bidirectional mode. + * | | |Note1: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * | | |Note2: + * | | |The initial value of this field is defined by CIOINI (Config0[10]). + * | | |If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. + * | | |If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. + * @var GPIO_T::OFFD + * Offset: 0x04 GPIO Port [A/B/C/D/E/F] Pin Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |OFFD |GPIOx Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. + * | | |If input is analog signal, users can disable GPIO digital input path to avoid current leakage. + * | | |0 = I/O digital input path Enabled. + * | | |1 = I/O digital input path Disabled (digital input tied to low). + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::DOUT + * Offset: 0x08 GPIO Port [A/B/C/D/E/F] Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |GPIOx Pin[n] Output Value + * | | |Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode. + * | | |0 = GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::DMASK + * Offset: 0x0C GPIO Port [A/B/C/D/E/F] Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DMASKn |Port [A/B/C/D/E/F] Data Output Write Mask + * | | |These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. + * | | |When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. + * | | |If the write signal is masked, write data to the protect bit is ignored. + * | | |0 = Corresponding GPIOx_DOUT[n] bit can be updated. + * | | |1 = Corresponding GPIOx_DOUT[n] bit protected. + * | | |Note1: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect the corresponding bit control register (PAn_PDIO, PBn_PDIO, PCn_PDIO, PDn_PDIO, PEn_PDIO and PFn_PDIO). + * | | |Note2: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::PIN + * Offset: 0x10 GPIO Port [A/B/C/D/E/F] Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port [A/B/C/D/E/F] Pin Values + * | | |Each bit of the register reflects the actual status of the respective GPIO pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::DBEN + * Offset: 0x14 GPIO Port [A/B/C/D/E/F] De-bounce Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port [A/B/C/D/E/F] Input Signal De-Bounce Enable + * | | |DBEN[n] is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]. + * | | |0 = Bit[n] de-bounce function Disabled. + * | | |1 = Bit[n] de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::IMD + * Offset: 0x18 GPIO Port [A/B/C/D/E/F] Interrupt Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |IMDn |Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control + * | | |IMD[n] is used to control the interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK. + * | | |clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::IEN + * Offset: 0x1C GPIO Port [A/B/C/D/E/F] Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |IF_ENn |Port [A/B/C/D/E/F] Interrupt Enable By Input Falling Edge Or Input Level Low + * | | |IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the IF_EN[n] bit to 1: + * | | |If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. + * | | |If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. + * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled. + * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * |[n+16] |IR_ENn |Port [A/B/C/D/E/F] Interrupt Enable By Input Rising Edge Or Input Level High + * | | |IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the IR_EN[n] bit to 1: + * | | |If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. + * | | |If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. + * | | |0 = PIN[n] level-high or low-to-high interrupt Disabled. + * | | |1 = PIN[n] level-high or low-to-high interrupt Enabled. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + * @var GPIO_T::ISRC + * Offset: 0x20 GPIO Port [A/B/C/D/E/F] Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |ISRCn |Port [A/B/C/D/E/F] Interrupt Source Flag + * | | |Read : + * | | |0 = No interrupt at GPIOx[n]. + * | | |1 = GPIOx[n] generates an interrupt. + * | | |Write : + * | | |0= No action. + * | | |1= Clear the corresponding pending interrupt. + * | | |Note: Max. n = 3 for GPIOF; Max. n = 15 for GPIOA/GPIOB/GPIOC/GPIOD/GPIOE. + */ + + __IO uint32_t PMD; /* Offset: 0x00 GPIO Port [A/B/C/D/E/F] Pin I/O Mode Control */ + __IO uint32_t OFFD; /* Offset: 0x04 GPIO Port [A/B/C/D/E/F] Pin Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08 GPIO Port [A/B/C/D/E/F] Data Output Value */ + __IO uint32_t DMASK; /* Offset: 0x0C GPIO Port [A/B/C/D/E/F] Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10 GPIO Port [A/B/C/D/E/F] Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14 GPIO Port [A/B/C/D/E/F] De-bounce Enable */ + __IO uint32_t IMD; /* Offset: 0x18 GPIO Port [A/B/C/D/E/F] Interrupt Mode Control */ + __IO uint32_t IEN; /* Offset: 0x1C GPIO Port [A/B/C/D/E/F] Interrupt Enable */ + __IO uint32_t ISRC; /* Offset: 0x20 GPIO Port [A/B/C/D/E/F] Interrupt Source Flag */ + +} GPIO_T; + + + + + +typedef struct +{ + + +/** + * @var GPIO_DBNCECON_T::DBNCECON + * Offset: 0x180 External Interrupt De-bounce Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks + * | | |0001 = Sample interrupt input once per 2 clocks + * | | |0010 = Sample interrupt input once per 4 clocks + * | | |0011 = Sample interrupt input once per 8 clocks + * | | |0100 = Sample interrupt input once per 16 clocks + * | | |0101 = Sample interrupt input once per 32 clocks + * | | |0110 = Sample interrupt input once per 64 clocks + * | | |0111 = Sample interrupt input once per 128 clocks + * | | |1000 = Sample interrupt input once per 256 clocks + * | | |1001 = Sample interrupt input once per 2*256 clocks + * | | |1010 = Sample interrupt input once per 4*256clocks + * | | |1011 = Sample interrupt input once per 8*256 clocks + * | | |1100 = Sample interrupt input once per 16*256 clocks + * | | |1101 = Sample interrupt input once per 32*256 clocks + * | | |1110 = Sample interrupt input once per 64*256 clocks + * | | |1111 = Sample interrupt input once per 128*256 clocks + * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the internal 10 kHz low speed oscillator. + * |[5] |ICLK_ON |Interrupt Clock On Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |It is recommended to turn off this bit to save system power if no special application concern. + */ + + __IO uint32_t DBNCECON; /* Offset: 0x180 External Interrupt De-bounce Control */ + +} GPIO_DBNCECON_T; + + + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + + +/* GPIO PMD Bit Field Definitions */ +#define GPIO_PMD_PMD15_Pos 30 /*!< GPIO_T::PMD: PMD15 Position */ +#define GPIO_PMD_PMD15_Msk (0x3ul << GPIO_PMD_PMD15_Pos) /*!< GPIO_T::PMD: PMD15 Mask */ + +#define GPIO_PMD_PMD14_Pos 28 /*!< GPIO_T::PMD: PMD14 Position */ +#define GPIO_PMD_PMD14_Msk (0x3ul << GPIO_PMD_PMD14_Pos) /*!< GPIO_T::PMD: PMD14 Mask */ + +#define GPIO_PMD_PMD13_Pos 26 /*!< GPIO_T::PMD: PMD13 Position */ +#define GPIO_PMD_PMD13_Msk (0x3ul << GPIO_PMD_PMD13_Pos) /*!< GPIO_T::PMD: PMD13 Mask */ + +#define GPIO_PMD_PMD12_Pos 24 /*!< GPIO_T::PMD: PMD12 Position */ +#define GPIO_PMD_PMD12_Msk (0x3ul << GPIO_PMD_PMD12_Pos) /*!< GPIO_T::PMD: PMD12 Mask */ + +#define GPIO_PMD_PMD11_Pos 22 /*!< GPIO_T::PMD: PMD11 Position */ +#define GPIO_PMD_PMD11_Msk (0x3ul << GPIO_PMD_PMD11_Pos) /*!< GPIO_T::PMD: PMD11 Mask */ + +#define GPIO_PMD_PMD10_Pos 20 /*!< GPIO_T::PMD: PMD10 Position */ +#define GPIO_PMD_PMD10_Msk (0x3ul << GPIO_PMD_PMD10_Pos) /*!< GPIO_T::PMD: PMD10 Mask */ + +#define GPIO_PMD_PMD9_Pos 18 /*!< GPIO_T::PMD: PMD9 Position */ +#define GPIO_PMD_PMD9_Msk (0x3ul << GPIO_PMD_PMD9_Pos) /*!< GPIO_T::PMD: PMD9 Mask */ + +#define GPIO_PMD_PMD8_Pos 16 /*!< GPIO_T::PMD: PMD8 Position */ +#define GPIO_PMD_PMD8_Msk (0x3ul << GPIO_PMD_PMD8_Pos) /*!< GPIO_T::PMD: PMD8 Mask */ + +#define GPIO_PMD_PMD7_Pos 14 /*!< GPIO_T::PMD: PMD7 Position */ +#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos) /*!< GPIO_T::PMD: PMD7 Mask */ + +#define GPIO_PMD_PMD6_Pos 12 /*!< GPIO_T::PMD: PMD6 Position */ +#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos) /*!< GPIO_T::PMD: PMD6 Mask */ + +#define GPIO_PMD_PMD5_Pos 10 /*!< GPIO_T::PMD: PMD5 Position */ +#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos) /*!< GPIO_T::PMD: PMD5 Mask */ + +#define GPIO_PMD_PMD4_Pos 8 /*!< GPIO_T::PMD: PMD4 Position */ +#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos) /*!< GPIO_T::PMD: PMD4 Mask */ + +#define GPIO_PMD_PMD3_Pos 6 /*!< GPIO_T::PMD: PMD3 Position */ +#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos) /*!< GPIO_T::PMD: PMD3 Mask */ + +#define GPIO_PMD_PMD2_Pos 4 /*!< GPIO_T::PMD: PMD2 Position */ +#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos) /*!< GPIO_T::PMD: PMD2 Mask */ + +#define GPIO_PMD_PMD1_Pos 2 /*!< GPIO_T::PMD: PMD1 Position */ +#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos) /*!< GPIO_T::PMD: PMD1 Mask */ + +#define GPIO_PMD_PMD0_Pos 0 /*!< GPIO_T::PMD: PMD0 Position */ +#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos) /*!< GPIO_T::PMD: PMD0 Mask */ + +/* GPIO OFFD Bit Field Definitions */ +#define GPIO_OFFD_OFFD_Pos 16 /*!< GPIO_T::OFFD: OFFD Position */ +#define GPIO_OFFD_OFFD_Msk (0xFFFFul << GPIO_OFFD_OFFD_Pos) /*!< GPIO_T::OFFD: OFFD Mask */ + +/* GPIO DOUT Bit Field Definitions */ +#define GPIO_DOUT_DOUT_Pos 0 /*!< GPIO_T::DOUT: DOUT Position */ +#define GPIO_DOUT_DOUT_Msk (0xFFFFul << GPIO_DOUT_DOUT_Pos) /*!< GPIO_T::DOUT: DOUT Mask */ + +/* GPIO DMASK Bit Field Definitions */ +#define GPIO_DMASK_DMASK_Pos 0 /*!< GPIO_T::DMASK: DMASK Position */ +#define GPIO_DMASK_DMASK_Msk (0xFFFFul << GPIO_DMASK_DMASK_Pos) /*!< GPIO_T::DMASK: DMASK Mask */ + +/* GPIO PIN Bit Field Definitions */ +#define GPIO_PIN_PIN_Pos 0 /*!< GPIO_T::PIN: PIN Position */ +#define GPIO_PIN_PIN_Msk (0xFFFFul << GPIO_PIN_PIN_Pos) /*!< GPIO_T::PIN: PIN Mask */ + +/* GPIO DBEN Bit Field Definitions */ +#define GPIO_DBEN_DBEN_Pos 0 /*!< GPIO_T::DBEN: DBEN Position */ +#define GPIO_DBEN_DBEN_Msk (0xFFFFul << GPIO_DBEN_DBEN_Pos) /*!< GPIO_T::DBEN: DBEN Mask */ + +/* GPIO IMD Bit Field Definitions */ +#define GPIO_IMD_IMD_Pos 0 /*!< GPIO_T::IMD: IMD Position */ +#define GPIO_IMD_IMD_Msk (0xFFFFul << GPIO_IMD_IMD_Pos) /*!< GPIO_T::IMD: IMD Mask */ + +/* GPIO IEN Bit Field Definitions */ +#define GPIO_IEN_IR_EN_Pos 16 /*!< GPIO_T::IEN: IR_EN Position */ +#define GPIO_IEN_IR_EN_Msk (0xFFFFul << GPIO_IEN_IR_EN_Pos) /*!< GPIO_T::IEN: IR_EN Mask */ + +#define GPIO_IEN_IF_EN_Pos 0 /*!< GPIO_T::IEN: IF_EN Position */ +#define GPIO_IEN_IF_EN_Msk (0xFFFFul << GPIO_IEN_IF_EN_Pos) /*!< GPIO_T::IEN: IF_EN Mask */ + +/* GPIO ISRC Bit Field Definitions */ +#define GPIO_ISRC_ISRC_Pos 0 /*!< GPIO_T::ISRC: ISRC Position */ +#define GPIO_ISRC_ISRC_Msk (0xFFFFul << GPIO_ISRC_ISRC_Pos) /*!< GPIO_T::ISRC: ISRC Mask */ + +/* GPIO DBNCECON Bit Field Definitions */ +#define GPIO_DBNCECON_ICLK_ON_Pos 5 /*!< GPIO_DBNCECON_T::DBNCECON: ICLK_ON Position */ +#define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: ICLK_ON Mask */ + +#define GPIO_DBNCECON_DBCLKSRC_Pos 4 /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSRC Position */ +#define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSRC Mask */ + +#define GPIO_DBNCECON_DBCLKSEL_Pos 0 /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSEL Position */ +#define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSEL Mask */ +/*@}*/ /* end of group GPIO_CONST */ +/*@}*/ /* end of group GPIO */ + + + + +/*---------------------- Inter-IC Bus Controller -------------------------*/ +/** + @addtogroup I2C Inter-IC Bus Controller (I2C) + Memory Mapped Structure for I2C Controller +@{ */ + + +typedef struct +{ + + +/** + * @var I2C_T::I2CON + * Offset: 0x00 I2C Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data received, an acknowledged (low level to I2Cn_SDA) will + * | | |be returned during the acknowledge clock pulse on the I2Cn_SCL line when 1.) A slave is + * | | |acknowledging the address sent from master, 2.) The receiver devices are acknowledging the + * | | |data sent by transmitter. + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to I2Cn_SDA) + * | | |will be returned during the acknowledge clock pulse on the I2Cn_SCL line. + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, + * | | |and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. + * | | |SI must be cleared by software. + * | | |Clear SI by writing 1 to this bit. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check + * | | |the bus condition if a STOP condition is detected this bit will be cleared by hardware + * | | |automatically. + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. + * | | |This means it is NO LONGER in the slave receiver mode to receive data from the master + * | | |transmit device. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START + * | | |condition to bus when the bus is free. + * |[6] |ENS1 |I2C Controller Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |Set to enable I2C serial function controller. + * | | |When ENS1=1 the I2C serial function enables. + * | | |The multi-function pin function of I2Cn_SDA and I2Cn_SCL must set to I2C function first. + * |[7] |EI |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::I2CADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[7:1] |I2CADDR |I2C Address Register + * | | |The content of this register is irrelevant when I2C is in Master mode. + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own + * | | |address. + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::I2CDAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |I2CDAT |I2C Data Register + * | | |Bit [7:0] is located with the 8-bit transferred data of I2C serial port. + * @var I2C_T::I2CSTATUS + * Offset: 0x0C I2C Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |I2CSTATUS |I2C Status Register + * | | |The status register of I2C: + * | | |The three least significant bits are always 0. + * | | |The five most significant bits contain the status code. + * | | |There are 26 possible status codes. + * | | |When I2CSTATUS contains F8H, no serial interrupt is requested. + * | | |All other I2CSTATUS values correspond to defined I2C states. + * | | |When each of these states is entered, a status interrupt is requested (SI = 1). + * | | |A valid status code is present in I2CSTATUS one cycle after SI is set by hardware and is + * | | |still present one cycle after SI has been reset by software. + * | | |In addition, states 00H stands for a Bus Error. + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the + * | | |formation frame. + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte + * | | |or an acknowledge bit. + * @var I2C_T::I2CLK + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |I2CLK |I2C clock divided Register + * | | |The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)). + * | | |Note: The minimum value of I2CLK is 4. + * @var I2C_T::I2CTOC + * Offset: 0x14 I2C Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Time-out Flag + * | | |This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt + * | | |enable bit (EI) is set to 1. + * | | |Note: Write 1 to clear this bit. + * |[1] |DIV4 |Time-out Counter Input Clock Divided by 4 + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |When Enabled, The time-out period is extend 4 times. + * |[2] |ENTI |Time-out Counter Enable/Disable + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear. + * | | |Setting flag SI to high will reset counter and re-start up counting after SI is cleared. + * @var I2C_T::I2CADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[7:1] |I2CADDR |I2C Address Register + * | | |The content of this register is irrelevant when I2C is in Master mode. + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own + * | | |address. + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::I2CADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[7:1] |I2CADDR |I2C Address Register + * | | |The content of this register is irrelevant when I2C is in Master mode. + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own + * | | |address. + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::I2CADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[7:1] |I2CADDR |I2C Address Register + * | | |The content of this register is irrelevant when I2C is in Master mode. + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own + * | | |address. + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::I2CADM0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:1] |I2CADM |I2C Address Mask Register + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as + * | | |address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register. + * | | |When the bit in the address mask register is set to one, it means the received corresponding + * | | |address bit is don't-care. + * | | |If the bit is set to zero, that means the received corresponding register bit should be + * | | |exact the same as address register. + * @var I2C_T::I2CADM1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:1] |I2CADM |I2C Address Mask Register + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as + * | | |address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register. + * | | |When the bit in the address mask register is set to one, it means the received corresponding + * | | |address bit is don't-care. + * | | |If the bit is set to zero, that means the received corresponding register bit should be + * | | |exact the same as address register. + * @var I2C_T::I2CADM2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:1] |I2CADM |I2C Address Mask Register + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as + * | | |address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register. + * | | |When the bit in the address mask register is set to one, it means the received corresponding + * | | |address bit is don't-care. + * | | |If the bit is set to zero, that means the received corresponding register bit should be + * | | |exact the same as address register. + * @var I2C_T::I2CADM3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:1] |I2CADM |I2C Address Mask Register + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as + * | | |address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register. + * | | |When the bit in the address mask register is set to one, it means the received corresponding + * | | |address bit is don't-care. + * | | |If the bit is set to zero, that means the received corresponding register bit should be + * | | |exact the same as address register. + * @var I2C_T::I2CWKUPCON + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKUPEN |I2C Wake-up Enable + * | | |0 = I2C wake-up function Disabled. + * | | |1= I2C wake-up function Enabled. + * @var I2C_T::I2CWKUPSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKUPIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1. + * | | |Software can write 1 to clear this bit. + */ + + __IO uint32_t I2CON; /* Offset: 0x00 I2C Control Register */ + __IO uint32_t I2CADDR0; /* Offset: 0x04 I2C Slave Address Register0 */ + __IO uint32_t I2CDAT; /* Offset: 0x08 I2C Data Register */ + __I uint32_t I2CSTATUS; /* Offset: 0x0C I2C Status Register */ + __IO uint32_t I2CLK; /* Offset: 0x10 I2C Clock Divided Register */ + __IO uint32_t I2CTOC; /* Offset: 0x14 I2C Time-out Counter Register */ + __IO uint32_t I2CADDR1; /* Offset: 0x18 I2C Slave Address Register1 */ + __IO uint32_t I2CADDR2; /* Offset: 0x1C I2C Slave Address Register2 */ + __IO uint32_t I2CADDR3; /* Offset: 0x20 I2C Slave Address Register3 */ + __IO uint32_t I2CADM0; /* Offset: 0x24 I2C Slave Address Mask Register0 */ + __IO uint32_t I2CADM1; /* Offset: 0x28 I2C Slave Address Mask Register1 */ + __IO uint32_t I2CADM2; /* Offset: 0x2C I2C Slave Address Mask Register2 */ + __IO uint32_t I2CADM3; /* Offset: 0x30 I2C Slave Address Mask Register3 */ + __I uint32_t RESERVED0[2]; + __IO uint32_t I2CWKUPCON; /* Offset: 0x3C I2C Wake-up Control Register */ + __IO uint32_t I2CWKUPSTS; /* Offset: 0x40 I2C Wake-up Status Register */ + +} I2C_T; + + + + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +/* I2C I2CON Bit Field Definitions */ +#define I2C_I2CON_EI_Pos 7 /*!< I2C_T::I2CON: EI Position */ +#define I2C_I2CON_EI_Msk (1ul << I2C_I2CON_EI_Pos) /*!< I2C_T::I2CON: EI Mask */ + +#define I2C_I2CON_ENS1_Pos 6 /*!< I2C_T::I2CON: ENS1 Position */ +#define I2C_I2CON_ENS1_Msk (1ul << I2C_I2CON_ENS1_Pos) /*!< I2C_T::I2CON: ENS1 Mask */ + +#define I2C_I2CON_STA_Pos 5 /*!< I2C_T::I2CON: STA Position */ +#define I2C_I2CON_STA_Msk (1ul << I2C_I2CON_STA_Pos) /*!< I2C_T::I2CON: STA Mask */ + +#define I2C_I2CON_STO_Pos 4 /*!< I2C_T::I2CON: STO Position */ +#define I2C_I2CON_STO_Msk (1ul << I2C_I2CON_STO_Pos) /*!< I2C_T::I2CON: STO Mask */ + +#define I2C_I2CON_SI_Pos 3 /*!< I2C_T::I2CON: SI Position */ +#define I2C_I2CON_SI_Msk (1ul << I2C_I2CON_SI_Pos) /*!< I2C_T::I2CON: SI Mask */ + +#define I2C_I2CON_AA_Pos 2 /*!< I2C_T::I2CON: AA Position */ +#define I2C_I2CON_AA_Msk (1ul << I2C_I2CON_AA_Pos) /*!< I2C_T::I2CON: AA Mask */ + +/* I2C I2CADDR Bit Field Definitions */ +#define I2C_I2CADDR_I2CADDR_Pos 1 /*!< I2C_T::I2CADDR1: I2CADDR Position */ +#define I2C_I2CADDR_I2CADDR_Msk (0x7Ful << I2C_I2CADDR_I2CADDR_Pos) /*!< I2C_T::I2CADDR1: I2CADDR Mask */ + +#define I2C_I2CADDR_GC_Pos 0 /*!< I2C_T::I2CADDR1: GC Position */ +#define I2C_I2CADDR_GC_Msk (1ul << I2C_I2CADDR_GC_Pos) /*!< I2C_T::I2CADDR1: GC Mask */ + +/* I2C I2CDAT Bit Field Definitions */ +#define I2C_I2CDAT_I2CDAT_Pos 0 /*!< I2C_T::I2CDAT: I2CDAT Position */ +#define I2C_I2CDAT_I2CDAT_Msk (0xFFul << I2C_I2CDAT_I2CDAT_Pos) /*!< I2C_T::I2CDAT: I2CDAT Mask */ + +/* I2C I2CSTATUS Bit Field Definitions */ +#define I2C_I2CSTATUS_I2CSTATUS_Pos 0 /*!< I2C_T::I2CSTATUS: I2CSTATUS Position */ +#define I2C_I2CSTATUS_I2CSTATUS_Msk (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos) /*!< I2C_T::I2CSTATUS: I2CSTATUS Mask */ + +/* I2C I2CLK Bit Field Definitions */ +#define I2C_I2CLK_I2CLK_Pos 0 /*!< I2C_T::I2CLK: I2CLK Position */ +#define I2C_I2CLK_I2CLK_Msk (0xFFul << I2C_I2CLK_I2CLK_Pos) /*!< I2C_T::I2CLK: I2CLK Mask */ + +/* I2C I2CTOC Bit Field Definitions */ +#define I2C_I2CTOC_ENTI_Pos 2 /*!< I2C_T::I2CTOC: ENTI Position */ +#define I2C_I2CTOC_ENTI_Msk (1ul << I2C_I2CTOC_ENTI_Pos) /*!< I2C_T::I2CTOC: ENTI Mask */ + +#define I2C_I2CTOC_DIV4_Pos 1 /*!< I2C_T::I2CTOC: DIV4 Position */ +#define I2C_I2CTOC_DIV4_Msk (1ul << I2C_I2CTOC_DIV4_Pos) /*!< I2C_T::I2CTOC: DIV4 Mask */ + +#define I2C_I2CTOC_TIF_Pos 0 /*!< I2C_T::I2CTOC: TIF Position */ +#define I2C_I2CTOC_TIF_Msk (1ul << I2C_I2CTOC_TIF_Pos) /*!< I2C_T::I2CTOC: TIF Mask */ + +/* I2C I2CADM Bit Field Definitions */ +#define I2C_I2CADM_I2CADM_Pos 1 /*!< I2C_T::I2CADM0: I2CADM Position */ +#define I2C_I2CADM_I2CADM_Msk (0x7Ful << I2C_I2CADM_I2CADM_Pos) /*!< I2C_T::I2CADM0: I2CADM Mask */ + +/* I2C I2CWKUPCON Bit Field Definitions */ +#define I2C_I2CWKUPCON_WKUPEN_Pos 0 /*!< I2C_T::I2CWKUPCON: WKUPEN Position */ +#define I2C_I2CWKUPCON_WKUPEN_Msk (1ul << I2C_I2CWKUPCON_WKUPEN_Pos) /*!< I2C_T::I2CWKUPCON: WKUPEN Mask */ + +/* I2C I2CWKUPSTS Bit Field Definitions */ +#define I2C_I2CWKUPSTS_WKUPIF_Pos 0 /*!< I2C_T::I2CWKUPSTS: WKUPIF Position */ +#define I2C_I2CWKUPSTS_WKUPIF_Msk (1ul << I2C_I2CWKUPSTS_WKUPIF_Pos) /*!< I2C_T::I2CWKUPSTS: WKUPIF Mask */ + +/*@}*/ /* end of group I2C_CONST */ +/*@}*/ /* end of group I2C */ + + + +/*----------------------------- I2S Controller -------------------------------*/ +/** @addtogroup I2S Integrated Interchip Sound(I2S) + Memory Mapped Structure for I2S Interface Controller + @{ + */ + + +typedef struct +{ + + +/** + * @var I2S_T::CON + * Offset: 0x00 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[1] |TXEN |Transmit Enable + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |WORDWIDTH |Word Width + * | | |00 = data is 8-bit word. + * | | |01 = data is 16-bit word. + * | | |10 = data is 24-bit word. + * | | |11 = data is 32-bit word. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |FORMAT |Data Format + * | | |0 = I2S data format. + * | | |1 = MSB justified data format. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave. + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from MCU to + * | | |Audio CODEC chip. + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals + * | | |are received from outer Audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[11:9] |TXTH |Transmit FIFO Threshold Level + * | | |If the count of remaining data word (32 bits) in transmit FIFO is equal to or less than + * | | |threshold level then TXTHF (I2SSTATUS[18]) is set. + * | | |000 = 0 word data in transmit FIFO. + * | | |001 = 1 word data in transmit FIFO. + * | | |010 = 2 words data in transmit FIFO. + * | | |011 = 3 words data in transmit FIFO. + * | | |100 = 4 words data in transmit FIFO. + * | | |101 = 5 words data in transmit FIFO. + * | | |110 = 6 words data in transmit FIFO. + * | | |111 = 7 words data in transmit FIFO. + * |[14:12] |RXTH |Receive FIFO Threshold Level + * | | |When the count of received data word(s) in buffer is equal to or higher than threshold + * | | |level, RXTHF (I2SSTATUS[10]) will be set. + * | | |000 = 1 word data in receive FIFO. + * | | |001 = 2 word data in receive FIFO. + * | | |010 = 3 word data in receive FIFO. + * | | |011 = 4 word data in receive FIFO. + * | | |100 = 5 word data in receive FIFO. + * | | |101 = 6 word data in receive FIFO. + * | | |110 = 7 word data in receive FIFO. + * | | |111 = 8 word data in receive FIFO. + * |[15] |MCLKEN |Master Clock Enable + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for + * | | |external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RCHZCEN |Right Channel Zero Cross Detection Enable + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are + * | | |all 0 then RZCF flag in I2SSTATUS register is set to 1. + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LCHZCEN |Left Channel Zero Cross Detection Enable + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are + * | | |all 0 then LZCF flag in I2SSTATUS register is set to 1. + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[18] |CLR_TXFIFO|Clear Transmit FIFO + * | | |Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and + * | | |TX_LEVEL[3:0] returns to 0 and + * | | |transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |This bit is cleared by hardware automatically. Returns 0 on read. + * |[19] |CLR_RXFIFO|Clear Receive FIFO + * | | |Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and + * | | |RX_LEVEL[3:0] returns 0 and receive FIFO becomes empty. + * | | |This bit is cleared by hardware automatically. Returns 0 on read. + * |[20] |TXDMA |Enable Transmit DMA + * | | |When TX DMA is enabled, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO + * | | |is not full. + * | | |0 = TX DMA Disabled. + * | | |1 = TX DMA Enabled. + * |[21] |RXDMA |Enable Receive DMA + * | | |When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO + * | | |is not empty. + * | | |0 = RX DMA Disabled. + * | | |1 = RX DMA Enabled. + * |[23] |RXLCH |Receive Left Channel Enable + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data + * | | |if RXLCH is set to 0, + * | | |and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |MCLK_DIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. + * | | |The master clock rate, F_MCLK, is determined by the following expressions. + * | | |If MCLK_DIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLK_DIV)). + * | | |If MCLK_DIV = 0, F_MCLK = F_I2SCLK. + * | | |F_I2SCLK is the frequency of I2S peripheral clock. + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[15:8] |BCLK_DIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode. + * | | |The bit clock rate, F_BCLK, is determined by the following expression. + * | | |F_BCLK = F_I2SCLK /(2x(BCLK_DIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral + * | | |clock. + * @var I2S_T::IE + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIE |Receive FIFO Underflow Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |RXOVFIE |Receive FIFO Overflow Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[2] |RXTHIE |Receive FIFO Threshold Level Interrupt Enable + * | | |When the count of data words in receive FIFO is equal to or higher than RXTH (I2SCON[14:12]) + * | | |and + * | | |this bit is set to 1, receive FIFO threshold level interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[8] |TXUDFIE |Transmit FIFO Underflow Interrupt Enable + * | | |Interrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |TXOVFIE |Transmit FIFO Overflow Interrupt Enable + * | | |Interrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1 + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |TXTHIE |Transmit FIFO Threshold Level Interrupt Enable + * | | |Interrupt occurs if this bit is set to 1 and the count of data words in transmit FIFO is + * | | |less than TXTH (I2SCON[11:9]). + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |RZCIE |Right Channel Zero-Cross Interrupt Enable + * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event is detected. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[12] |LZCIE |Left Channel Zero-Cross Interrupt Enable + * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event is detected. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var I2S_T::STATUS + * Offset: 0x0C I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag + * | | |This bit is wire-OR of I2STXINT and I2SRXINT bits. + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: This bit is read only. + * |[1] |I2SRXINT |I2S Receive Interrupt + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * | | |Note: This bit is read only. + * |[2] |I2STXINT |I2S Transmit Interrupt + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * | | |Note: This bit is read only. + * |[3] |RIGHT |Right Channel + * | | |This bit indicates current transmit data is belong to which channel + * | | |0 = Left channel. + * | | |1 = Right channel. + * | | |Note: This bit is read only. + * |[8] |RXUDF |Receive FIFO Underflow Flag + * | | |Underflow event will occur if read the empty receive FIFO. + * | | |0 = No underflow event occurred. + * | | |1 = Underflow. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |RXOVF |Receive FIFO Overflow Flag + * | | |When receive FIFO is full and hardware attempt to write data to receive FIFO, this bit will + * | | |be set to 1, data in 1st buffer will be overwrote. + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |RXTHF |Receive FIFO Threshold Flag + * | | |When data word(s) in receive FIFO is equal to or larger than threshold value set in RXTH + * | | |(I2SCON[14:12]). + * | | |The RXTHF bit becomes to 1. + * | | |It keeps at 1 till RX_LEVEL (I2SSTATUS[27:24]) is less than RXTH. + * | | |0 = Data word(s) in FIFO is less than threshold level. + * | | |1 = Data word(s) in FIFO is equal to or larger than threshold level. + * | | |Note: This bit is read only. + * |[11] |RXFULL |Receive FIFO Full + * | | |This bit reflects the count of data in receive FIFO is 8 + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit is read only. + * |[12] |RXEMPTY |Receive FIFO Empty + * | | |This bit reflects the count of data in receive FIFO is 0 + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit is read only. + * |[16] |TXUDF |Transmit FIFO Underflow Flag + * | | |If transmit FIFO is empty and hardware reads data from transmit FIFO. This bit will be set + * | | |to 1. + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note: Software can write 1 to clear this bit to 0. + * |[17] |TXOVF |Transmit FIFO Overflow Flag + * | | |This bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full. + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note: Write 1 to clear this bit to 0. + * |[18] |TXTHF |Transmit FIFO Threshold Flag + * | | |When the count of data stored in transmit-FIFO is equal to or less than threshold value set + * | | |in TXTH (I2SCON[11:9]). + * | | |The TXTHF bit becomes to 1. + * | | |It keeps at 1 till TX_LEVEL (I2SSTATUS[31:28]) is larger than TXTH. + * | | |0 = Data word(s) in FIFO is larger than threshold level. + * | | |1 = Data word(s) in FIFO is equal to or less than threshold level. + * | | |Note: This bit is read only. + * |[19] |TXFULL |Transmit FIFO Full + * | | |This bit reflects data word number in transmit FIFO is 8 + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit is read only. + * |[20] |TXEMPTY |Transmit FIFO Empty + * | | |This bit reflects data word number in transmit FIFO is 0 + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit is read only. + * |[21] |TXBUSY |Transmit Busy + * | | |This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. + * | | |And set to 1 when 1st data is load to shift buffer. + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is not empty. + * | | |Note: This bit is read only. + * |[22] |RZCF |Right Channel Zero-Cross Flag + * | | |It indicates the sign bit of right channel sample data is changed or all data bits are 0. + * | | |0 = No zero-cross. + * | | |1 = Right channel zero-cross event is detected. + * | | |Note: Write 1 to clear this bit to 0. + * |[23] |LZCF |Left Channel Zero-Cross Flag + * | | |It indicates the sign bit of left channel sample data is changed or all data bits are 0. + * | | |0 = No zero-cross. + * | | |1 = Left channel zero-cross event is detected. + * | | |Note: Write 1 to clear this bit to 0. + * |[27:24] |RX_LEVEL |Receive FIFO Level + * | | |These bits indicate word number in receive FIFO + * | | |0000 = No data. + * | | |0001 = 1 word in receive FIFO. + * | | |.... + * | | |1000 = 8 words in receive FIFO. + * |[31:28] |TX_LEVEL |Transmit FIFO Level + * | | |These bits indicate word number in transmit FIFO + * | | |0000 = No data. + * | | |0001 = 1 word in transmit FIFO. + * | | |.... + * | | |1000 = 8 words in transmit FIFO. + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Register + * | | |I2S contains 8 words (8x32 bits) data buffer for data transmit. + * | | |Write data to this register to prepare data for transmission. + * | | |The remaining word number is indicated by TX_LEVEL (I2SSTATUS[31:28]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Register + * | | |I2S contains 8 words (8x32 bits) data buffer for data receive. + * | | |Read this register to get data of receive FIFO. + * | | |The remaining data word number is indicated by RX_LEVEL (I2SSTATUS[27:24]). + */ + + __IO uint32_t CON; /* Offset: 0x00 I2S Control Register */ + __IO uint32_t CLKDIV; /* Offset: 0x04 I2S Clock Divider Control Register */ + __IO uint32_t IE; /* Offset: 0x08 I2S Interrupt Enable Register */ + __IO uint32_t STATUS; /* Offset: 0x0C I2S Status Register */ + __O uint32_t TXFIFO; /* Offset: 0x10 I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /* Offset: 0x14 I2S Receive FIFO Register */ + + +} I2S_T; + + + + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +/* I2S I2SCON Bit Field Definitions */ +#define I2S_CON_RXLCH_Pos 23 /*!< I2S_T::CON: RXLCH Position */ +#define I2S_CON_RXLCH_Msk (1ul << I2S_CON_RXLCH_Pos) /*!< I2S_T::CON: RXLCH Mask */ + +#define I2S_CON_RXDMA_Pos 21 /*!< I2S_T::CON: RXDMA Position */ +#define I2S_CON_RXDMA_Msk (1ul << I2S_CON_RXDMA_Pos) /*!< I2S_T::CON: RXDMA Mask */ + +#define I2S_CON_TXDMA_Pos 20 /*!< I2S_T::CON: TXDMA Position */ +#define I2S_CON_TXDMA_Msk (1ul << I2S_CON_TXDMA_Pos) /*!< I2S_T::CON: TXDMA Mask */ + +#define I2S_CON_CLR_RXFIFO_Pos 19 /*!< I2S_T::CON: CLR_RXFIFO Position */ +#define I2S_CON_CLR_RXFIFO_Msk (1ul << I2S_CON_CLR_RXFIFO_Pos) /*!< I2S_T::CON: CLR_RXFIFO Mask */ + +#define I2S_CON_CLR_TXFIFO_Pos 18 /*!< I2S_T::CON: CLR_TXFIFO Position */ +#define I2S_CON_CLR_TXFIFO_Msk (1ul << I2S_CON_CLR_TXFIFO_Pos) /*!< I2S_T::CON: CLR_TXFIFO Mask */ + +#define I2S_CON_LCHZCEN_Pos 17 /*!< I2S_T::CON: LCHZCEN Position */ +#define I2S_CON_LCHZCEN_Msk (1ul << I2S_CON_LCHZCEN_Pos) /*!< I2S_T::CON: LCHZCEN Mask */ + +#define I2S_CON_RCHZCEN_Pos 16 /*!< I2S_T::CON: RCHZCEN Position */ +#define I2S_CON_RCHZCEN_Msk (1ul << I2S_CON_RCHZCEN_Pos) /*!< I2S_T::CON: RCHZCEN Mask */ + +#define I2S_CON_MCLKEN_Pos 15 /*!< I2S_T::CON: MCLKEN Position */ +#define I2S_CON_MCLKEN_Msk (1ul << I2S_CON_MCLKEN_Pos) /*!< I2S_T::CON: MCLKEN Mask */ + +#define I2S_CON_RXTH_Pos 12 /*!< I2S_T::CON: RXTH Position */ +#define I2S_CON_RXTH_Msk (7ul << I2S_CON_RXTH_Pos) /*!< I2S_T::CON: RXTH Mask */ + +#define I2S_CON_TXTH_Pos 9 /*!< I2S_T::CON: TXTH Position */ +#define I2S_CON_TXTH_Msk (7ul << I2S_CON_TXTH_Pos) /*!< I2S_T::CON: TXTH Mask */ + +#define I2S_CON_SLAVE_Pos 8 /*!< I2S_T::CON: SLAVE Position */ +#define I2S_CON_SLAVE_Msk (1ul << I2S_CON_SLAVE_Pos) /*!< I2S_T::CON: SLAVE Mask */ + +#define I2S_CON_FORMAT_Pos 7 /*!< I2S_T::CON: FORMAT Position */ +#define I2S_CON_FORMAT_Msk (1ul << I2S_CON_FORMAT_Pos) /*!< I2S_T::CON: FORMAT Mask */ + +#define I2S_CON_MONO_Pos 6 /*!< I2S_T::CON: MONO Position */ +#define I2S_CON_MONO_Msk (1ul << I2S_CON_MONO_Pos) /*!< I2S_T::CON: MONO Mask */ + +#define I2S_CON_WORDWIDTH_Pos 4 /*!< I2S_T::CON: WORDWIDTH Position */ +#define I2S_CON_WORDWIDTH_Msk (3ul << I2S_CON_WORDWIDTH_Pos) /*!< I2S_T::CON: WORDWIDTH Mask */ + +#define I2S_CON_MUTE_Pos 3 /*!< I2S_T::CON: MUTE Position */ +#define I2S_CON_MUTE_Msk (1ul << I2S_CON_MUTE_Pos) /*!< I2S_T::CON: MUTE Mask */ + +#define I2S_CON_RXEN_Pos 2 /*!< I2S_T::CON: RXEN Position */ +#define I2S_CON_RXEN_Msk (1ul << I2S_CON_RXEN_Pos) /*!< I2S_T::CON: RXEN Mask */ + +#define I2S_CON_TXEN_Pos 1 /*!< I2S_T::CON: TXEN Position */ +#define I2S_CON_TXEN_Msk (1ul << I2S_CON_TXEN_Pos) /*!< I2S_T::CON: TXEN Mask */ + +#define I2S_CON_I2SEN_Pos 0 /*!< I2S_T::CON: I2SEN Position */ +#define I2S_CON_I2SEN_Msk (1ul << I2S_CON_I2SEN_Pos) /*!< I2S_T::CON: I2SEN Mask */ + +/* I2S I2SCLKDIV Bit Field Definitions */ +#define I2S_CLKDIV_BCLK_DIV_Pos 8 /*!< I2S_T::CLKDIV: BCLK_DIV Position */ +#define I2S_CLKDIV_BCLK_DIV_Msk (0xFFul << I2S_CLKDIV_BCLK_DIV_Pos) /*!< I2S_T::CLKDIV: BCLK_DIV Mask */ + +#define I2S_CLKDIV_MCLK_DIV_Pos 0 /*!< I2S_T::CLKDIV: MCLK_DIV Position */ +#define I2S_CLKDIV_MCLK_DIV_Msk (7ul << I2S_CLKDIV_MCLK_DIV_Pos) /*!< I2S_T::CLKDIV: MCLK_DIV Mask */ + +/* I2S I2SIE Bit Field Definitions */ +#define I2S_IE_LZCIE_Pos 12 /*!< I2S_T::IE: LZCIE Position */ +#define I2S_IE_LZCIE_Msk (1ul << I2S_IE_LZCIE_Pos) /*!< I2S_T::IE: LZCIE Mask */ + +#define I2S_IE_RZCIE_Pos 11 /*!< I2S_T::IE: RZCIE Position */ +#define I2S_IE_RZCIE_Msk (1ul << I2S_IE_RZCIE_Pos) /*!< I2S_T::IE: RZCIE Mask */ + +#define I2S_IE_TXTHIE_Pos 10 /*!< I2S_T::IE: TXTHIE Position */ +#define I2S_IE_TXTHIE_Msk (1ul << I2S_IE_TXTHIE_Pos) /*!< I2S_T::IE: TXTHIE Mask */ + +#define I2S_IE_TXOVFIE_Pos 9 /*!< I2S_T::IE: TXOVFIE Position */ +#define I2S_IE_TXOVFIE_Msk (1ul << I2S_IE_TXOVFIE_Pos) /*!< I2S_T::IE: TXOVFIE Mask */ + +#define I2S_IE_TXUDFIE_Pos 8 /*!< I2S_T::IE: TXUDFIE Position */ +#define I2S_IE_TXUDFIE_Msk (1ul << I2S_IE_TXUDFIE_Pos) /*!< I2S_T::IE: TXUDFIE Mask */ + +#define I2S_IE_RXTHIE_Pos 2 /*!< I2S_T::IE: RXTHIE Position */ +#define I2S_IE_RXTHIE_Msk (1ul << I2S_IE_RXTHIE_Pos) /*!< I2S_T::IE: RXTHIE Mask */ + +#define I2S_IE_RXOVFIE_Pos 1 /*!< I2S_T::IE: RXOVFIE Position */ +#define I2S_IE_RXOVFIE_Msk (1ul << I2S_IE_RXOVFIE_Pos) /*!< I2S_T::IE: RXOVFIE Mask */ + +#define I2S_IE_RXUDFIE_Pos 0 /*!< I2S_T::IE: RXUDFIE Position */ +#define I2S_IE_RXUDFIE_Msk (1ul << I2S_IE_RXUDFIE_Pos) /*!< I2S_T::IE: RXUDFIE Mask */ + + +/* I2S I2SSTATUS Bit Field Definitions */ +#define I2S_STATUS_TX_LEVEL_Pos 28 /*!< I2S_T::STATUS: TX_LEVEL Position */ +#define I2S_STATUS_TX_LEVEL_Msk (0xFul << I2S_STATUS_TX_LEVEL_Pos) /*!< I2S_T::STATUS: TX_LEVEL Mask */ + +#define I2S_STATUS_RX_LEVEL_Pos 24 /*!< I2S_T::STATUS: RX_LEVEL Position */ +#define I2S_STATUS_RX_LEVEL_Msk (0xFul << I2S_STATUS_RX_LEVEL_Pos) /*!< I2S_T::STATUS: RX_LEVEL Mask */ + +#define I2S_STATUS_LZCF_Pos 23 /*!< I2S_T::STATUS: LZCF Position */ +#define I2S_STATUS_LZCF_Msk (1ul << I2S_STATUS_LZCF_Pos) /*!< I2S_T::STATUS: LZCF Mask */ + +#define I2S_STATUS_RZCF_Pos 22 /*!< I2S_T::STATUS: RZCF Position */ +#define I2S_STATUS_RZCF_Msk (1ul << I2S_STATUS_RZCF_Pos) /*!< I2S_T::STATUS: RZCF Mask */ + +#define I2S_STATUS_TXBUSY_Pos 21 /*!< I2S_T::STATUS: TXBUSY Position */ +#define I2S_STATUS_TXBUSY_Msk (1ul << I2S_STATUS_TXBUSY_Pos) /*!< I2S_T::STATUS: TXBUSY Mask */ + +#define I2S_STATUS_TXEMPTY_Pos 20 /*!< I2S_T::STATUS: TXEMPTY Position */ +#define I2S_STATUS_TXEMPTY_Msk (1ul << I2S_STATUS_TXEMPTY_Pos) /*!< I2S_T::STATUS: TXEMPTY Mask */ + +#define I2S_STATUS_TXFULL_Pos 19 /*!< I2S_T::STATUS: TXFULL Position */ +#define I2S_STATUS_TXFULL_Msk (1ul << I2S_STATUS_TXFULL_Pos) /*!< I2S_T::STATUS: TXFULL Mask */ + +#define I2S_STATUS_TXTHF_Pos 18 /*!< I2S_T::STATUS: TXTHF Position */ +#define I2S_STATUS_TXTHF_Msk (1ul << I2S_STATUS_TXTHF_Pos) /*!< I2S_T::STATUS: TXTHF Mask */ + +#define I2S_STATUS_TXOVF_Pos 17 /*!< I2S_T::STATUS: TXOVF Position */ +#define I2S_STATUS_TXOVF_Msk (1ul << I2S_STATUS_TXOVF_Pos) /*!< I2S_T::STATUS: TXOVF Mask */ + +#define I2S_STATUS_TXUDF_Pos 16 /*!< I2S_T::STATUS: TXUDF Position */ +#define I2S_STATUS_TXUDF_Msk (1ul << I2S_STATUS_TXUDF_Pos) /*!< I2S_T::STATUS: TXUDF Mask */ + +#define I2S_STATUS_RXEMPTY_Pos 12 /*!< I2S_T::STATUS: RXEMPTY Position */ +#define I2S_STATUS_RXEMPTY_Msk (1ul << I2S_STATUS_RXEMPTY_Pos) /*!< I2S_T::STATUS: RXEMPTY Mask */ + +#define I2S_STATUS_RXFULL_Pos 11 /*!< I2S_T::STATUS: RXFULL Position */ +#define I2S_STATUS_RXFULL_Msk (1ul << I2S_STATUS_RXFULL_Pos) /*!< I2S_T::STATUS: RXFULL Mask */ + +#define I2S_STATUS_RXTHF_Pos 10 /*!< I2S_T::STATUS: RXTHF Position */ +#define I2S_STATUS_RXTHF_Msk (1ul << I2S_STATUS_RXTHF_Pos) /*!< I2S_T::STATUS: RXTHF Mask */ + +#define I2S_STATUS_RXOVF_Pos 9 /*!< I2S_T::STATUS: RXOVF Position */ +#define I2S_STATUS_RXOVF_Msk (1ul << I2S_STATUS_RXOVF_Pos) /*!< I2S_T::STATUS: RXOVF Mask */ + +#define I2S_STATUS_RXUDF_Pos 8 /*!< I2S_T::STATUS: RXUDF Position */ +#define I2S_STATUS_RXUDF_Msk (1ul << I2S_STATUS_RXUDF_Pos) /*!< I2S_T::STATUS: RXUDF Mask */ + +#define I2S_STATUS_RIGHT_Pos 3 /*!< I2S_T::STATUS: RIGHT Position */ +#define I2S_STATUS_RIGHT_Msk (1ul << I2S_STATUS_RIGHT_Pos) /*!< I2S_T::STATUS: RIGHT Mask */ + +#define I2S_STATUS_I2STXINT_Pos 2 /*!< I2S_T::STATUS: I2STXINT Position */ +#define I2S_STATUS_I2STXINT_Msk (1ul << I2S_STATUS_I2STXINT_Pos) /*!< I2S_T::STATUS: I2STXINT Mask */ + +#define I2S_STATUS_I2SRXINT_Pos 1 /*!< I2S_T::STATUS: I2SRXINT Position */ +#define I2S_STATUS_I2SRXINT_Msk (1ul << I2S_STATUS_I2SRXINT_Pos) /*!< I2S_T::STATUS: I2SRXINT Mask */ + +#define I2S_STATUS_I2SINT_Pos 0 /*!< I2S_T::STATUS: I2SINT Position */ +#define I2S_STATUS_I2SINT_Msk (1ul << I2S_STATUS_I2SINT_Pos) /*!< I2S_T::STATUS: I2SINT Mask */ + +/*@}*/ /* end of group I2S_CONST */ +/*@}*/ /* end of group I2S */ + + + +/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller (PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + + +/** + * @var PDMA_T::CSR + * Offset: 0x00 PDMA Channel x Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMACEN |PDMA Channel Enable + * | | |Setting this bit to 1 enables PDMA operation. + * | | |If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE + * | | |state. + * | | |Note: SW_RST(PDMA_CSRx[1], x= 0~8) will clear this bit. + * |[1] |SW_RST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine, pointers and internal buffer. + * | | |The contents of control register will not be cleared. + * | | |This bit will be automatically cleared after few clock cycles. + * |[3:2] |MODE_SEL |PDMA Mode Selection + * | | |00 = Memory to Memory mode (Memory-to-Memory). + * | | |01 = Peripheral to Memory mode (Peripheral-to-Memory). + * | | |10 = Memory to Peripheral mode (Memory-to-Peripheral). + * |[5:4] |SAD_SEL |Transfer Source Address Direction Selection + * | | |00 = Transfer source address is increasing successively. + * | | |01 = Reserved. + * | | |10 = Transfer source address is fixed (This feature can be used when data where transferred + * | | |from a single source to multiple destinations). + * | | |11 = Reserved. + * |[7:6] |DAD_SEL |Transfer Destination Address Direction Selection + * | | |00 = Transfer destination address is increasing successively. + * | | |01 = Reserved. + * | | |10 = Transfer destination address is fixed. + * | | |(This feature can be used when data where transferred from multiple sources to a single + * | | |destination). + * | | |11 = Reserved. + * |[20:19] |APB_TWS |Peripheral Transfer Width Selection + * | | |00 = One word (32-bit) is transferred for every PDMA operation. + * | | |01 = One byte (8-bit) is transferred for every PDMA operation. + * | | |10 = One half-word (16-bit) is transferred for every PDMA operation. + * | | |11 = Reserved. + * | | |Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory + * | | |mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). + * |[23] |TRIG_EN |Trigger Enable + * | | |0 = No effect. + * | | |1 = PDMA data read or write transfer Enabled. + * | | |Note: When PDMA transfer completed, this bit will be cleared automatically. + * | | |If the bus error occurs, all PDMA transfer will be stopped. + * | | |Software must reset all PDMA channel, and then trigger again. + * @var PDMA_T::SAR + * Offset: 0x04 PDMA Channel x Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMA_SAR |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA. + * | | |Note: The source address must be word alignment. + * @var PDMA_T::DAR + * Offset: 0x08 PDMA Channel x Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMA_DAR |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA. + * | | |Note: The destination address must be word alignment + * @var PDMA_T::BCR + * Offset: 0x0C PDMA Channel x Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDMA_BCR |PDMA Transfer Byte Count Register + * | | |This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. + * @var PDMA_T::POINT + * Offset: 0x10 PDMA Channel x Internal buffer pointer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PDMA_POINT|PDMA Internal Buffer Pointer Register (Read Only) + * | | |This field indicates the internal buffer pointer. + * @var PDMA_T::CSAR + * Offset: 0x14 PDMA Channel x Current Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMA_CSAR |PDMA Current Source Address Register (Read Only) + * | | |This field indicates the source address where the PDMA transfer just occurred. + * @var PDMA_T::CDAR + * Offset: 0x18 PDMA Channel x Current Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMA_CDAR |PDMA Current Destination Address Register (Read Only) + * | | |This field indicates the destination address where the PDMA transfer just occurred. + * @var PDMA_T::CBCR + * Offset: 0x1C PDMA Channel x Current Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDMA_CBCR |PDMA Current Byte Count Register (Read Only) + * | | |This field indicates the current remained byte count of PDMA. + * | | |Note: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1". + * @var PDMA_T::IER + * Offset: 0x20 PDMA Channel x Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TABORT_IE |PDMA Read/Write Target Abort Interrupt Enable + * | | |0 = Target abort interrupt generation Disabled during PDMA transfer. + * | | |1 = Target abort interrupt generation Enabled during PDMA transfer. + * |[1] |BLKD_IE |PDMA Block Transfer Done Interrupt Enable + * | | |0 = Interrupt generator Disabled when PDMA transfer is done. + * | | |1 = Interrupt generator Enabled when PDMA transfer is done. + * @var PDMA_T::ISR + * Offset: 0x24 PDMA Channel x Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TABORT_IF |PDMA Read/Write Target Abort Interrupt Flag + * | | |Write 1 to clear this bit to 0. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit filed indicates bus master received ERROR response or not. + * | | |If bus master received ERROR response, it means that target abort is happened. + * | | |PDMA controller will stop transfer and respond this event to software then goes to IDLE + * | | |state. + * | | |When target abort occurred, software must reset PDMA, and then transfer those data again. + * |[1] |BLKD_IF |PDMA Block Transfer Done Interrupt Flag + * | | |This bit indicates that PDMA has finished all transfers. + * | | |0 = Not finished. + * | | |1 = Done. + * | | |Write 1 to clear this bit to 0. + * @var PDMA_T::SBUF + * Offset: 0x80 PDMA Channel x Shared Buffer FIFO x Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMA_SBUF0|PDMA Shared Buffer FIFO 0 (Read Only) + * | | |Each channel has its own 1 word internal buffer. + */ + + __IO uint32_t CSR; /* Offset: 0x00 PDMA Channel x Control Register */ + __IO uint32_t SAR; /* Offset: 0x04 PDMA Channel x Source Address Register */ + __IO uint32_t DAR; /* Offset: 0x08 PDMA Channel x Destination Address Register */ + __IO uint32_t BCR; /* Offset: 0x0C PDMA Channel x Transfer Byte Count Register */ + __I uint32_t POINT; /* Offset: 0x10 PDMA Channel x Internal buffer pointer Register */ + __I uint32_t CSAR; /* Offset: 0x14 PDMA Channel x Current Source Address Register */ + __I uint32_t CDAR; /* Offset: 0x18 PDMA Channel x Current Destination Address Register */ + __I uint32_t CBCR; /* Offset: 0x1C PDMA Channel x Current Transfer Byte Count Register */ + __IO uint32_t IER; /* Offset: 0x20 PDMA Channel x Interrupt Enable Register */ + __IO uint32_t ISR; /* Offset: 0x24 PDMA Channel x Interrupt Status Register */ + __I uint32_t RESERVE[22]; + __I uint32_t SBUF; /* Offset: 0x80 PDMA Channel x Shared Buffer FIFO x Register */ + +} PDMA_T; + + + + + +typedef struct +{ + + +/** + * @var PDMA_GCR_T::GCRCSR + * Offset: 0x00 PDMA Global Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |CLK0_EN |PDMA Controller Channel 0 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[9] |CLK1_EN |PDMA Controller Channel 1 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[10] |CLK2_EN |PDMA Controller Channel 2 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[11] |CLK3_EN |PDMA Controller Channel 3 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[12] |CLK4_EN |PDMA Controller Channel 4 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[13] |CLK5_EN |PDMA Controller Channel 5 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[14] |CLK6_EN |PDMA Controller Channel 6 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[15] |CLK7_EN |PDMA Controller Channel 7 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[16] |CLK8_EN |PDMA Controller Channel 8 Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[24] |CRC_CLK_EN|CRC Controller Clock Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * @var PDMA_GCR_T::PDSSR0 + * Offset: 0x04 PDMA Service Selection Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SPI0_RXSEL|PDMA SPI0 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. + * | | |Software can change the channel RX setting by this field. + * | | |For example, SPI0_RXSEL (PDMA_PDSSR0[3:0]) = 0110, that means SPI0_RX is connected to + * | | |PDMA_CH6. + * | | |0000: CH0 + * | | |0001: CH1 + * | | |0010: CH2 + * | | |0011: CH3 + * | | |0100: CH4 + * | | |0101: CH5 + * | | |0110: CH6 + * | | |0111: CH7 + * | | |1000: CH8 + * | | |Others : Reserved + * |[7:4] |SPI0_TXSEL|PDMA SPI0 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[11:8] |SPI1_RXSEL|PDMA SPI1 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. + * | | |Software can configure the RX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[15:12] |SPI1_TXSEL|PDMA SPI1 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[19:16] |SPI2_RXSEL|PDMA SPI2 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. + * | | |Software can configure the RX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[23:20] |SPI2_TXSEL|PDMA SPI2 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[27:24] |SPI3_RXSEL|PDMA SPI3 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. + * | | |Software can configure the RX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * |[31:28] |SPI3_TXSEL|PDMA SPI3 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. + * | | |Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]). + * @var PDMA_GCR_T::PDSSR1 + * Offset: 0x08 PDMA Service Selection Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART0_RXSEL|PDMA UART0 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART0 RX. + * | | |Software can change the channel RX setting by this field. + * | | |For example, UART0_RXSEL (PDMA_PDSSR1[3:0]) = 0110, which means UART0_RX is connected to + * | | |PDMA_CH6. + * | | |0000: CH0 + * | | |0001: CH1 + * | | |0010: CH2 + * | | |0011: CH3 + * | | |0100: CH4 + * | | |0101: CH5 + * | | |0110: CH6 + * | | |0111: CH7 + * | | |1000: CH8 + * | | |Others : Reserved + * |[7:4] |UART0_TXSEL|PDMA UART0 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. + * | | |Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]). + * |[11:8] |UART1_RXSEL|PDMA UART1 RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. + * | | |Software can configure the RX channel setting by this field. + * | | |The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. + * | | |Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]). + * |[15:12] |UART1_TXSEL|PDMA UART1 TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. + * | | |Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]). + * |[27:24] |ADC_RXSEL |PDMA ADC RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral ADC RX. + * | | |Software can configure the RX channel setting by this field. + * | | |The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. + * | | |Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]). + * @var PDMA_GCR_T::GCRISR + * Offset: 0x0C PDMA Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTR0 |Interrupt Status Of Channel 0 + * | | |This bit is the interrupt status of PDMA channel0. + * | | |Note: This bit is read only + * |[1] |INTR1 |Interrupt Status Of Channel 1 + * | | |This bit is the interrupt status of PDMA channel1. + * | | |Note: This bit is read only + * |[2] |INTR2 |Interrupt Status Of Channel 2 + * | | |This bit is the interrupt status of PDMA channel2. + * | | |Note: This bit is read only + * |[3] |INTR3 |Interrupt Status Of Channel 3 + * | | |This bit is the interrupt status of PDMA channel3. + * | | |Note: This bit is read only + * |[4] |INTR4 |Interrupt Status Of Channel 4 + * | | |This bit is the interrupt status of PDMA channel4. + * | | |Note: This bit is read only + * |[5] |INTR5 |Interrupt Status Of Channel 5 + * | | |This bit is the interrupt status of PDMA channel5. + * | | |Note: This bit is read only + * |[6] |INTR6 |Interrupt Status Of Channel 6 + * | | |This bit is the interrupt status of PDMA channel6. + * | | |Note: This bit is read only + * |[7] |INTR7 |Interrupt Status Of Channel 7 + * | | |This bit is the interrupt status of PDMA channel7. + * | | |Note: This bit is read only + * |[8] |INTR8 |Interrupt Status Of Channel 8 + * | | |This bit is the interrupt status of PDMA channel8. + * | | |Note: This bit is read only + * |[16] |INTRCRC |Interrupt Status Of CRC Controller + * | | |This bit is the interrupt status of CRC controller + * | | |Note: This bit is read only + * |[31] |INTR |Interrupt Status + * | | |This bit is the interrupt status of PDMA controller. + * | | |Note: This bit is read only + * @var PDMA_GCR_T::PDSSR2 + * Offset: 0x10 PDMA Service Selection Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |I2S_RXSEL |PDMA I2S RX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral I2S RX. + * | | |Software can change the channel RX setting by this field. + * | | |For example: I2S_RXSEL (PDMA_PDSSR2[3:0]) = 0110, that means I2S_RX is connected to + * | | |PDMA_CH6. + * | | |0000: CH0 + * | | |0001: CH1 + * | | |0010: CH2 + * | | |0011: CH3 + * | | |0100: CH4 + * | | |0101: CH5 + * | | |0110: CH6 + * | | |0111: CH7 + * | | |1000: CH8 + * | | |Others : Reserved + * |[7:4] |I2S_TXSEL |PDMA I2S TX Selection + * | | |This field defines which PDMA channel is connected to the on-chip peripheral I2S TX. + * | | |Software can configure the TX channel setting by this field. + * | | |The channel configuration is the same as I2S_RXSEL (PDMA_PDSSR2[3:0]) field. + * | | |Please refer to the explanation of I2S_RXSEL (PDMA_PDSSR2[3:0]). + */ + + __IO uint32_t GCRCSR; /* Offset: 0x00 PDMA Global Control Register */ + __IO uint32_t PDSSR0; /* Offset: 0x04 PDMA Service Selection Control Register 0 */ + __IO uint32_t PDSSR1; /* Offset: 0x08 PDMA Service Selection Control Register 1 */ + __IO uint32_t GCRISR; /* Offset: 0x0C PDMA Global Interrupt Status Register */ + __IO uint32_t PDSSR2; /* Offset: 0x10 PDMA Service Selection Control Register 2 */ + +} PDMA_GCR_T; + + + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + + +/* PDMA CSR Bit Field Definitions */ +#define PDMA_CSR_TRIG_EN_Pos 23 /*!< PDMA_T::CSR: TRIG_EN Position */ +#define PDMA_CSR_TRIG_EN_Msk (1ul << PDMA_CSR_TRIG_EN_Pos) /*!< PDMA_T::CSR: TRIG_EN Mask */ + +#define PDMA_CSR_APB_TWS_Pos 19 /*!< PDMA_T::CSR: APB_TWS Position */ +#define PDMA_CSR_APB_TWS_Msk (3ul << PDMA_CSR_APB_TWS_Pos) /*!< PDMA_T::CSR: APB_TWS Mask */ + +#define PDMA_CSR_DAD_SEL_Pos 6 /*!< PDMA_T::CSR: DAD_SEL Position */ +#define PDMA_CSR_DAD_SEL_Msk (3ul << PDMA_CSR_DAD_SEL_Pos) /*!< PDMA_T::CSR: DAD_SEL Mask */ + +#define PDMA_CSR_SAD_SEL_Pos 4 /*!< PDMA_T::CSR: SAD_SEL Position */ +#define PDMA_CSR_SAD_SEL_Msk (3ul << PDMA_CSR_SAD_SEL_Pos) /*!< PDMA_T::CSR: SAD_SEL Mask */ + +#define PDMA_CSR_MODE_SEL_Pos 2 /*!< PDMA_T::CSR: MODE_SEL Position */ +#define PDMA_CSR_MODE_SEL_Msk (3ul << PDMA_CSR_MODE_SEL_Pos) /*!< PDMA_T::CSR: MODE_SEL Mask */ + +#define PDMA_CSR_SW_RST_Pos 1 /*!< PDMA_T::CSR: SW_RST Position */ +#define PDMA_CSR_SW_RST_Msk (1ul << PDMA_CSR_SW_RST_Pos) /*!< PDMA_T::CSR: SW_RST Mask */ + +#define PDMA_CSR_PDMACEN_Pos 0 /*!< PDMA_T::CSR: PDMACEN Position */ +#define PDMA_CSR_PDMACEN_Msk (1ul << PDMA_CSR_PDMACEN_Pos) /*!< PDMA_T::CSR: PDMACEN Mask */ + +/* PDMA BCR Bit Field Definitions */ +#define PDMA_BCR_BCR_Pos 0 /*!< PDMA_T::BCR: BCR Position */ +#define PDMA_BCR_BCR_Msk (0xFFFFul << PDMA_BCR_BCR_Pos) /*!< PDMA_T::BCR: BCR Mask */ + +/* PDMA POINT Bit Field Definitions */ +#define PDMA_POINT_POINT_Pos 0 /*!< PDMA_T::POINT: POINT Position */ +#define PDMA_POINT_POINT_Msk (0xFul << PDMA_POINT_POINT_Pos) /*!< PDMA_T::POINT: POINT Mask */ + +/* PDMA CBCR Bit Field Definitions */ +#define PDMA_CBCR_CBCR_Pos 0 /*!< PDMA_T::CBCR: CBCR Position */ +#define PDMA_CBCR_CBCR_Msk (0xFFFFul << PDMA_CBCR_CBCR_Pos) /*!< PDMA_T::CBCR: CBCR Mask */ + + +/* PDMA IER Bit Field Definitions */ +#define PDMA_IER_BLKD_IE_Pos 1 /*!< PDMA_T::IER: BLKD_IE Position */ +#define PDMA_IER_BLKD_IE_Msk (1ul << PDMA_IER_BLKD_IE_Pos) /*!< PDMA_T::IER: BLKD_IE Mask */ + +#define PDMA_IER_TABORT_IE_Pos 0 /*!< PDMA_T::IER: TABORT_IE Position */ +#define PDMA_IER_TABORT_IE_Msk (1ul << PDMA_IER_TABORT_IE_Pos) /*!< PDMA_T::IER: TABORT_IE Mask */ + +/* PDMA ISR Bit Field Definitions */ +#define PDMA_ISR_BLKD_IF_Pos 1 /*!< PDMA_T::ISR: BLKD_IF Position */ +#define PDMA_ISR_BLKD_IF_Msk (1ul << PDMA_ISR_BLKD_IF_Pos) /*!< PDMA_T::ISR: BLKD_IF Mask */ + +#define PDMA_ISR_TABORT_IF_Pos 0 /*!< PDMA_T::ISR: TABORT_IF Position */ +#define PDMA_ISR_TABORT_IF_Msk (1ul << PDMA_ISR_TABORT_IF_Pos) /*!< PDMA_T::ISR: TABORT_IF Mask */ + +/* PDMA GCRCSR Bit Field Definitions */ +#define PDMA_GCRCSR_CRC_CLK_EN_Pos 24 /*!< PDMA_GCR_T::GCRCSR: CRC_CLK_EN Position */ +#define PDMA_GCRCSR_CRC_CLK_EN_Msk (1ul << PDMA_GCRCSR_CRC_CLK_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CRC_CLK_EN Mask */ + +#define PDMA_GCRCSR_CLK8_EN_Pos 16 /*!< PDMA_GCR_T::GCRCSR: CLK8_EN Position */ +#define PDMA_GCRCSR_CLK8_EN_Msk (1ul << PDMA_GCRCSR_CLK8_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK8_EN Mask */ + +#define PDMA_GCRCSR_CLK7_EN_Pos 15 /*!< PDMA_GCR_T::GCRCSR: CLK7_EN Position */ +#define PDMA_GCRCSR_CLK7_EN_Msk (1ul << PDMA_GCRCSR_CLK7_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK7_EN Mask */ + +#define PDMA_GCRCSR_CLK6_EN_Pos 14 /*!< PDMA_GCR_T::GCRCSR: CLK6_EN Position */ +#define PDMA_GCRCSR_CLK6_EN_Msk (1ul << PDMA_GCRCSR_CLK6_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK6_EN Mask */ + +#define PDMA_GCRCSR_CLK5_EN_Pos 13 /*!< PDMA_GCR_T::GCRCSR: CLK5_EN Position */ +#define PDMA_GCRCSR_CLK5_EN_Msk (1ul << PDMA_GCRCSR_CLK5_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK5_EN Mask */ + +#define PDMA_GCRCSR_CLK4_EN_Pos 12 /*!< PDMA_GCR_T::GCRCSR: CLK4_EN Position */ +#define PDMA_GCRCSR_CLK4_EN_Msk (1ul << PDMA_GCRCSR_CLK4_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK4_EN Mask */ + +#define PDMA_GCRCSR_CLK3_EN_Pos 11 /*!< PDMA_GCR_T::GCRCSR: CLK3_EN Position */ +#define PDMA_GCRCSR_CLK3_EN_Msk (1ul << PDMA_GCRCSR_CLK3_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK3_EN Mask */ + +#define PDMA_GCRCSR_CLK2_EN_Pos 10 /*!< PDMA_GCR_T::GCRCSR: CLK2_EN Position */ +#define PDMA_GCRCSR_CLK2_EN_Msk (1ul << PDMA_GCRCSR_CLK2_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK2_EN Mask */ + +#define PDMA_GCRCSR_CLK1_EN_Pos 9 /*!< PDMA_GCR_T::GCRCSR: CLK1_EN Position */ +#define PDMA_GCRCSR_CLK1_EN_Msk (1ul << PDMA_GCRCSR_CLK1_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK1_EN Mask */ + +#define PDMA_GCRCSR_CLK0_EN_Pos 8 /*!< PDMA_GCR_T::GCRCSR: CLK0_EN Position */ +#define PDMA_GCRCSR_CLK0_EN_Msk (1ul << PDMA_GCRCSR_CLK0_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK0_EN Mask */ + +/* PDMA PDSSR0 Bit Field Definitions */ +#define PDMA_PDSSR0_SPI3_TXSEL_Pos 28 /*!< PDMA_GCR_T::PDSSR0: SPI3_TXSEL Position */ +#define PDMA_PDSSR0_SPI3_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI3_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI3_TXSEL Mask */ + +#define PDMA_PDSSR0_SPI3_RXSEL_Pos 24 /*!< PDMA_GCR_T::PDSSR0: SPI3_RXSEL Position */ +#define PDMA_PDSSR0_SPI3_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI3_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI3_RXSEL Mask */ + +#define PDMA_PDSSR0_SPI2_TXSEL_Pos 20 /*!< PDMA_GCR_T::PDSSR0: SPI2_TXSEL Position */ +#define PDMA_PDSSR0_SPI2_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI2_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI2_TXSEL Mask */ + +#define PDMA_PDSSR0_SPI2_RXSEL_Pos 16 /*!< PDMA_GCR_T::PDSSR0: SPI2_RXSEL Position */ +#define PDMA_PDSSR0_SPI2_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI2_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI2_RXSEL Mask */ + +#define PDMA_PDSSR0_SPI1_TXSEL_Pos 12 /*!< PDMA_GCR_T::PDSSR0: SPI1_TXSEL Position */ +#define PDMA_PDSSR0_SPI1_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI1_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI1_TXSEL Mask */ + +#define PDMA_PDSSR0_SPI1_RXSEL_Pos 8 /*!< PDMA_GCR_T::PDSSR0: SPI1_RXSEL Position */ +#define PDMA_PDSSR0_SPI1_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI1_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI1_RXSEL Mask */ + +#define PDMA_PDSSR0_SPI0_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR0: SPI0_TXSEL Position */ +#define PDMA_PDSSR0_SPI0_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI0_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI0_TXSEL Mask */ + +#define PDMA_PDSSR0_SPI0_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR0: SPI0_RXSEL Position */ +#define PDMA_PDSSR0_SPI0_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI0_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI0_RXSEL Mask */ + +/* PDMA PDSSR1 Bit Field Definitions */ +#define PDMA_PDSSR1_ADC_RXSEL_Pos 24 /*!< PDMA_GCR_T::PDSSR1: ADC_RXSEL Position */ +#define PDMA_PDSSR1_ADC_RXSEL_Msk (0xFul << PDMA_PDSSR1_ADC_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: ADC_RXSEL Mask */ + +#define PDMA_PDSSR1_UART1_TXSEL_Pos 12 /*!< PDMA_GCR_T::PDSSR1: UART1_TXSEL Position */ +#define PDMA_PDSSR1_UART1_TXSEL_Msk (0xFul << PDMA_PDSSR1_UART1_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART1_TXSEL Mask */ + +#define PDMA_PDSSR1_UART1_RXSEL_Pos 8 /*!< PDMA_GCR_T::PDSSR1: UART1_RXSEL Position */ +#define PDMA_PDSSR1_UART1_RXSEL_Msk (0xFul << PDMA_PDSSR1_UART1_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART1_RXSEL Mask */ + +#define PDMA_PDSSR1_UART0_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR1: UART0_TXSEL Position */ +#define PDMA_PDSSR1_UART0_TXSEL_Msk (0xFul << PDMA_PDSSR1_UART0_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART0_TXSEL Mask */ + +#define PDMA_PDSSR1_UART0_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR1: UART0_RXSEL Position */ +#define PDMA_PDSSR1_UART0_RXSEL_Msk (0xFul << PDMA_PDSSR1_UART0_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART0_RXSEL Mask */ + +/* PDMA GCRISR Bit Field Definitions */ +#define PDMA_GCRISR_INTR_Pos 31 /*!< PDMA_GCR_T::GCRISR: INTR Position */ +#define PDMA_GCRISR_INTR_Msk (1ul << PDMA_GCRISR_INTR_Pos) /*!< PDMA_GCR_T::GCRISR: INTR Mask */ + +#define PDMA_GCRISR_INTRCRC_Pos 16 /*!< PDMA_GCR_T::GCRISR: INTRCRC Position */ +#define PDMA_GCRISR_INTRCRC_Msk (1ul << PDMA_GCRISR_INTRCRC_Pos) /*!< PDMA_GCR_T::GCRISR: INTRCRC Mask */ + +#define PDMA_GCRISR_INTR8_Pos 8 /*!< PDMA_GCR_T::GCRISR: INTR8 Position */ +#define PDMA_GCRISR_INTR8_Msk (1ul << PDMA_GCRISR_INTR8_Pos) /*!< PDMA_GCR_T::GCRISR: INTR8 Mask */ + +#define PDMA_GCRISR_INTR7_Pos 7 /*!< PDMA_GCR_T::GCRISR: INTR7 Position */ +#define PDMA_GCRISR_INTR7_Msk (1ul << PDMA_GCRISR_INTR7_Pos) /*!< PDMA_GCR_T::GCRISR: INTR7 Mask */ + +#define PDMA_GCRISR_INTR6_Pos 6 /*!< PDMA_GCR_T::GCRISR: INTR6 Position */ +#define PDMA_GCRISR_INTR6_Msk (1ul << PDMA_GCRISR_INTR6_Pos) /*!< PDMA_GCR_T::GCRISR: INTR6 Mask */ + +#define PDMA_GCRISR_INTR5_Pos 5 /*!< PDMA_GCR_T::GCRISR: INTR5 Position */ +#define PDMA_GCRISR_INTR5_Msk (1ul << PDMA_GCRISR_INTR5_Pos) /*!< PDMA_GCR_T::GCRISR: INTR5 Mask */ + +#define PDMA_GCRISR_INTR4_Pos 4 /*!< PDMA_GCR_T::GCRISR: INTR4 Position */ +#define PDMA_GCRISR_INTR4_Msk (1ul << PDMA_GCRISR_INTR4_Pos) /*!< PDMA_GCR_T::GCRISR: INTR4 Mask */ + +#define PDMA_GCRISR_INTR3_Pos 3 /*!< PDMA_GCR_T::GCRISR: INTR3 Position */ +#define PDMA_GCRISR_INTR3_Msk (1ul << PDMA_GCRISR_INTR3_Pos) /*!< PDMA_GCR_T::GCRISR: INTR3 Mask */ + +#define PDMA_GCRISR_INTR2_Pos 2 /*!< PDMA_GCR_T::GCRISR: INTR2 Position */ +#define PDMA_GCRISR_INTR2_Msk (1ul << PDMA_GCRISR_INTR2_Pos) /*!< PDMA_GCR_T::GCRISR: INTR2 Mask */ + +#define PDMA_GCRISR_INTR1_Pos 1 /*!< PDMA_GCR_T::GCRISR: INTR1 Position */ +#define PDMA_GCRISR_INTR1_Msk (1ul << PDMA_GCRISR_INTR1_Pos) /*!< PDMA_GCR_T::GCRISR: INTR1 Mask */ + +#define PDMA_GCRISR_INTR0_Pos 0 /*!< PDMA_GCR_T::GCRISR: INTR0 Position */ +#define PDMA_GCRISR_INTR0_Msk (1ul << PDMA_GCRISR_INTR0_Pos) /*!< PDMA_GCR_T::GCRISR: INTR0 Mask */ + +/* PDMA PDSSR2 Bit Field Definitions */ +#define PDMA_PDSSR2_I2S_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR2: I2S_TXSEL Position */ +#define PDMA_PDSSR2_I2S_TXSEL_Msk (0xFul << PDMA_PDSSR2_I2S_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: I2S_TXSEL Mask */ + +#define PDMA_PDSSR2_I2S_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR2: I2S_RXSEL Position */ +#define PDMA_PDSSR2_I2S_RXSEL_Msk (0xFul << PDMA_PDSSR2_I2S_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: I2S_RXSEL Mask */ +/*@}*/ /* end of group PDMA_CONST */ +/*@}*/ /* end of group PDMA */ + + + +/*------------------------------ PS2 Controller ------------------------------*/ +/** @addtogroup PS2 PS2 Serial Interface(PS2) + Memory Mapped Structure for PS2 Serial Interface Controller + @{ + */ + + +typedef struct +{ + + +/** + * @var PS2_T::PS2CON + * Offset: 0x00 PS/2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PS2EN |Enable PS/2 Device + * | | |Enable PS/2 device controller + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[1] |TXINTEN |Enable Transmit Interrupt + * | | |0 = Data transmit complete interrupt Disabled. + * | | |1 = Data transmit complete interrupt Enabled. + * |[2] |RXINTEN |Enable Receive Interrupt + * | | |0 = Data receive complete interrupt Disabled. + * | | |1 = Data receive complete interrupt Enabled. + * |[6:3] |TXFIFO_DEPTH|Transmit Data FIFO Depth + * | | |There are 16 bytes buffer for data transmit. + * | | |Software can define the FIFO depth from 1 to 16 bytes depends on application needs. + * | | |0 = 1 byte. + * | | |1 = 2 bytes. + * | | |... + * | | |14 = 15 bytes. + * | | |15 = 16 bytes. + * |[7] |ACK |Acknowledge Enable + * | | |0 = Always send acknowledge to host at 12th clock for host to device communication. + * | | |1 = If parity bit error or stop bit is not received correctly, acknowledge bit will not be + * | | |sent to host at 12th clock. + * |[8] |CLRFIFO |Clear TX FIFO + * | | |Write 1 to this bit to terminate device to host transmission. + * | | |The TXEMPTY(PS2STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2STATUS[11:8]) is + * | | |reset to 0 regardless there is residue data in buffer or not. + * | | |The buffer content is not been cleared. + * | | |0 = Not active. + * | | |1 = Clear FIFO. + * |[9] |OVERRIDE |Software Override PS/2 CLK/DATA Pin State + * | | |0 = PS2_CLK and PS2_DATA pins are controlled by internal state machine. + * | | |1 = PS2_CLK and PS2_DATA pins are controlled by software. + * |[10] |FPS2CLK |Force PS2CLK Line + * | | |It forces PS2_CLK line high or low regardless of the internal state of the device controller + * | | |if OVERRIDE(PS2CON[9]) is set to 1. + * | | |0 = Force PS2_CLK line low. + * | | |1 = Force PS2_CLK line high. + * |[11] |FPS2DAT |Force PS2DATA Line + * | | |It forces PS2_DATA high or low regardless of the internal state of the device controller if + * | | |OVERRIDE (PS2CON[9]) is set to 1. + * | | |0 = Force PS2_DATA low. + * | | |1 = Force PS2_DATA high. + * @var PS2_T::PS2TXDATA0 + * Offset: 0x04 PS/2 Transmit Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PS2TXDATAx|Transmit Data + * | | |Writing data to this register starts in device to host communication if bus is in IDLE + * | | |state. + * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer. + * @var PS2_T::PS2TXDATA1 + * Offset: 0x08 PS/2 Transmit Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PS2TXDATAx|Transmit Data + * | | |Writing data to this register starts in device to host communication if bus is in IDLE + * | | |state. + * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer. + * @var PS2_T::PS2TXDATA2 + * Offset: 0x0C PS/2 Transmit Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PS2TXDATAx|Transmit Data + * | | |Writing data to this register starts in device to host communication if bus is in IDLE + * | | |state. + * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer. + * @var PS2_T::PS2TXDATA3 + * Offset: 0x10 PS/2 Transmit Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PS2TXDATAx|Transmit Data + * | | |Writing data to this register starts in device to host communication if bus is in IDLE + * | | |state. + * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer. + * @var PS2_T::PS2RXDATA + * Offset: 0x14 PS/2 Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RXDATA |Received Data + * | | |For host to device communication, after acknowledge bit is sent, the received data is copied + * | | |from receive shift register to PS2RXDATA register. + * | | |CPU must read this register before next byte reception complete, otherwise the data will be + * | | |overwritten and RXOVF(PS2STATUS[6]) bit will be set to 1. + * @var PS2_T::PS2STATUS + * Offset: 0x18 PS/2 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PS2CLK |CLK Pin State + * | | |This bit reflects the status of the PS2_CLK line after synchronizing. + * |[1] |PS2DATA |DATA Pin State + * | | |This bit reflects the status of the PS2_DATA line after synchronizing and sampling. + * |[2] |FRAMERR |Frame Error + * | | |For host to device communication, this bit sets to 1 if STOP bit (logic 1) is not received. + * | | |If frame error occurs, the PS/2_DATA line may keep at low state after 12th clock. + * | | |At this moment, software overrides PS2_CLK to send clock till PS2_DATA release to high + * | | |state. + * | | |After that, device sends a "Resend" command to host. + * | | |0 = No frame error. + * | | |1 = Frame error occur. + * | | |Write 1 to clear this bit. + * |[3] |RXPARITY |Received Parity + * | | |This bit reflects the parity bit for the last received data byte (odd parity). + * | | |This bit is read only. + * |[4] |RXBUSY |Receive Busy + * | | |This bit indicates that the PS/2 device is currently receiving data. + * | | |0 = Idle. + * | | |1 = Currently receiving data. + * | | |This bit is read only. + * |[5] |TXBUSY |Transmit Busy + * | | |This bit indicates that the PS/2 device is currently sending data. + * | | |0 = Idle. + * | | |1 = Currently sending data. + * | | |This bit is read only. + * |[6] |RXOVF |RX Buffer Overwrite + * | | |0 = No overwrite. + * | | |1 = Data in PS2RXDATA register is overwritten by new received data. + * | | |Write 1 to clear this bit. + * |[7] |TXEMPTY |TX FIFO Empty + * | | |When software writes data to PS2TXDATA0-3, the TXEMPTY bit is cleared to 0 immediately if + * | | |PS2EN(PS2CON[0]) is enabled. + * | | |When transmitted data byte number is equal to FIFODEPTH(PS2CON[6:3]) then TXEMPTY bit is set + * | | |to 1. + * | | |0 = There is data to be transmitted. + * | | |1 = FIFO is empty. + * | | |This bit is read only. + * |[11:8] |BYTEIDX |Byte Index + * | | |It indicates which data byte in transmit data shift register. + * | | |When all data in FIFO is transmitted and it will be cleared to 0. + * | | |This bit is read only. + * | | |BYTEIDX, DATA Transmit , BYTEIDX, DATA Transmit + * | | |0000 , PS2TXDATA0[ 7: 0], 1000 , PS2TXDATA2[ 7: 0], + * | | |0001 , PS2TXDATA0[15: 8], 1001 , PS2TXDATA2[15: 8], + * | | |0010 , PS2TXDATA0[23:16], 1010 , PS2TXDATA2[23:16], + * | | |0011 , PS2TXDATA0[31:24], 1011 , PS2TXDATA2[31:24], + * | | |0100 , PS2TXDATA1[ 7: 0], 1100 , PS2TXDATA3[ 7: 0], + * | | |0101 , PS2TXDATA1[15: 8], 1101 , PS2TXDATA3[15: 8], + * | | |0110 , PS2TXDATA1[23:16], 1110 , PS2TXDATA3[23:16], + * | | |0111 , PS2TXDATA1[31:24], 1111 , PS2TXDATA3[31:24], + * @var PS2_T::PS2INTID + * Offset: 0x1C PS/2 Interrupt Identification Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXINT |Receive Interrupt + * | | |This bit is set to 1 when acknowledge bit is sent for Host to device communication. + * | | |Interrupt occurs if RXINTEN(PS2CON[2]) bit is set to 1. + * | | |0 = No interrupt. + * | | |1 = Receive interrupt occurs. + * | | |Write 1 to clear this bit to 0. + * |[1] |TXINT |Transmit Interrupt + * | | |This bit is set to 1 after STOP bit is transmitted. + * | | |Interrupt occur if TXINTEN(PS2CON[1]) bit is set to 1. + * | | |0 = No interrupt. + * | | |1 = Transmit interrupt occurs. + * | | |Write 1 to clear this bit to 0. + */ + + __IO uint32_t PS2CON; /* Offset: 0x00 PS/2 Control Register */ + __IO uint32_t PS2TXDATA0; /* Offset: 0x04 PS/2 Transmit Data Register 0 */ + __IO uint32_t PS2TXDATA1; /* Offset: 0x08 PS/2 Transmit Data Register 1 */ + __IO uint32_t PS2TXDATA2; /* Offset: 0x0C PS/2 Transmit Data Register 2 */ + __IO uint32_t PS2TXDATA3; /* Offset: 0x10 PS/2 Transmit Data Register 3 */ + __IO uint32_t PS2RXDATA; /* Offset: 0x14 PS/2 Receive Data Register */ + __IO uint32_t PS2STATUS; /* Offset: 0x18 PS/2 Status Register */ + __IO uint32_t PS2INTID; /* Offset: 0x1C PS/2 Interrupt Identification Register */ + +} PS2_T; + + + + +/** + @addtogroup PS2_CONST PS2 Bit Field Definition + Constant Definitions for PS2 Controller +@{ */ + +/* PS2 PS2CON Bit Field Definitions */ +#define PS2_PS2CON_PS2EN_Pos 0 /*!< PS2_T::PS2CON: PS2EN Position */ +#define PS2_PS2CON_PS2EN_Msk (1ul << PS2_PS2CON_PS2EN_Pos) /*!< PS2_T::PS2CON: PS2EN Mask */ + +#define PS2_PS2CON_TXINTEN_Pos 1 /*!< PS2_T::PS2CON: TXINTEN Position */ +#define PS2_PS2CON_TXINTEN_Msk (1ul << PS2_PS2CON_TXINTEN_Pos) /*!< PS2_T::PS2CON: TXINTEN Mask */ + +#define PS2_PS2CON_RXINTEN_Pos 2 /*!< PS2_T::PS2CON: RXINTEN Position */ +#define PS2_PS2CON_RXINTEN_Msk (1ul << PS2_PS2CON_RXINTEN_Pos) /*!< PS2_T::PS2CON: RXINTEN Mask */ + +#define PS2_PS2CON_TXFIFO_DEPTH_Pos 3 /*!< PS2_T::PS2CON: TXFIFO_DEPTH Position */ +#define PS2_PS2CON_TXFIFO_DEPTH_Msk (0xFul << PS2_PS2CON_TXFIFO_DEPTH_Pos) /*!< PS2_T::PS2CON: TXFIFO_DEPTH Mask */ + +#define PS2_PS2CON_ACK_Pos 7 /*!< PS2_T::PS2CON: ACK Position */ +#define PS2_PS2CON_ACK_Msk (1ul << PS2_PS2CON_ACK_Pos) /*!< PS2_T::PS2CON: ACK Mask */ + +#define PS2_PS2CON_CLRFIFO_Pos 8 /*!< PS2_T::PS2CON: CLRFIFO Position */ +#define PS2_PS2CON_CLRFIFO_Msk (1ul << PS2_PS2CON_CLRFIFO_Pos) /*!< PS2_T::PS2CON: CLRFIFO Mask */ + +#define PS2_PS2CON_OVERRIDE_Pos 9 /*!< PS2_T::PS2CON: OVERRIDE Position */ +#define PS2_PS2CON_OVERRIDE_Msk (1ul << PS2_PS2CON_OVERRIDE_Pos) /*!< PS2_T::PS2CON: OVERRIDE Mask */ + +#define PS2_PS2CON_FPS2CLK_Pos 10 /*!< PS2_T::PS2CON: FPS2CLK Position */ +#define PS2_PS2CON_FPS2CLK_Msk (1ul << PS2_PS2CON_FPS2CLK_Pos) /*!< PS2_T::PS2CON: FPS2CLK Mask */ + +#define PS2_PS2CON_FPS2DAT_Pos 11 /*!< PS2_T::PS2CON: FPS2DAT Position */ +#define PS2_PS2CON_FPS2DAT_Msk (1ul << PS2_PS2CON_FPS2DAT_Pos) /*!< PS2_T::PS2CON: FPS2DAT Mask */ + +/* PS/2 PS2RXDATA Bit Field Definitions */ +#define PS2_PS2RXDATA_RXDATA_Pos 0 /*!< PS2_T::PS2RXDATA: RXDATA Position */ +#define PS2_PS2RXDATA_RXDATA_Msk (0xFFul << PS2_PS2RXDATA_RXDATA_Pos) /*!< PS2_T::PS2RXDATA: RXDATA Mask */ + +/* PS/2 PS2STATUS Bit Field Definitions */ +#define PS2_PS2STATUS_PS2CLK_Pos 0 /*!< PS2_T::PS2STATUS: PS2CLK Position */ +#define PS2_PS2STATUS_PS2CLK_Msk (1ul << PS2_PS2STATUS_PS2CLK_Pos) /*!< PS2_T::PS2STATUS: PS2CLK Mask */ + +#define PS2_PS2STATUS_PS2DATA_Pos 1 /*!< PS2_T::PS2STATUS: PS2DATA Position */ +#define PS2_PS2STATUS_PS2DATA_Msk (1ul << PS2_PS2STATUS_PS2DATA_Pos) /*!< PS2_T::PS2STATUS: PS2DATA Mask */ + +#define PS2_PS2STATUS_FRAMERR_Pos 2 /*!< PS2_T::PS2STATUS: FRAMERR Position */ +#define PS2_PS2STATUS_FRAMERR_Msk (1ul << PS2_PS2STATUS_FRAMERR_Pos) /*!< PS2_T::PS2STATUS: FRAMERR Mask */ + +#define PS2_PS2STATUS_RXPARITY_Pos 3 /*!< PS2_T::PS2STATUS: RXPARITY Position */ +#define PS2_PS2STATUS_RXPARITY_Msk (1ul << PS2_PS2STATUS_RXPARITY_Pos) /*!< PS2_T::PS2STATUS: RXPARITY Mask */ + +#define PS2_PS2STATUS_RXBUSY_Pos 4 /*!< PS2_T::PS2STATUS: RXBUSY Position */ +#define PS2_PS2STATUS_RXBUSY_Msk (1ul << PS2_PS2STATUS_RXBUSY_Pos) /*!< PS2_T::PS2STATUS: RXBUSY Mask */ + +#define PS2_PS2STATUS_TXBUSY_Pos 5 /*!< PS2_T::PS2STATUS: TXBUSY Position */ +#define PS2_PS2STATUS_TXBUSY_Msk (1ul << PS2_PS2STATUS_TXBUSY_Pos) /*!< PS2_T::PS2STATUS: TXBUSY Mask */ + +#define PS2_PS2STATUS_RXOVF_Pos 6 /*!< PS2_T::PS2STATUS: RXOVF Position */ +#define PS2_PS2STATUS_RXOVF_Msk (1ul << PS2_PS2STATUS_RXOVF_Pos) /*!< PS2_T::PS2STATUS: RXOVF Mask */ + +#define PS2_PS2STATUS_TXEMPTY_Pos 7 /*!< PS2_T::PS2STATUS: TXEMPTY Position */ +#define PS2_PS2STATUS_TXEMPTY_Msk (1ul << PS2_PS2STATUS_TXEMPTY_Pos) /*!< PS2_T::PS2STATUS: TXEMPTY Mask */ + +#define PS2_PS2STATUS_BYTEIDX_Pos 8 /*!< PS2_T::PS2STATUS: BYTEIDX Position */ +#define PS2_PS2STATUS_BYTEIDX_Msk (0xFul << PS2_PS2STATUS_BYTEIDX_Pos) /*!< PS2_T::PS2STATUS: BYTEIDX Mask */ + +/* PS/2 PS2INTID Bit Field Definitions */ +#define PS2_PS2INTID_RXINT_Pos 0 /*!< PS2_T::PS2INTID: RXINT Position */ +#define PS2_PS2INTID_RXINT_Msk (1ul << PS2_PS2INTID_RXINT_Pos) /*!< PS2_T::PS2INTID: RXINT Mask */ + +#define PS2_PS2INTID_TXINT_Pos 1 /*!< PS2_T::PS2INTID: TXINT Position */ +#define PS2_PS2INTID_TXINT_Msk (1ul << PS2_PS2INTID_TXINT_Pos) /*!< PS2_T::PS2INTID: TXINT Mask */ +/*@}*/ /* end of group PS2_CONST */ +/*@}*/ /* end of group PS2 */ + + +/*---------------------- Pulse Width Modulation Controller -------------------------*/ +/** + @addtogroup PWM Pulse Width Modulation Controller (PWM) + Memory Mapped Structure for PWM Controller +@{ */ + + +typedef struct +{ + + +/** + * @var PWM_T::PPR + * Offset: 0x00 PWM Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CP01 |Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B) + * | | |Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer + * | | |If CP01=0, then the clock prescaler 0 output clock will be stopped. + * | | |So corresponding PWM-timer will also be stopped. + * |[15:8] |CP23 |Clock Prescaler 2 (PWM-Timer2 / 3 For Group A And PWM-Timer 6 / 7 For Group B) + * | | |Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer + * | | |If CP23=0, then the clock prescaler 2 output clock will be stopped. + * | | |So corresponding PWM-timer will also be stopped. + * |[23:16] |DZI01 |Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B) + * | | |These 8-bit determine the Dead-zone length. + * | | |The unit time of Dead-zone length = [(prescale+1)*(clock source divider)]/ PWMxy_CLK (where + * | | |xy could be 01 or 45, depends on selected PWM channel.). + * |[31:24] |DZI23 |Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B) + * | | |These 8-bit determine the Dead-zone length. + * | | |The unit time of Dead-zone length = [(prescale+1)*(clock source divider)]/ PWMxy_CLK (where + * | | |xy could be 23 or 67, depends on selected PWM channel.). + * @var PWM_T::CSR + * Offset: 0x04 PWM Clock Source Divider Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CSR0 |Timer 0 Clock Source Selection(PWM timer 0 for group A and PWM timer 4 for group B) + * | | |Select clock input for timer. + * | | |(Table is the same as CSR3) + * |[6:4] |CSR1 |Timer 1 Clock Source Selection(PWM timer 1 for group A and PWM timer 5 for group B) + * | | |Select clock input for timer. + * | | |(Table is the same as CSR3) + * |[10:8] |CSR2 |Timer 2 Clock Source Selection(PWM timer 2 for group A and PWM timer 6 for group B) + * | | |Select clock input for timer. + * | | |(Table is the same as CSR3) + * |[14:12] |CSR3 |Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B) + * | | |Select clock input for timer. + * | | |CSRx[2:0] = Input clock divider + * | | |100 = 1 + * | | |011 = 16 + * | | |010 = 8 + * | | |001 = 4 + * | | |000 = 2 + * @var PWM_T::PCR + * Offset: 0x08 PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0EN |PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B) + * | | |0 = The corresponding PWM-Timer stops running. + * | | |1 = The corresponding PWM-Timer starts running. + * |[1] |CH0PINV |PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B) + * | | |0 = PWM0 output polar inverse Disabled. + * | | |1 = PWM0 output polar inverse Enabled. + * |[2] |CH0INV |PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B) + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. + * |[3] |CH0MOD |PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B) + * | | |0 = One-shot mode. + * | | |1 = Auto-reload mode. + * | | |Note: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared. + * |[4] |DZEN01 |Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B) + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |Note: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary + * | | |pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM + * | | |group B. + * |[5] |DZEN23 |Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B) + * | | |0 = Disabled. + * | | |1 = Enabled. + * | | |Note: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary + * | | |pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM + * | | |group B. + * |[8] |CH1EN |PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B) + * | | |0 = Corresponding PWM-Timer Stopped. + * | | |1 = Corresponding PWM-Timer Start Running. + * |[9] |CH1PINV |PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B) + * | | |0 = PWM1 output polar inverse Disabled. + * | | |1 = PWM1 output polar inverse Enabled. + * |[10] |CH1INV |PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B) + * | | |0 = Inverter Disable. + * | | |1 = Inverter Enable. + * |[11] |CH1MOD |PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B) + * | | |0 = One-shot mode. + * | | |1 = Auto-reload mode. + * | | |Note: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared. + * |[16] |CH2EN |PWM-Timer 2 Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B) + * | | |0 = Corresponding PWM-Timer Stopped. + * | | |1 = Corresponding PWM-Timer Start Running. + * |[17] |CH2PINV |PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B) + * | | |0 = PWM2 output polar inverse Disabled. + * | | |1 = PWM2 output polar inverse Enabled. + * |[18] |CH2INV |PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B) + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. + * |[19] |CH2MOD |PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A And PWM Timer 6 For Group B) + * | | |0 = One-shot mode. + * | | |1 = Auto-reload mode. + * | | |Note: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared. + * |[24] |CH3EN |PWM-Timer 3 Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B) + * | | |0 = Corresponding PWM-Timer Stopped. + * | | |1 = Corresponding PWM-Timer Start Running. + * |[25] |CH3PINV |PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B) + * | | |0 = PWM3 output polar inverse Disable. + * | | |1 = PWM3 output polar inverse Enable. + * |[26] |CH3INV |PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B) + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. + * |[27] |CH3MOD |PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A And PWM Timer 7 For Group B) + * | | |0 = One-shot mode. + * | | |1 = Auto-reload mode. + * | | |Note: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared. + * |[30] |PWM01TYPE |PWM01 Aligned Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B) + * | | |0 = Edge-aligned type. + * | | |1 = Center-aligned type. + * |[31] |PWM23TYPE |PWM23 Aligned Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B) + * | | |0 = Edge-aligned type. + * | | |1 = Center-aligned type. + * @var PWM_T::CNR0 + * Offset: 0x0C PWM Counter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNRx |PWM Timer Loaded Value + * | | |CNR determines the PWM period. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * | | |Note: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to + * | | |0xFFFE. + * | | |If CNR equal to 0xFFFF, the PWM will work unpredictable. + * | | |Note: When CNR value is set to 0, PWM output is always high. + * @var PWM_T::CMR0 + * Offset: 0x0C PWM Counter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNRx |PWM Timer Loaded Value + * | | |CNR determines the PWM period. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * | | |Note: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to + * | | |0xFFFE. + * | | |If CNR equal to 0xFFFF, the PWM will work unpredictable. + * | | |Note: When CNR value is set to 0, PWM output is always high. + * @var PWM_T::PDR0 + * Offset: 0x14 PWM Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDRx |PWM Data Register + * | | |User can monitor PDR to know the current value in 16-bit counter. + * @var PWM_T::CNR1 + * Offset: 0x18 PWM Counter Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNRx |PWM Timer Loaded Value + * | | |CNR determines the PWM period. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * | | |Note: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to + * | | |0xFFFE. + * | | |If CNR equal to 0xFFFF, the PWM will work unpredictable. + * | | |Note: When CNR value is set to 0, PWM output is always high. + * @var PWM_T::CMR1 + * Offset: 0x1C PWM Comparator Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMRx |PWM Comparator Register + * | | |CMR determines the PWM duty. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * @var PWM_T::PDR1 + * Offset: 0x20 PWM Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDRx |PWM Data Register + * | | |User can monitor PDR to know the current value in 16-bit counter. + * @var PWM_T::CNR2 + * Offset: 0x24 PWM Counter Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNRx |PWM Timer Loaded Value + * | | |CNR determines the PWM period. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * | | |Note: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to + * | | |0xFFFE. + * | | |If CNR equal to 0xFFFF, the PWM will work unpredictable. + * | | |Note: When CNR value is set to 0, PWM output is always high. + * @var PWM_T::CMR2 + * Offset: 0x28 PWM Comparator Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMRx |PWM Comparator Register + * | | |CMR determines the PWM duty. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * @var PWM_T::PDR2 + * Offset: 0x2C PWM Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDRx |PWM Data Register + * | | |User can monitor PDR to know the current value in 16-bit counter. + * @var PWM_T::CNR3 + * Offset: 0x30 PWM Counter Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNRx |PWM Timer Loaded Value + * | | |CNR determines the PWM period. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * | | |Note: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to + * | | |0xFFFE. + * | | |If CNR equal to 0xFFFF, the PWM will work unpredictable. + * | | |Note: When CNR value is set to 0, PWM output is always high. + * @var PWM_T::CMR3 + * Offset: 0x34 PWM Comparator Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMRx |PWM Comparator Register + * | | |CMR determines the PWM duty. + * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(CNR+1)]; where xy, could be 01, 23, + * | | |45 or 67, depends on selected PWM channel. + * | | |For Edge-aligned type: + * | | | Duty ratio = (CMR+1)/(CNR+1). + * | | | CMR >= CNR: PWM output is always high. + * | | | CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. + * | | | CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit. + * | | |For Center-aligned type: + * | | | Duty ratio = [(2 x CMR) + 1]/[2 x (CNR+1)]. + * | | | CMR > CNR: PWM output is always high. + * | | | CMR <= CNR: PWM low width = 2 x (CNR-CMR) + 1 unit; PWM high width = (2 x CMR) + 1 unit. + * | | | CMR = 0: PWM low width = 2 x CNR + 1 unit; PWM high width = 1 unit. + * | | |(Unit = one PWM clock cycle). + * | | |Note: Any write to CNR will take effect in next PWM cycle. + * @var PWM_T::PDR3 + * Offset: 0x38 PWM Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PDRx |PWM Data Register + * | | |User can monitor PDR to know the current value in 16-bit counter. + * @var PWM_T::PBCR + * Offset: 0x3C PWM Backward Compatible Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BCn |PWM Backward Compatible Register + * | | |0 = Configure write 0 to clear CFLRI0~3 and CRLRI0~3. + * | | |1 = Configure write 1 to clear CFLRI0~3 and CRLRI0~3. + * | | |Refer to the CCR0/CCR2 register bit 6, 7, 22, 23 description + * | | |Note: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being + * | | |cleared when writing CCR0/CCR2. + * @var PWM_T::PIER + * Offset: 0x40 PWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWMIE0 |PWM Channel 0 Period Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[1] |PWMIE1 |PWM Channel 1 Period Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[2] |PWMIE2 |PWM Channel 2 Period Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[3] |PWMIE3 |PWM Channel 3 Period Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[8] |PWMDIE0 |PWM Channel 0 Duty Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[9] |PWMDIE1 |PWM Channel 1 Duty Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[10] |PWMDIE2 |PWM Channel 2 Duty Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[11] |PWMDIE3 |PWM Channel 3 Duty Interrupt Enable + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[16] |INT01TYPE |PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B) + * | | |0 = PWMIFn will be set if PWM counter underflow. + * | | |1 = PWMIFn will be set if PWM counter matches CNRn register. + * | | |Note: This bit is effective when PWM in Center-aligned type only. + * |[17] |INT23TYPE |PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B) + * | | |0 = PWMIFn will be set if PWM counter underflow. + * | | |1 = PWMIFn will be set if PWM counter matches CNRn register. + * | | |Note: This bit is effective when PWM in Center-aligned type only. + * @var PWM_T::PIIR + * Offset: 0x44 PWM Interrupt Indication Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWMIF0 |PWM Channel 0 Period Interrupt Status + * | | |This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend + * | | |on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0. + * |[1] |PWMIF1 |PWM Channel 1 Period Interrupt Status + * | | |This bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend + * | | |on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0. + * |[2] |PWMIF2 |PWM Channel 2 Period Interrupt Status + * | | |This bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend + * | | |on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0. + * |[3] |PWMIF3 |PWM Channel 3 Period Interrupt Status + * | | |This bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend + * | | |on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0. + * |[8] |PWMDIF0 |PWM Channel 0 Duty Interrupt Flag + * | | |Flag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can + * | | |clear this bit by writing a one to it. + * | | |Note: If CMR equal to CNR, this flag is not working in Edge-aligned type selection + * |[9] |PWMDIF1 |PWM Channel 1 Duty Interrupt Flag + * | | |Flag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can + * | | |clear this bit by writing a one to it. + * | | |Note: If CMR equal to CNR, this flag is not working in Edge-aligned type selection + * |[10] |PWMDIF2 |PWM Channel 2 Duty Interrupt Flag + * | | |Flag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can + * | | |clear this bit by writing a one to it. + * | | |Note: If CMR equal to CNR, this flag is not working in Edge-aligned type selection + * |[11] |PWMDIF3 |PWM Channel 3 Duty Interrupt Flag + * | | |Flag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can + * | | |clear this bit by writing a one to it. + * | | |Note: If CMR equal to CNR, this flag is not working in Edge-aligned type selection + * @var PWM_T::CCR0 + * Offset: 0x50 PWM Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INV0 |Channel 0 Inverter Enable + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer + * |[1] |CRL_IE0 |Channel 0 Rising Latch Interrupt Enable + * | | |0 = Rising latch interrupt Disabled. + * | | |1 = Rising latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will + * | | |issue an Interrupt. + * |[2] |CFL_IE0 |Channel 0 Falling Latch Interrupt Enable + * | | |0 = Falling latch interrupt Disabled. + * | | |1 = Falling latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will + * | | |issue an Interrupt. + * |[3] |CAPCH0EN |Channel 0 Capture Function Enable + * | | |0 = Capture function on PWM group channel 0 Disabled. + * | | |1 = Capture function on PWM group channel 0 Enabled. + * | | |When Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and + * | | |CFLR (Falling latch). + * | | |When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 + * | | |Interrupt. + * |[4] |CAPIF0 |Channel 0 Capture Interrupt Indication Flag + * | | |If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0 = 1), a rising transition + * | | |occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition + * | | |will cause CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled + * | | |(CFL_IE0 = 1). + * | | |Write 1 to clear this bit to 0. + * |[6] |CRLRI0 |CRLR0 Latched Indicator Bit + * | | |When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear + * | | |this bit to 0 if the BCn bit is 1. + * |[7] |CFLRI0 |CFLR0 Latched Indicator Bit + * | | |When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear + * | | |this bit to0 if BCn bit is 1. + * |[16] |INV1 |Channel 1 Inverter Enable + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer + * |[17] |CRL_IE1 |Channel 1 Rising Latch Interrupt Enable + * | | |0 = Rising latch interrupt Disabled. + * | | |1 = Rising latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will + * | | |issue an Interrupt. + * |[18] |CFL_IE1 |Channel 1 Falling Latch Interrupt Enable + * | | |0 = Falling latch interrupt Disabled. + * | | |1 = Falling latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will + * | | |issue an Interrupt. + * |[19] |CAPCH1EN |Channel 1 Capture Function Enable + * | | |0 = Capture function on PWM group channel 1 Disabled. + * | | |1 = Capture function on PWM group channel 1 Enabled. + * | | |When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR + * | | |(Falling latch). + * | | |When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 + * | | |Interrupt. + * |[20] |CAPIF1 |Channel 1 Capture Interrupt Indication Flag + * | | |If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1 = 1), a rising transition + * | | |occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition + * | | |will cause CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled + * | | |(CFL_IE1 = 1). + * | | |Write 1 to clear this bit to 0. + * |[22] |CRLRI1 |CRLR1 Latched Indicator Bit + * | | |When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this + * | | |bit to0 if BCn bit is 1. + * |[23] |CFLRI1 |CFLR1 Latched Indicator Bit + * | | |When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this + * | | |bit to 0 if BCn bit is 1. + * @var PWM_T::CCR2 + * Offset: 0x54 PWM Capture Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INV2 |Channel 2 Inverter Enable + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer + * |[1] |CRL_IE2 |Channel 2 Rising Latch Interrupt Enable + * | | |0 = Rising latch interrupt Disabled. + * | | |1 = Rising latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will + * | | |issue an Interrupt. + * |[2] |CFL_IE2 |Channel 2 Falling Latch Interrupt Enable + * | | |0 = Falling latch interrupt Disabled. + * | | |1 = Falling latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will + * | | |issue an Interrupt. + * |[3] |CAPCH2EN |Channel 2 Capture Function Enable + * | | |0 = Capture function on PWM group channel 2 Disabled. + * | | |1 = Capture function on PWM group channel 2 Enabled. + * | | |When Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and + * | | |CFLR (Falling latch). + * | | |When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 + * | | |Interrupt. + * |[4] |CAPIF2 |Channel 2 Capture Interrupt Indication Flag + * | | |If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition + * | | |occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition + * | | |will cause CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled + * | | |(CFL_IE2=1). + * | | |Write 1 to clear this bit to 0 + * |[6] |CRLRI2 |CRLR2 Latched Indicator Bit + * | | |When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear + * | | |this bit to 0 if the BCn bit is 1. + * |[7] |CFLRI2 |CFLR2 Latched Indicator Bit + * | | |When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this + * | | |bit to 0 if the BCn bit is 1. + * |[16] |INV3 |Channel 3 Inverter Enable + * | | |0 = Inverter Disabled. + * | | |1 = Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer + * |[17] |CRL_IE3 |Channel 3 Rising Latch Interrupt Enable + * | | |0 = Rising latch interrupt Disabled. + * | | |1 = Rising latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will + * | | |issue an Interrupt. + * |[18] |CFL_IE3 |Channel 3 Falling Latch Interrupt Enable + * | | |0 = Falling latch interrupt Disabled. + * | | |1 = Falling latch interrupt Enabled. + * | | |When Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will + * | | |issue an Interrupt. + * |[19] |CAPCH3EN |Channel 3 Capture Function Enable + * | | |0 = Capture function on PWM group channel 3 Disabled. + * | | |1 = Capture function on PWM group channel 3 Enabled. + * | | |When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR + * | | |(Falling latch). + * | | |When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 + * | | |Interrupt. + * |[20] |CAPIF3 |Channel 3 Capture Interrupt Indication Flag + * | | |If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition + * | | |occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition + * | | |will cause CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled + * | | |(CFL_IE3=1). + * | | |Write 1 to clear this bit to 0 + * |[22] |CRLRI3 |CRLR3 Latched Indicator Bit + * | | |When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear + * | | |this bit to 0 if the BCn bit is 1. + * |[23] |CFLRI3 |CFLR3 Latched Indicator Bit + * | | |When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of + * | | |PWM down-counter and this bit is set by hardware. + * | | |Software can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear + * | | |this bit to 0 if the BCn bit is 1. + * @var PWM_T::CRLR0 + * Offset: 0x58 PWM Capture Rising Latch Register (Channel 0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRLRx |Capture Rising Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition. + * @var PWM_T::CFLR0 + * Offset: 0x5C PWM Capture Falling Latch Register (Channel 0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CFLRx |Capture Falling Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition. + * @var PWM_T::CRLR1 + * Offset: 0x60 PWM Capture Rising Latch Register (Channel 1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRLRx |Capture Rising Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition. + * @var PWM_T::CFLR1 + * Offset: 0x64 PWM Capture Falling Latch Register (Channel 1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CFLRx |Capture Falling Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition. + * @var PWM_T::CRLR2 + * Offset: 0x68 PWM Capture Rising Latch Register (Channel 2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRLRx |Capture Rising Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition. + * @var PWM_T::CFLR2 + * Offset: 0x6C PWM Capture Falling Latch Register (Channel 2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CFLRx |Capture Falling Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition. + * @var PWM_T::CRLR3 + * Offset: 0x70 PWM Capture Rising Latch Register (Channel 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CRLRx |Capture Rising Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition. + * @var PWM_T::CFLR3 + * Offset: 0x74 PWM Capture Falling Latch Register (Channel 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CFLRx |Capture Falling Latch Register + * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition. + * @var PWM_T::CAPENR + * Offset: 0x78 PWM Capture Input 0~3 Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CINEN0 |Channel 0 Capture Input Enable + * | | |0 = PWM Channel 0 capture input path Disabled. + * | | |The input of PWM channel 0 capture function is always regarded as 0. + * | | |1 = PWM Channel 0 capture input path Enabled. + * | | |The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO + * | | |multi-function is set as PWM0. + * |[1] |CINEN1 |Channel 1 Capture Input Enable + * | | |0 = PWM Channel 1 capture input path Disabled. + * | | |The input of PWM channel 1 capture function is always regarded as 0. + * | | |1 = PWM Channel 1 capture input path Enabled. + * | | |The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO + * | | |multi-function is set as PWM1. + * |[2] |CINEN2 |Channel 2 Capture Input Enable + * | | |0 = PWM Channel 2 capture input path Disabled. + * | | |The input of PWM channel 2 capture function is always regarded as 0. + * | | |1 = PWM Channel 2 capture input path Enabled. + * | | |The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO + * | | |multi-function is set as PWM2. + * |[3] |CINEN3 |Channel 3 Capture Input Enable + * | | |0 = PWM Channel 3 capture input path Disabled. + * | | |The input of PWM channel 3 capture function is always regarded as 0. + * | | |1 = PWM Channel 3 capture input path Enabled. + * | | |The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO + * | | |multi-function is set as PWM3. + * @var PWM_T::POE + * Offset: 0x7C PWM Output Enable for Channel 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POE0 |Channel 0 Output Enable Register + * | | |0 = PWM channel 0 output to pin Disabled. + * | | |1 = PWM channel 0 output to pin Enabled. + * | | |Note: The corresponding GPIO pin must also be switched to PWM function + * |[1] |POE1 |Channel 1 Output Enable Register + * | | |0 = PWM channel 1 output to pin Disabled. + * | | |1 = PWM channel 1 output to pin Enabled. + * | | |Note: The corresponding GPIO pin must also be switched to PWM function + * |[2] |POE2 |Channel 2 Output Enable Register + * | | |0 = PWM channel 2 output to pin Disabled. + * | | |1 = PWM channel 2 output to pin Enabled. + * | | |Note: The corresponding GPIO pin must also be switched to PWM function + * |[3] |POE3 |Channel 3 Output Enable Register + * | | |0 = PWM channel 3 output to pin Disabled. + * | | |1 = PWM channel 3 output to pin Enabled. + * | | |Note: The corresponding GPIO pin must also be switched to PWM function + * @var PWM_T::TCON + * Offset: 0x80 PWM Trigger Control for Channel 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWM0TEN |Channel 0 Center-Aligned Trigger Enable Register + * | | |0 = PWM channel 0 trigger ADC function Disabled. + * | | |1 = PWM channel 0 trigger ADC function Enabled. + * | | |PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set + * | | |to 1. + * | | |Note: This function is only supported when PWM operating at Center-aligned type. + * |[1] |PWM1TEN |Channel 1 Center-Aligned Trigger Enable Register + * | | |0 = PWM channel 1 trigger ADC function Disabled. + * | | |1 = PWM channel 1 trigger ADC function Enabled. + * | | |PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set + * | | |to 1. + * | | |Note: This function is only supported when PWM operating at Center-aligned type. + * |[2] |PWM2TEN |Channel 2 Center-Aligned Trigger Enable Register + * | | |0 = PWM channel 2 trigger ADC function Disabled. + * | | |1 = PWM channel 2 trigger ADC function Enabled. + * | | |PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set + * | | |to 1. + * | | |Note: This function is only supported when PWM operating at Center-aligned type. + * |[3] |PWM3TEN |Channel 3 Center-Aligned Trigger Enable Register + * | | |0 = PWM channel 3 trigger ADC function Disabled. + * | | |1 = PWM channel 3 trigger ADC function Enabled. + * | | |PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set + * | | |to 1. + * | | |Note: This function is only supported when PWM operating at Center-aligned type. + * @var PWM_T::TSTATUS + * Offset: 0x84 PWM Trigger Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWM0TF |Channel 0 Center-Aligned Trigger Flag + * | | |For Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up + * | | |counts to CNR if PWM0TEN bit is set to 1. + * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by + * | | |PWM. + * | | |Software can write 1 to clear this bit. + * |[1] |PWM1TF |Channel 1 Center-Aligned Trigger Flag + * | | |For Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up + * | | |count to CNR if PWM1TEN bit is set to 1. + * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by + * | | |PWM. + * | | |Software can write 1 to clear this bit. + * |[2] |PWM2TF |Channel 2 Center-Aligned Trigger Flag + * | | |For Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up + * | | |count to CNR if PWM2TEN bit is set to 1. + * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by + * | | |PWM. + * | | |Software can write 1 to clear this bit. + * |[3] |PWM3TF |Channel 3 Center-Aligned Trigger Flag + * | | |For Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up + * | | |count to CNR if PWM3TEN bit is set to 1. + * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by + * | | |PWM. + * | | |Software can write 1 to clear this bit. + * @var PWM_T::SYNCBUSY0 + * Offset: 0x88 PWM0 Synchronous Busy Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |S_BUSY |PWM Synchronous Busy + * | | |When software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a + * | | |busy time to update these values completely because PWM clock may be different from system + * | | |clock domain. + * | | |Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 + * | | |operation mode (PCR[3]) to make sure previous setting has been updated completely. + * | | |This bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode + * | | |(PCR[3]) and will be cleared by hardware automatically when PWM update these value + * | | |completely. + * @var PWM_T::SYNCBUSY1 + * Offset: 0x8C PWM1 Synchronous Busy Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |S_BUSY |PWM Synchronous Busy + * | | |When Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have + * | | |a busy time to update these values completely because PWM clock may be different from system + * | | |clock domain. + * | | |Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 + * | | |operation mode (PCR[11]) to make sure previous setting has been updated completely. + * | | |This bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode + * | | |(PCR[11]) and will be cleared by hardware automatically when PWM update these value + * | | |completely. + * @var PWM_T::SYNCBUSY2 + * Offset: 0x90 PWM2 Synchronous Busy Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |S_BUSY |PWM Synchronous Busy + * | | |When Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a + * | | |busy time to update these values completely because PWM clock may be different from system + * | | |clock domain. + * | | |Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 + * | | |operation mode (PCR[19]) to make sure previous setting has been updated completely. + * | | |This bit will be set when software writes CNR2/CMR2/PPR or switch PWM2 operation mode + * | | |(PCR[19]) and will be cleared by hardware automatically when PWM update these value + * | | |completely. + * @var PWM_T::SYNCBUSY3 + * Offset: 0x94 PWM3 Synchronous Busy Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |S_BUSY |PWM Synchronous Busy + * | | |When Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a + * | | |busy time to update these values completely because PWM clock may be different from system + * | | |clock domain. + * | | |Software need to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 + * | | |operation mode (PCR[27]) to make sure previous setting has been updated completely. + * | | |This bit will be set when Software writes CNR3/CMR3/PPR or switch PWM3 operation mode + * | | |(PCR[27]) and will be cleared by hardware automatically when PWM update these value + * | | |completely. + */ + + __IO uint32_t PPR; /* Offset: 0x00 PWM Prescaler Register */ + __IO uint32_t CSR; /* Offset: 0x04 PWM Clock Source Divider Select Register */ + __IO uint32_t PCR; /* Offset: 0x08 PWM Control Register */ + __IO uint32_t CNR0; /* Offset: 0x0C PWM Counter Register 0 */ + __IO uint32_t CMR0; /* Offset: 0x0C PWM Counter Register 0 */ + __I uint32_t PDR0; /* Offset: 0x14 PWM Data Register 0 */ + __IO uint32_t CNR1; /* Offset: 0x18 PWM Counter Register 1 */ + __IO uint32_t CMR1; /* Offset: 0x1C PWM Comparator Register 1 */ + __I uint32_t PDR1; /* Offset: 0x20 PWM Data Register 1 */ + __IO uint32_t CNR2; /* Offset: 0x24 PWM Counter Register 2 */ + __IO uint32_t CMR2; /* Offset: 0x28 PWM Comparator Register 2 */ + __I uint32_t PDR2; /* Offset: 0x2C PWM Data Register 2 */ + __IO uint32_t CNR3; /* Offset: 0x30 PWM Counter Register 3 */ + __IO uint32_t CMR3; /* Offset: 0x34 PWM Comparator Register 3 */ + __I uint32_t PDR3; /* Offset: 0x38 PWM Data Register 3 */ + __IO uint32_t PBCR; /* Offset: 0x3C PWM Backward Compatible Register */ + __IO uint32_t PIER; /* Offset: 0x40 PWM Interrupt Enable Register */ + __IO uint32_t PIIR; /* Offset: 0x44 PWM Interrupt Indication Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CCR0; /* Offset: 0x50 PWM Capture Control Register 0 */ + __IO uint32_t CCR2; /* Offset: 0x54 PWM Capture Control Register 2 */ + __IO uint32_t CRLR0; /* Offset: 0x58 PWM Capture Rising Latch Register (Channel 0) */ + __IO uint32_t CFLR0; /* Offset: 0x5C PWM Capture Falling Latch Register (Channel 0) */ + __IO uint32_t CRLR1; /* Offset: 0x60 PWM Capture Rising Latch Register (Channel 1) */ + __IO uint32_t CFLR1; /* Offset: 0x64 PWM Capture Falling Latch Register (Channel 1) */ + __IO uint32_t CRLR2; /* Offset: 0x68 PWM Capture Rising Latch Register (Channel 2) */ + __IO uint32_t CFLR2; /* Offset: 0x6C PWM Capture Falling Latch Register (Channel 2) */ + __IO uint32_t CRLR3; /* Offset: 0x70 PWM Capture Rising Latch Register (Channel 3) */ + __IO uint32_t CFLR3; /* Offset: 0x74 PWM Capture Falling Latch Register (Channel 3) */ + __IO uint32_t CAPENR; /* Offset: 0x78 PWM Capture Input 0~3 Enable Register */ + __IO uint32_t POE; /* Offset: 0x7C PWM Output Enable for Channel 0~3 */ + __IO uint32_t TCON; /* Offset: 0x80 PWM Trigger Control for Channel 0~3 */ + __IO uint32_t TSTATUS; /* Offset: 0x84 PWM Trigger Status Register */ + __IO uint32_t SYNCBUSY0; /* Offset: 0x88 PWM0 Synchronous Busy Status Register */ + __IO uint32_t SYNCBUSY1; /* Offset: 0x8C PWM1 Synchronous Busy Status Register */ + __IO uint32_t SYNCBUSY2; /* Offset: 0x90 PWM2 Synchronous Busy Status Register */ + __IO uint32_t SYNCBUSY3; /* Offset: 0x94 PWM3 Synchronous Busy Status Register */ + +} PWM_T; + + + +/** + @addtogroup PWM_CONST PWM Bit Field Definition + Constant Definitions for PWM Controller +@{ */ + +/* PWM PPR Bit Field Definitions */ +#define PWM_PPR_DZI23_Pos 24 /*!< PWM_T::PPR: DZI23 Position */ +#define PWM_PPR_DZI23_Msk (0xFFul << PWM_PPR_DZI23_Pos) /*!< PWM_T::PPR: DZI23 Mask */ + +#define PWM_PPR_DZI01_Pos 16 /*!< PWM_T::PPR: DZI01 Position */ +#define PWM_PPR_DZI01_Msk (0xFFul << PWM_PPR_DZI01_Pos) /*!< PWM_T::PPR: DZI01 Mask */ + +#define PWM_PPR_CP23_Pos 8 /*!< PWM_T::PPR: CP23 Position */ +#define PWM_PPR_CP23_Msk (0xFFul << PWM_PPR_CP23_Pos) /*!< PWM_T::PPR: CP23 Mask */ + +#define PWM_PPR_CP01_Pos 0 /*!< PWM_T::PPR: CP01 Position */ +#define PWM_PPR_CP01_Msk (0xFFul << PWM_PPR_CP01_Pos) /*!< PWM_T::PPR: CP01 Mask */ + +/* PWM CSR Bit Field Definitions */ +#define PWM_CSR_CSR3_Pos 12 /*!< PWM_T::CSR: CSR3 Position */ +#define PWM_CSR_CSR3_Msk (7ul << PWM_CSR_CSR3_Pos) /*!< PWM_T::CSR: CSR3 Mask */ + +#define PWM_CSR_CSR2_Pos 8 /*!< PWM_T::CSR: CSR2 Position */ +#define PWM_CSR_CSR2_Msk (7ul << PWM_CSR_CSR2_Pos) /*!< PWM_T::CSR: CSR2 Mask */ + +#define PWM_CSR_CSR1_Pos 4 /*!< PWM_T::CSR: CSR1 Position */ +#define PWM_CSR_CSR1_Msk (7ul << PWM_CSR_CSR1_Pos) /*!< PWM_T::CSR: CSR1 Mask */ + +#define PWM_CSR_CSR0_Pos 0 /*!< PWM_T::CSR: CSR0 Position */ +#define PWM_CSR_CSR0_Msk (7ul << PWM_CSR_CSR0_Pos) /*!< PWM_T::CSR: CSR0 Mask */ + +/* PWM PCR Bit Field Definitions */ +#define PWM_PCR_PWM23TYPE_Pos 31 /*!< PWM_T::PCR: PWM23TYPE Position */ +#define PWM_PCR_PWM23TYPE_Msk (1ul << PWM_PCR_PWM23TYPE_Pos) /*!< PWM_T::PCR: PWM23TYPE Mask */ + +#define PWM_PCR_PWM01TYPE_Pos 30 /*!< PWM_T::PCR: PWM01TYPE Position */ +#define PWM_PCR_PWM01TYPE_Msk (1ul << PWM_PCR_PWM01TYPE_Pos) /*!< PWM_T::PCR: PWM01TYPE Mask */ + +#define PWM_PCR_CH3MOD_Pos 27 /*!< PWM_T::PCR: CH3MOD Position */ +#define PWM_PCR_CH3MOD_Msk (1ul << PWM_PCR_CH3MOD_Pos) /*!< PWM_T::PCR: CH3MOD Mask */ + +#define PWM_PCR_CH3INV_Pos 26 /*!< PWM_T::PCR: CH3INV Position */ +#define PWM_PCR_CH3INV_Msk (1ul << PWM_PCR_CH3INV_Pos) /*!< PWM_T::PCR: CH3INV Mask */ + +#define PWM_PCR_CH3PINV_Pos 25 /*!< PWM_T::PCR: CH3PINV Position */ +#define PWM_PCR_CH3PINV_Msk (1ul << PWM_PCR_CH3PINV_Pos) /*!< PWM_T::PCR: CH3PINV Mask */ + +#define PWM_PCR_CH3EN_Pos 24 /*!< PWM_T::PCR: CH3EN Position */ +#define PWM_PCR_CH3EN_Msk (1ul << PWM_PCR_CH3EN_Pos) /*!< PWM_T::PCR: CH3EN Mask */ + +#define PWM_PCR_CH2MOD_Pos 19 /*!< PWM_T::PCR: CH2MOD Position */ +#define PWM_PCR_CH2MOD_Msk (1ul << PWM_PCR_CH2MOD_Pos) /*!< PWM_T::PCR: CH2MOD Mask */ + +#define PWM_PCR_CH2INV_Pos 18 /*!< PWM_T::PCR: CH2INV Position */ +#define PWM_PCR_CH2INV_Msk (1ul << PWM_PCR_CH2INV_Pos) /*!< PWM_T::PCR: CH2INV Mask */ + +#define PWM_PCR_CH2PINV_Pos 17 /*!< PWM_T::PCR: CH2PINV Position */ +#define PWM_PCR_CH2PINV_Msk (1ul << PWM_PCR_CH2PINV_Pos) /*!< PWM_T::PCR: CH2PINV Mask */ + +#define PWM_PCR_CH2EN_Pos 16 /*!< PWM_T::PCR: CH2EN Position */ +#define PWM_PCR_CH2EN_Msk (1ul << PWM_PCR_CH2EN_Pos) /*!< PWM_T::PCR: CH2EN Mask */ + +#define PWM_PCR_CH1MOD_Pos 11 /*!< PWM_T::PCR: CH1MOD Position */ +#define PWM_PCR_CH1MOD_Msk (1ul << PWM_PCR_CH1MOD_Pos) /*!< PWM_T::PCR: CH1MOD Mask */ + +#define PWM_PCR_CH1INV_Pos 10 /*!< PWM_T::PCR: CH1INV Position */ +#define PWM_PCR_CH1INV_Msk (1ul << PWM_PCR_CH1INV_Pos) /*!< PWM_T::PCR: CH1INV Mask */ + +#define PWM_PCR_CH1PINV_Pos 9 /*!< PWM_T::PCR: CH1PINV Position */ +#define PWM_PCR_CH1PINV_Msk (1ul << PWM_PCR_CH1PINV_Pos) /*!< PWM_T::PCR: CH1PINV Mask */ + +#define PWM_PCR_CH1EN_Pos 8 /*!< PWM_T::PCR: CH1EN Position */ +#define PWM_PCR_CH1EN_Msk (1ul << PWM_PCR_CH1EN_Pos) /*!< PWM_T::PCR: CH1EN Mask */ + +#define PWM_PCR_DZEN23_Pos 5 /*!< PWM_T::PCR: DZEN23 Position */ +#define PWM_PCR_DZEN23_Msk (1ul << PWM_PCR_DZEN23_Pos) /*!< PWM_T::PCR: DZEN23 Mask */ + +#define PWM_PCR_DZEN01_Pos 4 /*!< PWM_T::PCR: DZEN01 Position */ +#define PWM_PCR_DZEN01_Msk (1ul << PWM_PCR_DZEN01_Pos) /*!< PWM_T::PCR: DZEN01 Mask */ + +#define PWM_PCR_CH0MOD_Pos 3 /*!< PWM_T::PCR: CH0MOD Position */ +#define PWM_PCR_CH0MOD_Msk (1ul << PWM_PCR_CH0MOD_Pos) /*!< PWM_T::PCR: CH0MOD Mask */ + +#define PWM_PCR_CH0INV_Pos 2 /*!< PWM_T::PCR: CH0INV Position */ +#define PWM_PCR_CH0INV_Msk (1ul << PWM_PCR_CH0INV_Pos) /*!< PWM_T::PCR: CH0INV Mask */ + +#define PWM_PCR_CH0PINV_Pos 1 /*!< PWM_T::PCR: CH0PINV Position */ +#define PWM_PCR_CH0PINV_Msk (1ul << PWM_PCR_CH0PINV_Pos) /*!< PWM_T::PCR: CH0PINV Mask */ + +#define PWM_PCR_CH0EN_Pos 0 /*!< PWM_T::PCR: CH0EN Position */ +#define PWM_PCR_CH0EN_Msk (1ul << PWM_PCR_CH0EN_Pos) /*!< PWM_T::PCR: CH0EN Mask */ + +/* PWM CNR Bit Field Definitions */ +#define PWM_CNR_CNR_Pos 0 /*!< PWM_T::CNR0: CNR Position */ +#define PWM_CNR_CNR_Msk (0xFFFFul << PWM_CNR_CNR_Pos) /*!< PWM_T::CNR0: CNR Mask */ + +/* PWM CMR Bit Field Definitions */ +#define PWM_CMR_CMR_Pos 0 /*!< PWM_T::CMR0: CMR Position */ +#define PWM_CMR_CMR_Msk (0xFFFFul << PWM_CMR_CMR_Pos) /*!< PWM_T::CMR0: CMR Mask */ + +/* PWM PDR Bit Field Definitions */ +#define PWM_PDR_PDR_Pos 0 /*!< PWM_T::PDR0: PDR Position */ +#define PWM_PDR_PDR_Msk (0xFFFFul << PWM_PDR_PDR_Pos) /*!< PWM_T::PDR0: PDR Mask */ + +/* PWM PBCR Bit Field Definitions */ +#define PWM_PBCR_BCn_Pos 0 /*!< PWM_T::PBCR: BCn Position */ +#define PWM_PBCR_BCn_Msk (1ul << PWM_PBCR_BCn_Pos) /*!< PWM_T::PBCR: BCn Mask */ + +/* PWM PIER Bit Field Definitions */ + +#define PWM_PIER_INT23TYPE_Pos 17 /*!< PWM_T::PIER: INT23TYPE Position */ +#define PWM_PIER_INT23TYPE_Msk (1ul << PWM_PIER_INT23TYPE_Pos) /*!< PWM_T::PIER: INT23TYPE Mask */ + +#define PWM_PIER_INT01TYPE_Pos 16 /*!< PWM_T::PIER: INT01TYPE Position */ +#define PWM_PIER_INT01TYPE_Msk (1ul << PWM_PIER_INT01TYPE_Pos) /*!< PWM_T::PIER: INT01TYPE Mask */ + +#define PWM_PIER_PWMDIE3_Pos 11 /*!< PWM_T::PIER: PWMDIE3 Position */ +#define PWM_PIER_PWMDIE3_Msk (1ul << PWM_PIER_PWMDIE3_Pos) /*!< PWM_T::PIER: PWMDIE3 Mask */ + +#define PWM_PIER_PWMDIE2_Pos 10 /*!< PWM_T::PIER: PWMDIE2 Position */ +#define PWM_PIER_PWMDIE2_Msk (1ul << PWM_PIER_PWMDIE2_Pos) /*!< PWM_T::PIER: PWMDIE2 Mask */ + +#define PWM_PIER_PWMDIE1_Pos 9 /*!< PWM_T::PIER: PWMDIE1 Position */ +#define PWM_PIER_PWMDIE1_Msk (1ul << PWM_PIER_PWMDIE1_Pos) /*!< PWM_T::PIER: PWMDIE1 Mask */ + +#define PWM_PIER_PWMDIE0_Pos 8 /*!< PWM_T::PIER: PWMDIE0 Position */ +#define PWM_PIER_PWMDIE0_Msk (1ul << PWM_PIER_PWMDIE0_Pos) /*!< PWM_T::PIER: PWMDIE0 Mask */ + +#define PWM_PIER_PWMIE3_Pos 3 /*!< PWM_T::PIER: PWMIE3 Position */ +#define PWM_PIER_PWMIE3_Msk (1ul << PWM_PIER_PWMIE3_Pos) /*!< PWM_T::PIER: PWMIE3 Mask */ + +#define PWM_PIER_PWMIE2_Pos 2 /*!< PWM_T::PIER: PWMIE2 Position */ +#define PWM_PIER_PWMIE2_Msk (1ul << PWM_PIER_PWMIE2_Pos) /*!< PWM_T::PIER: PWMIE2 Mask */ + +#define PWM_PIER_PWMIE1_Pos 1 /*!< PWM_T::PIER: PWMIE1 Position */ +#define PWM_PIER_PWMIE1_Msk (1ul << PWM_PIER_PWMIE1_Pos) /*!< PWM_T::PIER: PWMIE1 Mask */ + +#define PWM_PIER_PWMIE0_Pos 0 /*!< PWM_T::PIER: PWMIE0 Position */ +#define PWM_PIER_PWMIE0_Msk (1ul << PWM_PIER_PWMIE0_Pos) /*!< PWM_T::PIER: PWMIE0 Mask */ + +/* PWM PIIR Bit Field Definitions */ +#define PWM_PIIR_PWMDIF3_Pos 11 /*!< PWM_T::PIIR: PWMDIF3 Position */ +#define PWM_PIIR_PWMDIF3_Msk (1ul << PWM_PIIR_PWMDIF3_Pos) /*!< PWM_T::PIIR: PWMDIF3 Mask */ + +#define PWM_PIIR_PWMDIF2_Pos 10 /*!< PWM_T::PIIR: PWMDIF2 Position */ +#define PWM_PIIR_PWMDIF2_Msk (1ul << PWM_PIIR_PWMDIF2_Pos) /*!< PWM_T::PIIR: PWMDIF2 Mask */ + +#define PWM_PIIR_PWMDIF1_Pos 9 /*!< PWM_T::PIIR: PWMDIF1 Position */ +#define PWM_PIIR_PWMDIF1_Msk (1ul << PWM_PIIR_PWMDIF1_Pos) /*!< PWM_T::PIIR: PWMDIF1 Mask */ + +#define PWM_PIIR_PWMDIF0_Pos 8 /*!< PWM_T::PIIR: PWMDIF0 Position */ +#define PWM_PIIR_PWMDIF0_Msk (1ul << PWM_PIIR_PWMDIF0_Pos) /*!< PWM_T::PIIR: PWMDIF0 Mask */ + +#define PWM_PIIR_PWMIF3_Pos 3 /*!< PWM_T::PIIR: PWMIF3 Position */ +#define PWM_PIIR_PWMIF3_Msk (1ul << PWM_PIIR_PWMIF3_Pos) /*!< PWM_T::PIIR: PWMIF3 Mask */ + +#define PWM_PIIR_PWMIF2_Pos 2 /*!< PWM_T::PIIR: PWMIF2 Position */ +#define PWM_PIIR_PWMIF2_Msk (1ul << PWM_PIIR_PWMIF2_Pos) /*!< PWM_T::PIIR: PWMIF2 Mask */ + +#define PWM_PIIR_PWMIF1_Pos 1 /*!< PWM_T::PIIR: PWMIF1 Position */ +#define PWM_PIIR_PWMIF1_Msk (1ul << PWM_PIIR_PWMIF1_Pos) /*!< PWM_T::PIIR: PWMIF1 Mask */ + +#define PWM_PIIR_PWMIF0_Pos 0 /*!< PWM_T::PIIR: PWMIF0 Position */ +#define PWM_PIIR_PWMIF0_Msk (1ul << PWM_PIIR_PWMIF0_Pos) /*!< PWM_T::PIIR: PWMIF0 Mask */ + +/* PWM CCR0 Bit Field Definitions */ +#define PWM_CCR0_CFLRI1_Pos 23 /*!< PWM_T::CCR0: CFLRI1 Position */ +#define PWM_CCR0_CFLRI1_Msk (1ul << PWM_CCR0_CFLRI1_Pos) /*!< PWM_T::CCR0: CFLRI1 Mask */ + +#define PWM_CCR0_CRLRI1_Pos 22 /*!< PWM_T::CCR0: CRLRI1 Position */ +#define PWM_CCR0_CRLRI1_Msk (1ul << PWM_CCR0_CRLRI1_Pos) /*!< PWM_T::CCR0: CRLRI1 Mask */ + +#define PWM_CCR0_CAPIF1_Pos 20 /*!< PWM_T::CCR0: CAPIF1 Position */ +#define PWM_CCR0_CAPIF1_Msk (1ul << PWM_CCR0_CAPIF1_Pos) /*!< PWM_T::CCR0: CAPIF1 Mask */ + +#define PWM_CCR0_CAPCH1EN_Pos 19 /*!< PWM_T::CCR0: CAPCH1EN Position */ +#define PWM_CCR0_CAPCH1EN_Msk (1ul << PWM_CCR0_CAPCH1EN_Pos) /*!< PWM_T::CCR0: CAPCH1EN Mask */ + +#define PWM_CCR0_CFL_IE1_Pos 18 /*!< PWM_T::CCR0: CFL_IE1 Position */ +#define PWM_CCR0_CFL_IE1_Msk (1ul << PWM_CCR0_CFL_IE1_Pos) /*!< PWM_T::CCR0: CFL_IE1 Mask */ + +#define PWM_CCR0_CRL_IE1_Pos 17 /*!< PWM_T::CCR0: CRL_IE1 Position */ +#define PWM_CCR0_CRL_IE1_Msk (1ul << PWM_CCR0_CRL_IE1_Pos) /*!< PWM_T::CCR0: CRL_IE1 Mask */ + +#define PWM_CCR0_INV1_Pos 16 /*!< PWM_T::CCR0: INV1 Position */ +#define PWM_CCR0_INV1_Msk (1ul << PWM_CCR0_INV1_Pos) /*!< PWM_T::CCR0: INV1 Mask */ + +#define PWM_CCR0_CFLRI0_Pos 7 /*!< PWM_T::CCR0: CFLRI0 Position */ +#define PWM_CCR0_CFLRI0_Msk (1ul << PWM_CCR0_CFLRI0_Pos) /*!< PWM_T::CCR0: CFLRI0 Mask */ + +#define PWM_CCR0_CRLRI0_Pos 6 /*!< PWM_T::CCR0: CRLRI0 Position */ +#define PWM_CCR0_CRLRI0_Msk (1ul << PWM_CCR0_CRLRI0_Pos) /*!< PWM_T::CCR0: CRLRI0 Mask */ + +#define PWM_CCR0_CAPIF0_Pos 4 /*!< PWM_T::CCR0: CAPIF0 Position */ +#define PWM_CCR0_CAPIF0_Msk (1ul << PWM_CCR0_CAPIF0_Pos) /*!< PWM_T::CCR0: CAPIF0 Mask */ + +#define PWM_CCR0_CAPCH0EN_Pos 3 /*!< PWM_T::CCR0: CAPCH0EN Position */ +#define PWM_CCR0_CAPCH0EN_Msk (1ul << PWM_CCR0_CAPCH0EN_Pos) /*!< PWM_T::CCR0: CAPCH0EN Mask */ + +#define PWM_CCR0_CFL_IE0_Pos 2 /*!< PWM_T::CCR0: CFL_IE0 Position */ +#define PWM_CCR0_CFL_IE0_Msk (1ul << PWM_CCR0_CFL_IE0_Pos) /*!< PWM_T::CCR0: CFL_IE0 Mask */ + +#define PWM_CCR0_CRL_IE0_Pos 1 /*!< PWM_T::CCR0: CRL_IE0 Position */ +#define PWM_CCR0_CRL_IE0_Msk (1ul << PWM_CCR0_CRL_IE0_Pos) /*!< PWM_T::CCR0: CRL_IE0 Mask */ + +#define PWM_CCR0_INV0_Pos 0 /*!< PWM_T::CCR0: INV0 Position */ +#define PWM_CCR0_INV0_Msk (1ul << PWM_CCR0_INV0_Pos) /*!< PWM_T::CCR0: INV0 Mask */ + +/* PWM CCR2 Bit Field Definitions */ +#define PWM_CCR2_CFLRI3_Pos 23 /*!< PWM_T::CCR2: CFLRI3 Position */ +#define PWM_CCR2_CFLRI3_Msk (1ul << PWM_CCR2_CFLRI3_Pos) /*!< PWM_T::CCR2: CFLRI3 Mask */ + +#define PWM_CCR2_CRLRI3_Pos 22 /*!< PWM_T::CCR2: CRLRI3 Position */ +#define PWM_CCR2_CRLRI3_Msk (1ul << PWM_CCR2_CRLRI3_Pos) /*!< PWM_T::CCR2: CRLRI3 Mask */ + +#define PWM_CCR2_CAPIF3_Pos 20 /*!< PWM_T::CCR2: CAPIF3 Position */ +#define PWM_CCR2_CAPIF3_Msk (1ul << PWM_CCR2_CAPIF3_Pos) /*!< PWM_T::CCR2: CAPIF3 Mask */ + +#define PWM_CCR2_CAPCH3EN_Pos 19 /*!< PWM_T::CCR2: CAPCH3EN Position */ +#define PWM_CCR2_CAPCH3EN_Msk (1ul << PWM_CCR2_CAPCH3EN_Pos) /*!< PWM_T::CCR2: CAPCH3EN Mask */ + +#define PWM_CCR2_CFL_IE3_Pos 18 /*!< PWM_T::CCR2: CFL_IE3 Position */ +#define PWM_CCR2_CFL_IE3_Msk (1ul << PWM_CCR2_CFL_IE3_Pos) /*!< PWM_T::CCR2: CFL_IE3 Mask */ + +#define PWM_CCR2_CRL_IE3_Pos 17 /*!< PWM_T::CCR2: CRL_IE3 Position */ +#define PWM_CCR2_CRL_IE3_Msk (1ul << PWM_CCR2_CRL_IE3_Pos) /*!< PWM_T::CCR2: CRL_IE3 Mask */ + +#define PWM_CCR2_INV3_Pos 16 /*!< PWM_T::CCR2: INV3 Position */ +#define PWM_CCR2_INV3_Msk (1ul << PWM_CCR2_INV3_Pos) /*!< PWM_T::CCR2: INV3 Mask */ + +#define PWM_CCR2_CFLRI2_Pos 7 /*!< PWM_T::CCR2: CFLRI2 Position */ +#define PWM_CCR2_CFLRI2_Msk (1ul << PWM_CCR2_CFLRI2_Pos) /*!< PWM_T::CCR2: CFLRI2 Mask */ + +#define PWM_CCR2_CRLRI2_Pos 6 /*!< PWM_T::CCR2: CRLRI2 Position */ +#define PWM_CCR2_CRLRI2_Msk (1ul << PWM_CCR2_CRLRI2_Pos) /*!< PWM_T::CCR2: CRLRI2 Mask */ + +#define PWM_CCR2_CAPIF2_Pos 4 /*!< PWM_T::CCR2: CAPIF2 Position */ +#define PWM_CCR2_CAPIF2_Msk (1ul << PWM_CCR2_CAPIF2_Pos) /*!< PWM_T::CCR2: CAPIF2 Mask */ + +#define PWM_CCR2_CAPCH2EN_Pos 3 /*!< PWM_T::CCR2: CAPCH2EN Position */ +#define PWM_CCR2_CAPCH2EN_Msk (1ul << PWM_CCR2_CAPCH2EN_Pos) /*!< PWM_T::CCR2: CAPCH2EN Mask */ + +#define PWM_CCR2_CFL_IE2_Pos 2 /*!< PWM_T::CCR2: CFL_IE2 Position */ +#define PWM_CCR2_CFL_IE2_Msk (1ul << PWM_CCR2_CFL_IE2_Pos) /*!< PWM_T::CCR2: CFL_IE2 Mask */ + +#define PWM_CCR2_CRL_IE2_Pos 1 /*!< PWM_T::CCR2: CRL_IE2 Position */ +#define PWM_CCR2_CRL_IE2_Msk (1ul << PWM_CCR2_CRL_IE2_Pos) /*!< PWM_T::CCR2: CRL_IE2 Mask */ + +#define PWM_CCR2_INV2_Pos 0 /*!< PWM_T::CCR2: INV2 Position */ +#define PWM_CCR2_INV2_Msk (1ul << PWM_CCR2_INV2_Pos) /*!< PWM_T::CCR2: INV2 Mask */ + +/* PWM CRLR Bit Field Definitions */ +#define PWM_CRLR_CRLR_Pos 0 /*!< PWM_T::CRLR0: CRLR Position */ +#define PWM_CRLR_CRLR_Msk (0xFFFFul << PWM_CRLR_CRLR_Pos) /*!< PWM_T::CRLR0: CRLR Mask */ + +/* PWM CFLR Bit Field Definitions */ +#define PWM_CFLR_CFLR_Pos 0 /*!< PWM_T::CFLR0: CFLR Position */ +#define PWM_CFLR_CFLR_Msk (0xFFFFul << PWM_CFLR_CFLR_Pos) /*!< PWM_T::CFLR0: CFLR Mask */ + +/* PWM CAPENR Bit Field Definitions */ +#define PWM_CAPENR_CINEN3_Pos 3 /*!< PWM_T::CAPENR: CINEN3 Position */ +#define PWM_CAPENR_CINEN3_Msk (1ul << PWM_CAPENR_CINEN3_Pos) /*!< PWM_T::CAPENR: CINEN3 Mask */ + +#define PWM_CAPENR_CINEN2_Pos 2 /*!< PWM_T::CAPENR: CINEN2 Position */ +#define PWM_CAPENR_CINEN2_Msk (1ul << PWM_CAPENR_CINEN2_Pos) /*!< PWM_T::CAPENR: CINEN2 Mask */ + +#define PWM_CAPENR_CINEN1_Pos 1 /*!< PWM_T::CAPENR: CINEN1 Position */ +#define PWM_CAPENR_CINEN1_Msk (1ul << PWM_CAPENR_CINEN1_Pos) /*!< PWM_T::CAPENR: CINEN1 Mask */ + +#define PWM_CAPENR_CINEN0_Pos 0 /*!< PWM_T::CAPENR: CINEN0 Position */ +#define PWM_CAPENR_CINEN0_Msk (1ul << PWM_CAPENR_CINEN0_Pos) /*!< PWM_T::CAPENR: CINEN0 Mask */ + +/* PWM POE Bit Field Definitions */ +#define PWM_POE_POE3_Pos 3 /*!< PWM_T::POE: POE3 Position */ +#define PWM_POE_POE3_Msk (1ul << PWM_POE_POE3_Pos) /*!< PWM_T::POE: POE3 Mask */ + +#define PWM_POE_POE2_Pos 2 /*!< PWM_T::POE: POE2 Position */ +#define PWM_POE_POE2_Msk (1ul << PWM_POE_POE2_Pos) /*!< PWM_T::POE: POE2 Mask */ + +#define PWM_POE_POE1_Pos 1 /*!< PWM_T::POE: POE1 Position */ +#define PWM_POE_POE1_Msk (1ul << PWM_POE_POE1_Pos) /*!< PWM_T::POE: POE1 Mask */ + +#define PWM_POE_POE0_Pos 0 /*!< PWM_T::POE: POE0 Position */ +#define PWM_POE_POE0_Msk (1ul << PWM_POE_POE0_Pos) /*!< PWM_T::POE: POE0 Mask */ + +/* PWM TCON Bit Field Definitions */ + +#define PWM_TCON_PWM3TEN_Pos 3 /*!< PWM_T::TCON: PWM3TEN Position */ +#define PWM_TCON_PWM3TEN_Msk (1ul << PWM_TCON_PWM3TEN_Pos) /*!< PWM_T::TCON: PWM3TEN Mask */ + +#define PWM_TCON_PWM2TEN_Pos 2 /*!< PWM_T::TCON: PWM2TEN Position */ +#define PWM_TCON_PWM2TEN_Msk (1ul << PWM_TCON_PWM2TEN_Pos) /*!< PWM_T::TCON: PWM2TEN Mask */ + +#define PWM_TCON_PWM1TEN_Pos 1 /*!< PWM_T::TCON: PWM1TEN Position */ +#define PWM_TCON_PWM1TEN_Msk (1ul << PWM_TCON_PWM1TEN_Pos) /*!< PWM_T::TCON: PWM1TEN Mask */ + +#define PWM_TCON_PWM0TEN_Pos 0 /*!< PWM_T::TCON: PWM0TEN Position */ +#define PWM_TCON_PWM0TEN_Msk (1ul << PWM_TCON_PWM0TEN_Pos) /*!< PWM_T::TCON: PWM0TEN Mask */ + +/* PWM TSTATUS Bit Field Definitions */ + +#define PWM_TSTATUS_PWM3TF_Pos 3 /*!< PWM_T::TSTATUS: PWM3TF Position */ +#define PWM_TSTATUS_PWM3TF_Msk (1ul << PWM_TSTATUS_PWM3TF_Pos) /*!< PWM_T::TSTATUS: PWM3TF Mask */ + +#define PWM_TSTATUS_PWM2TF_Pos 2 /*!< PWM_T::TSTATUS: PWM2TF Position */ +#define PWM_TSTATUS_PWM2TF_Msk (1ul << PWM_TSTATUS_PWM2TF_Pos) /*!< PWM_T::TSTATUS: PWM2TF Mask */ + +#define PWM_TSTATUS_PWM1TF_Pos 1 /*!< PWM_T::TSTATUS: PWM1TF Position */ +#define PWM_TSTATUS_PWM1TF_Msk (1ul << PWM_TSTATUS_PWM1TF_Pos) /*!< PWM_T::TSTATUS: PWM1TF Mask */ + +#define PWM_TSTATUS_PWM0TF_Pos 0 /*!< PWM_T::TSTATUS: PWM0TF Position */ +#define PWM_TSTATUS_PWM0TF_Msk (1ul << PWM_TSTATUS_PWM0TF_Pos) /*!< PWM_T::TSTATUS: PWM0TF Mask */ + +/* PWM SYNCBUSY0 Bit Field Definitions */ +#define PWM_SYNCBUSY0_S_BUSY_Pos 0 /*!< PWM_T::SYNCBUSY0: S_BUSY Position */ +#define PWM_SYNCBUSY0_S_BUSY_Msk (1ul << PWM_SYNCBUSY0_S_BUSY_Pos) /*!< PWM_T::SYNCBUSY0: S_BUSY Mask */ + +/* PWM SYNCBUSY1 Bit Field Definitions */ +#define PWM_SYNCBUSY1_S_BUSY_Pos 0 /*!< PWM_T::SYNCBUSY1: S_BUSY Position */ +#define PWM_SYNCBUSY1_S_BUSY_Msk (1ul << PWM_SYNCBUSY1_S_BUSY_Pos) /*!< PWM_T::SYNCBUSY1: S_BUSY Mask */ + +/* PWM SYNCBUSY2 Bit Field Definitions */ +#define PWM_SYNCBUSY2_S_BUSY_Pos 0 /*!< PWM_T::SYNCBUSY2: S_BUSY Position */ +#define PWM_SYNCBUSY2_S_BUSY_Msk (1ul << PWM_SYNCBUSY2_S_BUSY_Pos) /*!< PWM_T::SYNCBUSY2: S_BUSY Mask */ + +/* PWM SYNCBUSY3 Bit Field Definitions */ +#define PWM_SYNCBUSY3_S_BUSY_Pos 0 /*!< PWM_T::SYNCBUSY3: S_BUSY Position */ +#define PWM_SYNCBUSY3_S_BUSY_Msk (1ul << PWM_SYNCBUSY3_S_BUSY_Pos) /*!< PWM_T::SYNCBUSY3: S_BUSY Mask */ +/*@}*/ /* end of group PWM_CONST */ +/*@}*/ /* end of group PWM */ + + + + + +/*---------------------- Real Time Clock Controller -------------------------*/ +/** + @addtogroup RTC Real Time Clock Controller (RTC) + Memory Mapped Structure for RTC Controller +@{ */ + + +typedef struct +{ + + +/** + * @var RTC_T::INIR + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIR0_Active|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIR |RTC Initiation + * | | |When RTC block is powered on, RTC is at reset state. + * | | |User has to write a number (0xa5eb1357) to INIR to make RTC leaving reset state. + * | | |Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIR is a write-only field and read value will be always 0. + * @var RTC_T::AER + * Offset: 0x04 RTC Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |AER |RTC Register Access Enable Password (Write Only) + * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clocks. + * |[16] |ENF |RTC Register Access Enable Flag (Read Only) + * | | |0 = RTC register read/write access Disabled. + * | | |1 = RTC register read/write access Enabled. + * | | |This bit will be set after AER[15:0] is load a 0xA965, and will be cleared automatically + * | | |after 1024 RTC clocks. + * @var RTC_T::FCR + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRACTION |Fraction Part + * | | |Formula = (fraction part of detected value) x 60. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[11:8] |INTEGER |Integer Part + * @var RTC_T::TLR + * Offset: 0x0C Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |1SEC |1-Sec Time Digit (0~9) + * |[6:4] |10SEC |10-Sec Time Digit (0~5) + * |[11:8] |1MIN |1-Min Time Digit (0~9) + * |[14:12] |10MIN |10-Min Time Digit (0~5) + * |[19:16] |1HR |1-Hour Time Digit (0~9) + * |[21:20] |10HR |10-Hour Time Digit (0~2) + * @var RTC_T::CLR + * Offset: 0x10 Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |1DAY |1-Day Calendar Digit (0~9) + * |[5:4] |10DAY |10-Day Calendar Digit (0~3) + * |[11:8] |1MON |1-Month Calendar Digit (0~9) + * |[12] |10MON |10-Month Calendar Digit (0~1) + * |[19:16] |1YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |10YEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::TSSR + * Offset: 0x14 Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24H_12H |24-Hour / 12-Hour Time Scale Selection + * | | |It indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale. + * | | |0 = 24-hour time scale selected. + * | | |1 = 24-hour time scale selected. + * @var RTC_T::DWR + * Offset: 0x18 Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |DWR |Day Of The Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TAR + * Offset: 0x1C Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |1SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |10SEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |1MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |10MIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |1HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |10HR |10-Hour Time Digit of Alarm Setting (0~2) + * @var RTC_T::CAR + * Offset: 0x20 Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |1DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |10DAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |1MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |10MON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |1YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |10YEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LIR + * Offset: 0x24 Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LIR |Leap Year Indication Register (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is a leap year. + * @var RTC_T::RIER + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AIER |Alarm Interrupt Enable + * | | |This bit is used to enable/disable RTC Alarm Interrupt, and generate an interrupt signal if + * | | |AIF (RIIR[0] RTC Alarm Interrupt Flag) is set to 1. + * | | |0 = RTC Alarm Interrupt Disabled. + * | | |1 = RTC Alarm Interrupt Enabled. + * | | |Note: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode + * | | |and RTC Alarm Interrupt signal generated. + * |[1] |TIER |Time Tick Interrupt Enable + * | | |This bit is used to enable/disable RTC Time Tick Interrupt, and generate an interrupt signal + * | | |if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1. + * | | |0 = RTC Time Tick Interrupt Disabled. + * | | |1 = RTC Time Tick Interrupt Enabled. + * | | |Note: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode + * | | |and RTC Time Tick Interrupt signal generated. + * |[2] |SNOOPIER |Snoop Detection Interrupt Enable + * | | |This bit is used to enable/disable RTC Snoop Detection Interrupt, and generate an interrupt + * | | |signal if SNOOPIF (RIIR[2] RTC Snoop Detection Interrupt Flag) is set to 1. + * | | |0 = Snoop detected interrupt Disabled. + * | | |1 = Snoop detected interrupt Enabled. + * | | |Note: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode + * | | |and RTC Snoop Interrupt signal generated. + * @var RTC_T::RIIR + * Offset: 0x2C RTC Interrupt Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AIF |RTC Alarm Interrupt Flag + * | | |When RTC time counters TLR and CLR match the alarm setting time registers TAR and CAR, this + * | | |bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled AIER + * | | |(RIER[0]) is set to 1. + * | | |Chip will be wake-up if RTC Alarm Interrupt is enabled when chip is at Power-down mode. + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TIF |RTC Time Tick Interrupt Flag + * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if + * | | |RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1. + * | | |Chip will also be wake-up if RTC Tick Interrupt is enabled and this bit is set to 1 when + * | | |chip is running at Power-down mode. + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear to clear this bit. + * |[2] |SNOOPIF |Snoop Detection Interrupt Flag + * | | |When snooper pin transition event is detected, this bit is set to 1 and an interrupt is + * | | |generated if Snoop Detection Interrupt enabled SNOOPIER (RIER[2]) is set to1. + * | | |Chip will be wake-up from Power-down mode if Snoop Detection Interrupt is enabled. + * | | |0 = No snoop event is detected. + * | | |1 = Snoop event is detected. + * | | |Note: Write 1 to clear this bit. + * @var RTC_T::TTR + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TTR |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/28 second. + * | | |Note: This register can be read back after the RTC register access enable bit ENF (AER[16]) + * | | |is active. + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SNOOPEN |Snoop Detection Enable + * | | |0 = Snoop detection function Disabled. + * | | |1 = Snoop detection function Enabled. + * |[1] |SNOOPLEVEL|Snoop Detection Level Selection + * | | |This bit controls snoop detect event is high level/rising edge or low level/falling edge. + * | | |0 = Low level/Falling edge detection. + * | | |1 = High level/Rising edge detection. + * |[2] |SPREN |SPR Register Enable + * | | |0 = Spare register is Disabled. + * | | |1 = Spare register is Enabled. + * | | |Note: When spare register is disabled, RTC SPR0 ~ SPR19 cannot be accessed. + * |[3] |SNOOPMODE |Snoop Detection Mode Selection + * | | |This bit controls snoop detect event is edge or level detection. + * | | |0 = Level detection. + * | | |1 = Edge detection. + * |[5] |SPRCFLG |Spare Register Clear Flag + * | | |This bit indicates if the SPR0 ~ SPR19 content is cleared when snoop specify event is + * | | |detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Note: Writes 1 to clear this bit. + * |[7] |SPRRDY |SPR Register Ready + * | | |This bit indicates if the registers SPRCTL, SPR0 ~ SPR19 are ready to be accessed. + * | | |After user writing registers SPRCTL, SPR0 ~ SPR19, read this bit to check if these registers + * | | |are updated done is necessary. + * | | |0 = SPRCTL, SPR0 ~ SPR19 updating is in progress. + * | | |1 = SPRCTL, SPR0 ~ SPR19 are updated done and ready to be accessed. + * | | |Note: This bit is read only and any write to it won't take any effect. + * @var RTC_T::SPR + * Offset: 0x40 RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |SPARE Register + * | | |This field is used to store back-up information defined by software. + * | | |This field will be cleared by hardware automatically once a snooper pin event is detected. + * | | |Before store back-up information in to SPARE register, software should write 0xA965 to AER + * | | |to make sure register read/write enable. + */ + + __IO uint32_t INIR; /* Offset: 0x00 RTC Initiation Register */ + __IO uint32_t AER; /* Offset: 0x04 RTC Access Enable Register */ + __IO uint32_t FCR; /* Offset: 0x08 RTC Frequency Compensation Register */ + __IO uint32_t TLR; /* Offset: 0x0C Time Loading Register */ + __IO uint32_t CLR; /* Offset: 0x10 Calendar Loading Register */ + __IO uint32_t TSSR; /* Offset: 0x14 Time Scale Selection Register */ + __IO uint32_t DWR; /* Offset: 0x18 Day of the Week Register */ + __IO uint32_t TAR; /* Offset: 0x1C Time Alarm Register */ + __IO uint32_t CAR; /* Offset: 0x20 Calendar Alarm Register */ + __I uint32_t LIR; /* Offset: 0x24 Leap Year Indicator Register */ + __IO uint32_t RIER; /* Offset: 0x28 RTC Interrupt Enable Register */ + __IO uint32_t RIIR; /* Offset: 0x2C RTC Interrupt Indicator Register */ + __IO uint32_t TTR; /* Offset: 0x30 RTC Time Tick Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /* Offset: 0x40 RTC Spare Register 0 ~ 19 */ + +} RTC_T; + + + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller +@{ */ + +/* RTC INIR Bit Field Definitions */ +#define RTC_INIR_INIR_Pos 0 /*!< RTC_T::INIR: INIR Position */ +#define RTC_INIR_INIR_Msk (0xFFFFFFFFul << RTC_INIR_INIR_Pos) /*!< RTC_T::INIR: INIR Mask */ + +#define RTC_INIR_ACTIVE_Pos 0 /*!< RTC_T::INIR: ACTIVE Position */ +#define RTC_INIR_ACTIVE_Msk (1ul << RTC_INIR_ACTIVE_Pos) /*!< RTC_T::INIR: ACTIVE Mask */ + +/* RTC AER Bit Field Definitions */ +#define RTC_AER_ENF_Pos 16 /*!< RTC_T::AER: ENF Position */ +#define RTC_AER_ENF_Msk (1ul << RTC_AER_ENF_Pos) /*!< RTC_T::AER: ENF Mask */ + +#define RTC_AER_AER_Pos 0 /*!< RTC_T::AER: AER Position */ +#define RTC_AER_AER_Msk (0xFFFFul << RTC_AER_AER_Pos) /*!< RTC_T::AER: AER Mask */ + +/* RTC FCR Bit Field Definitions */ +#define RTC_FCR_INTEGER_Pos 8 /*!< RTC_T::FCR: INTEGER Position */ +#define RTC_FCR_INTEGER_Msk (0xFul << RTC_FCR_INTEGER_Pos) /*!< RTC_T::FCR: INTEGER Mask */ + +#define RTC_FCR_FRACTION_Pos 0 /*!< RTC_T::FCR: FRACTION Position */ +#define RTC_FCR_FRACTION_Msk (0x3Ful << RTC_FCR_FRACTION_Pos) /*!< RTC_T::FCR: FRACTION Mask */ + +/* RTC TLR Bit Field Definitions */ +#define RTC_TLR_10HR_Pos 20 /*!< RTC_T::TLR: 10HR Position */ +#define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos) /*!< RTC_T::TLR: 10HR Mask */ + +#define RTC_TLR_1HR_Pos 16 /*!< RTC_T::TLR: 1HR Position */ +#define RTC_TLR_1HR_Msk (0xFul << RTC_TLR_1HR_Pos) /*!< RTC_T::TLR: 1HR Mask */ + +#define RTC_TLR_10MIN_Pos 12 /*!< RTC_T::TLR: 10MIN Position */ +#define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos) /*!< RTC_T::TLR: 10MIN Mask */ + +#define RTC_TLR_1MIN_Pos 8 /*!< RTC_T::TLR: 1MIN Position */ +#define RTC_TLR_1MIN_Msk (0xFul << RTC_TLR_1MIN_Pos) /*!< RTC_T::TLR: 1MIN Mask */ + +#define RTC_TLR_10SEC_Pos 4 /*!< RTC_T::TLR: 10SEC Position */ +#define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos) /*!< RTC_T::TLR: 10SEC Mask */ + +#define RTC_TLR_1SEC_Pos 0 /*!< RTC_T::TLR: 1SEC Position */ +#define RTC_TLR_1SEC_Msk (0xFul << RTC_TLR_1SEC_Pos) /*!< RTC_T::TLR: 1SEC Mask */ + +/* RTC CLR Bit Field Definitions */ +#define RTC_CLR_10YEAR_Pos 20 /*!< RTC_T::CLR: 10YEAR Position */ +#define RTC_CLR_10YEAR_Msk (0xFul << RTC_CLR_10YEAR_Pos) /*!< RTC_T::CLR: 10YEAR Mask */ + +#define RTC_CLR_1YEAR_Pos 16 /*!< RTC_T::CLR: 1YEAR Position */ +#define RTC_CLR_1YEAR_Msk (0xFul << RTC_CLR_1YEAR_Pos) /*!< RTC_T::CLR: 1YEAR Mask */ + +#define RTC_CLR_10MON_Pos 12 /*!< RTC_T::CLR: 10MON Position */ +#define RTC_CLR_10MON_Msk (1ul << RTC_CLR_10MON_Pos) /*!< RTC_T::CLR: 10MON Mask */ + +#define RTC_CLR_1MON_Pos 8 /*!< RTC_T::CLR: 1MON Position */ +#define RTC_CLR_1MON_Msk (0xFul << RTC_CLR_1MON_Pos) /*!< RTC_T::CLR: 1MON Mask */ + +#define RTC_CLR_10DAY_Pos 4 /*!< RTC_T::CLR: 10DAY Position */ +#define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos) /*!< RTC_T::CLR: 10DAY Mask */ + +#define RTC_CLR_1DAY_Pos 0 /*!< RTC_T::CLR: 1DAY Position */ +#define RTC_CLR_1DAY_Msk (0xFul << RTC_CLR_1DAY_Pos) /*!< RTC_T::CLR: 1DAY Mask */ + +/* RTC TSSR Bit Field Definitions */ +#define RTC_TSSR_24H_12H_Pos 0 /*!< RTC_T::TSSR: 24H_12H Position */ +#define RTC_TSSR_24H_12H_Msk (1ul << RTC_TSSR_24H_12H_Pos) /*!< RTC_T::TSSR: 24H_12H Mask */ + +/* RTC DWR Bit Field Definitions */ +#define RTC_DWR_DWR_Pos 0 /*!< RTC_T::DWR: DWR Position */ +#define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos) /*!< RTC_T::DWR: DWR Mask */ + +/* RTC TAR Bit Field Definitions */ +#define RTC_TAR_10HR_Pos 20 /*!< RTC_T::TAR: 10HR Position */ +#define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos) /*!< RTC_T::TAR: 10HR Mask */ + +#define RTC_TAR_1HR_Pos 16 /*!< RTC_T::TAR: 1HR Position */ +#define RTC_TAR_1HR_Msk (0xFul << RTC_TAR_1HR_Pos) /*!< RTC_T::TAR: 1HR Mask */ + +#define RTC_TAR_10MIN_Pos 12 /*!< RTC_T::TAR: 10MIN Position */ +#define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos) /*!< RTC_T::TAR: 10MIN Mask */ + +#define RTC_TAR_1MIN_Pos 8 /*!< RTC_T::TAR: 1MIN Position */ +#define RTC_TAR_1MIN_Msk (0xFul << RTC_TAR_1MIN_Pos) /*!< RTC_T::TAR: 1MIN Mask */ + +#define RTC_TAR_10SEC_Pos 4 /*!< RTC_T::TAR: 10SEC Position */ +#define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos) /*!< RTC_T::TAR: 10SEC Mask */ + +#define RTC_TAR_1SEC_Pos 0 /*!< RTC_T::TAR: 1SEC Position */ +#define RTC_TAR_1SEC_Msk (0xFul << RTC_TAR_1SEC_Pos) /*!< RTC_T::TAR: 1SEC Mask */ + +/* RTC CAR Bit Field Definitions */ +#define RTC_CAR_10YEAR_Pos 20 /*!< RTC_T::CAR: 10YEAR Position */ +#define RTC_CAR_10YEAR_Msk (0xFul << RTC_CAR_10YEAR_Pos) /*!< RTC_T::CAR: 10YEAR Mask */ + +#define RTC_CAR_1YEAR_Pos 16 /*!< RTC_T::CAR: 1YEAR Position */ +#define RTC_CAR_1YEAR_Msk (0xFul << RTC_CAR_1YEAR_Pos) /*!< RTC_T::CAR: 1YEAR Mask */ + +#define RTC_CAR_10MON_Pos 12 /*!< RTC_T::CAR: 10MON Position */ +#define RTC_CAR_10MON_Msk (1ul << RTC_CAR_10MON_Pos) /*!< RTC_T::CAR: 10MON Mask */ + +#define RTC_CAR_1MON_Pos 8 /*!< RTC_T::CAR: 1MON Position */ +#define RTC_CAR_1MON_Msk (0xFul << RTC_CAR_1MON_Pos) /*!< RTC_T::CAR: 1MON Mask */ + +#define RTC_CAR_10DAY_Pos 4 /*!< RTC_T::CAR: 10DAY Position */ +#define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos) /*!< RTC_T::CAR: 10DAY Mask */ + +#define RTC_CAR_1DAY_Pos 0 /*!< RTC_T::CAR: 1DAY Position */ +#define RTC_CAR_1DAY_Msk (0xFul << RTC_CAR_1DAY_Pos) /*!< RTC_T::CAR: 1DAY Mask */ + +/* RTC LIR Bit Field Definitions */ +#define RTC_LIR_LIR_Pos 0 /*!< RTC_T::LIR: LIR Position */ +#define RTC_LIR_LIR_Msk (1ul << RTC_LIR_LIR_Pos) /*!< RTC_T::LIR: LIR Mask */ + +/* RTC RIER Bit Field Definitions */ +#define RTC_RIER_SNOOPIER_Pos 2 /*!< RTC_T::RIER: SNOOPIER Position */ +#define RTC_RIER_SNOOPIER_Msk (1ul << RTC_RIER_SNOOPIER_Pos) /*!< RTC_T::RIER: SNOOPIER Mask */ + +#define RTC_RIER_TIER_Pos 1 /*!< RTC_T::RIER: TIER Position */ +#define RTC_RIER_TIER_Msk (1ul << RTC_RIER_TIER_Pos) /*!< RTC_T::RIER: TIER Mask */ + +#define RTC_RIER_AIER_Pos 0 /*!< RTC_T::RIER: AIER Position */ +#define RTC_RIER_AIER_Msk (1ul << RTC_RIER_AIER_Pos) /*!< RTC_T::RIER: AIER Mask */ + +/* RTC RIIR Bit Field Definitions */ +#define RTC_RIIR_SNOOPIF_Pos 2 /*!< RTC_T::RIIR: SNOOPIF Position */ +#define RTC_RIIR_SNOOPIF_Msk (1ul << RTC_RIIR_SNOOPIF_Pos) /*!< RTC_T::RIIR: SNOOPIF Mask */ + +#define RTC_RIIR_TIF_Pos 1 /*!< RTC_T::RIIR: TIF Position */ +#define RTC_RIIR_TIF_Msk (1ul << RTC_RIIR_TIF_Pos) /*!< RTC_T::RIIR: TIF Mask */ + +#define RTC_RIIR_AIF_Pos 0 /*!< RTC_T::RIIR: AIF Position */ +#define RTC_RIIR_AIF_Msk (1ul << RTC_RIIR_AIF_Pos) /*!< RTC_T::RIIR: AIF Mask */ + +/* RTC TTR Bit Field Definitions */ +#define RTC_TTR_TTR_Pos 0 /*!< RTC_T::TTR: TTR Position */ +#define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos) /*!< RTC_T::TTR: TTR Mask */ + +/* RTC SPRCTL Bit Field Definitions */ +#define RTC_SPRCTL_SPRRDY_Pos 7 /*!< RTC_T::SPRCTL: SPRRDY Position */ +#define RTC_SPRCTL_SPRRDY_Msk (1ul << RTC_SPRCTL_SPRRDY_Pos) /*!< RTC_T::SPRCTL: SPRRDY Mask */ + +#define RTC_SPRCTL_SPRCFLG_Pos 5 /*!< RTC_T::SPRCTL: SPRCFLG Position */ +#define RTC_SPRCTL_SPRCFLG_Msk (1ul << RTC_SPRCTL_SPRCFLG_Pos) /*!< RTC_T::SPRCTL: SPRCFLG Mask */ + +#define RTC_SPRCTL_SNOOPMODE_Pos 3 /*!< RTC_T::SPRCTL: SNOOPMODE Position */ +#define RTC_SPRCTL_SNOOPMODE_Msk (1ul << RTC_SPRCTL_SNOOPMODE_Pos) /*!< RTC_T::SPRCTL: SNOOPMODE Mask */ + +#define RTC_SPRCTL_SPREN_Pos 2 /*!< RTC_T::SPRCTL: SPREN Position */ +#define RTC_SPRCTL_SPREN_Msk (1ul << RTC_SPRCTL_SPREN_Pos) /*!< RTC_T::SPRCTL: SPREN Mask */ + +#define RTC_SPRCTL_SNOOPLEVEL_Pos 1 /*!< RTC_T::SPRCTL: SNOOPLEVEL Position */ +#define RTC_SPRCTL_SNOOPLEVEL_Msk (1ul << RTC_SPRCTL_SNOOPLEVEL_Pos) /*!< RTC_T::SPRCTL: SNOOPLEVEL Mask */ + +#define RTC_SPRCTL_SNOOPEN_Pos 0 /*!< RTC_T::SPRCTL: SNOOPEN Position */ +#define RTC_SPRCTL_SNOOPEN_Msk (1ul << RTC_SPRCTL_SNOOPEN_Pos) /*!< RTC_T::SPRCTL: SNOOPEN Mask */ +/*@}*/ /* end of group RTC_CONST */ +/*@}*/ /* end of group RTC */ + + + + +/*---------------------- Smart Card Host Interface Controller -------------------------*/ +/** + @addtogroup SC Smart Card Host Interface Controller (SC) + Memory Mapped Structure for SC Controller +@{ */ + + +typedef struct +{ + + + /** + * @var SC_T::RBR + * Offset: 0x00 SC Receiving Buffer Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RBR |Receiving Buffer + * | | |By reading RBR, the SC will return an 8-bit received data. + * @var SC_T::THR + * Offset: 0x00 SC Transmit Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |THR |Transmit Holding Buffer + * | | |By writing data to THR, the SC will send out an 8-bit data. + * | | |Note: If SC_CEN(SC_CTL[0]) is not enabled, THR cannot be programmed. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC_CEN |SC Engine Enable Control + * | | |Set this bit to 1 to enable SC operation. + * | | |If this bit is cleared, SC will force all transition to IDLE state. + * |[1] |DIS_RX |RX Transition Disable Control + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note: + * | | |If AUTO_CON_EN (SC_CTL[3])is enabled, these fields must be ignored. + * |[2] |DIS_TX |TX Transition Disable Control + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTO_CON_EN|Auto Convention Enable Control + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |When hardware receives TS in answer to reset state and the TS is direct convention, + * | | |CON_SEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse + * | | |convention, and CON_SEL (SC_CTL[5:4]) will be set to 11. + * | | |If software enables auto convention function, the setting step must be done before Answer to + * | | |Reset state and the first data must be 0x3B or 0x3F. + * | | |After hardware received first data and stored it at buffer, hardware will decided the + * | | |convention and change the CON_SEL (SC_CTL[5:4]) bits automatically. + * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR (if + * | | |ACON_ERR IE (SC_IER[10]) = 1 to CPU. + * |[5:4] |CON_SEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: + * | | |If AUTO_CON_EN(SC_CTL[3]) enabled, this fields are ignored. + * |[7:6] |RX_FTRI_LEV|Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be + * | | |set (if IER [RDA_IEN] is enabled, an interrupt will be generated). + * | | |00 = INTR_RDA Trigger Level with 01 Bytes. + * | | |01 = INTR_RDA Trigger Level with 02 Bytes. + * | | |10 = INTR_RDA Trigger Level with 03 Bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum bit length between the leading edges of two consecutive + * | | |characters between different transfer directions. + * | | |This field indicates the counter for the bit length of block guard time. + * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) + * | | |to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. + * | | |Note: + * | | |The real block guard time is BGT + 1. + * |[14:13] |TMR_SEL |Timer Selection + * | | |00 = All internal timer function Disabled. + * | | |01 = Internal 24 bit timer Enabled. + * | | |Software can configure it by setting SC_TMR0 [23:0]. + * | | |SC_TMR1 and SC_TMR2 will be ignored in this mode. + * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled. + * | | |Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit + * | | |timer by setting SC_TMR1[7:0]. + * | | |SC_TMR2 will be ignored in this mode. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled. + * | | |Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]. + * |[15] |SLEN |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note: + * | | |The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length + * |[18:16] |RX_ERETRY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity + * | | |error has occurred + * | | |Note1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RX_ERETRY_EN enabled. + * | | |The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. + * |[19] |RX_ERETRY_EN|RX Error Retry Enable Control + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: Software must fill in the RX_ERETRY value before enabling this bit. + * |[22:20] |TX_ERETRY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity + * | | |error has occurred. + * | | |Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TX_ERETRY_EN enabled. + * | | |The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value. + * |[23] |TX_ERETRY_EN|TX Error Retry Enable Control + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CD_DEB_SEL|Card Detect De-Bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample + * | | |card removal once per 128 engine clocks. + * | | |01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample + * | | |card removal once per 64 engine clocks. + * | | |10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample + * | | |card removal once per 32 engine clocks. + * | | |11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample + * | | |card removal once per 16 engine clocks. + * |[30] |SYNC |SYNC Flag Indicator + * | | |Due to synchronization, software should check this bit before writing a new value to + * | | |RX_ERETRY and TX_ERETRY. + * | | |0 = synchronizing is completion, user can write new data to RX_ERETRY and TX_ERETRY. + * | | |1 = Last value is synchronizing. + * | | |Note: This bit is read only. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TX_RST |TX Software Reset + * | | |When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will + * | | |be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: + * | | |This bit will be auto cleared after reset is complete. + * |[1] |RX_RST |Rx Software Reset + * | | |When RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will + * | | |be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: + * | | |This bit will be auto cleared after reset is complete. + * |[2] |DACT_EN |Deactivation Sequence Generator Enable Control + * | | |This bit enables SC controller to initiate the card by deactivation sequence + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: + * | | |When the deactivation sequence completed, this bit will be cleared automatically and the + * | | |INIT_IS(SC_ISR[8]) will be set to 1. + * | | |Note2: + * | | |This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). + * | | |So don't fill this bit, TX_RST, and RX_RST at the same time. + * | | |Note3: + * | | |If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACT_EN |Activation Sequence Generator Enable Control + * | | |This bit enables SC controller to initiate the card by activation sequence + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: + * | | |When the activation sequence completed, this bit will be cleared automatically and the + * | | |INIT_IS(SC_ISR[8]) will be set to 1. + * | | |Note2: + * | | |This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill + * | | |this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time. + * | | |Note3: + * | | |If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[4] |WARST_EN |Warm Reset Sequence Generator Enable Control + * | | |This bit enables SC controller to initiate the card by warm reset sequence + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: + * | | |When the warm reset sequence completed, this bit will be cleared automatically and the + * | | |INIT_IS(SC_ISR[8]) will be set to 1. + * | | |Note2: + * | | |This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill + * | | |this bit, TX_RST, and RX_RST at the same time. + * | | |Note3: + * | | |If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[5] |TMR0_SEN |Internal Timer0 Start Enable Control + * | | |This bit enables Timer 0 to start counting. + * | | |Software can fill 0 to stop it and set 1 to reload and count. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: + * | | |This field is used for internal 24 bit timer when TMR_SEL (SC_CTL[14:13]) = 01. + * | | |Note2: + * | | |If the operation mode is not in auto-reload mode (SC_TMR0[26] = 0), this bit will be + * | | |auto-cleared by hardware. + * | | |Note3: + * | | |This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). + * | | |So don't fill this bit, TX_RST and RX_RST at the same time. + * | | |Note4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |TMR1_SEN |Internal Timer1 Start Enable Control + * | | |This bit enables Timer 1 to start counting. + * | | |Software can fill 0 to stop it and set 1 to reload and count. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: + * | | |This field is used for internal 8 bit timer when TMR_SEL(SC_CTL[14:13]) = 10 or + * | | |TMR_SEL(SC_CTL[14:13]) = 11. + * | | |Don't filled TMR1_SEN when TMR_SEL(SC_CTL[14:13]) = 00 or TMR_SEL(SC_CTL[14:13]) = 01. + * | | |Note2: + * | | |If the operation mode is not in auto-reload mode (SC_TMR1[26] = 0), this bit will be + * | | |auto-cleared by hardware. + * | | |Note3: + * | | |This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill + * | | |this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time. + * | | |Note4: + * | | |If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |TMR2_SEN |Internal Timer2 Start Enable Control + * | | |This bit enables Timer 2 to start counting. + * | | |Software can fill 0 to stop it and set 1 to reload and count. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: + * | | |This field is used for internal 8 bit timer when TMR_SEL(SC_CTL[14:13]) = 11. + * | | |Don't filled TMR2_SEN when TMR_SEL(SC_CTL[14:13]) = 00 or TMR_SEL(SC_CTL[14:13]) = 01 or + * | | |TMR_SEL(SC_CTL[14:13]) = 10. + * | | |Note2: + * | | |If the operation mode is not in auto-reload mode (SC_TMR2[26] = 0), this bit will be + * | | |auto-cleared by hardware. + * | | |Note3: + * | | |This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). + * | | |So don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time. + * | | |Note4: + * | | |If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INIT_SEL |Initial Timing Selection + * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or + * | | |deactivation). + * | | |Unit: SC clock + * | | |Activation: refer to SC Activation Sequence in Figure 5-100. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 5-101. + * | | |Deactivation: refer to Deactivation Sequence in Figure 5-102. + * |[12] |RX_BGT_EN |Receiver Block Guard Time Function Enable Control + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |TMR0_ATV |Internal Timer0 Active State (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * |[14] |TMR1_ATV |Internal Timer1 Active State (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * |[15] |TMR2_ATV |Internal Timer2 Active State (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * |[16] |OUTSEL |Smartcard Data Pin Output Mode Selection + * | | |Use this bit to select smartcard data pin (SC_DATA) output mode + * | | |0 = Quasi mode. + * | | |1 = Open-drain mode. + * @var SC_T::EGTR + * Offset: 0x0C SC Extend Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extended Guard Time + * | | |This field indicates the extended guard timer value. + * | | |Note: + * | | |The counter is ETU base and the real extended guard time is EGT. + * @var SC_T::RFTMR + * Offset: 0x10 SC Receive buffer Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver Buffer Time-Out (ETU Base) + * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data + * | | |word. + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by + * | | |reading SC_RBR buffer, a receiver time-out interrupt INT_RTMR will be generated(if + * | | |RTMR_IE(SC_IER[9]) = 1 ). + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5 + * | | |Note2: + * | | |Fill all 0 to this field indicates to disable this function. + * @var SC_T::ETUCR + * Offset: 0x14 SC ETU Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETU_RDIV |ETU Rate Divider + * | | |The field indicates the clock rate divider. + * | | |The real ETU is ETU_RDIV + 1. + * | | |Note: + * | | |Software can configure this field, but this field must be greater than 0x004. + * |[15] |COMPEN_EN |Compensation Mode Enable Control + * | | |This bit enables clock compensation function. + * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, + * | | |where n is the value to be written into the ETU_RDIV . + * | | |0 = Compensation function Disabled. + * | | |1 = Compensation function Enabled. + * @var SC_T::IER + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDA_IE |Receive Data Reach Interrupt Enable Control + * | | |This field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) + * | | |interrupt enable. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TXBE_IE |Transmit Buffer Empty Interrupt Enable Control + * | | |This field is used for transmit buffer empty interrupt enable. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERR_IE |Transfer Error Interrupt Enable Control + * | | |This field is used for transfer error interrupt enable. + * | | |The transfer error states is at SC_SR register which includes receiver break error + * | | |RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_SR[5]), parity error RX_EPA_F(SC_SR[4]), + * | | |receiver buffer overflow error RX_OVER_F(SC_SR[0]), transmit buffer overflow error + * | | |TX_OVER_F(SC_SR[8]), receiver retry over limit error RX_OVER_REERR(SC_SR[22]) and + * | | |transmitter retry over limit error TX_OVER_REERR(SC_SR[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0_IE |Timer0 Interrupt Enable Control + * | | |This field is used to enable TMR0 interrupt enable. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1_IE |Timer1 Interrupt Enable Control + * | | |This field is used to enable the TMR1 interrupt. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2_IE |Timer2 Interrupt Enable Control + * | | |This field is used for TMR2 interrupt enable. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGT_IE |Block Guard Time Interrupt Enable Control + * | | |This field is used for block guard time interrupt enable. + * | | |0 = Block guard time Disabled. + * | | |1 = Block guard time Enabled. + * |[7] |CD_IE |Card Detect Interrupt Enable Control + * | | |This field is used for card detect interrupt enable. The card detect status is + * | | |CD_INS_F(SC_SR[12]) + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INIT_IE |Initial End Interrupt Enable Control + * | | |This field is used for activation (ACT_EN(SC_ALTCTL[3] = 1)), deactivation ((DACT_EN + * | | |SC_ALTCTL[2]) = 1) and warm reset (WARST_EN (SC_ALTCTL [4])) sequence interrupt enable. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RTMR_IE |Receiver Buffer Time-Out Interrupt Enable Control + * | | |This field is used for receiver buffer time-out interrupt enable. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACON_ERR_IE|Auto Convention Error Interrupt Enable Control + * | | |This field is used for auto-convention error interrupt enable. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::ISR + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDA_IS |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) + * | | |interrupt status flag. + * | | |Note: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). + * | | |If software reads data from SC_RBR and receiver buffer data byte number is less than + * | | |RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically. + * |[1] |TBE_IS |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |Note: This field is the status flag of transmit buffer empty state. + * | | |If software wants to clear this bit, software must write data to THR(SC_THR[7:0]) buffer and + * | | |then this bit will be cleared automatically. + * |[2] |TERR_IS |Transfer Error Interrupt Status Flag (Read Only) + * | | |This field is used for transfer error interrupt status flag. + * | | |The transfer error states is at SC_SR register which includes receiver break error + * | | |RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_TRSR[5], parity error RX_EPA_F(SC_TRSR[4] and + * | | |receiver buffer overflow error RX_OVER_F(SC_TRSR[0]), transmit buffer overflow error + * | | |TX_OVER_F(SC_TRSR[8]), receiver retry over limit error RX_OVER_REERR(SC_TRSR[22] and + * | | |transmitter retry over limit error TX_OVER_REERR(SC_TRSR[30]). + * | | |Note: This field is the status flag of + * | | |RX_EBR_F(SC_TRSR[6]), RX_EFR_F(SC_TRSR[5]), RX_EPA_F(SC_TRSR[4]), RX_OVER_F(SC_TRSR[0]), + * | | |TX_OVER_F(SC_TRSR[8]), RX_OVER_REERR(SC_TRSR[22]) or TX_OVER_REERR(SC_TRSR[30]). + * | | |So, if software wants to clear this bit, software must write 1 to each field. + * |[3] |TMR0_IS |Timer0 Interrupt Status Flag (Read Only) + * | | |This field is used for TMR0 interrupt status flag. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[4] |TMR1_IS |Timer1 Interrupt Status Flag (Read Only) + * | | |This field is used for TMR1 interrupt status flag. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[5] |TMR2_IS |Timer2 Interrupt Status Flag (Read Only) + * | | |This field is used for TMR2 interrupt status flag. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[6] |BGT_IS |Block Guard Time Interrupt Status Flag (Read Only) + * | | |This field is used for block guard time interrupt status flag. + * | | |Note1: This bit is valid when RX_BGT_EN (SC_ALTCTL[12]) is enabled. + * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it. + * |[7] |CD_IS |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag. + * | | |The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F(SC_SR[11]). + * | | |Note: + * | | |This field is the status flag of CD_INS_F(SC_SR[12]) or CD_REM_F(SC_TRSR[11])]. + * | | |So if software wants to clear this bit, software must write 1 to this field. + * |[8] |INIT_IS |Initial End Interrupt Status Flag (Read Only) + * | | |This field is used for activation (ACT_EN(SC_ALTCTL[3])), deactivation (DACT_EN + * | | |(SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[9] |RTMR_IS |Receiver Buffer Time-Out Interrupt Status Flag (Read Only) + * | | |This field is used for receiver buffer time-out interrupt status flag. + * | | |Note: This field is the status flag of receiver buffer time-out state. + * | | |If software wants to clear this bit, software must read all receiver buffer remaining data + * | | |by reading SC_RBR buffer,. + * |[10] |ACON_ERR_IS|Auto Convention Error Interrupt Status Flag (Read Only) + * | | |This field indicates auto convention sequence error. + * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * @var SC_T::TRSR + * Offset: 0x20 SC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RX_OVER_F |RX Overflow Error Status Flag (Read Only) + * | | |This bit is set when RX buffer overflow. + * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be + * | | |set. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[1] |RX_EMPTY_F|Receiver Buffer Empty Status Flag(Read Only) + * | | |This bit indicates RX buffer empty or not. + * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high. + * | | |It will be cleared when SC receives any new data. + * |[2] |RX_FULL_F |Receiver Buffer Full Status Flag (Read Only) + * | | |This bit indicates RX buffer full or not. + * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. + * |[4] |RX_EPA_F |Receiver Parity Error Status Flag (Read Only) + * | | |This bit is set to logic 1 whenever the received character does not have a valid + * | | |"parity bit". + * | | |Note1: + * | | |This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2: + * | | |If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will + * | | |not set this flag. + * |[5] |RX_EFR_F |Receiver Frame Error Status Flag (Read Only) + * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |Note1: + * | | |This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2: + * | | |If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will + * | | |not set this flag. + * |[6] |RX_EBR_F |Receiver Break Error Status Flag (Read Only) + * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" + * | | |(logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + * | | |+ data bits + parity + stop bits). + * | | |Note1: + * | | |This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2: + * | | |If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will + * | | |not set this flag. + * |[8] |TX_OVER_F |TX Overflow Error Interrupt Status Flag (Read Only) + * | | |If TX buffer is full, an additional write to THR(SC_THR[7:0]) will cause this bit be set to + * | | |"1" by hardware. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[9] |TX_EMPTY_F|Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware + * | | |sets this bit high. + * | | |It will be cleared when writing data into THR(SC_THR[7:0]) (TX buffer not empty). + * |[10] |TX_FULL_F |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, + * | | |otherwise is cleared by hardware. + * |[17:16] |RX_POINT_F|Receiver Buffer Pointer Status Flag (Read Only) + * | | |This field indicates the RX buffer pointer status flag. + * | | |When SC receives one byte from external device, RX_POINT_F(SC_SR[17:16]) increases one. + * | | |When one byte of RX buffer is read by CPU, RX_POINT_F(SC_SR[17:16]) decreases one. + * |[21] |RX_REERR |Receiver Retry Error (Read Only) + * | | |This bit is set by hardware when RX has any error and retries transfer. + * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retry function by setting RX_ERETRY_EN + * | | |(SC_CTL[19]) , the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set + * | | |RX_EPA_F(SC_TRSR[4])). + * |[22] |RX_OVER_REERR|Receiver Over Retry Error (Read Only) + * | | |This bit is set by hardware when RX transfer error retry over retry number limit. + * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RX_ERETRY_EN + * | | |(SC_CTL[19]), the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set + * | | |RX_EPA_F(SC_TRSR[4])). + * |[23] |RX_ATV |Receiver In Active Status Flag (Read Only) + * | | |This bit is set by hardware when RX transfer is in active. + * | | |This bit is cleared automatically when RX transfer is finished. + * |[25:24] |TX_POINT_F|Transmit Buffer Pointer Status Flag (Read Only) + * | | |This field indicates the TX buffer pointer status flag. + * | | |When CPU writes data into SC_THR, TX_POINT_F increases one. + * | | |When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F + * | | |decreases one. + * |[29] |TX_REERR |Transmitter Retry Error (Read Only) + * | | |This bit is set by hardware when transmitter re-transmits. + * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TX_OVER_REERR|Transmitter Over Retry Error (Read Only) + * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to it. + * |[31] |TX_ATV |Transmit In Active Status Flag (Read Only) + * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte + * | | |transmission has completed. + * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last + * | | |byte has been transmitted. + * @var SC_T::PINCSR + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POW_EN |SC_POW_EN Pin Signal + * | | |Software can set POW_EN (SC_PINCSR[0]) and POW_INV (SC_PINCSR[11])to decide SC_PWR pin is in + * | | |high or low level. + * | | |Write this field to drive SC_PWR pin + * | | |Refer POW_INV (SC_PINCSR[11]) description for programming SC_PWR pin voltage level. + * | | |Read this field to get SC_PWR pin status. + * | | |0 = SC_PWR pin status is low. + * | | |1 = SC_PWR pin status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be + * | | |changed automatically. + * | | |So don't fill this field when operating in these modes. + * |[1] |SC_RST |SC_RST Pin Signal + * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting + * | | |this bit. + * | | |Write this field to drive SC_RST pin. + * | | |0 = Drive SC_RST pin to low. + * | | |1 = Drive SC_RST pin to high. + * | | |Read this field to get SC_RST pin status. + * | | |0 = SC_RST pin status is low. + * | | |1 = SC_RST pin status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be + * | | |changed automatically. + * | | |So don't fill this field when operating in these modes. + * |[2] |CD_REM_F |Card Detect Removal Status Of SC_CD Pin (Read Only) + * | | |This bit is set whenever a card has been removed. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it. + * | | |Note2: Card detect engine will start after SC_CEN (SC_CTL[0] )set. + * |[3] |CD_INS_F |Card Detect Insert Status Of SC_CD Pin (Read Only) + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it. + * | | |Note2: The + * | | |card detect engine will start after SC_CEN (SC_CTL[0] )set. + * |[4] |CD_PIN_ST |Card Detect Status Of SC_CD Pin Status (Read Only) + * | | |This bit is the pin status flag of SC_CD + * | | |0 = The SC_CD pin state at low. + * | | |1 = The SC_CD pin state at high. + * |[6] |CLK_KEEP |SC Clock Enable Control + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be + * | | |changed automatically. + * | | |So don't fill this field when operating in these modes. + * |[7] |ADAC_CD_EN|Auto Deactivation When Card Removal + * | | |0 = Auto deactivation Disabled when hardware detected the card removal. + * | | |1 = Auto deactivation Enabled when hardware detected the card removal. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation + * | | |sequence (if this bit be setting). + * | | |If this process completes. + * | | |Hardware will generate an initial end. + * | | |interrupt to CPU. + * |[8] |SC_OEN_ST |SC Data Output Enable Pin Status (Read Only) + * | | |This bit is the pin status of SC_DATA_OEN + * | | |0 = The SC_DATA_OEN pin state at low. + * | | |1 = The SC_DATA_OEN pin state at high. + * |[9] |SC_DATA_O |SC Data Output Pin + * | | |This bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by + * | | |setting this bit. + * | | |0 = Drive SC_DATA_O pin to low. + * | | |1 = Drive SC_DATA_O pin to high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed + * | | |automatically. + * | | |So don't fill this field when SC is in these modes. + * |[10] |CD_LEV |Card Detect Level + * | | |0 = When hardware detects the card detect pin from high to low, it indicates a card is + * | | |detected. + * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is + * | | |detected. + * | | |Note: Software must select card detect level before Smart Card engine is enabled + * |[11] |POW_INV |SC_POW Pin Inverse + * | | |This bit is used for inverse the SC_POW pin. + * | | |There are four kinds of combination for SC_POW pin setting by POW_INV(SC_PINCSR[11]) and + * | | |POW_EN(SC_PINCSR[0]). + * | | |POW_INV (SC_PINCSR[11]) is bit 1 and POW_EN(SC_PINCSR[0]) is bit 0 for SC_POW_Pin as high or + * | | |low voltage selection. + * | | |00 = SC_POW_ Pin is 0. + * | | |01 = SC_POW _Pin is 1. + * | | |10 = SC_POW _Pin is 1. + * | | |11 = SC_POW_ Pin is 0. + * | | |Note: Software must select POW_INV (SC_PINCSR[11]) before Smart Card is enabled by SC_CEN + * | | |(SC_CTL[0]). + * |[16] |SC_DATA_I_ST|SC Data Pin Status (Read Only) + * | | |This bit is the pin status of SC_DATA + * | | |0 = The SC_DATA pin is low. + * | | |1 = The SC_DATA pin is high. + * |[30] |SYNC |SYNC Flag Indicator + * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCSR + * | | |register. + * | | |0 = Synchronizing is completion, user can write new data to SC_PINCSR register. + * | | |1 = Last value is synchronizing. + * | | |Note: This bit is read only. + * @var SC_T::TMR0 + * Offset: 0x28 SC Internal Timer Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT0 |Timer 0 Counter Value (ETU Base) + * | | |This field indicates the internal timer operation values. + * |[27:24] |MODE |Timer 0 Operation Mode Selection + * | | |This field indicates the internal 24-bit timer operation selection. + * | | |Refer to 5.15.5.4 for programming Timer0 + * @var SC_T::TMR1 + * Offset: 0x2C SC Internal Timer Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT1 |Timer 1 Counter Value (ETU Base) + * | | |This field indicates the internal timer operation values. + * |[27:24] |MODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit timer operation selection. + * | | |Refer to 5.15.5.4 for programming Timer1 + * @var SC_T::TMR2 + * Offset: 0x30 SC Internal Timer Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT2 |Timer 2 Counter Value (ETU Base) + * | | |This field indicates the internal timer operation values. + * |[27:24] |MODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit timer operation selection + * | | |Refer to 5.15.5.4 for programming Timer2 + * @var SC_T::UACTL + * Offset: 0x34 SC UART Mode Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UA_MODE_EN|UART Mode Enable Control + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CON_SEL (SC_CTL[5:4]) = 00 and + * | | |AUTO_CON_EN(SC_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UA_MODE_EN(SC_UACTL [0]) = 00. + * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state + * | | |machine. + * |[5:4] |DATA_LEN10|Data Length + * | | |00 = Character Data Length is 8 bits. + * | | |01 = Character Data Length is 7 bits. + * | | |10 = Character Data length is 6 bits. + * | | |11 = Character Data Length is 5 bits. + * | | |Note: In smart card mode, this DATA_LEN must be '00' + * |[6] |PBDIS |Parity Bit Disable Control + * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of + * | | |the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during + * | | |transfer. + * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit) + * |[7] |OPE |Odd Parity Enable Control + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in + * | | |receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in + * | | |receiving mode. + * | | |Note: This bit has effect only when PBDIS bit is '0'. + * @var SC_T::TDRA + * Offset: 0x38 SC Timer Current Data Register A + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TDR0 |Timer0 Current Data value(Read Only) + * | | |This field indicates the current count values of timer0. + * @var SC_T::TDRB + * Offset: 0x3C SC Timer Current Data Register B + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TDR1 |Timer1 Current Data value(Read Only) + * | | |This field indicates the current count values of timer1. + * |[15:8] |TDR2 |Timer2 Current Data value (Read Only) + * | | |This field indicates the current count values of timer2. + */ + + union { + __I uint32_t RBR; /* Offset: 0x00 SC Receiving Buffer Register. */ + __O uint32_t THR; /* Offset: 0x00 SC Transmit Holding Register */ + }; + __IO uint32_t CTL; /* Offset: 0x04 SC Control Register */ + __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register */ + __IO uint32_t EGTR; /* Offset: 0x0C SC Extend Guard Time Register */ + __IO uint32_t RFTMR; /* Offset: 0x10 SC Receive buffer Time-out Register */ + __IO uint32_t ETUCR; /* Offset: 0x14 SC ETU Control Register */ + __IO uint32_t IER; /* Offset: 0x18 SC Interrupt Enable Control Register */ + __IO uint32_t ISR; /* Offset: 0x1C SC Interrupt Status Register */ + __IO uint32_t TRSR; /* Offset: 0x20 SC Status Register */ + __IO uint32_t PINCSR; /* Offset: 0x24 SC Pin Control State Register */ + __IO uint32_t TMR0; /* Offset: 0x28 SC Internal Timer Control Register 0 */ + __IO uint32_t TMR1; /* Offset: 0x2C SC Internal Timer Control Register 1 */ + __IO uint32_t TMR2; /* Offset: 0x30 SC Internal Timer Control Register 2 */ + __I uint32_t RESERVED0; + __I uint32_t TDRA; /* Offset: 0x38 SC Timer Current Data Register A */ + __I uint32_t TDRB; /* Offset: 0x3C SC Timer Current Data Register B */ + +} SC_T; + + + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller +@{ */ + +/* SC RBR Bit Field Definitions */ +#define SC_RBR_RBR_Pos 0 /*!< SC_T::RBR: RBR Position */ +#define SC_RBR_RBR_Msk (0xFFul << SC_RBR_RBR_Pos) /*!< SC_T::RBR: RBR Mask */ + +/* SC THR Bit Field Definitions */ +#define SC_THR_THR_Pos 0 /*!< SC_T::THR: THR Position */ +#define SC_THR_THR_Msk (0xFFul << SC_THR_THR_Pos) /*!< SC_T::THR: THR Mask */ + +/* SC CTL Bit Field Definitions */ +#define SC_CTL_SYNC_Pos 30 /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_CTL_CD_DEB_SEL_Pos 24 /*!< SC_T::CTL: CD_DEB_SEL Position */ +#define SC_CTL_CD_DEB_SEL_Msk (3ul << SC_CTL_CD_DEB_SEL_Pos) /*!< SC_T::CTL: CD_DEB_SEL Mask */ + +#define SC_CTL_TX_ERETRY_EN_Pos 23 /*!< SC_T::CTL: TX_ERETRY_EN Position */ +#define SC_CTL_TX_ERETRY_EN_Msk (1ul << SC_CTL_TX_ERETRY_EN_Pos) /*!< SC_T::CTL: TX_ERETRY_EN Mask */ + +#define SC_CTL_TX_ERETRY_Pos 20 /*!< SC_T::CTL: TX_ERETRY Position */ +#define SC_CTL_TX_ERETRY_Msk (7ul << SC_CTL_TX_ERETRY_Pos) /*!< SC_T::CTL: TX_ERETRY Mask */ + +#define SC_CTL_RX_ERETRY_EN_Pos 19 /*!< SC_T::CTL: RX_ERETRY_EN Position */ +#define SC_CTL_RX_ERETRY_EN_Msk (1ul << SC_CTL_RX_ERETRY_EN_Pos) /*!< SC_T::CTL: RX_ERETRY_EN Mask */ + +#define SC_CTL_RX_ERETRY_Pos 16 /*!< SC_T::CTL: RX_ERETRY Position */ +#define SC_CTL_RX_ERETRY_Msk (7ul << SC_CTL_RX_ERETRY_Pos) /*!< SC_T::CTL: RX_ERETRY Mask */ + +#define SC_CTL_SLEN_Pos 15 /*!< SC_T::CTL: SLEN Position */ +#define SC_CTL_SLEN_Msk (1ul << SC_CTL_SLEN_Pos) /*!< SC_T::CTL: SLEN Mask */ + +#define SC_CTL_TMR_SEL_Pos 13 /*!< SC_T::CTL: TMR_SEL Position */ +#define SC_CTL_TMR_SEL_Msk (3ul << SC_CTL_TMR_SEL_Pos) /*!< SC_T::CTL: TMR_SEL Mask */ + +#define SC_CTL_BGT_Pos 8 /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1Ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_RX_FTRI_LEV_Pos 6 /*!< SC_T::CTL: RX_FTRI_LEV Position */ +#define SC_CTL_RX_FTRI_LEV_Msk (3ul << SC_CTL_RX_FTRI_LEV_Pos) /*!< SC_T::CTL: RX_FTRI_LEV Mask */ + +#define SC_CTL_CON_SEL_Pos 4 /*!< SC_T::CTL: CON_SEL Position */ +#define SC_CTL_CON_SEL_Msk (3ul << SC_CTL_CON_SEL_Pos) /*!< SC_T::CTL: CON_SEL Mask */ + +#define SC_CTL_AUTO_CON_EN_Pos 3 /*!< SC_T::CTL: AUTO_CON_EN Position */ +#define SC_CTL_AUTO_CON_EN_Msk (1ul << SC_CTL_AUTO_CON_EN_Pos) /*!< SC_T::CTL: AUTO_CON_EN Mask */ + +#define SC_CTL_DIS_TX_Pos 2 /*!< SC_T::CTL: DIS_TX Position */ +#define SC_CTL_DIS_TX_Msk (1ul << SC_CTL_DIS_TX_Pos) /*!< SC_T::CTL: DIS_TX Mask */ + +#define SC_CTL_DIS_RX_Pos 1 /*!< SC_T::CTL: DIS_RX Position */ +#define SC_CTL_DIS_RX_Msk (1ul << SC_CTL_DIS_RX_Pos) /*!< SC_T::CTL: DIS_RX Mask */ + +#define SC_CTL_SC_CEN_Pos 0 /*!< SC_T::CTL: SC_CEN Position */ +#define SC_CTL_SC_CEN_Msk (1ul << SC_CTL_SC_CEN_Pos) /*!< SC_T::CTL: SC_CEN Mask */ + +/* SC ALTCTL Bit Field Definitions */ +#define SC_ALTCTL_OUTSEL_Pos 16 /*!< SC_T::ALTCTL: OUTSEL Position */ +#define SC_ALTCTL_OUTSEL_Msk (1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */ + +#define SC_ALTCTL_TMR2_ATV_Pos 15 /*!< SC_T::ALTCTL: TMR2_ATV Position */ +#define SC_ALTCTL_TMR2_ATV_Msk (1ul << SC_ALTCTL_TMR2_ATV_Pos) /*!< SC_T::ALTCTL: TMR2_ATV Mask */ + +#define SC_ALTCTL_TMR1_ATV_Pos 14 /*!< SC_T::ALTCTL: TMR1_ATV Position */ +#define SC_ALTCTL_TMR1_ATV_Msk (1ul << SC_ALTCTL_TMR1_ATV_Pos) /*!< SC_T::ALTCTL: TMR1_ATV Mask */ + +#define SC_ALTCTL_TMR0_ATV_Pos 13 /*!< SC_T::ALTCTL: TMR0_ATV Position */ +#define SC_ALTCTL_TMR0_ATV_Msk (1ul << SC_ALTCTL_TMR0_ATV_Pos) /*!< SC_T::ALTCTL: TMR0_ATV Mask */ + +#define SC_ALTCTL_RX_BGT_EN_Pos 12 /*!< SC_T::ALTCTL: RX_BGT_EN Position */ +#define SC_ALTCTL_RX_BGT_EN_Msk (1ul << SC_ALTCTL_RX_BGT_EN_Pos) /*!< SC_T::ALTCTL: RX_BGT_EN Mask */ + +#define SC_ALTCTL_INIT_SEL_Pos 8 /*!< SC_T::ALTCTL: INIT_SEL Position */ +#define SC_ALTCTL_INIT_SEL_Msk (3ul << SC_ALTCTL_INIT_SEL_Pos) /*!< SC_T::ALTCTL: INIT_SEL Mask */ + +#define SC_ALTCTL_TMR2_SEN_Pos 7 /*!< SC_T::ALTCTL: TMR2_SEN Position */ +#define SC_ALTCTL_TMR2_SEN_Msk (1ul << SC_ALTCTL_TMR2_SEN_Pos) /*!< SC_T::ALTCTL: TMR2_SEN Mask */ + +#define SC_ALTCTL_TMR1_SEN_Pos 6 /*!< SC_T::ALTCTL: TMR1_SEN Position */ +#define SC_ALTCTL_TMR1_SEN_Msk (1ul << SC_ALTCTL_TMR1_SEN_Pos) /*!< SC_T::ALTCTL: TMR1_SEN Mask */ + +#define SC_ALTCTL_TMR0_SEN_Pos 5 /*!< SC_T::ALTCTL: TMR0_SEN Position */ +#define SC_ALTCTL_TMR0_SEN_Msk (1ul << SC_ALTCTL_TMR0_SEN_Pos) /*!< SC_T::ALTCTL: TMR0_SEN Mask */ + +#define SC_ALTCTL_WARST_EN_Pos 4 /*!< SC_T::ALTCTL: WARST_EN Position */ +#define SC_ALTCTL_WARST_EN_Msk (1ul << SC_ALTCTL_WARST_EN_Pos) /*!< SC_T::ALTCTL: WARST_EN Mask */ + +#define SC_ALTCTL_ACT_EN_Pos 3 /*!< SC_T::ALTCTL: ACT_EN Position */ +#define SC_ALTCTL_ACT_EN_Msk (1ul << SC_ALTCTL_ACT_EN_Pos) /*!< SC_T::ALTCTL: ACT_EN Mask */ + +#define SC_ALTCTL_DACT_EN_Pos 2 /*!< SC_T::ALTCTL: DACT_EN Position */ +#define SC_ALTCTL_DACT_EN_Msk (1ul << SC_ALTCTL_DACT_EN_Pos) /*!< SC_T::ALTCTL: DACT_EN Mask */ + +#define SC_ALTCTL_RX_RST_Pos 1 /*!< SC_T::ALTCTL: RX_RST Position */ +#define SC_ALTCTL_RX_RST_Msk (1ul << SC_ALTCTL_RX_RST_Pos) /*!< SC_T::ALTCTL: RX_RST Mask */ + +#define SC_ALTCTL_TX_RST_Pos 0 /*!< SC_T::ALTCTL: TX_RST Position */ +#define SC_ALTCTL_TX_RST_Msk (1ul << SC_ALTCTL_TX_RST_Pos) /*!< SC_T::ALTCTL: TX_RST Mask */ + +/* SC EGTR Bit Field Definitions */ +#define SC_EGTR_EGT_Pos 0 /*!< SC_T::EGTR: EGT Position */ +#define SC_EGTR_EGT_Msk (0xFFul << SC_EGTR_EGT_Pos) /*!< SC_T::EGTR: EGT Mask */ + +/* SC RFTMR Bit Field Definitions */ +#define SC_RFTMR_RFTM_Pos 0 /*!< SC_T::RFTMR: RFTM Position */ +#define SC_RFTMR_RFTM_Msk (0x1FFul << SC_RFTMR_RFTM_Pos) /*!< SC_T::RFTMR: RFTM Mask */ + +/* SC ETUCR Bit Field Definitions */ +#define SC_ETUCR_COMPEN_EN_Pos 15 /*!< SC_T::ETUCR: COMPEN_EN Position */ +#define SC_ETUCR_COMPEN_EN_Msk (1ul << SC_ETUCR_COMPEN_EN_Pos) /*!< SC_T::ETUCR: COMPEN_EN Mask */ + +#define SC_ETUCR_ETU_RDIV_Pos 0 /*!< SC_T::ETUCR: ETU_RDIV Position */ +#define SC_ETUCR_ETU_RDIV_Msk (0xFFFul << SC_ETUCR_ETU_RDIV_Pos) /*!< SC_T::ETUCR: ETU_RDIV Mask */ + +/* SC IER Bit Field Definitions */ +#define SC_IER_ACON_ERR_IE_Pos 10 /*!< SC_T::IER: ACON_ERR_IE Position */ +#define SC_IER_ACON_ERR_IE_Msk (1ul << SC_IER_ACON_ERR_IE_Pos) /*!< SC_T::IER: ACON_ERR_IE Mask */ + +#define SC_IER_RTMR_IE_Pos 9 /*!< SC_T::IER: RTMR_IE Position */ +#define SC_IER_RTMR_IE_Msk (1ul << SC_IER_RTMR_IE_Pos) /*!< SC_T::IER: RTMR_IE Mask */ + +#define SC_IER_INIT_IE_Pos 8 /*!< SC_T::IER: INIT_IE Position */ +#define SC_IER_INIT_IE_Msk (1ul << SC_IER_INIT_IE_Pos) /*!< SC_T::IER: INIT_IE Mask */ + +#define SC_IER_CD_IE_Pos 7 /*!< SC_T::IER: CD_IE Position */ +#define SC_IER_CD_IE_Msk (1ul << SC_IER_CD_IE_Pos) /*!< SC_T::IER: CD_IE Mask */ + +#define SC_IER_BGT_IE_Pos 6 /*!< SC_T::IER: BGT_IE Position */ +#define SC_IER_BGT_IE_Msk (1ul << SC_IER_BGT_IE_Pos) /*!< SC_T::IER: BGT_IE Mask */ + +#define SC_IER_TMR2_IE_Pos 5 /*!< SC_T::IER: TMR2_IE Position */ +#define SC_IER_TMR2_IE_Msk (1ul << SC_IER_TMR2_IE_Pos) /*!< SC_T::IER: TMR2_IE Mask */ + +#define SC_IER_TMR1_IE_Pos 4 /*!< SC_T::IER: TMR1_IE Position */ +#define SC_IER_TMR1_IE_Msk (1ul << SC_IER_TMR1_IE_Pos) /*!< SC_T::IER: TMR1_IE Mask */ + +#define SC_IER_TMR0_IE_Pos 3 /*!< SC_T::IER: TMR0_IE Position */ +#define SC_IER_TMR0_IE_Msk (1ul << SC_IER_TMR0_IE_Pos) /*!< SC_T::IER: TMR0_IE Mask */ + +#define SC_IER_TERR_IE_Pos 2 /*!< SC_T::IER: TERR_IE Position */ +#define SC_IER_TERR_IE_Msk (1ul << SC_IER_TERR_IE_Pos) /*!< SC_T::IER: TERR_IE Mask */ + +#define SC_IER_TBE_IE_Pos 1 /*!< SC_T::IER: TBE_IE Position */ +#define SC_IER_TBE_IE_Msk (1ul << SC_IER_TBE_IE_Pos) /*!< SC_T::IER: TBE_IE Mask */ + +#define SC_IER_RDA_IE_Pos 0 /*!< SC_T::IER: RDA_IE Position */ +#define SC_IER_RDA_IE_Msk (1ul << SC_IER_RDA_IE_Pos) /*!< SC_T::IER: RDA_IE Mask */ + +/* SC ISR Bit Field Definitions */ +#define SC_ISR_ACON_ERR_IS_Pos 10 /*!< SC_T::ISR: ACON_ERR_IS Position */ +#define SC_ISR_ACON_ERR_IS_Msk (1ul << SC_ISR_ACON_ERR_IS_Pos) /*!< SC_T::ISR: ACON_ERR_IS Mask */ + +#define SC_ISR_RTMR_IS_Pos 9 /*!< SC_T::ISR: RTMR_IS Position */ +#define SC_ISR_RTMR_IS_Msk (1ul << SC_ISR_RTMR_IS_Pos) /*!< SC_T::ISR: RTMR_IS Mask */ + +#define SC_ISR_INIT_IS_Pos 8 /*!< SC_T::ISR: INIT_IS Position */ +#define SC_ISR_INIT_IS_Msk (1ul << SC_ISR_INIT_IS_Pos) /*!< SC_T::ISR: INIT_IS Mask */ + +#define SC_ISR_CD_IS_Pos 7 /*!< SC_T::ISR: CD_IS Position */ +#define SC_ISR_CD_IS_Msk (1ul << SC_ISR_CD_IS_Pos) /*!< SC_T::ISR: CD_IS Mask */ + +#define SC_ISR_BGT_IS_Pos 6 /*!< SC_T::ISR: BGT_IS Position */ +#define SC_ISR_BGT_IS_Msk (1ul << SC_ISR_BGT_IS_Pos) /*!< SC_T::ISR: BGT_IS Mask */ + +#define SC_ISR_TMR2_IS_Pos 5 /*!< SC_T::ISR: TMR2_IS Position */ +#define SC_ISR_TMR2_IS_Msk (1ul << SC_ISR_TMR2_IS_Pos) /*!< SC_T::ISR: TMR2_IS Mask */ + +#define SC_ISR_TMR1_IS_Pos 4 /*!< SC_T::ISR: TMR1_IS Position */ +#define SC_ISR_TMR1_IS_Msk (1ul << SC_ISR_TMR1_IS_Pos) /*!< SC_T::ISR: TMR1_IS Mask */ + +#define SC_ISR_TMR0_IS_Pos 3 /*!< SC_T::ISR: TMR0_IS Position */ +#define SC_ISR_TMR0_IS_Msk (1ul << SC_ISR_TMR0_IS_Pos) /*!< SC_T::ISR: TMR0_IS Mask */ + +#define SC_ISR_TERR_IS_Pos 2 /*!< SC_T::ISR: TERR_IS Position */ +#define SC_ISR_TERR_IS_Msk (1ul << SC_ISR_TERR_IS_Pos) /*!< SC_T::ISR: TERR_IS Mask */ + +#define SC_ISR_TBE_IS_Pos 1 /*!< SC_T::ISR: TXBE_IS Position */ +#define SC_ISR_TBE_IS_Msk (1ul << SC_ISR_TBE_IS_Pos) /*!< SC_T::ISR: TXBE_IS Mask */ + +#define SC_ISR_RDA_IS_Pos 0 /*!< SC_T::ISR: RDA_IS Position */ +#define SC_ISR_RDA_IS_Msk (1ul << SC_ISR_RDA_IS_Pos) /*!< SC_T::ISR: RDA_IS Mask */ + + +/* SC TRSR Bit Field Definitions */ +#define SC_TRSR_TX_ATV_Pos 31 /*!< SC_T::TRSR: TX_ATV Position */ +#define SC_TRSR_TX_ATV_Msk (1ul << SC_TRSR_TX_ATV_Pos) /*!< SC_T::TRSR: TX_ATV Mask */ + +#define SC_TRSR_TX_OVER_REERR_Pos 30 /*!< SC_T::TRSR: TX_OVER_REERR Position */ +#define SC_TRSR_TX_OVER_REERR_Msk (1ul << SC_TRSR_TX_OVER_REERR_Pos) /*!< SC_T::TRSR: TX_OVER_REERR Mask */ + +#define SC_TRSR_TX_REERR_Pos 29 /*!< SC_T::TRSR: TX_REERR Position */ +#define SC_TRSR_TX_REERR_Msk (1ul << SC_TRSR_TX_REERR_Pos) /*!< SC_T::TRSR: TX_REERR Mask */ + +#define SC_TRSR_TX_POINT_F_Pos 24 /*!< SC_T::TRSR: TX_POINT_F Position */ +#define SC_TRSR_TX_POINT_F_Msk (7ul << SC_TRSR_TX_POINT_F_Pos) /*!< SC_T::TRSR: TX_POINT_F Mask */ + +#define SC_TRSR_RX_ATV_Pos 23 /*!< SC_T::TRSR: RX_ATV Position */ +#define SC_TRSR_RX_ATV_Msk (1ul << SC_TRSR_RX_ATV_Pos) /*!< SC_T::TRSR: RX_ATV Mask */ + +#define SC_TRSR_RX_OVER_REERR_Pos 22 /*!< SC_T::TRSR: RX_OVER_REERR Position */ +#define SC_TRSR_RX_OVER_REERR_Msk (1ul << SC_TRSR_RX_OVER_REERR_Pos) /*!< SC_T::TRSR: RX_OVER_REERR Mask */ + +#define SC_TRSR_RX_REERR_Pos 21 /*!< SC_T::TRSR: RX_REERR Position */ +#define SC_TRSR_RX_REERR_Msk (1ul << SC_TRSR_RX_REERR_Pos) /*!< SC_T::TRSR: RX_REERR Mask */ + +#define SC_TRSR_RX_POINT_F_Pos 16 /*!< SC_T::TRSR: RX_POINT_F Position */ +#define SC_TRSR_RX_POINT_F_Msk (7ul << SC_TRSR_RX_POINT_F_Pos) /*!< SC_T::TRSR: RX_POINT_F Mask */ + +#define SC_TRSR_TX_FULL_F_Pos 10 /*!< SC_T::TRSR: TX_FULL_F Position */ +#define SC_TRSR_TX_FULL_F_Msk (1ul << SC_TRSR_TX_FULL_F_Pos) /*!< SC_T::TRSR: TX_FULL_F Mask */ + +#define SC_TRSR_TX_EMPTY_F_Pos 9 /*!< SC_T::TRSR: TX_EMPTY_F Position */ +#define SC_TRSR_TX_EMPTY_F_Msk (1ul << SC_TRSR_TX_EMPTY_F_Pos) /*!< SC_T::TRSR: TX_EMPTY_F Mask */ + +#define SC_TRSR_TX_OVER_F_Pos 8 /*!< SC_T::TRSR: TX_OVER_F Position */ +#define SC_TRSR_TX_OVER_F_Msk (1ul << SC_TRSR_TX_OVER_F_Pos) /*!< SC_T::TRSR: TX_OVER_F Mask */ + +#define SC_TRSR_RX_EBR_F_Pos 6 /*!< SC_T::TRSR: RX_EBR_F Position */ +#define SC_TRSR_RX_EBR_F_Msk (1ul << SC_TRSR_RX_EBR_F_Pos) /*!< SC_T::TRSR: RX_EBR_F Mask */ + +#define SC_TRSR_RX_EFR_F_Pos 5 /*!< SC_T::TRSR: RX_EFR_F Position */ +#define SC_TRSR_RX_EFR_F_Msk (1ul << SC_TRSR_RX_EFR_F_Pos) /*!< SC_T::TRSR: RX_EFR_F Mask */ + +#define SC_TRSR_RX_EPA_F_Pos 4 /*!< SC_T::TRSR: RX_EPA_F Position */ +#define SC_TRSR_RX_EPA_F_Msk (1ul << SC_TRSR_RX_EPA_F_Pos) /*!< SC_T::TRSR: RX_EPA_F Mask */ + +#define SC_TRSR_RX_FULL_F_Pos 2 /*!< SC_T::TRSR: RX_FULL_F Position */ +#define SC_TRSR_RX_FULL_F_Msk (1ul << SC_TRSR_RX_FULL_F_Pos) /*!< SC_T::TRSR: RX_FULL_F Mask */ + +#define SC_TRSR_RX_EMPTY_F_Pos 1 /*!< SC_T::TRSR: RX_EMPTY_F Position */ +#define SC_TRSR_RX_EMPTY_F_Msk (1ul << SC_TRSR_RX_EMPTY_F_Pos) /*!< SC_T::TRSR: RX_EMPTY_F Mask */ + +#define SC_TRSR_RX_OVER_F_Pos 0 /*!< SC_T::TRSR: RX_OVER_F Position */ +#define SC_TRSR_RX_OVER_F_Msk (1ul << SC_TRSR_RX_OVER_F_Pos) /*!< SC_T::TRSR: RX_OVER_F Mask */ + +/* SC PINCSR Bit Field Definitions */ +#define SC_PINCSR_SYNC_Pos 30 /*!< SC_T::PINCSR: SYNC Position */ +#define SC_PINCSR_SYNC_Msk (1ul << SC_PINCSR_SYNC_Pos) /*!< SC_T::PINCSR: SYNC Mask */ + +#define SC_PINCSR_SC_DATA_I_ST_Pos 16 /*!< SC_T::PINCSR: SC_DATA_I_ST Position */ +#define SC_PINCSR_SC_DATA_I_ST_Msk (1ul << SC_PINCSR_SC_DATA_I_ST_Pos) /*!< SC_T::PINCSR: SC_DATA_I_ST Mask */ + +#define SC_PINCSR_POW_INV_Pos 11 /*!< SC_T::PINCSR: POW_INV Position */ +#define SC_PINCSR_POW_INV_Msk (1ul << SC_PINCSR_POW_INV_Pos) /*!< SC_T::PINCSR: POW_INV Mask */ + +#define SC_PINCSR_CD_LEV_Pos 10 /*!< SC_T::PINCSR: CD_LEV Position */ +#define SC_PINCSR_CD_LEV_Msk (1ul << SC_PINCSR_CD_LEV_Pos) /*!< SC_T::PINCSR: CD_LEV Mask */ + +#define SC_PINCSR_SC_DATA_O_Pos 9 /*!< SC_T::PINCSR: SC_DATA_O Position */ +#define SC_PINCSR_SC_DATA_O_Msk (1ul << SC_PINCSR_SC_DATA_O_Pos) /*!< SC_T::PINCSR: SC_DATA_O Mask */ + +#define SC_PINCSR_SC_OEN_ST_Pos 8 /*!< SC_T::PINCSR: SC_OEN_ST Position */ +#define SC_PINCSR_SC_OEN_ST_Msk (1ul << SC_PINCSR_SC_OEN_ST_Pos) /*!< SC_T::PINCSR: SC_OEN_ST Mask */ + +#define SC_PINCSR_ADAC_CD_EN_Pos 7 /*!< SC_T::PINCSR: ADAC_CD_EN Position */ +#define SC_PINCSR_ADAC_CD_EN_Msk (1ul << SC_PINCSR_ADAC_CD_EN_Pos) /*!< SC_T::PINCSR: ADAC_CD_EN Mask */ + +#define SC_PINCSR_CLK_KEEP_Pos 6 /*!< SC_T::PINCSR: CLK_KEEP Position */ +#define SC_PINCSR_CLK_KEEP_Msk (1ul << SC_PINCSR_CLK_KEEP_Pos) /*!< SC_T::PINCSR: CLK_KEEP Mask */ + +#define SC_PINCSR_CD_PIN_ST_Pos 4 /*!< SC_T::PINCSR: CD_PIN_ST Position */ +#define SC_PINCSR_CD_PIN_ST_Msk (1ul << SC_PINCSR_CD_PIN_ST_Pos) /*!< SC_T::PINCSR: CD_PIN_ST Mask */ + +#define SC_PINCSR_CD_INS_F_Pos 3 /*!< SC_T::PINCSR: CD_INS_F Position */ +#define SC_PINCSR_CD_INS_F_Msk (1ul << SC_PINCSR_CD_INS_F_Pos) /*!< SC_T::PINCSR: CD_INS_F Mask */ + +#define SC_PINCSR_CD_REM_F_Pos 2 /*!< SC_T::PINCSR: CD_REM_F Position */ +#define SC_PINCSR_CD_REM_F_Msk (1ul << SC_PINCSR_CD_REM_F_Pos) /*!< SC_T::PINCSR: CD_REM_F Mask */ + +#define SC_PINCSR_SC_RST_Pos 1 /*!< SC_T::PINCSR: SC_RST Position */ +#define SC_PINCSR_SC_RST_Msk (1ul << SC_PINCSR_SC_RST_Pos) /*!< SC_T::PINCSR: SC_RST Mask */ + +#define SC_PINCSR_POW_EN_Pos 0 /*!< SC_T::PINCSR: POW_EN Position */ +#define SC_PINCSR_POW_EN_Msk (1ul << SC_PINCSR_POW_EN_Pos) /*!< SC_T::PINCSR: POW_EN Mask */ + +/* SC TMR0 Bit Field Definitions */ +#define SC_TMR0_MODE_Pos 24 /*!< SC_T::TMR0: MODE Position */ +#define SC_TMR0_MODE_Msk (0xFul << SC_TMR0_MODE_Pos) /*!< SC_T::TMR0: MODE Mask */ + +#define SC_TMR0_CNT_Pos 0 /*!< SC_T::TMR0: CNT Position */ +#define SC_TMR0_CNT_Msk (0xFFFFFFul << SC_TMR0_CNT_Pos) /*!< SC_T::TMR0: CNT Mask */ + +/* SC TMR1 Bit Field Definitions */ +#define SC_TMR1_MODE_Pos 24 /*!< SC_T::TMR1: MODE Position */ +#define SC_TMR1_MODE_Msk (0xFul << SC_TMR1_MODE_Pos) /*!< SC_T::TMR1: MODE Mask */ + +#define SC_TMR1_CNT_Pos 0 /*!< SC_T::TMR1: CNT Position */ +#define SC_TMR1_CNT_Msk (0xFFul << SC_TMR1_CNT_Pos) /*!< SC_T::TMR1: CNT Mask */ + +/* SC TMR2 Bit Field Definitions */ +#define SC_TMR2_MODE_Pos 24 /*!< SC_T::TMR2: MODE Position */ +#define SC_TMR2_MODE_Msk (0xFul << SC_TMR2_MODE_Pos) /*!< SC_T::TMR2: MODE Mask */ + +#define SC_TMR2_CNT_Pos 0 /*!< SC_T::TMR2: CNT Position */ +#define SC_TMR2_CNT_Msk (0xFFul << SC_TMR2_CNT_Pos) /*!< SC_T::TMR2: CNT Mask */ + +/* SC TDRA Bit Field Definitions */ +#define SC_TDRA_TDR0_Pos 0 /*!< SC_T::TDRA: TDR0 Position */ +#define SC_TDRA_TDR0_Msk (0xFFFFFFul << SC_TDRA_TDR0_Pos) /*!< SC_T::TDRA: TDR0 Mask */ + +/* SC TDRB Bit Field Definitions */ +#define SC_TDRB_TDR2_Pos 8 /*!< SC_T::TDRB: TDR2 Position */ +#define SC_TDRB_TDR2_Msk (0xFFul << SC_TDRB_TDR2_Pos) /*!< SC_T::TDRB: TDR2 Mask */ + +#define SC_TDRB_TDR1_Pos 0 /*!< SC_T::TDRB: TDR1 Position */ +#define SC_TDRB_TDR1_Msk (0xFFul << SC_TDRB_TDR1_Pos) /*!< SC_T::TDRB: TDR1 Mask */ +/*@}*/ /* end of group SC_CONST */ +/*@}*/ /* end of group SC */ + + + + +/*---------------------- Serial Peripheral Interface Controller -------------------------*/ +/** + @addtogroup SPI Serial Peripheral Interface Controller (SPI) + Memory Mapped Structure for SPI Controller +@{ */ + + +typedef struct +{ + + +/** + * @var SPI_T::CNTRL + * Offset: 0x00 Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GO_BUSY |SPI Transfer Control Bit And Busy Status + * | | |0 = Data transfer stopped. + * | | |1 = In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, + * | | | writing 1 to this bit indicates that the slave is ready to communicate with a master. + * | | |If FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. + * | | |As the transfer is finished, this bit will be cleared automatically. + * | | |Software can read this bit to check if the SPI is in busy status. + * | | |In FIFO mode, this bit will be controlled by hardware. + * | | |Software should not modify this bit. + * | | |In Slave mode, this bit always returns 1 when this register is read by software. + * | | |In Master mode, this bit reflects the busy or idle status of SPI. + * | | |Note: + * | | |1. When FIFO mode is disabled, all configurations should be set before writing 1 to this + * | | |GO_BUSY bit. + * | | |2. When FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, + * | | |this bit + * | | | will be cleared after the PDMA finishes the data transfer. + * |[1] |RX_NEG |Receive On Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TX_NEG |Transmit On Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[7:3] |TX_BIT_LEN|Transmit Bit Length + * | | |This field specifies how many bits can be transmitted / received in one transaction. + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |TX_BIT_LEN = 0x08 ... 8 bits. + * | | |TX_BIT_LEN = 0x09 ... 9 bits. + * | | |...... + * | | |TX_BIT_LEN = 0x1F ... 31 bits. + * | | |TX_BIT_LEN = 0x00 ... 32 bits. + * |[10] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is + * | | |transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and + * | | |the first bit received from + * | | | the SPI data input pin will be put in the LSB position of the RX register (bit 0 of + * | | |SPI_RX0/1). + * |[11] |CLKP |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[15:12] |SP_CYCLE |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive + * | | |transaction in a transfer. + * | | |The definition of the suspend interval is the interval between the last clock edge of the + * | | |preceding transaction word + * | | |and the first clock edge of the following transaction word. + * | | |The default value is 0x3. + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle + * | | |Example: + * | | |SP_CYCLE = 0x0 ... 0.5 SPI bus clock cycle. + * | | |SP_CYCLE = 0x1 ... 1.5 SPI bus clock cycle. + * | | |...... + * | | |SP_CYCLE = 0xE ... 14.5 SPI bus clock cycle. + * | | |SP_CYCLE = 0xF ... 15.5 SPI bus clock cycle. + * | | |If the variable clock function is enabled and the transmit FIFO buffer is not empty, the + * | | |minimum period of suspend + * | | |interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle. + * |[16] |IF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to itself. + * |[17] |IE |Unit Transfer Interrupt Enable + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Enable + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled. + * | | |A byte suspend interval will be inserted among each byte. + * | | |The period of the byte suspend interval depends on the setting of SP_CYCLE. + * | | |Note: + * | | |1. Byte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits. + * | | |2. In Slave mode with level-trigger configuration, the slave select pin must be kept at + * | | |active state during the + * | | | byte suspend interval. + * | | |3. The Byte Reorder function is not supported when the variable bus clock function or Dual + * | | |I/O mode is enabled. + * |[21] |FIFO |FIFO Mode Enable + * | | |0 = FIFO mode Disabled. + * | | |1 = FIFO mode Enabled. + * | | |Note: + * | | |1. Before enabling FIFO mode, the other related settings should be set in advance. + * | | |2. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 + * | | |automatically after writing data + * | | | to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the + * | | |SPI controller is in idle. + * | | | If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 + * | | |and the GO_BUSY bit will be cleared to 0. + * | | |3. After clearing this bit to 0, user must wait for at least 2 peripheral clock periods + * | | |before setting this bit to 1 again. + * |[22] |TWOB |2-Bit Transfer Mode Enable + * | | |0 = 2-bit Transfer mode Disabled. + * | | |1 = 2-bit Transfer mode Enabled. + * | | |Note: When 2-bit Transfer mode is enabled, the serial transmitted 2-bit data are from + * | | |SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. + * |[23] |VARCLK_EN |Variable Clock Enable (Master Only) + * | | |0 = SPI clock output frequency is fixed and decided only by the value of DIVIDER. + * | | |1 = SPI clock output frequency is variable. + * | | |The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2. + * | | |Note: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as + * | | |0x10 (16-bit mode). + * |[24] |RX_EMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_STATUS[24]. + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[25] |RX_FULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_STATUS[25]. + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[26] |TX_EMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_STATUS[26]. + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[27] |TX_FULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_STATUS[27]. + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * @var SPI_T::DIVIDER + * Offset: 0x04 Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DIVIDER |Clock Divider 1 Register + * | | |The value in this field is the frequency divider for generating the SPI peripheral clock and + * | | |the SPI bus clock of SPI master. + * | | |The frequency is obtained according to the following equation. + * | | |If the bit of BCn, SPI_CNTRL2[31], is set to 0, + * | | | SPI peripheral clock frequency = system clock frequency / (DIVIDER + 1) / 2 + * | | |else if BCn is set to 1, + * | | | SPI peripheral clock frequency = SPI peripheral clock source frequency / (DIVIDER + 1) + * | | |The SPI peripheral clock source is defined in the CLKSEL1 register. + * |[23:16] |DIVIDER2 |Clock Divider 2 Register (Master Only) + * | | |The value in this field is the 2nd frequency divider for generating the second clock of the + * | | |variable clock function. + * | | |The frequency is obtained according to the following equation: + * | | | f_clk2 = SPI peripheral clock frequency / (DIVIDER2 + 1) / 2 + * | | |If the VARCLK_EN bit is cleared to 0, this setting is unmeaning. + * @var SPI_T::SSR + * Offset: 0x08 Slave Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SSR |Slave Select Control Bits (Master Only) + * | | |If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPIn_SPISS0/1 + * | | |line to an active state and writing 0 sets the line back to inactive state. + * | | |If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the + * | | |corresponding + * | | |SPIn_SPISS0/1 line at inactive state; writing 1 to any bit location of this field will + * | | |select + * | | |appropriate SPIn_SPISS0/1 line to be automatically driven to active state for the duration + * | | |of the + * | | |transmit/receive, and will be driven to inactive state for the rest of the time. + * | | |The active state of SPIn_SPISS0/1 is specified in SS_LVL. + * | | |Note: SPIn_SPISS0 is defined as the slave select input in Slave mode. + * |[2] |SS_LVL |Slave Select Active Level + * | | |This bit defines the active status of slave select signal (SPIn_SPISS0/1). + * | | |0 = The slave select signal SPIn_SPISS0/1 is active on low-level/falling-edge. + * | | |1 = The slave select signal SPIn_SPISS0/1 is active on high-level/rising-edge. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = If this bit is cleared, slave select signals will be asserted/de-asserted by setting + * | | |/clearing + * | | | the corresponding bits of SPI_SSR[1:0]. + * | | |1 = If this bit is set, SPIn_SPISS0/1 signals will be generated automatically. + * | | | It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by + * | | |the + * | | | SPI controller when transmit/receive is started, and will be de-asserted after each + * | | |transmit/receive is finished. + * |[4] |SS_LTRIG |Slave Select Level Trigger Enable (Slave Only) + * | | |0 = Slave select signal is edge-trigger. + * | | | This is the default value. + * | | | The SS_LVL bit decides the signal is active after a falling-edge or rising-edge. + * | | |1 = Slave select signal is level-trigger. + * | | | The SS_LVL bit decides the signal is active low or active high. + * |[5] |LTRIG_FLAG|Level Trigger Accomplish Flag + * | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or + * | | |not after the current transaction done. + * | | |0 = Transferred bit length of one transaction does not meet the specified requirement. + * | | |1 = Transferred bit length meets the specified requirement which defined in TX_BIT_LEN. + * | | |Note: This bit is READ only. + * | | |As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI + * | | |peripheral clock periods plus 1 system clock period. + * | | |In FIFO mode, this bit has no meaning. + * @var SPI_T::RX + * Offset: 0x10 Data Receive Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |The data receive register holds the datum received from SPI data input pin. + * | | |If FIFO mode is disabled, the last received data can be accessed through software by reading + * | | |this register. + * | | |If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not + * | | |set to 1, the receive + * | | |FIFO buffer can be accessed through software by reading this register. This is a read-only + * | | |register. + * @var SPI_T::TX + * Offset: 0x20 Data Transmit Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers hold the data to be transmitted in the next transfer. + * | | |The number of valid bits depends on the setting of transmit bit length field of the + * | | |SPI_CNTRL register. + * | | |For example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next + * | | |transfer. + * | | |If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer. + * | | |Note 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, + * | | |if the SPI + * | | | controller attempts to transmit data to a master, the transmit data register should be + * | | |updated + * | | | by software before setting the GO_BUSY bit to 1. + * | | |Note 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock + * | | |cycles after user writes to this register. + * @var SPI_T::VARCLK + * Offset: 0x34 Variable Clock Pattern Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VARCLK |Variable Clock Pattern + * | | |This register defines the clock pattern of the SPI transfer. + * | | |If the variable clock function is disabled, this setting is unmeaning. + * @var SPI_T::DMA + * Offset: 0x38 SPI DMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TX_DMA_GO |Transmit DMA Start + * | | |Setting this bit to 1 will start the transmit PDMA process. + * | | |SPI controller will issue request to PDMA controller automatically. + * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done. + * | | |If the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be + * | | |set to 1 by software. + * | | |The PDMA control logic of SPI controller will set it automatically whenever necessary. + * | | |In Slave mode and when FIFO mode is disabled, the minimal suspend interval between two + * | | |successive transactions + * | | |must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or + * | | |(9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. + * | | |If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above + * | | |conditions is required. + * |[1] |RX_DMA_GO |Receive DMA Start + * | | |Setting this bit to 1 will start the receive PDMA process. + * | | |The SPI controller will issue request to PDMA controller automatically when the SPI receive + * | | |buffer is not empty. + * | | |This bit will be cleared to 0 by hardware automatically after PDMA transfer is done. + * | | |If the software uses the receive PDMA function to access the received data of SPI and does + * | | |not use the transmit + * | | |PDMA function, the GO_BUSY bit should be set by software. + * | | |Enabling FIFO mode is recommended if the software uses more than one PDMA channel to + * | | |transfer data. + * | | |In Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for + * | | |SPI receive PDMA + * | | |function and the other PDMA channels are not in use, the minimal suspend interval between + * | | |two successive + * | | |transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock + * | | |periods) for Edge-trigger + * | | |mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger + * | | |mode. + * |[2] |PDMA_RST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 + * | | |automatically. + * @var SPI_T::CNTRL2 + * Offset: 0x3C Control and Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |NOSLVSEL |Slave 3-Wire Mode Enable + * | | |This is used to ignore the slave select signal in Slave mode. + * | | |The SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO, and + * | | |SPIn_MOSI. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * | | |Note: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. + * |[9] |SLV_ABORT |Slave 3-Wire Mode Abort Control + * | | |In normal operation, there is an interrupt event when the received data meet the required + * | | |bits which defined in TX_BIT_LEN. + * | | |If the received bits are less than the requirement and there is no more SPI clock input over + * | | |the one transfer time in + * | | |Slave 3-wire mode, the user can set this bit to force the current transfer done and then the + * | | |user can get a transfer done interrupt event. + * | | |Note: This bit will be cleared to 0 automatically by hardware after it is set to 1 by + * | | |software. + * |[10] |SSTA_INTEN|Slave 3-Wire Mode Start Interrupt Enable + * | | |Used to enable interrupt when the transfer has started in Slave 3-wire mode. + * | | |If there is no transfer done interrupt over the time period which is defined by user after + * | | |the transfer start, + * | | |the user can set the SLV_ABORT bit to force the transfer done. + * | | |0 = Transaction start interrupt Disabled. + * | | |1 = Transaction start interrupt Enabled. + * | | |It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is + * | | |cleared. + * |[11] |SLV_START_INTSTS|Slave 3-Wire Mode Start Interrupt Status + * | | |This bit indicates if a transaction has started in Slave 3-wire mode. + * | | |It is a mutual mirror bit of SPI_STATUS[11]. + * | | |0 = Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. + * | | |1 = A transaction has started in Slave 3-wire mode. + * | | |It will be cleared automatically when a transaction is done or by writing 1 to this bit. + * |[12] |DUAL_IO_DIR|Dual I/O Mode Direction Control + * | | |0 = Dual Input mode. + * | | |1 = Dual Output mode. + * |[13] |DUAL_IO_EN|Dual I/O Mode Enable + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[16] |SS_INT_OPT|Slave Select Inactive Interrupt Option + * | | |This setting is only available if the SPI controller is configured as level trigger slave + * | | |device. + * | | |0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1. + * | | |1 = As the slave select signal goes to inactive level, the IF bit will be set to 1. + * |[31] |BCn |SPI Peripheral Clock Backward Compatible Option + * | | |0 = Backward compatible clock configuration. + * | | |1 = Clock configuration is not backward compatible. + * | | |Refer to the description of SPI_DIVIDER register for details. + * @var SPI_T::FIFO_CTL + * Offset: 0x40 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RX_CLR |Clear Receive FIFO Buffer + * | | |0 = No effect. + * | | |1 = Clear receive FIFO buffer. + * | | |The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. + * | | |This bit will be cleared to 0 by hardware after it is set to 1 by software. + * |[1] |TX_CLR |Clear Transmit FIFO Buffer + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO buffer. + * | | |The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. + * | | |This bit will be cleared to 0 by hardware after it is set to 1 by software. + * |[2] |RX_INTEN |Receive Threshold Interrupt Enable + * | | |0 = RX threshold interrupt Disabled. + * | | |1 = RX threshold interrupt Enabled. + * |[3] |TX_INTEN |Transmit Threshold Interrupt Enable + * | | |0 = TX threshold interrupt Disabled. + * | | |1 = TX threshold interrupt Enabled. + * |[6] |RXOV_INTEN|Receive FIFO Overrun Interrupt Enable + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[21] |TIMEOUT_INTEN|Receive FIFO Time-Out Interrupt Enable + * | | |0 = Time-out interrupt Disabled. + * | | |1 = Time-out interrupt Enabled. + * |[26:24] |RX_THRESHOLD|Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, + * | | |the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. + * |[30:28] |TX_THRESHOLD|Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the + * | | |TX_THRESHOLD + * | | |setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. + * @var SPI_T::STATUS + * Offset: 0x44 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RX_INTSTS |Receive FIFO Threshold Interrupt Status (Read Only) + * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting + * | | |value of RX_THRESHOLD. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of + * | | |RX_THRESHOLD. + * | | |Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt + * | | |request. + * |[2] |RX_OVERRUN|Receive FIFO Overrun Status + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will + * | | |be set to 1. + * | | |Note: This bit will be cleared by writing 1 to itself. + * |[4] |TX_INTSTS |Transmit FIFO Threshold Interrupt Status (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of + * | | |TX_THRESHOLD. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the + * | | |setting value of TX_THRESHOLD. + * | | |Note: If TX_INTEN = 1 and TX_INTSTS = 1, the SPI controller will generate a SPI interrupt + * | | |request. + * |[11] |SLV_START_INTSTS|Slave Start Interrupt Status + * | | |It is used to dedicate if a transaction has started in Slave 3-wire mode. + * | | |It is a mutual mirror bit of SPI_CNTRL2[11]. + * | | |0 = Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. + * | | |1 = A transaction has started in Slave 3-wire mode. + * | | |It will be cleared as a transaction is done or by writing 1 to this bit. + * |[15:12] |RX_FIFO_COUNT|Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[16] |IF |SPI Unit Transfer Interrupt Flag + * | | |It is a mutual mirror bit of SPI_CNTRL[16]. + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to itself. + * |[20] |TIMEOUT |Time-Out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 + * | | |SPI clock + * | | |period in Master mode or over 576 SPI peripheral clock period in Slave mode. + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared + * | | |automatically. + * | | |Note: This bit will be cleared by writing 1 to itself. + * |[24] |RX_EMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_CNTRL[24]. + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[25] |RX_FULL |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_CNTRL[25]. + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[26] |TX_EMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_CNTRL[26]. + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[27] |TX_FULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |It is a mutual mirror bit of SPI_CNTRL[27]. + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[31:28] |TX_FIFO_COUNT|Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + + __IO uint32_t CNTRL; /* Offset: 0x00 Control and Status Register */ + __IO uint32_t DIVIDER; /* Offset: 0x04 Clock Divider Register */ + __IO uint32_t SSR; /* Offset: 0x08 Slave Select Register */ + __I uint32_t RESERVE0; + __I uint32_t RX[2]; /* Offset: 0x10 Data Receive Register */ + __I uint32_t RESERVE1; + __I uint32_t RESERVE2; + __O uint32_t TX[2]; /* Offset: 0x20 Data Transmit Register 0 */ + __I uint32_t RESERVE3; + __I uint32_t RESERVE4; + __I uint32_t RESERVE5; + __IO uint32_t VARCLK; /* Offset: 0x34 Variable Clock Pattern Register */ + __IO uint32_t DMA; /* Offset: 0x38 SPI DMA Control Register */ + __IO uint32_t CNTRL2; /* Offset: 0x3C Control and Status Register 2 */ + __IO uint32_t FIFO_CTL; /* Offset: 0x40 SPI FIFO Control Register */ + __IO uint32_t STATUS; /* Offset: 0x44 SPI Status Register */ + +} SPI_T; + + + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +/* SPI_CNTRL Bit Field Definitions */ +#define SPI_CNTRL_TX_FULL_Pos 27 /*!< SPI_T::CNTRL: TX_FULL Position */ +#define SPI_CNTRL_TX_FULL_Msk (1ul << SPI_CNTRL_TX_FULL_Pos) /*!< SPI_T::CNTRL: TX_FULL Mask */ + +#define SPI_CNTRL_TX_EMPTY_Pos 26 /*!< SPI_T::CNTRL: TX_EMPTY Position */ +#define SPI_CNTRL_TX_EMPTY_Msk (1ul << SPI_CNTRL_TX_EMPTY_Pos) /*!< SPI_T::CNTRL: TX_EMPTY Mask */ + +#define SPI_CNTRL_RX_FULL_Pos 25 /*!< SPI_T::CNTRL: RX_FULL Position */ +#define SPI_CNTRL_RX_FULL_Msk (1ul << SPI_CNTRL_RX_FULL_Pos) /*!< SPI_T::CNTRL: RX_FULL Mask */ + +#define SPI_CNTRL_RX_EMPTY_Pos 24 /*!< SPI_T::CNTRL: RX_EMPTY Position */ +#define SPI_CNTRL_RX_EMPTY_Msk (1ul << SPI_CNTRL_RX_EMPTY_Pos) /*!< SPI_T::CNTRL: RX_EMPTY Mask */ + +#define SPI_CNTRL_VARCLK_EN_Pos 23 /*!< SPI_T::CNTRL: VARCLK_EN Position */ +#define SPI_CNTRL_VARCLK_EN_Msk (1ul << SPI_CNTRL_VARCLK_EN_Pos) /*!< SPI_T::CNTRL: VARCLK_EN Mask */ + +#define SPI_CNTRL_TWOB_Pos 22 /*!< SPI_T::CNTRL: TWOB Position */ +#define SPI_CNTRL_TWOB_Msk (1ul << SPI_CNTRL_TWOB_Pos) /*!< SPI_T::CNTRL: TWOB Mask */ + +#define SPI_CNTRL_FIFO_Pos 21 /*!< SPI_T::CNTRL: FIFO Position */ +#define SPI_CNTRL_FIFO_Msk (1ul << SPI_CNTRL_FIFO_Pos) /*!< SPI_T::CNTRL: FIFO Mask */ + +#define SPI_CNTRL_REORDER_Pos 19 /*!< SPI_T::CNTRL: REORDER Position */ +#define SPI_CNTRL_REORDER_Msk (1ul << SPI_CNTRL_REORDER_Pos) /*!< SPI_T::CNTRL: REORDER Mask */ + +#define SPI_CNTRL_SLAVE_Pos 18 /*!< SPI_T::CNTRL: SLAVE Position */ +#define SPI_CNTRL_SLAVE_Msk (1ul << SPI_CNTRL_SLAVE_Pos) /*!< SPI_T::CNTRL: SLAVE Mask */ + +#define SPI_CNTRL_IE_Pos 17 /*!< SPI_T::CNTRL: IE Position */ +#define SPI_CNTRL_IE_Msk (1ul << SPI_CNTRL_IE_Pos) /*!< SPI_T::CNTRL: IE Mask */ + +#define SPI_CNTRL_IF_Pos 16 /*!< SPI_T::CNTRL: IF Position */ +#define SPI_CNTRL_IF_Msk (1ul << SPI_CNTRL_IF_Pos) /*!< SPI_T::CNTRL: IF Mask */ + +#define SPI_CNTRL_SP_CYCLE_Pos 12 /*!< SPI_T::CNTRL: SP_CYCLE Position */ +#define SPI_CNTRL_SP_CYCLE_Msk (0xFul << SPI_CNTRL_SP_CYCLE_Pos) /*!< SPI_T::CNTRL: SP_CYCLE Mask */ + +#define SPI_CNTRL_CLKP_Pos 11 /*!< SPI_T::CNTRL: CLKP Position */ +#define SPI_CNTRL_CLKP_Msk (1ul << SPI_CNTRL_CLKP_Pos) /*!< SPI_T::CNTRL: CLKP Mask */ + +#define SPI_CNTRL_LSB_Pos 10 /*!< SPI_T::CNTRL: LSB Position */ +#define SPI_CNTRL_LSB_Msk (1ul << SPI_CNTRL_LSB_Pos) /*!< SPI_T::CNTRL: LSB Mask */ + +#define SPI_CNTRL_TX_BIT_LEN_Pos 3 /*!< SPI_T::CNTRL: TX_BIT_LEN Position */ +#define SPI_CNTRL_TX_BIT_LEN_Msk (0x1Ful << SPI_CNTRL_TX_BIT_LEN_Pos) /*!< SPI_T::CNTRL: TX_BIT_LEN Mask */ + +#define SPI_CNTRL_TX_NEG_Pos 2 /*!< SPI_T::CNTRL: TX_NEG Position */ +#define SPI_CNTRL_TX_NEG_Msk (1ul << SPI_CNTRL_TX_NEG_Pos) /*!< SPI_T::CNTRL: TX_NEG Mask */ + +#define SPI_CNTRL_RX_NEG_Pos 1 /*!< SPI_T::CNTRL: RX_NEG Position */ +#define SPI_CNTRL_RX_NEG_Msk (1ul << SPI_CNTRL_RX_NEG_Pos) /*!< SPI_T::CNTRL: RX_NEG Mask */ + +#define SPI_CNTRL_GO_BUSY_Pos 0 /*!< SPI_T::CNTRL: GO_BUSY Position */ +#define SPI_CNTRL_GO_BUSY_Msk (1ul << SPI_CNTRL_GO_BUSY_Pos) /*!< SPI_T::CNTRL: GO_BUSY Mask */ + +/* SPI_DIVIDER Bit Field Definitions */ +#define SPI_DIVIDER_DIVIDER2_Pos 16 /*!< SPI_T::DIVIDER: DIVIDER2 Position */ +#define SPI_DIVIDER_DIVIDER2_Msk (0xFFul << SPI_DIVIDER_DIVIDER2_Pos) /*!< SPI_T::DIVIDER: DIVIDER2 Mask */ + +#define SPI_DIVIDER_DIVIDER_Pos 0 /*!< SPI_T::DIVIDER: DIVIDER Position */ +#define SPI_DIVIDER_DIVIDER_Msk (0xFFul << SPI_DIVIDER_DIVIDER_Pos) /*!< SPI_T::DIVIDER: DIVIDER Mask */ + +/* SPI_SSR Bit Field Definitions */ +#define SPI_SSR_LTRIG_FLAG_Pos 5 /*!< SPI_T::SSR: LTRIG_FLAG Position */ +#define SPI_SSR_LTRIG_FLAG_Msk (1ul << SPI_SSR_LTRIG_FLAG_Pos) /*!< SPI_T::SSR: LTRIG_FLAG Mask */ + +#define SPI_SSR_SS_LTRIG_Pos 4 /*!< SPI_T::SSR: SS_LTRIG Position */ +#define SPI_SSR_SS_LTRIG_Msk (1ul << SPI_SSR_SS_LTRIG_Pos) /*!< SPI_T::SSR: SS_LTRIG Mask */ + +#define SPI_SSR_AUTOSS_Pos 3 /*!< SPI_T::SSR: AUTOSS Position */ +#define SPI_SSR_AUTOSS_Msk (1ul << SPI_SSR_AUTOSS_Pos) /*!< SPI_T::SSR: AUTOSS Mask */ + +#define SPI_SSR_SS_LVL_Pos 2 /*!< SPI_T::SSR: SS_LVL Position */ +#define SPI_SSR_SS_LVL_Msk (1ul << SPI_SSR_SS_LVL_Pos) /*!< SPI_T::SSR: SS_LVL Mask */ + +#define SPI_SSR_SSR_Pos 0 /*!< SPI_T::SSR: SSR Position */ +#define SPI_SSR_SSR_Msk (3ul << SPI_SSR_SSR_Pos) /*!< SPI_T::SSR: SSR Mask */ + +/* SPI_DMA Bit Field Definitions */ +#define SPI_DMA_PDMA_RST_Pos 2 /*!< SPI_T::DMA: PDMA_RST Position */ +#define SPI_DMA_PDMA_RST_Msk (1ul << SPI_DMA_PDMA_RST_Pos) /*!< SPI_T::DMA: PDMA_RST Mask */ + +#define SPI_DMA_RX_DMA_GO_Pos 1 /*!< SPI_T::DMA: RX_DMA_GO Position */ +#define SPI_DMA_RX_DMA_GO_Msk (1ul << SPI_DMA_RX_DMA_GO_Pos) /*!< SPI_T::DMA: RX_DMA_GO Mask */ + +#define SPI_DMA_TX_DMA_GO_Pos 0 /*!< SPI_T::DMA: TX_DMA_GO Position */ +#define SPI_DMA_TX_DMA_GO_Msk (1ul << SPI_DMA_TX_DMA_GO_Pos) /*!< SPI_T::DMA: TX_DMA_GO Mask */ + +/* SPI_CNTRL2 Bit Field Definitions */ +#define SPI_CNTRL2_BCn_Pos 31 /*!< SPI_T::CNTRL2: BCn Position */ +#define SPI_CNTRL2_BCn_Msk (1ul << SPI_CNTRL2_BCn_Pos) /*!< SPI_T::CNTRL2: BCn Mask */ + +#define SPI_CNTRL2_SS_INT_OPT_Pos 16 /*!< SPI_T::CNTRL2: SS_INT_OPT Position */ +#define SPI_CNTRL2_SS_INT_OPT_Msk (1ul << SPI_CNTRL2_SS_INT_OPT_Pos) /*!< SPI_T::CNTRL2: SS_INT_OPT Mask */ + +#define SPI_CNTRL2_DUAL_IO_EN_Pos 13 /*!< SPI_T::CNTRL2: DUAL_IO_EN Position */ +#define SPI_CNTRL2_DUAL_IO_EN_Msk (1ul << SPI_CNTRL2_DUAL_IO_EN_Pos) /*!< SPI_T::CNTRL2: DUAL_IO_EN Mask */ + +#define SPI_CNTRL2_DUAL_IO_DIR_Pos 12 /*!< SPI_T::CNTRL2: DUAL_IO_DIR Position */ +#define SPI_CNTRL2_DUAL_IO_DIR_Msk (1ul << SPI_CNTRL2_DUAL_IO_DIR_Pos) /*!< SPI_T::CNTRL2: DUAL_IO_DIR Mask */ + +#define SPI_CNTRL2_SLV_START_INTSTS_Pos 11 /*!< SPI_T::CNTRL2: SLV_START_INTSTS Position */ +#define SPI_CNTRL2_SLV_START_INTSTS_Msk (1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos) /*!< SPI_T::CNTRL2: SLV_START_INTSTS Mask */ + +#define SPI_CNTRL2_SSTA_INTEN_Pos 10 /*!< SPI_T::CNTRL2: SSTA_INTEN Position */ +#define SPI_CNTRL2_SSTA_INTEN_Msk (1ul << SPI_CNTRL2_SSTA_INTEN_Pos) /*!< SPI_T::CNTRL2: SSTA_INTEN Mask */ + +#define SPI_CNTRL2_SLV_ABORT_Pos 9 /*!< SPI_T::CNTRL2: SLV_ABORT Position */ +#define SPI_CNTRL2_SLV_ABORT_Msk (1ul << SPI_CNTRL2_SLV_ABORT_Pos) /*!< SPI_T::CNTRL2: SLV_ABORT Mask */ + +#define SPI_CNTRL2_NOSLVSEL_Pos 8 /*!< SPI_T::CNTRL2: NOSLVSEL Position */ +#define SPI_CNTRL2_NOSLVSEL_Msk (1ul << SPI_CNTRL2_NOSLVSEL_Pos) /*!< SPI_T::CNTRL2: NOSLVSEL Mask */ + +/* SPI_FIFO_CTL Bit Field Definitions */ +#define SPI_FIFO_CTL_TX_THRESHOLD_Pos 28 /*!< SPI_T::FIFO_CTL: TX_THRESHOLD Position */ +#define SPI_FIFO_CTL_TX_THRESHOLD_Msk (7ul << SPI_FIFO_CTL_TX_THRESHOLD_Pos) /*!< SPI_T::FIFO_CTL: TX_THRESHOLD Mask */ + +#define SPI_FIFO_CTL_RX_THRESHOLD_Pos 24 /*!< SPI_T::FIFO_CTL: RX_THRESHOLD Position */ +#define SPI_FIFO_CTL_RX_THRESHOLD_Msk (7ul << SPI_FIFO_CTL_RX_THRESHOLD_Pos) /*!< SPI_T::FIFO_CTL: RX_THRESHOLD Mask */ + +#define SPI_FIFO_CTL_TIMEOUT_INTEN_Pos 21 /*!< SPI_T::FIFO_CTL: TIMEOUT_INTEN Position */ +#define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk (1ul << SPI_FIFO_CTL_TIMEOUT_INTEN_Pos) /*!< SPI_T::FIFO_CTL: TIMEOUT_INTEN Mask */ + +#define SPI_FIFO_CTL_RXOV_INTEN_Pos 6 /*!< SPI_T::FIFO_CTL: RXOV_INTEN Position */ +#define SPI_FIFO_CTL_RXOV_INTEN_Msk (1ul << SPI_FIFO_CTL_RXOV_INTEN_Pos) /*!< SPI_T::FIFO_CTL: RXOV_INTEN Mask */ + +#define SPI_FIFO_CTL_TX_INTEN_Pos 3 /*!< SPI_T::FIFO_CTL: TX_INTEN Position */ +#define SPI_FIFO_CTL_TX_INTEN_Msk (1ul << SPI_FIFO_CTL_TX_INTEN_Pos) /*!< SPI_T::FIFO_CTL: TX_INTEN Mask */ + +#define SPI_FIFO_CTL_RX_INTEN_Pos 2 /*!< SPI_T::FIFO_CTL: RX_INTEN Position */ +#define SPI_FIFO_CTL_RX_INTEN_Msk (1ul << SPI_FIFO_CTL_RX_INTEN_Pos) /*!< SPI_T::FIFO_CTL: RX_INTEN Mask */ + +#define SPI_FIFO_CTL_TX_CLR_Pos 1 /*!< SPI_T::FIFO_CTL: TX_CLR Position */ +#define SPI_FIFO_CTL_TX_CLR_Msk (1ul << SPI_FIFO_CTL_TX_CLR_Pos) /*!< SPI_T::FIFO_CTL: TX_CLR Mask */ + +#define SPI_FIFO_CTL_RX_CLR_Pos 0 /*!< SPI_T::FIFO_CTL: RX_CLR Position */ +#define SPI_FIFO_CTL_RX_CLR_Msk (1ul << SPI_FIFO_CTL_RX_CLR_Pos) /*!< SPI_T::FIFO_CTL: RX_CLR Mask */ + +/* SPI_STATUS Bit Field Definitions */ +#define SPI_STATUS_TX_FIFO_COUNT_Pos 28 /*!< SPI_T::STATUS: TX_FIFO_COUNT Position */ +#define SPI_STATUS_TX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_TX_FIFO_COUNT_Pos) /*!< SPI_T::STATUS: TX_FIFO_COUNT Mask */ + +#define SPI_STATUS_TX_FULL_Pos 27 /*!< SPI_T::STATUS: TX_FULL Position */ +#define SPI_STATUS_TX_FULL_Msk (1ul << SPI_STATUS_TX_FULL_Pos) /*!< SPI_T::STATUS: TX_FULL Mask */ + +#define SPI_STATUS_TX_EMPTY_Pos 26 /*!< SPI_T::STATUS: TX_EMPTY Position */ +#define SPI_STATUS_TX_EMPTY_Msk (1ul << SPI_STATUS_TX_EMPTY_Pos) /*!< SPI_T::STATUS: TX_EMPTY Mask */ + +#define SPI_STATUS_RX_FULL_Pos 25 /*!< SPI_T::STATUS: RX_FULL Position */ +#define SPI_STATUS_RX_FULL_Msk (1ul << SPI_STATUS_RX_FULL_Pos) /*!< SPI_T::STATUS: RX_FULL Mask */ + +#define SPI_STATUS_RX_EMPTY_Pos 24 /*!< SPI_T::STATUS: RX_EMPTY Position */ +#define SPI_STATUS_RX_EMPTY_Msk (1ul << SPI_STATUS_RX_EMPTY_Pos) /*!< SPI_T::STATUS: RX_EMPTY Mask */ + +#define SPI_STATUS_TIMEOUT_Pos 20 /*!< SPI_T::STATUS: TIMEOUT Position */ +#define SPI_STATUS_TIMEOUT_Msk (1ul << SPI_STATUS_TIMEOUT_Pos) /*!< SPI_T::STATUS: TIMEOUT Mask */ + +#define SPI_STATUS_IF_Pos 16 /*!< SPI_T::STATUS: IF Position */ +#define SPI_STATUS_IF_Msk (1ul << SPI_STATUS_IF_Pos) /*!< SPI_T::STATUS: IF Mask */ + +#define SPI_STATUS_RX_FIFO_COUNT_Pos 12 /*!< SPI_T::STATUS: RX_FIFO_COUNT Position */ +#define SPI_STATUS_RX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_RX_FIFO_COUNT_Pos) /*!< SPI_T::STATUS: RX_FIFO_COUNT Mask */ + +#define SPI_STATUS_SLV_START_INTSTS_Pos 11 /*!< SPI_T::STATUS: SLV_START_INTSTS Position */ +#define SPI_STATUS_SLV_START_INTSTS_Msk (1ul << SPI_STATUS_SLV_START_INTSTS_Pos) /*!< SPI_T::STATUS: SLV_START_INTSTS Mask */ + +#define SPI_STATUS_TX_INTSTS_Pos 4 /*!< SPI_T::STATUS: TX_INTSTS Position */ +#define SPI_STATUS_TX_INTSTS_Msk (1ul << SPI_STATUS_TX_INTSTS_Pos) /*!< SPI_T::STATUS: TX_INTSTS Mask */ + +#define SPI_STATUS_RX_OVERRUN_Pos 2 /*!< SPI_T::STATUS: RX_OVERRUN Position */ +#define SPI_STATUS_RX_OVERRUN_Msk (1ul << SPI_STATUS_RX_OVERRUN_Pos) /*!< SPI_T::STATUS: RX_OVERRUN Mask */ + +#define SPI_STATUS_RX_INTSTS_Pos 0 /*!< SPI_T::STATUS: RX_INTSTS Position */ +#define SPI_STATUS_RX_INTSTS_Msk (1ul << SPI_STATUS_RX_INTSTS_Pos) /*!< SPI_T::STATUS: RX_INTSTS Mask */ +/*@}*/ /* end of group SPI_CONST */ +/*@}*/ /* end of group SPI */ + + + + +/*---------------------- System Manger Controller -------------------------*/ +/** + @addtogroup SYS System Manger Controller (SYS) + Memory Mapped Structure for SYS Controller +@{ */ + + + +typedef struct +{ + + + +/** + * @var GCR_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number + * | | |This register reflects device part number code. + * | | |Software can read this register to identify which device is used. + * @var GCR_T::RSTSRC + * Offset: 0x04 System Reset Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RSTS_POR |Power-on Reset Flag + * | | |The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIP_RST (IPRSTC1[0]). + * | | |1 = Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]) had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |RSTS_RESET|Reset Pin Reset Flag + * | | |The RSTS_RESET flag is set by the "Reset Signal" from the /RESET pin to indicate the previous reset source. + * | | |0 = No reset from /RESET pin. + * | | |1 = The Pin /RESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |RSTS_WDT |Watchdog Reset Flag + * | | |The RSTS_WDT flag is set by The "Reset Signal" from the Watchdog Timer to indicate the previous reset source + * | | |0 = No reset from watchdog timer. + * | | |1 = The watchdog timer had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |RSTS_LVR |Low Voltage Reset Flag + * | | |The RSTS_LVR flag Is Set By The "Reset Signal" From The Low-Voltage-Reset Controller To Indicate The Previous Reset Source + * | | |0 = No reset from LVR. + * | | |1 = The LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |RSTS_BOD |Brown-out Detector Reset Flag + * | | |The RSTS_BOD flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |RSTS_SYS |SYS Reset Flag + * | | |The RSTS_SYS flag is set by the "Reset Signal" from the Cortex-M0 kernel to indicate the previous reset source. + * | | |0 = No reset from Cortex-M0. + * | | |1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |RSTS_CPU |CPU Reset Flag + * | | |The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and flash. Memory Controller (FMC) + * | | |0 = No reset from CPU. + * | | |1 = Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST(IPRSTC1[1]) to 1. + * | | |Note: Write 1 to clear this bit to 0. + * @var GCR_T::IPRSTC1 + * Offset: 0x08 IP Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIP_RST |CHIP One-Shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload. + * | | |0 = CHIP normal operation. + * | | |1 = CHIP one-shot reset. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[1] |CPU_RST |CPU Kernel One-Shot Reset (Write Protect) + * | | |Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles. + * | | |0 = CPU normal operation. + * | | |1 = CPU one-shot reset. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[2] |PDMA_RST |PDMA Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA. + * | | |User need to set this bit to 0 to release from reset state. + * | | |0 = PDMA controller normal operation. + * | | |1 = PDMA controller reset. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * @var GCR_T::IPRSTC2 + * Offset: 0x0C IP Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIO_RST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0_RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1_RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2_RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3_RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[8] |I2C0_RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1_RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[12] |SPI0_RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[13] |SPI1_RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[14] |SPI2_RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[15] |SPI3_RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[16] |UART0_RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1_RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2_RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[20] |PWM03_RST |PWM03 Controller Reset + * | | |0 = PWM03 controller normal operation. + * | | |1 = PWM03 controller reset. + * |[21] |PWM47_RST |PWM47 Controller Reset + * | | |0 = PWM47 controller normal operation. + * | | |1 = PWM47 controller reset. + * |[22] |ACMP_RST |Analog Comparator Controller Reset + * | | |0 = Analog Comparator controller normal operation. + * | | |1 = Analog Comparator controller reset. + * |[23] |PS2_RST |PS/2 Controller Reset + * | | |0 = PS/2 controller normal operation. + * | | |1 = PS/2 controller reset. + * |[27] |USBD_RST |USB Device Controller Reset + * | | |0 = USB device controller normal operation. + * | | |1 = USB device controller reset. + * |[28] |ADC_RST |ADC Controller Reset + * | | |0 = ADC controller normal operation. + * | | |1 = ADC controller reset. + * |[29] |I2S_RST |I2S Controller Reset + * | | |0 = I2S controller normal operation. + * | | |1 = I2S controller reset. + * @var GCR_T::IPRSTC3 + * Offset: 0x10 IP Reset Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0_RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1_RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2_RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * @var GCR_T::BODCR + * Offset: 0x18 Brown-out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BOD_EN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash memory controller user configuration register CBODEN (Config0[23]) bit. + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[2:1] |BOD_VL |Brown-Out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (Config0[22:21]) bit. + * | | |00 = Brown-out voltage is 2.2V. + * | | |01 = Brown-out voltage is 2.7V. + * | | |10 = Brown-out voltage is 3.7V. + * | | |11 = Brown-out voltage is 4.4V. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * |[3] |BOD_RSTEN |Brown-out Reset Enable Control (Write Protect) + * | | |0 = Brown-out "INTERRUPT" function Enabled. + * | | |While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. + * | | |BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). + * | | |1 = Brown-out "RESET" function Enabled. + * | | |Note1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). + * | | |Note2: The default value is set by flash controller user configuration register CBORST (Config0[20]) bit. + * | | |Note3: This bit is write protected bit. Refer to the REGWRPROT register. + * |[4] |BOD_INTF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BOD_LPM |Brown-out Detector Low Power Mode (Write Protection) + * | | |0 = BOD operated in Normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note2: This bit is write protected bit. Refer to the REGWRPROT register. + * |[6] |BOD_OUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0. + * | | |1 = Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled, this bit always responds to 0. + * |[7] |LVR_EN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * @var GCR_T::TEMPCR + * Offset: 0x1C Temperature Sensor Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMP_EN |Temperature Sensor Enable Control + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature can be obtained from ADC conversion result. + * | | |Please refer to the EADC function chapter for detail ADC conversion functional description. + * @var GCR_T::PORCR + * Offset: 0x24 Power-on-Reset Controller Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POR_DIS_CODE|Power-on Reset Enable Control (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected bit. Refer to the REGWRPROT register. + * @var GCR_T::GPA_MFP + * Offset: 0x30 GPIOA Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPA_MFP0 |PA.0 Pin Function Selection + * | | |Bits PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] determine the PA.0 function. + * | | |(PA0_SC0PWR, GPA_MFP0) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC0 function is selected. + * | | |(1, 1) = SC0_PWR function is selected. + * |[1] |GPA_MFP1 |PA.1 Pin Function Selection + * | | |Bit PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] determine the PA.1 function. + * | | |(PA1_SC0RST, GPA_MFP1) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC1 function is selected. + * | | |(1, 1) = SC0_RST function is selected. + * |[2] |GPA_MFP2 |PA.2 Pin Function Selection + * | | |Bits PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] determine the PA.2 function. + * | | |(PA2_SC0CLK, GPA_MFP2) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC2 function is selected. + * | | |(1, 1) = SC0_CLK function is selected. + * |[3] |GPA_MFP3 |PA.3 Pin Function Selection + * | | |Bits PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] determine the PA.3 function. + * | | |(PA3_SC0DAT, GPA_MFP3) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC3 function is selected. + * | | |(1, 1) = SC0_DAT function is selected. + * |[4] |GPA_MFP4 |PA.4 Pin Function Selection + * | | |Bits PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] determine the PA.4 function. + * | | |(PA4_SC1PWR, GPA_MFP4) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC4 function is selected. + * | | |(1, 1) = SC1_PWR function is selected. + * |[5] |GPA_MFP5 |PA.5 Pin Function Selection + * | | |Bits PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function. + * | | |(PA5_SC1RST, GPA_MFP5) value and function mapping is as following list, + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC5 function is selected. + * | | |(1, 1) = SC1_RST function is selected. + * |[6] |GPA_MFP6 |PA.6 Pin Function Selection + * | | |Bits PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] determine the PA.6 function. + * | | |(PA6_SC1CLK, GPA_MFP6) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC6 function is selected. + * | | |(1, 1) = SC1_CLK function is selected. + * |[7] |GPA_MFP7 |PA.7 Pin Function Selection + * | | |Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function. + * | | |(PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = ADC7 function is selected. + * | | |(0, 1, 1) = SPI2_SS1 function is selected. + * | | |(1, 0, 1) = SC1_DAT function is selected. + * |[8] |GPA_MFP8 |PA.8 Pin Function Selection + * | | |Bit GPA_MFP[8] determines the PA.8 function. + * | | |0 = GPIO function is selected to the pin PA.8. + * | | |1 = I2C0_SDA function is selected to the pin PA.8. + * |[10] |GPA_MFP9 |PA.9 Pin Function Selection + * | | |Bit GPA_MFP[9] determines the PA.9 function. + * | | |0 = GPIO function is selected to the pin PA.9. + * | | |1 = I2C0_SCL function is selected to the pin PA.9. + * |[10] |GPA_MFP10 |PA.10 Pin Function Selection + * | | |Bit GPA_MFP[10] determine the PA.10 function. + * | | |0 = GPIO function is selected to the pin PA.10. + * | | |1 = I2C1_SDA function is selected to the pin PA.10. + * |[11] |GPA_MFP11 |PA.11 Pin Function Selection + * | | |Bit GPA_MFP[11] determine the PA.11 function. + * | | |0 = GPIO function is selected to the pin PA.11. + * | | |1 = I2C1_SCL function is selected to the pin PA.11. + * |[12] |GPA_MFP12 |PA.12 Pin Function Selection + * | | |Bits PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] determine the PA.12 function. + * | | |(PA12_SC2DAT, GPA_MFP12) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM0 function is selected. + * | | |(1, 1) = SC2_DAT function is selected. + * |[13] |GPA_MFP13 |PA.13 Pin Function Selection + * | | |Bits PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] determine the PA.13 function. + * | | |(PA13_SC2CLK, GPA_MFP13) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM1 function is selected. + * | | |(1, 1) = SC2_CLK function is selected. + * |[14] |GPA_MFP14 |PA.14 Pin Function Selection + * | | |Bits PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] determine the PA.14 function. + * | | |(PA14_SC2RST, GPA_MFP14) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM2 function is selected. + * | | |(1, 1) = SC2_RST function is selected. + * |[15] |GPA_MFP15 |PA.15 Pin Function Selection + * | | |Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function. + * | | |(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = PWM3 function is selected. + * | | |(0, 1, 1) = I2S_MCLK function is selected. + * | | |(1, 0, 1) = SC2_PWR function is selected. + * |[16:31] |GPA_TYPEn |Trigger Function Selection + * | | |0 = GPIOA[15:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOA[15:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::GPB_MFP + * Offset: 0x34 GPIOB Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPB_MFP0 |PB.0 Pin Function Selection + * | | |Bit GPB_MFP[0] determines the PB.0 function. + * | | |0 = GPIO function is selected to the pin PB.0. + * | | |1 = UART0_RXD function is selected to the pin PB.0. + * |[1] |GPB_MFP1 |PB.1 Pin Function Selection + * | | |Bit GPB_MFP[1] determines the PB.1 function. + * | | |0 = GPIO function is selected to the pin PB.1. + * | | |1 = UART0_TXD function is selected to the pin PB.1. + * |[2] |GPB_MFP2 |PB.2 Pin Function Selection + * | | |Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function. + * | | |(PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nRTS function is selected. + * | | |(0, 1, 1) = TM2_EXT function is selected. + * | | |(1, 0, 1) = ACMP0_O function is selected. + * |[3] |GPB_MFP3 |PB.3 Pin Function Selection + * | | |Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. + * | | |(PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nCTS function is selected. + * | | |(0, 1, 1) = TM3_EXT function is selected. + * | | |(1, 0, 1) = SC2_CD function is selected. + * |[4] |GPB_MFP4 |PB.4 Pin Function Selection + * | | |Bit GPB_MFP[4] determines the PB.4 function. + * | | |0 = GPIO function is selected to the pin PB.4. + * | | |1 = UART1_RXD function is selected to the pin PB.4. + * |[5] |GPB_MFP5 |PB 5 Pin Function Selection + * | | |Bit GPB_MFP[5] determines the PB.5 function. + * | | |0 = GPIO function is selected to the pin PB.5. + * | | |1 = UART1_TXD function is selected to the pin PB.5. + * |[6] |GPB_MFP6 |PB.6 Pin Function Selection + * | | |Bit GPB_MFP[6] determines the PB.6 function. + * | | |0 = GPIO function is selected to the pin PB.6. + * | | |1 = UART1_nRTS function is selected to the pin PB.6. + * |[7] |GPB_MFP7 |PB.7 Pin Function Selection + * | | |Bit GPB_MFP[7] determines the PB.7 function. + * | | |0 = GPIO function is selected to the pin PB.7. + * | | |1 = UART1_nCTS function is selected to the pin PB.7. + * |[8] |GPB_MFP8 |PB.8 Pin Function Selection + * | | |Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function. + * | | |(PB8_CLKO, GPB_MFP8) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM0 function is selected. + * | | |(1, 1) = CLKO function is selected. + * |[9] |GPB_MFP9 |PB.9 Pin Function Selection + * | | |Bits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function. + * | | |(PB9_S11, GPB_MFP9) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM1 function is selected. + * | | |(1, 1) = SPI1_SS1 function is selected. + * |[10] |GPB_MFP10 |PB.10 Pin Function Selection + * | | |Bits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function. + * | | |(PB10_S01, GPB_MFP10) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM2 function is selected. + * | | |(1, 1) = SPI0_SS1 function is selected. + * |[11] |GPB_MFP11 |PB.11 Pin Function Selection + * | | |Bits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function. + * | | |(PB11_PWM4, GPB_MFP11) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM3 function is selected. + * | | |(1, 1) = PWM4 function is selected. + * |[13] |GPB_MFP13 |PB.13 Pin Function Selection + * | | |Bit GPB_MFP[13] determines the PB.13 function. + * | | |0 = GPIO function is selected. + * | | |1 = ACMP1_O function is selected. + * |[14] |GPB_MFP14 |PB.14 Pin Function Selection + * | | |Bits PB14_S31 (ALT_MFP[3]) and GPB_MFP[14] determine the PB.14 function. + * | | |(PB14_S31, GPB_MFP14) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = INT0 function is selected. + * | | |(1, 1) = SPI3_SS1 function is selected. + * |[15] |GPB_MFP15 |PB.15 Pin Function Selection + * | | |Bits PB15_T0EX (ALT_MFP[24]) and GPB_MFP[15] determine the PB.15 function. + * | | |(PB15_T0EX, GPB_MFP15) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = INT1 function is selected. + * | | |(1, 1) = TM0_EXT function is selected. + * |[16:31] |GPB_TYPEn |Trigger Function Selection + * | | |0 = GPIOB[15:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOB[15:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::GPC_MFP + * Offset: 0x38 GPIOC Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPC_MFP0 |PC.0 Pin Function Selection + * | | |Bits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC.0 function. + * | | |(PC0_I2SLRCLK, GPC_MFP0) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_SS0 function is selected. + * | | |(1, 1) = I2S_LRCLK function is selected. + * |[1] |GPC_MFP1 |PC.1 Pin Function Selection + * | | |Bits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function. + * | | |(PC1_I2SBCLK, GPC_MFP1) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_CLK function is selected. + * | | |(1, 1) = I2S_BCLK function is selected. + * |[2] |GPC_MFP2 |PC.2 Pin Function Selection + * | | |Bits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function. + * | | |(PC2_I2SDI, GPC_MFP2) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_MISO0 function is selected. + * | | |(1, 1) = I2S_DI function is selected. + * |[3] |GPC_MFP3 |PC.3 Pin Function Selection + * | | |Bits PC3_I2SDO (ALT_MFP[8]) and GPC_MFP[3] determine the PC.3 function. + * | | |(PC3_I2SDO, GPC_MFP3) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_MOSI0 function is selected. + * | | |(1, 1) = I2S_DO function is selected. + * |[4] |GPC_MFP4 |PC.4 Pin Function Selection + * | | |Bit GPC_MFP[9] determines the PC.4 function. + * | | |0 = GPIO function is selected to the pin PC.4. + * | | |1 = SPI0_MISO1 function is selected to the pin PC.4. + * |[5] |GPC_MFP5 |PC.5 Pin Function Selection + * | | |Bit GPC_MFP[5] determines the PC.5 function. + * | | |0 = GPIO function is selected to the pin PC.5. + * | | |1 = SPI0_MOSI1 function is selected to the pin PC.5. + * |[6] |GPC_MFP6 |PC.6 Pin Function Selection + * | | |Bits PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] determine the PC.6 function. + * | | |(PC6_SC0CD, GPC_MFP6) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ACMP0_P function is selected. + * | | |(1, 1) = SC0_CD function is selected. + * |[7] |GPC_MFP7 |PC.7 Pin Function Selection + * | | |Bits PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] determine the PC.7 function. + * | | |(PC7_SC1CD, GPC_MFP7) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ACMP0_N function is selected. + * | | |(1, 1) = SC1_CD function is selected. + * |[8] |GPC_MFP8 |PC.8 Pin Function Selection + * | | |Bit GPC_MFP[8] determines the PC.8 function. + * | | |0 = GPIO function is selected to the pin PC.8. + * | | |1 = SPI1_SS0 function is selected to the pin PC.8. + * |[9] |GPC_MFP9 |PC.9 Pin Function Selection + * | | |Bit GPC_MFP[9] determines the PC.9 function. + * | | |0 = GPIO function is selected to the pin PC.9. + * | | |1 = SPI1_CLK function is selected to the pin PC.9. + * |[10] |GPC_MFP10 |PC.10 Pin Function Selection + * | | |Bit GPC_MFP[10] determines the PC.10 function. + * | | |0 = GPIO function is selected to the pin PC.10. + * | | |1 = SPI1_MISO0 function is selected to the pin PC.10. + * |[11] |GPC_MFP11 |PC.11 Pin Function Selection + * | | |Bit GPC_MFP[11] determines the PC.11 function. + * | | |0 = GPIO function is selected to the pin PC.11. + * | | |1 = SPI1_MOSI0 function is selected to the pin PC.11. + * |[12] |GPC_MFP12 |PC.12 Pin Function Selection + * | | |Bit GPC_MFP[12] determines the PC.12 function. + * | | |0 = GPIO function is selected to the pin PC.12. + * | | |1 = SPI1_MISO1 function is selected to the pin PC.12. + * |[13] |GPC_MFP13 |PC.13 Pin Function Selection + * | | |Bit GPC_MFP[13] determines the PC.13 function. + * | | |0 = GPIO function is selected to the pin PC.13. + * | | |1 = SPI1_MOSI1 function is selected to the pin PC.13. + * |[14] |GPC_MFP14 |PC.14 Pin Function Selection + * | | |Bit GPC_MFP[14] determines the PC.14 function. + * | | |0 = GPIO function is selected to the pin PC.14. + * | | |1 = ACMP1_P function is selected to the pin PC.14. + * |[15] |GPC_MFP15 |PC.15 Pin Function Selection + * | | |Bit GPC_MFP[15] determines the PC.15 function. + * | | |0 = GPIO function is selected to the pin PC.15. + * | | |1 = ACMP1_N function is selected to the pin PC.15. + * |[16:31] |GPC_TYPEn |Trigger Function Selection + * | | |0 = GPIOC[15:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOC[15:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::GPD_MFP + * Offset: 0x3C GPIOD Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPD_MFP0 |PD.0 Pin Function Selection + * | | |Bit GPD_MFP[0] determines the PD.0 function. + * | | |0 = GPIO function is selected to the pin PD.0. + * | | |1 = SPI2_SS0 function is selected to the pin PD.0. + * |[1] |GPD_MFP1 |PD.1 Pin Function Selection + * | | |Bit GPD_MFP[1] determines the PD.1 function. + * | | |0 = GPIO function is selected to the pin PD.1. + * | | |1 = SPI2_CLK function is selected to the pin PD.1. + * |[2] |GPD_MFP2 |PD.2 Pin Function Selection + * | | |Bit GPD_MFP[2] determines the PD.2 function. + * | | |0 = GPIO function is selected to the pin PD.2. + * | | |1 = SPI2_MISO0 function is selected to the pin PD.2. + * |[3] |GPD_MFP3 |PD.3 Pin Function Selection + * | | |Bit GPD_MFP[3] determines the PD.3 function. + * | | |0 = GPIO function is selected to the pin PD.3. + * | | |1 = SPI2_MOSI0 function is selected to the pin PD.3. + * |[4] |GPD_MFP4 |PD.4 Pin Function Selection + * | | |Bit GPD_MFP[4] determines the PD.4 function. + * | | |0 = GPIO function is selected to the pin PD.4. + * | | |1 = SPI2_MISO1 function is selected to the pin PD.4. + * |[5] |GPD_MFP5 |PD.5 Pin Function Selection + * | | |Bit GPD_MFP[9] determines the PD.5 function. + * | | |0 = GPIO function is selected to the pin PD.5. + * | | |1 = SPI2_MOSI1 function is selected to the pin PD.5. + * |[8] |GPD_MFP8 |PD.8 Pin Function Selection + * | | |Bit GPD_MFP[8] determines the PD.8 function. + * | | |0 = GPIO function is selected to the pin PD.8. + * | | |1 = SPI3_SS0 function is selected to the pin PD.8. + * |[9] |GPD_MFP9 |PD.9 Pin Function Selection + * | | |Bit GPD_MFP[9] determines the PD.9 function. + * | | |0 = GPIO is function is selected to the pin PD.9. + * | | |1 = SPI3_CLK function is selected to the pin PD.9. + * |[10] |GPD_MFP10 |PD.10 Pin Function Selection + * | | |Bit GPD_MFP[10] determines the PD.10 function. + * | | |0 = GPIO function is selected to the pin PD.10. + * | | |1 = SPI3_MISO0 function is selected to the pin PD.10. + * |[11] |GPD_MFP11 |PD.11 Pin Function Selection + * | | |Bit GPD_MFP[11] determines the PD.11 function. + * | | |0 = GPIO function is selected to the pin PD.11. + * | | |1 = SPI3_MOSI0 function is selected to the pin PD.11. + * |[12] |GPD_MFP12 |PD.12 Pin Function Selection + * | | |Bit GPD_MFP[12] determines the PD.12 function. + * | | |0 = GPIO function is selected to the pin PD.12. + * | | |1 = SPI3_MISO1 function is selected to the pin PD.12. + * |[13] |GPD_MFP13 |PD.13 Pin Function Selection + * | | |Bit GPD_MFP[13] determines the PD.13 function. + * | | |0 = GPIO function is selected to the pin PD.13. + * | | |1 = SPI3_MOSI1 function is selected to the pin PD.13. + * |[14] |GPD_MFP14 |PD.14 Pin Function Selection + * | | |Bit GPD_MFP[14] determines the PD.14 function. + * | | |0 = GPIO function is selected. + * | | |1 = UART2_RXD function is selected. + * |[15] |GPD_MFP15 |PD.15 Pin Function Selection + * | | |Bit GPD_MFP[15] determines the PD.15 function. + * | | |0 = GPIO function is selected. + * | | |1 = UART2_TXD function is selected. + * |[16:31] |GPD_TYPEn |Trigger Function Selection + * | | |0 = GPIOD[15:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOD[15:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::GPE_MFP + * Offset: 0x40 GPIOE Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPE_MFP0 |PE.0 Pin Function Selection + * | | |Bit GPE_MFP[0] determines the PE.0 function. + * | | |0 = GPIO function is selected to the pin PE.0. + * | | |1 = PWM6 function is selected to the pin PE.0. + * |[1] |GPE_MFP1 |PE.1 Pin Function Selection + * | | |Bit GPE_MFP[1] determines the PE.1 function. + * | | |0 = GPIO function is selected to the pin PE.1. + * | | |1 = PWM7 function is selected to the pin PE.1. + * |[5] |GPE_MFP5 |PE.5 Pin Function Selection + * | | |Bits PE5_T1EX (ALT_MFP[25]) and GPE_MFP5 determine the PE.5 function. + * | | |(PE5_T1EX, GPE_MFP5) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM5 function is selected. + * | | |(1, 1) = TM1_EXT function is selected. + * |[16:31] |GPE_TYPEn |Trigger Function Selection + * | | |0 = GPIOD[15:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOD[15:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::GPF_MFP + * Offset: 0x44 GPIOF Multiple Function and Input Type Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPF_MFP0 |PF.0 Pin Function Selection + * | | |Bit GPF_MFP[0] determines the PF.0 function + * | | |0 = GPIO function is selected to the pin PF.0. + * | | |1 = XT1_OUT function is selected to the pin PF.0. + * | | |Note: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]). + * |[1] |GPF_MFP1 |PF.1 Pin Function Selection + * | | |Bit GPF_MFP[1] determines the PF.1 function. + * | | |0 = GPIO function is selected to the pin PF.1. + * | | |1 = XT1_IN function is selected to the pin PF.1. + * | | |Note: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]). + * |[2] |GPF_MFP2 |PF.2 Pin Function Selection + * | | |Bit GPF_MFP[2] determines the PF.2 function. + * | | |0 = GPIO function is selected to the pin PF.2. + * | | |1 = PS2_DAT function is selected to the pin PF.2. + * |[3] |GPF_MFP3 |PF.3 Pin Function Selection + * | | |Bit GPF_MFP[3] determines the PF.3 function. + * | | |0 = GPIO function is selected to the pin PF.3. + * | | |1 = PS2_CLK function is selected to the pin PF.3. + * |[16:19] |GPF_TYPEn |Trigger Function Selection + * | | |0 = GPIOF[3:0] I/O input Schmitt Trigger function Disabled. + * | | |1 = GPIOF[3:0] I/O input Schmitt Trigger function Enabled. + * @var GCR_T::ALT_MFP + * Offset: 0x50 Alternative Multiple Function Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PB10_S01 |PB.10 Pin Alternative Function Selection + * | | |Bits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function. + * | | |(PB10_S01, GPB_MFP10) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM2 function is selected. + * | | |(1, 1) = SPI0_SS1 function is selected. + * |[1] |PB9_S11 |PB.9 Pin Alternative Function Selection + * | | |Bits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function. + * | | |(PB9_S11, GPB_MFP9) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM1 function is selected. + * | | |(1, 1) = SPI1_SS1 function is selected. + * |[2] |PA7_S21 |PA.7 Pin Alternative Function Selection + * | | |Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function. + * | | |(PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = ADC7 function is selected. + * | | |(0, 1, 1) = SPI2_SS1 function is selected. + * | | |(1, 0, 1) = SC1_DAT function is selected. + * |[3] |PB14_S31 |PB.14 Pin Alternative Function Selection + * | | |Bits PB14_S31 (ALT_MFP[3]) and GPB_MFP[14] determine the PB.14 function. + * | | |(PB14_S31, GPB_MFP14) value and function mapping is as following list + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = INT0 function is selected. + * | | |(1, 1) = SPI3_SS1 function is selected. + * |[4] |PB11_PWM4 |PB.11 Pin Alternative Function Selection + * | | |Bits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function. + * | | |(PB11_PWM4, GPB_MFP11) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM3 function is selected. + * | | |(1, 1) = PWM4 function is selected. + * |[5] |PC0_I2SLRCLK|PC.0 Pin Alternative Function Selection + * | | |Bits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC.0 function. + * | | |(PC0_I2SLRCLK, GPC_MFP0) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_SS0 function is selected. + * | | |(1, 1) = I2S_LRLCK function is selected. + * |[6] |PC1_I2SBCLK|PC.1 Pin Alternative Function Selection + * | | |Bits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function. + * | | |(PC1_I2SBCLK, GPC_MFP1) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_CLK function is selected. + * | | |(1, 1) = I2S_BCLK function is selected. + * |[7] |PC2_I2SDI |PC.2 Pin Alternative Function Selection + * | | |Bits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function. + * | | |(PC2_I2SDI, GPC_MFP2) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_MISO0 function is selected. + * | | |(1, 1) = I2S_DI function is selected. + * |[8] |PC3_I2SDO |PC.3 Pin Alternative Function Selection + * | | |Bits PC3_I2SDO (ALT_MFP[8]) and GPC_MFP[3] determine the PC.3 function. + * | | |(PC3_I2SDO, GPC_MFP3) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = SPI0_MOSI0 function is selected. + * | | |(1, 1) = I2S_DO function is selected. + * |[9] |PA15_I2SMCLK|PA.15 Pin Alternative Function Selection + * | | |Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function. + * | | |(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = PWM3 function is selected. + * | | |(0, 1, 1) = I2S_MCLK function is selected. + * | | |(1, 0, 1) = SC2_PWR function is selected. + * |[24] |PB15_T0EX |PB.15 Pin Alternative Function Selection + * | | |Bits PB15_T0EX (ALT_MFP[24]) and GPB_MFP[15] determine the PB.15 function. + * | | |(PB15_T0EX, GPB_MFP15) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = INT1 function is selected. + * | | |(1, 1) = TM0_EXT function is selected. + * |[25] |PE5_T1EX |PE.5 Pin Alternative Function Selection + * | | |Bits PE5_T1EX (ALT_MFP[25]) and GPE_MFP5 determine the PE.5 function. + * | | |(PE5_T1EX, GPE_MFP5) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM5 function is selected. + * | | |(1, 1) = TM1_EXT function is selected. + * |[26] |PB2_T2EX |PB.2 Pin Alternative Function Selection + * | | |Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function. + * | | |(PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nRTS function is selected. + * | | |(0, 1, 1) = TM2_EXT function is selected. + * | | |(1, 0, 1) = ACMP0_O function is selected. + * |[27] |PB3_T3EX |PB.3 Pin Alternative Function Selection + * | | |Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. + * | | |(PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nCTS function is selected. + * | | |(0, 1, 1) = TM3_EXT function is selected. + * | | |(1, 0, 1) = SC2_CD function is selected. + * |[29] |PB8_CLKO |PB.8 Pin Alternative Function Selection + * | | |Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function. + * | | |(PB8_CLKO, GPB_MFP8) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = TM0 function is selected. + * | | |(1, 1) = CLKO function is selected. + * |[30] |PB2_CPO0 |PB.2 Pin Alternative Function Selection + * | | |Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function. + * | | |(PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nRTS function is selected. + * | | |(0, 1, 1) = TM2_EXT function is selected. + * | | |(1, 0, 1) = ACMP0_O function is selected. + * @var GCR_T::ALT_MFP1 + * Offset: 0x58 Alternative Multiple Function Pin Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PA2_SC0CLK|PA.2 Pin Alternative Function Selection + * | | |Bits PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] determine the PA.2 function. + * | | |(PA2_SC0CLK, GPA_MFP2) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC2 function is selected. + * | | |(1, 1) = SC0_CLK function is selected. + * |[1] |PA3_SC0DAT|PA.3 Pin Alternative Function Selection + * | | |Bits PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] determine the PA.3 function. + * | | |(PA3_SC0DAT, GPA_MFP3) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC3 function is selected. + * | | |(1, 1) = SC0_DAT function is selected. + * |[2] |PA0_SC0PWR|PA.0 Pin Alternative Function Selection + * | | |Bit PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] determine the PA.0 function. + * | | |(PA0_SC0PWR, GPA_MFP0) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC0 function is selected. + * | | |(1, 1) = SC0_PWR function is selected. + * |[3] |PA1_SC0RST|PA.1 Pin Alternative Function Selection + * | | |Bits PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] determine the PA.1 function. + * | | |(PA1_SC0RST, GPA_MFP1) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC1 function is selected. + * | | |(1, 1) = SC0_RST function is selected. + * |[4] |PC6_SC0CD |PC.6 Pin Alternative Function Selection + * | | |Bits PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] determine the PC.6 function. + * | | |(PC6_SC0CD, GPC_MFP6) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ACMP0_P function is selected. + * | | |(1, 1) = SC0_CD function is selected. + * |[5] |PA6_SC1CLK|PA.6 Pin Alternative Function Selection + * | | |Bits PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] determine the PA.6 function. + * | | |(PA6_SC1CLK, GPA_MFP6) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC6 function is selected. + * | | |(1, 1) = SC1_CLK function is selected. + * |[6] |PA7_SC1DAT|PA.7 Pin Alternative Function Selection + * | | |Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function. + * | | |(PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = ADC7 function is selected. + * | | |(0, 1, 1) = SPI2_SS1 function is selected. + * | | |(1, 0, 1) = SC1_DAT function is selected. + * |[7] |PA4_SC1PWR|PA.4 Pin Alternative Function Selection + * | | |Bits PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] determine the PA.4 function. + * | | |(PA4_SC1PWR, GPA_MFP4) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC4 function is selected. + * | | |(1, 1) = SC1_PWR function is selected. + * |[8] |PA5_SC1RST|PA.5 Pin Alternative Function Selection + * | | |Bits PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function. + * | | |(PA5_SC1RST, GPA_MFP5) value and function mapping is as following list, + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ADC5 function is selected. + * | | |(1, 1) = SC1_RST function is selected. + * |[9] |PC7_SC1CD |PC.7 Pin Alternative Function Selection + * | | |Bits PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] determine the PC.7 function. + * | | |(PC7_SC1CD, GPC_MFP7) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = ACMP0_N function is selected. + * | | |(1, 1) = SC1_CD function is selected. + * |[10] |PA13_SC2CLK|PA.13 Pin Alternative Function Selection + * | | |Bits PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] determine the PA.13 function. + * | | |(PA13_SC2CLK, GPA_MFP13) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM1 function is selected. + * | | |(1, 1) = SC2_CLK function is selected. + * |[11] |PA12_SC2DAT|PA.12 Pin Alternative Function Selection + * | | |Bits PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] determine the PA.12 function. + * | | |(PA12_SC2DAT, GPA_MFP12) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM0 function is selected. + * | | |(1, 1) = SC2_DAT function is selected. + * |[12] |PA15_SC2PWR|PA.15 Pin Alternative Function Selection + * | | |Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function. + * | | |(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = PWM3 function is selected. + * | | |(0, 1, 1) = I2S_MCLK function is selected. + * | | |(1, 0, 1) = SC2_PWR function is selected. + * |[13] |PA14_SC2RST|PA.14 Pin Alternative Function Selection + * | | |Bits PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] determine the PA.14 function. + * | | |(PA14_SC2RST, GPA_MFP14) value and function mapping is as following list. + * | | |(0, 0) = GPIO function is selected. + * | | |(0, 1) = PWM2 function is selected. + * | | |(1, 1) = SC2_RST function is selected. + * |[14] |PB3_SC2CD |PB.3 Pin Alternative Function Selection + * | | |Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. + * | | |(PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. + * | | |(0, 0, 0) = GPIO function is selected. + * | | |(0, 0, 1) = UART0_nCTS function is selected. + * | | |(0, 1, 1) = TM3_EXT function is selected. + * | | |(1, 0, 1) = SC2_CD function is selected. + * @var GCR_T::ALT_MFP2 + * Offset: 0x5C Alternative Multiple Function Pin Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Reserved |Reserved + * | | |Reserved + * @var GCR_T::IRCTRIMCTL + * Offset: 0x80 IRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TRIM_SEL |Trim Frequency Selection + * | | |This field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically. + * | | |If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled. + * | | |During auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically. + * | | |00 = HIRC auto trim function Disabled. + * | | |01 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz. + * | | |10 = HIRC auto trim function Enabled and HIRC trimmed to 24 MHz. + * | | |11 = Reserved. + * |[5:4] |TRIM_LOOP |Trim Calculation Loop + * | | |This field defines that trim value calculation is based on how many 32.768 kHz clocks in. + * | | |For example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. + * | | |00 = Trim value calculation is based on average difference in 4 clocks. + * | | |01 = Trim value calculation is based on average difference in 8 clocks. + * | | |10 = Trim value calculation is based on average difference in 16 clocks. + * | | |11 = Trim value calculation is based on average difference in 32 clocks. + * |[7:6] |TRIM_RETRY_CNT|Trim Value Update Limitation Count + * | | |The field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64. + * | | |01 = Trim retry count limitation is 128. + * | | |10 = Trim retry count limitation is 256. + * | | |11 = Trim retry count limitation is 512. + * |[8] |CLKERR_STOP_EN|Clock Error Stop Enable + * | | |When this bit is set to 0, the trim operation is keep going if clock is inaccuracy. + * | | |When this bit is set to 1, the trim operation is stopped if clock is inaccuracy. + * @var GCR_T::IRCTRIMIEN + * Offset: 0x84 IRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TRIM_FAIL_IEN|Trim Failure Interrupt Enable + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation |count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]). + * | | |If this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation. + * | | |An interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger an interrupt to CPU Disabled. + * | | |1 = TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger an interrupt to CPU Enabled. + * |[2] |CLKERR_IEN|Clock Error Interrupt Enable + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to 1, and CLKERR_INT (IRCTRIMINT[2]) is set during auto trim operation. + * | | |An interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = CLKERR_INT (IRCTRIMINT[2]) status to trigger an interrupt to CPU Disabled. + * | | |1 = CLKERR_INT (IRCTRIMINT[2]) status to trigger an interrupt to CPU Enabled. + * @var GCR_T::IRCTRIMINT + * Offset: 0x88 IRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQ_LOCK |HIRC Frequency Lock Status + * | | |This bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt. + * |[1] |TRIM_FAIL_INT|Trim Failure Interrupt Status + * | | |This bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. + * | | |Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL [1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TRIM_FAIL_IEN (IRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count did not reach. + * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high speed oscillator frequency was still not locked. + * |[2] |CLKERR_INT|Clock Error Interrupt Status + * | | |When the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL [1:0]) will be cleared to 00 by hardware automatically if CLKERR_STOP_EN (IRCTRIMCTL [8]) is set to 1. + * | | |If this bit is set and CLKERR_IEN (IRCTRIMIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accurate. + * | | |1 = Clock frequency is inaccurate. + * @var GCR_T::REGWRPROT + * Offset: 0x100 Register Write Protection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGPROTDIS|Register Write-Protection Disable Index (Read Only) + * | | |0 = Write-protection is enabled for writing protected registers. Any write to the protected register is ignored. + * | | |1 = Write-protection is disabled for writing protected registers. + * | | |The Protected registers are: + * | | |IPRSTC1: address 0x5000_0008 + * | | |BODCR: address 0x5000_0018 + * | | |PORCR: address 0x5000_0024 + * | | |PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) + * | | |APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enable) + * | | |CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection) + * | | |CLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source selection) + * | | |NMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN NMI interrupt enable) + * | | |ISPCON: address 0x5000_C000 (Flash ISP Control register) + * | | |ISPTRG: address 0x5000_C010 (ISP Trigger Control register) + * | | |WTCR: address 0x4000_4000 + * | | |FATCON: address 0x5000_C018 + * | | |Note: The bits which are write-protected will be noted as "(Write Protect)" beside the description. + * |[7:0] |REGWRPROT |Register Write-Protection Code (Write Only) + * | | |Some registers have write-protection function. + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. + * | | |After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. + */ + + __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */ + __IO uint32_t RSTSRC; /* Offset: 0x04 System Reset Source Register */ + __IO uint32_t IPRSTC1; /* Offset: 0x08 IP Reset Control Register 1 */ + __IO uint32_t IPRSTC2; /* Offset: 0x0C IP Reset Control Register 2 */ + __IO uint32_t IPRSTC3; /* Offset: 0x10 IP Reset Control Register 3 */ + __I uint32_t RESERVE0; + __IO uint32_t BODCR; /* Offset: 0x18 Brown-out Detector Control Register */ + __IO uint32_t TEMPCR; /* Offset: 0x1C Temperature Sensor Control Register */ + __I uint32_t RESERVE1; + __IO uint32_t PORCR; /* Offset: 0x24 Power-on-Reset Controller Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t GPA_MFP; /* Offset: 0x30 GPIOA Multiple Function and Input Type Control Register */ + __IO uint32_t GPB_MFP; /* Offset: 0x34 GPIOB Multiple Function and Input Type Control Register */ + __IO uint32_t GPC_MFP; /* Offset: 0x38 GPIOC Multiple Function and Input Type Control Register */ + __IO uint32_t GPD_MFP; /* Offset: 0x3C GPIOD Multiple Function and Input Type Control Register */ + __IO uint32_t GPE_MFP; /* Offset: 0x40 GPIOE Multiple Function and Input Type Control Register */ + __IO uint32_t GPF_MFP; /* Offset: 0x44 GPIOF Multiple Function and Input Type Control Register */ + __I uint32_t RESERVE3[2]; + __IO uint32_t ALT_MFP; /* Offset: 0x50 Alternative Multiple Function Pin Control Register */ + __I uint32_t RESERVE4; + __IO uint32_t ALT_MFP1; /* Offset: 0x58 Alternative Multiple Function Pin Control Register 1 */ + __IO uint32_t ALT_MFP2; /* Offset: 0x5C Alternative Multiple Function Pin Control Register 2 */ + __I uint32_t RESERVE5[8]; + __IO uint32_t IRCTRIMCTL; /* Offset: 0x80 IRC Trim Control Register */ + __IO uint32_t IRCTRIMIEN; /* Offset: 0x84 IRC Trim Interrupt Enable Register */ + __IO uint32_t IRCTRIMINT; /* Offset: 0x88 IRC Trim Interrupt Status Register */ + __I uint32_t RESERVE6[29]; + __IO uint32_t REGWRPROT; /* Offset: 0x100 Register Write Protection Register */ + +} GCR_T; + + + + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +/* GCR RSTSRC Bit Field Definitions */ +#define SYS_RSTSRC_RSTS_CPU_Pos 7 /*!< GCR_T::RSTSRC: RSTS_CPU Position */ +#define SYS_RSTSRC_RSTS_CPU_Msk (1ul << SYS_RSTSRC_RSTS_CPU_Pos) /*!< GCR_T::RSTSRC: RSTS_CPU Mask */ + +#define SYS_RSTSRC_RSTS_SYS_Pos 5 /*!< GCR_T::RSTSRC: RSTS_SYS Position */ +#define SYS_RSTSRC_RSTS_SYS_Msk (1ul << SYS_RSTSRC_RSTS_SYS_Pos) /*!< GCR_T::RSTSRC: RSTS_SYS Mask */ + +#define SYS_RSTSRC_RSTS_BOD_Pos 4 /*!< GCR_T::RSTSRC: RSTS_BOD Position */ +#define SYS_RSTSRC_RSTS_BOD_Msk (1ul << SYS_RSTSRC_RSTS_BOD_Pos) /*!< GCR_T::RSTSRC: RSTS_BOD Mask */ + +#define SYS_RSTSRC_RSTS_LVR_Pos 3 /*!< GCR_T::RSTSRC: RSTS_LVR Position */ +#define SYS_RSTSRC_RSTS_LVR_Msk (1ul << SYS_RSTSRC_RSTS_LVR_Pos) /*!< GCR_T::RSTSRC: RSTS_LVR Mask */ + +#define SYS_RSTSRC_RSTS_WDT_Pos 2 /*!< GCR_T::RSTSRC: RSTS_WDT Position */ +#define SYS_RSTSRC_RSTS_WDT_Msk (1ul << SYS_RSTSRC_RSTS_WDT_Pos) /*!< GCR_T::RSTSRC: RSTS_WDT Mask */ + +#define SYS_RSTSRC_RSTS_RESET_Pos 1 /*!< GCR_T::RSTSRC: RSTS_RESET Position */ +#define SYS_RSTSRC_RSTS_RESET_Msk (1ul << SYS_RSTSRC_RSTS_RESET_Pos) /*!< GCR_T::RSTSRC: RSTS_RESET Mask */ + +#define SYS_RSTSRC_RSTS_POR_Pos 0 /*!< GCR_T::RSTSRC: RSTS_POR Position */ +#define SYS_RSTSRC_RSTS_POR_Msk (1ul << SYS_RSTSRC_RSTS_POR_Pos) /*!< GCR_T::RSTSRC: RSTS_POR Mask */ + +/* GCR IPRSTC1 Bit Field Definitions */ +#define SYS_IPRSTC1_PDMA_RST_Pos 2 /*!< GCR_T::IPRSTC1: PDMA_RST Position */ +#define SYS_IPRSTC1_PDMA_RST_Msk (1ul << SYS_IPRSTC1_PDMA_RST_Pos) /*!< GCR_T::IPRSTC1: PDMA_RST Mask */ + +#define SYS_IPRSTC1_CPU_RST_Pos 1 /*!< GCR_T::IPRSTC1: CPU_RST Position */ +#define SYS_IPRSTC1_CPU_RST_Msk (1ul << SYS_IPRSTC1_CPU_RST_Pos) /*!< GCR_T::IPRSTC1: CPU_RST Mask */ + +#define SYS_IPRSTC1_CHIP_RST_Pos 0 /*!< GCR_T::IPRSTC1: CHIP_RST Position */ +#define SYS_IPRSTC1_CHIP_RST_Msk (1ul << SYS_IPRSTC1_CHIP_RST_Pos) /*!< GCR_T::IPRSTC1: CHIP_RST Mask */ + +/* GCR IPRSTC2 Bit Field Definitions */ +#define SYS_IPRSTC2_I2S_RST_Pos 29 /*!< GCR_T::IPRSTC2: I2S_RST Position */ +#define SYS_IPRSTC2_I2S_RST_Msk (1ul << SYS_IPRSTC2_I2S_RST_Pos) /*!< GCR_T::IPRSTC2: I2S_RST Mask */ + +#define SYS_IPRSTC2_ADC_RST_Pos 28 /*!< GCR_T::IPRSTC2: ADC_RST Position */ +#define SYS_IPRSTC2_ADC_RST_Msk (1ul << SYS_IPRSTC2_ADC_RST_Pos) /*!< GCR_T::IPRSTC2: ADC_RST Mask */ + +#define SYS_IPRSTC2_USBD_RST_Pos 27 /*!< GCR_T::IPRSTC2: USBD_RST Position */ +#define SYS_IPRSTC2_USBD_RST_Msk (1ul << SYS_IPRSTC2_USBD_RST_Pos) /*!< GCR_T::IPRSTC2: USBD_RST Mask */ + +#define SYS_IPRSTC2_PS2_RST_Pos 23 /*!< GCR_T::IPRSTC2: PS2_RST Position */ +#define SYS_IPRSTC2_PS2_RST_Msk (1ul << SYS_IPRSTC2_PS2_RST_Pos) /*!< GCR_T::IPRSTC2: PS2_RST Mask */ + +#define SYS_IPRSTC2_ACMP_RST_Pos 22 /*!< GCR_T::IPRSTC2: ACMP_RST Position */ +#define SYS_IPRSTC2_ACMP_RST_Msk (1ul << SYS_IPRSTC2_ACMP_RST_Pos) /*!< GCR_T::IPRSTC2: ACMP_RST Mask */ + +#define SYS_IPRSTC2_PWM47_RST_Pos 21 /*!< GCR_T::IPRSTC2: PWM47_RST Position */ +#define SYS_IPRSTC2_PWM47_RST_Msk (1ul << SYS_IPRSTC2_PWM47_RST_Pos) /*!< GCR_T::IPRSTC2: PWM47_RST Mask */ + +#define SYS_IPRSTC2_PWM03_RST_Pos 20 /*!< GCR_T::IPRSTC2: PWM03_RST Position */ +#define SYS_IPRSTC2_PWM03_RST_Msk (1ul << SYS_IPRSTC2_PWM03_RST_Pos) /*!< GCR_T::IPRSTC2: PWM03_RST Mask */ + +#define SYS_IPRSTC2_UART2_RST_Pos 18 /*!< GCR_T::IPRSTC2: UART2_RST Position */ +#define SYS_IPRSTC2_UART2_RST_Msk (1ul << SYS_IPRSTC2_UART2_RST_Pos) /*!< GCR_T::IPRSTC2: UART2_RST Mask */ + +#define SYS_IPRSTC2_UART1_RST_Pos 17 /*!< GCR_T::IPRSTC2: UART1_RST Position */ +#define SYS_IPRSTC2_UART1_RST_Msk (1ul << SYS_IPRSTC2_UART1_RST_Pos) /*!< GCR_T::IPRSTC2: UART1_RST Mask */ + +#define SYS_IPRSTC2_UART0_RST_Pos 16 /*!< GCR_T::IPRSTC2: UART0_RST Position */ +#define SYS_IPRSTC2_UART0_RST_Msk (1ul << SYS_IPRSTC2_UART0_RST_Pos) /*!< GCR_T::IPRSTC2: UART0_RST Mask */ + +#define SYS_IPRSTC2_SPI3_RST_Pos 15 /*!< GCR_T::IPRSTC2: SPI3_RST Position */ +#define SYS_IPRSTC2_SPI3_RST_Msk (1ul << SYS_IPRSTC2_SPI3_RST_Pos) /*!< GCR_T::IPRSTC2: SPI3_RST Mask */ + +#define SYS_IPRSTC2_SPI2_RST_Pos 14 /*!< GCR_T::IPRSTC2: SPI2_RST Position */ +#define SYS_IPRSTC2_SPI2_RST_Msk (1ul << SYS_IPRSTC2_SPI2_RST_Pos) /*!< GCR_T::IPRSTC2: SPI2_RST Mask */ + +#define SYS_IPRSTC2_SPI1_RST_Pos 13 /*!< GCR_T::IPRSTC2: SPI1_RST Position */ +#define SYS_IPRSTC2_SPI1_RST_Msk (1ul << SYS_IPRSTC2_SPI1_RST_Pos) /*!< GCR_T::IPRSTC2: SPI1_RST Mask */ + +#define SYS_IPRSTC2_SPI0_RST_Pos 12 /*!< GCR_T::IPRSTC2: SPI0_RST Position */ +#define SYS_IPRSTC2_SPI0_RST_Msk (1ul << SYS_IPRSTC2_SPI0_RST_Pos) /*!< GCR_T::IPRSTC2: SPI0_RST Mask */ + +#define SYS_IPRSTC2_I2C1_RST_Pos 9 /*!< GCR_T::IPRSTC2: I2C1_RST Position */ +#define SYS_IPRSTC2_I2C1_RST_Msk (1ul << SYS_IPRSTC2_I2C1_RST_Pos) /*!< GCR_T::IPRSTC2: I2C1_RST Mask */ + +#define SYS_IPRSTC2_I2C0_RST_Pos 8 /*!< GCR_T::IPRSTC2: I2C0_RST Position */ +#define SYS_IPRSTC2_I2C0_RST_Msk (1ul << SYS_IPRSTC2_I2C0_RST_Pos) /*!< GCR_T::IPRSTC2: I2C0_RST Mask */ + +#define SYS_IPRSTC2_TMR3_RST_Pos 5 /*!< GCR_T::IPRSTC2: TMR3_RST Position */ +#define SYS_IPRSTC2_TMR3_RST_Msk (1ul << SYS_IPRSTC2_TMR3_RST_Pos) /*!< GCR_T::IPRSTC2: TMR3_RST Mask */ + +#define SYS_IPRSTC2_TMR2_RST_Pos 4 /*!< GCR_T::IPRSTC2: TMR2_RST Position */ +#define SYS_IPRSTC2_TMR2_RST_Msk (1ul << SYS_IPRSTC2_TMR2_RST_Pos) /*!< GCR_T::IPRSTC2: TMR2_RST Mask */ + +#define SYS_IPRSTC2_TMR1_RST_Pos 3 /*!< GCR_T::IPRSTC2: TMR1_RST Position */ +#define SYS_IPRSTC2_TMR1_RST_Msk (1ul << SYS_IPRSTC2_TMR1_RST_Pos) /*!< GCR_T::IPRSTC2: TMR1_RST Mask */ + +#define SYS_IPRSTC2_TMR0_RST_Pos 2 /*!< GCR_T::IPRSTC2: TMR0_RST Position */ +#define SYS_IPRSTC2_TMR0_RST_Msk (1ul << SYS_IPRSTC2_TMR0_RST_Pos) /*!< GCR_T::IPRSTC2: TMR0_RST Mask */ + +#define SYS_IPRSTC2_GPIO_RST_Pos 1 /*!< GCR_T::IPRSTC2: GPIO_RST Position */ +#define SYS_IPRSTC2_GPIO_RST_Msk (1ul << SYS_IPRSTC2_GPIO_RST_Pos) /*!< GCR_T::IPRSTC2: GPIO_RST Mask */ + +/* GCR IPRSTC3 Bit Field Definitions */ +#define SYS_IPRSTC3_SC2_RST_Pos 2 /*!< GCR_T::IPRSTC3: SC2_RST Position */ +#define SYS_IPRSTC3_SC2_RST_Msk (1ul << SYS_IPRSTC3_SC2_RST_Pos) /*!< GCR_T::IPRSTC3: SC2_RST Mask */ + +#define SYS_IPRSTC3_SC1_RST_Pos 1 /*!< GCR_T::IPRSTC3: SC1_RST Position */ +#define SYS_IPRSTC3_SC1_RST_Msk (1ul << SYS_IPRSTC3_SC1_RST_Pos) /*!< GCR_T::IPRSTC3: SC1_RST Mask */ + +#define SYS_IPRSTC3_SC0_RST_Pos 0 /*!< GCR_T::IPRSTC3: SC0_RST Position */ +#define SYS_IPRSTC3_SC0_RST_Msk (1ul << SYS_IPRSTC3_SC0_RST_Pos) /*!< GCR_T::IPRSTC3: SC0_RST Mask */ + +/* GCR BODCR Bit Field Definitions */ +#define SYS_BODCR_LVR_EN_Pos 7 /*!< GCR_T::BODCR: LVR_EN Position */ +#define SYS_BODCR_LVR_EN_Msk (1ul << SYS_BODCR_LVR_EN_Pos) /*!< GCR_T::BODCR: LVR_EN Mask */ + +#define SYS_BODCR_BOD_OUT_Pos 6 /*!< GCR_T::BODCR: BOD_OUT Position */ +#define SYS_BODCR_BOD_OUT_Msk (1ul << SYS_BODCR_BOD_OUT_Pos) /*!< GCR_T::BODCR: BOD_OUT Mask */ + +#define SYS_BODCR_BOD_LPM_Pos 5 /*!< GCR_T::BODCR: BOD_LPM Position */ +#define SYS_BODCR_BOD_LPM_Msk (1ul << SYS_BODCR_BOD_LPM_Pos) /*!< GCR_T::BODCR: BOD_LPM Mask */ + +#define SYS_BODCR_BOD_INTF_Pos 4 /*!< GCR_T::BODCR: BOD_INTF Position */ +#define SYS_BODCR_BOD_INTF_Msk (1ul << SYS_BODCR_BOD_INTF_Pos) /*!< GCR_T::BODCR: BOD_INTF Mask */ + +#define SYS_BODCR_BOD_RSTEN_Pos 3 /*!< GCR_T::BODCR: BOD_RSTEN Position */ +#define SYS_BODCR_BOD_RSTEN_Msk (1ul << SYS_BODCR_BOD_RSTEN_Pos) /*!< GCR_T::BODCR: BOD_RSTEN Mask */ + +#define SYS_BODCR_BOD_VL_Pos 1 /*!< GCR_T::BODCR: BOD_VL Position */ +#define SYS_BODCR_BOD_VL_Msk (3ul << SYS_BODCR_BOD_VL_Pos) /*!< GCR_T::BODCR: BOD_VL Mask */ + +#define SYS_BODCR_BOD_EN_Pos 0 /*!< GCR_T::BODCR: BOD_EN Position */ +#define SYS_BODCR_BOD_EN_Msk (1ul << SYS_BODCR_BOD_EN_Pos) /*!< GCR_T::BODCR: BOD_EN Mask */ + +/* GCR TEMPCR Bit Field Definitions */ +#define SYS_TEMPCR_VTEMP_EN_Pos 0 /*!< GCR_T::TEMPCR: VTEMP_EN Position */ +#define SYS_TEMPCR_VTEMP_EN_Msk (1ul << SYS_TEMPCR_VTEMP_EN_Pos) /*!< GCR_T::TEMPCR: VTEMP_EN Mask */ + +/* GCR PORCR Bit Field Definitions */ +#define SYS_PORCR_POR_DIS_CODE_Pos 0 /*!< GCR_T::PORCR: POR_DIS_CODE Position */ +#define SYS_PORCR_POR_DIS_CODE_Msk (0xFFFFul << SYS_PORCR_POR_DIS_CODE_Pos) /*!< GCR_T::PORCR: POR_DIS_CODE Mask */ + +/* GCR GPAMFP Bit Field Definitions */ +#define SYS_GPA_MFP_GPA_TYPE_Pos 16 /*!< GCR_T::GPA_MFP: GPA_TYPE Position */ +#define SYS_GPA_MFP_GPA_TYPE_Msk (0xFFFFul << SYS_GPA_MFP_GPA_TYPE_Pos) /*!< GCR_T::GPA_MFP: GPA_TYPE Mask */ + +#define SYS_GPA_MFP_GPA_MFP_Pos 0 /*!< GCR_T::GPA_MFP: GPA_MFP Position */ +#define SYS_GPA_MFP_GPA_MFP_Msk (0xFFFFul << SYS_GPA_MFP_GPA_MFP_Pos) /*!< GCR_T::GPA_MFP: GPA_MFP Mask */ + + +/* GCR GPBMFP Bit Field Definitions */ +#define SYS_GPB_MFP_GPB_TYPE_Pos 16 /*!< GCR_T::GPB_MFP: GPB_TYPE Position */ +#define SYS_GPB_MFP_GPB_TYPE_Msk (0xFFFFul << SYS_GPB_MFP_GPB_TYPE_Pos) /*!< GCR_T::GPB_MFP: GPB_TYPE Mask */ + +#define SYS_GPB_MFP_GPB_MFP_Pos 0 /*!< GCR_T::GPB_MFP: GPB_MFP Position */ +#define SYS_GPB_MFP_GPB_MFP_Msk (0xFFFFul << SYS_GPB_MFP_GPB_MFP_Pos) /*!< GCR_T::GPB_MFP: GPB_MFP Mask */ + +/* GCR GPCMFP Bit Field Definitions */ +#define SYS_GPC_MFP_GPC_TYPE_Pos 16 /*!< GCR_T::GPC_MFP: GPC_TYPE Position */ +#define SYS_GPC_MFP_GPC_TYPE_Msk (0xFFFFul << SYS_GPC_MFP_GPC_TYPE_Pos) /*!< GCR_T::GPC_MFP: GPC_TYPE Mask */ + +#define SYS_GPC_MFP_GPC_MFP_Pos 0 /*!< GCR_T::GPC_MFP: GPC_MFP Position */ +#define SYS_GPC_MFP_GPC_MFP_Msk (0xFFFFul << SYS_GPC_MFP_GPC_MFP_Pos) /*!< GCR_T::GPC_MFP: GPC_MFP Mask */ + +/* GCR GPDMFP Bit Field Definitions */ +#define SYS_GPD_MFP_GPD_TYPE_Pos 16 /*!< GCR_T::GPD_MFP: GPD_TYPE Position */ +#define SYS_GPD_MFP_GPD_TYPE_Msk (0xFFFFul << SYS_GPD_MFP_GPD_TYPE_Pos) /*!< GCR_T::GPD_MFP: GPD_TYPE Mask */ + +#define SYS_GPD_MFP_GPD_MFP_Pos 0 /*!< GCR_T::GPD_MFP: GPD_MFP Position */ +#define SYS_GPD_MFP_GPD_MFP_Msk (0xFFFFul << SYS_GPD_MFP_GPD_MFP_Pos) /*!< GCR_T::GPD_MFP: GPD_MFP Mask */ + +/* GCR GPEMFP Bit Field Definitions */ +#define SYS_GPE_MFP_GPE_TYPE_Pos 16 /*!< GCR_T::GPE_MFP: GPE_TYPE Position */ +#define SYS_GPE_MFP_GPE_TYPE_Msk (0xFFFFul << SYS_GPE_MFP_GPE_TYPE_Pos) /*!< GCR_T::GPE_MFP: GPE_TYPE Mask */ + +#define SYS_GPE_MFP_GPE_MFP5_Pos 5 /*!< GCR_T::GPE_MFP: GPE_MFP5 Position */ +#define SYS_GPE_MFP_GPE_MFP5_Msk (1ul << SYS_GPE_MFP_GPE_MFP5_Pos) /*!< GCR_T::GPE_MFP: GPE_MFP5 Mask */ + +#define SYS_GPE_MFP_GPE_MFP1_Pos 1 /*!< GCR_T::GPE_MFP: GPE_MFP1 Position */ +#define SYS_GPE_MFP_GPE_MFP1_Msk (1ul << SYS_GPE_MFP_GPE_MFP1_Pos) /*!< GCR_T::GPE_MFP: GPE_MFP1 Mask */ + +#define SYS_GPE_MFP_GPE_MFP0_Pos 0 /*!< GCR_T::GPE_MFP: GPE_MFP0 Position */ +#define SYS_GPE_MFP_GPE_MFP0_Msk (1ul << SYS_GPE_MFP_GPE_MFP0_Pos) /*!< GCR_T::GPE_MFP: GPE_MFP0 Mask */ + +/* GCR GPFMFP Bit Field Definitions */ +#define SYS_GPF_MFP_GPF_TYPE_Pos 16 /*!< GCR_T::GPF_MFP: GPF_TYPE Position */ +#define SYS_GPF_MFP_GPF_TYPE_Msk (0xFul << SYS_GPF_MFP_GPF_TYPE_Pos) /*!< GCR_T::GPF_MFP: GPF_TYPE Mask */ + +#define SYS_GPF_MFP_GPF_MFP3_Pos 3 /*!< GCR_T::GPF_MFP: GPF_MFP3 Position */ +#define SYS_GPF_MFP_GPF_MFP3_Msk (1ul << SYS_GPF_MFP_GPF_MFP3_Pos) /*!< GCR_T::GPF_MFP: GPF_MFP3 Mask */ + +#define SYS_GPF_MFP_GPF_MFP2_Pos 2 /*!< GCR_T::GPF_MFP: GPF_MFP2 Position */ +#define SYS_GPF_MFP_GPF_MFP2_Msk (1ul << SYS_GPF_MFP_GPF_MFP2_Pos) /*!< GCR_T::GPF_MFP: GPF_MFP2 Mask */ + +#define SYS_GPF_MFP_GPF_MFP1_Pos 1 /*!< GCR_T::GPF_MFP: GPF_MFP1 Position */ +#define SYS_GPF_MFP_GPF_MFP1_Msk (1ul << SYS_GPF_MFP_GPF_MFP1_Pos) /*!< GCR_T::GPF_MFP: GPF_MFP1 Mask */ + +#define SYS_GPF_MFP_GPF_MFP0_Pos 0 /*!< GCR_T::GPF_MFP: GPF_MFP0 Position */ +#define SYS_GPF_MFP_GPF_MFP0_Msk (1ul << SYS_GPF_MFP_GPF_MFP0_Pos) /*!< GCR_T::GPF_MFP: GPF_MFP0 Mask */ + +/* GCR ALTMFP Bit Field Definitions */ +#define SYS_ALT_MFP_PB2_CPO0_Pos 30 /*!< GCR_T::ALT_MFP: PB2_CPO0 Position */ +#define SYS_ALT_MFP_PB2_CPO0_Msk (1ul << SYS_ALT_MFP_PB2_CPO0_Pos) /*!< GCR_T::ALT_MFP: PB2_CPO0 Mask */ + +#define SYS_ALT_MFP_PB8_CLKO_Pos 29 /*!< GCR_T::ALT_MFP: PB8_CLKO Position */ +#define SYS_ALT_MFP_PB8_CLKO_Msk (1ul << SYS_ALT_MFP_PB8_CLKO_Pos) /*!< GCR_T::ALT_MFP: PB8_CLKO Mask */ + +#define SYS_ALT_MFP_PA10_11_CAN1_Pos 28 /*!< GCR_T::ALT_MFP: PA10_11_CAN1 Position */ +#define SYS_ALT_MFP_PA10_11_CAN1_Msk (1ul << SYS_ALT_MFP_PA10_11_CAN1_Pos) /*!< GCR_T::ALT_MFP: PA10_11_CAN1 Mask */ + +#define SYS_ALT_MFP_PB3_T3EX_Pos 27 /*!< GCR_T::ALT_MFP: PB3_T3EX Position */ +#define SYS_ALT_MFP_PB3_T3EX_Msk (1ul << SYS_ALT_MFP_PB3_T3EX_Pos) /*!< GCR_T::ALT_MFP: PB3_T3EX Mask */ + +#define SYS_ALT_MFP_PB2_T2EX_Pos 26 /*!< GCR_T::ALT_MFP: PB2_T2EX Position */ +#define SYS_ALT_MFP_PB2_T2EX_Msk (1ul << SYS_ALT_MFP_PB2_T2EX_Pos) /*!< GCR_T::ALT_MFP: PB3_T3EX Mask */ + +#define SYS_ALT_MFP_PE5_T1EX_Pos 25 /*!< GCR_T::ALT_MFP: PE5_T1EX Position */ +#define SYS_ALT_MFP_PE5_T1EX_Msk (1ul << SYS_ALT_MFP_PE5_T1EX_Pos) /*!< GCR_T::ALT_MFP: PE5_T1EX Mask */ + +#define SYS_ALT_MFP_PB15_T0EX_Pos 24 /*!< GCR_T::ALT_MFP: PB15_T0EX Position */ +#define SYS_ALT_MFP_PB15_T0EX_Msk (1ul << SYS_ALT_MFP_PB15_T0EX_Pos) /*!< GCR_T::ALT_MFP: PB15_T0EX Mask */ + +#define SYS_ALT_MFP_PA15_I2SMCLK_Pos 9 /*!< GCR_T::ALT_MFP: PA15_I2SMCLK Position */ +#define SYS_ALT_MFP_PA15_I2SMCLK_Msk (1ul << SYS_ALT_MFP_PA15_I2SMCLK_Pos) /*!< GCR_T::ALT_MFP: PA15_I2SMCLK Mask */ + +#define SYS_ALT_MFP_PC3_I2SDO_Pos 8 /*!< GCR_T::ALT_MFP: PC3_I2SDO Position */ +#define SYS_ALT_MFP_PC3_I2SDO_Msk (1ul << SYS_ALT_MFP_PC3_I2SDO_Pos) /*!< GCR_T::ALT_MFP: PC3_I2SDO Mask */ + +#define SYS_ALT_MFP_PC2_I2SDI_Pos 7 /*!< GCR_T::ALT_MFP: PC2_I2SDI Position */ +#define SYS_ALT_MFP_PC2_I2SDI_Msk (1ul << SYS_ALT_MFP_PC2_I2SDI_Pos) /*!< GCR_T::ALT_MFP: PC2_I2SDI Mask */ + +#define SYS_ALT_MFP_PC1_I2SBCLK_Pos 6 /*!< GCR_T::ALT_MFP: PC1_I2SBCLK Position */ +#define SYS_ALT_MFP_PC1_I2SBCLK_Msk (1ul << SYS_ALT_MFP_PC1_I2SBCLK_Pos) /*!< GCR_T::ALT_MFP: PC1_I2SBCLK Mask */ + +#define SYS_ALT_MFP_PC0_I2SLRCLK_Pos 5 /*!< GCR_T::ALT_MFP: PC0_I2SLRCLK Position */ +#define SYS_ALT_MFP_PC0_I2SLRCLK_Msk (1ul << SYS_ALT_MFP_PC0_I2SLRCLK_Pos) /*!< GCR_T::ALT_MFP: PC0_I2SLRCLK Mask */ + +#define SYS_ALT_MFP_PB11_PWM4_Pos 4 /*!< GCR_T::ALT_MFP: PB11_PWM4 Position */ +#define SYS_ALT_MFP_PB11_PWM4_Msk (1ul << SYS_ALT_MFP_PB11_PWM4_Pos) /*!< GCR_T::ALT_MFP: PB11_PWM4 Mask */ + +#define SYS_ALT_MFP_PB14_S31_Pos 3 /*!< GCR_T::ALT_MFP: PB14_S31 Position */ +#define SYS_ALT_MFP_PB14_S31_Msk (1ul << SYS_ALT_MFP_PB14_S31_Pos) /*!< GCR_T::ALT_MFP: PB14_S31 Mask */ + +#define SYS_ALT_MFP_PA7_S21_Pos 2 /*!< GCR_T::ALT_MFP: PA7_S21 Position */ +#define SYS_ALT_MFP_PA7_S21_Msk (1ul << SYS_ALT_MFP_PA7_S21_Pos) /*!< GCR_T::ALT_MFP: PA7_S21 Mask */ + +#define SYS_ALT_MFP_PB9_S11_Pos 1 /*!< GCR_T::ALT_MFP: PB9_S11 Position */ +#define SYS_ALT_MFP_PB9_S11_Msk (1ul << SYS_ALT_MFP_PB9_S11_Pos) /*!< GCR_T::ALT_MFP: PB9_S11 Mask */ + +#define SYS_ALT_MFP_PB10_S01_Pos 0 /*!< GCR_T::ALT_MFP: PB10_S01 Position */ +#define SYS_ALT_MFP_PB10_S01_Msk (1ul << SYS_ALT_MFP_PB10_S01_Pos) /*!< GCR_T::ALT_MFP: PB10_S01 Mask */ + +/* GCR ALTMFP1 Bit Field Definitions */ +#define SYS_ALT_MFP1_PB3_SC2CD_Pos 14 /*!< GCR_T::ALT_MFP1: PB3_SC2CD Position */ +#define SYS_ALT_MFP1_PB3_SC2CD_Msk (1ul << SYS_ALT_MFP1_PB3_SC2CD_Pos) /*!< GCR_T::ALT_MFP1: PB3_SC2CD Mask */ + +#define SYS_ALT_MFP1_PA14_SC2RST_Pos 13 /*!< GCR_T::ALT_MFP1: PA14_SC2RST Position */ +#define SYS_ALT_MFP1_PA14_SC2RST_Msk (1ul << SYS_ALT_MFP1_PA14_SC2RST_Pos) /*!< GCR_T::ALT_MFP1: PA14_SC2RST Mask */ + +#define SYS_ALT_MFP1_PA15_SC2PWR_Pos 12 /*!< GCR_T::ALT_MFP1: PA15_SC2PWR Position */ +#define SYS_ALT_MFP1_PA15_SC2PWR_Msk (1ul << SYS_ALT_MFP1_PA15_SC2PWR_Pos) /*!< GCR_T::ALT_MFP1: PA15_SC2PWR Mask */ + +#define SYS_ALT_MFP1_PA12_SC2DAT_Pos 11 /*!< GCR_T::ALT_MFP1: PA12_SC2DAT Position */ +#define SYS_ALT_MFP1_PA12_SC2DAT_Msk (1ul << SYS_ALT_MFP1_PA12_SC2DAT_Pos) /*!< GCR_T::ALT_MFP1: PA12_SC2DAT Mask */ + +#define SYS_ALT_MFP1_PA13_SC2CLK_Pos 10 /*!< GCR_T::ALT_MFP1: PA13_SC2CLK Position */ +#define SYS_ALT_MFP1_PA13_SC2CLK_Msk (1ul << SYS_ALT_MFP1_PA13_SC2CLK_Pos) /*!< GCR_T::ALT_MFP1: PA13_SC2CLK Mask */ + +#define SYS_ALT_MFP1_PC7_SC1CD_Pos 9 /*!< GCR_T::ALT_MFP1: PC7_SC1CD Position */ +#define SYS_ALT_MFP1_PC7_SC1CD_Msk (1ul << SYS_ALT_MFP1_PC7_SC1CD_Pos) /*!< GCR_T::ALT_MFP1: PC7_SC1CD Mask */ + +#define SYS_ALT_MFP1_PA5_SC1RST_Pos 8 /*!< GCR_T::ALT_MFP1: PA5_SC1RST Position */ +#define SYS_ALT_MFP1_PA5_SC1RST_Msk (1ul << SYS_ALT_MFP1_PA5_SC1RST_Pos) /*!< GCR_T::ALT_MFP1: PA5_SC1RST Mask */ + +#define SYS_ALT_MFP1_PA4_SC1PWR_Pos 7 /*!< GCR_T::ALT_MFP1: PA4_SC1PWR Position */ +#define SYS_ALT_MFP1_PA4_SC1PWR_Msk (1ul << SYS_ALT_MFP1_PA4_SC1PWR_Pos) /*!< GCR_T::ALT_MFP1: PA4_SC1PWR Mask */ + +#define SYS_ALT_MFP1_PA7_SC1DAT_Pos 6 /*!< GCR_T::ALT_MFP1: PA7_SC1DAT Position */ +#define SYS_ALT_MFP1_PA7_SC1DAT_Msk (1ul << SYS_ALT_MFP1_PA7_SC1DAT_Pos) /*!< GCR_T::ALT_MFP1: PA7_SC1DAT Mask */ + +#define SYS_ALT_MFP1_PA6_SC1CLK_Pos 5 /*!< GCR_T::ALT_MFP1: PA6_SC1CLK Position */ +#define SYS_ALT_MFP1_PA6_SC1CLK_Msk (1ul << SYS_ALT_MFP1_PA6_SC1CLK_Pos) /*!< GCR_T::ALT_MFP1: PA6_SC1CLK Mask */ + +#define SYS_ALT_MFP1_PC6_SC0CD_Pos 4 /*!< GCR_T::ALT_MFP1: PC6_SC0CD Position */ +#define SYS_ALT_MFP1_PC6_SC0CD_Msk (1ul << SYS_ALT_MFP1_PC6_SC0CD_Pos) /*!< GCR_T::ALT_MFP1: PC6_SC0CD Mask */ + +#define SYS_ALT_MFP1_PA1_SC0RST_Pos 3 /*!< GCR_T::ALT_MFP1: PA1_SC0RST Position */ +#define SYS_ALT_MFP1_PA1_SC0RST_Msk (1ul << SYS_ALT_MFP1_PA1_SC0RST_Pos) /*!< GCR_T::ALT_MFP1: PA1_SC0RST Mask */ + +#define SYS_ALT_MFP1_PA0_SC0PWR_Pos 2 /*!< GCR_T::ALT_MFP1: PA0_SC0PWR Position */ +#define SYS_ALT_MFP1_PA0_SC0PWR_Msk (1ul << SYS_ALT_MFP1_PA0_SC0PWR_Pos) /*!< GCR_T::ALT_MFP1: PA0_SC0PWR Mask */ + +#define SYS_ALT_MFP1_PA3_SC0DAT_Pos 1 /*!< GCR_T::ALT_MFP1: PA3_SC0DAT Position */ +#define SYS_ALT_MFP1_PA3_SC0DAT_Msk (1ul << SYS_ALT_MFP1_PA3_SC0DAT_Pos) /*!< GCR_T::ALT_MFP1: PA3_SC0DAT Mask */ + +#define SYS_ALT_MFP1_PA2_SC0CLK_Pos 0 /*!< GCR_T::ALT_MFP1: PA2_SC0CLK Position */ +#define SYS_ALT_MFP1_PA2_SC0CLK_Msk (1ul << SYS_ALT_MFP1_PA2_SC0CLK_Pos) /*!< GCR_T::ALT_MFP1: PA2_SC0CLK Mask */ + +/* GCR IRCTRIMCTL Bit Field Definitions */ +#define SYS_IRCTRIMCTL_CLKERR_STOP_EN_Pos 8 /*!< GCR_T::IRCTRIMCTL: CLKERR_STOP_EN Position */ +#define SYS_IRCTRIMCTL_CLKERR_STOP_EN_Msk (1ul << SYS_IRCTRIMCTL_CLKERR_STOP_EN_Pos) /*!< GCR_T::IRCTRIMCTL: CLKERR_STOP_EN Mask */ + +#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos 6 /*!< GCR_T::IRCTRIMCTL: TRIM_RETRY_CNT Position */ +#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!< GCR_T::IRCTRIMCTL: TRIM_RETRY_CNT Mask */ + +#define SYS_IRCTRIMCTL_TRIM_LOOP_Pos 4 /*!< GCR_T::IRCTRIMCTL: TRIM_LOOP Position */ +#define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!< GCR_T::IRCTRIMCTL: TRIM_LOOP Mask */ + +#define SYS_IRCTRIMCTL_TRIM_SEL_Pos 0 /*!< GCR_T::IRCTRIMCTL: TRIM_SEL Position */ +#define SYS_IRCTRIMCTL_TRIM_SEL_Msk (3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!< GCR_T::IRCTRIMCTL: TRIM_SEL Mask */ + +/* GCR IRCTRIMIEN Bit Field Definitions */ +#define SYS_IRCTRIMIEN_CLKERR_IEN_Pos 2 /*!< GCR_T::IRCTRIMIEN: CLKERR_IEN Position */ +#define SYS_IRCTRIMIEN_CLKERR_IEN_Msk (1ul << SYS_IRCTRIMIEN_CLKERR_IEN_Pos) /*!< GCR_T::IRCTRIMIEN: CLKERR_IEN Mask */ + +#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos 1 /*!< GCR_T::IRCTRIMIEN: TRIM_FAIL_IEN Position */ +#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos) /*!< GCR_T::IRCTRIMIEN: TRIM_FAIL_IEN Mask */ + +/* GCR IRCTRIMINT Bit Field Definitions */ +#define SYS_IRCTRIMINT_CLKERR_INT_Pos 2 /*!< GCR_T::IRCTRIMINT: CLKERR_INT Position */ +#define SYS_IRCTRIMINT_CLKERR_INT_Msk (1ul << SYS_IRCTRIMINT_CLKERR_INT_Pos) /*!< GCR_T::IRCTRIMINT: CLKERR_INT Mask */ + +#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos 1 /*!< GCR_T::IRCTRIMINT: TRIM_FAIL_INT Position */ +#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos) /*!< GCR_T::IRCTRIMINT: TRIM_FAIL_INT Mask */ + +#define SYS_IRCTRIMINT_FREQ_LOCK_Pos 0 /*!< GCR_T::IRCTRIMINT: FREQ_LOCK Position */ +#define SYS_IRCTRIMINT_FREQ_LOCK_Msk (1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos) /*!< GCR_T::IRCTRIMINT: FREQ_LOCK Mask */ + +/* GCR REGWRPROT Bit Field Definitions */ +#define SYS_REGWRPROT_REGWRPROT_Pos 0 /*!< GCR_T::REGWRPROT: REGWRPROT Position */ +#define SYS_REGWRPROT_REGWRPROT_Msk (0xFFul << SYS_REGWRPROT_REGWRPROT_Pos) /*!< GCR_T::REGWRPROT: REGWRPROT Mask */ + +#define SYS_REGWRPROT_REGPROTDIS_Pos 0 /*!< GCR_T::REGWRPROT: REGPROTDIS Position */ +#define SYS_REGWRPROT_REGPROTDIS_Msk (1ul << SYS_REGWRPROT_REGPROTDIS_Pos) /*!< GCR_T::REGWRPROT: REGPROTDIS Mask */ + + + +typedef struct +{ + + /** + * @var GCR_INT_T::IRQSRC[32] + * Offset: 0x00-0x7C IRQn(n=0~31) Interrupt Source Identity Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |INT_SRC |Interrupt Source Identity + * | | |IRQ_SRC[0].0 - BOD INT + * | | |IRQ_SRC[1].0 - WDT INT + * | | |IRQ_SRC[1].1 - WWDT INT + * | | |IRQ_SRC[2].0 - EINT0, external interrupt 0 from PB.14 + * | | |IRQ_SRC[3].0 - EINT1, external interrupt 1 from PB.15 + * | | |IRQ_SRC[4].0 - GPA INT + * | | |IRQ_SRC[4].1 - GPB INT + * | | |IRQ_SRC[5].0 - GPC INT + * | | |IRQ_SRC[5].1 - GPD INT + * | | |IRQ_SRC[5].2 - GPE INT + * | | |IRQ_SRC[5].3 - GPF INT + * | | |IRQ_SRC[6].0 - PWM0 INT + * | | |IRQ_SRC[6].1 - PWM1 INT + * | | |IRQ_SRC[6].2 - PWM2 INT + * | | |IRQ_SRC[6].3 - PWM3 INT + * | | |IRQ_SRC[7].0 - PWM4 INT + * | | |IRQ_SRC[7].1 - PWM5 INT + * | | |IRQ_SRC[7].2 - PWM6 INT + * | | |IRQ_SRC[7].3 - PWM7 INT + * | | |IRQ_SRC[8].0 - TMR0 INT + * | | |IRQ_SRC[9].0 - TMR1 INT + * | | |IRQ_SRC[10].0 - TMR2 INT + * | | |IRQ_SRC[11].0 - TMR3 INT + * | | |IRQ_SRC[12].0 - UART0 INT + * | | |IRQ_SRC[12].1 - UART2 INT + * | | |IRQ_SRC[13].0 - UART1 INT + * | | |IRQ_SRC[14].0 - SPI0 INT + * | | |IRQ_SRC[15].0 - SPI1 INT + * | | |IRQ_SRC[16].0 - SPI2 INT + * | | |IRQ_SRC[17].0 - SPI3 INT + * | | |IRQ_SRC[18].0 - I2C0 INT + * | | |IRQ_SRC[19].0 - I2C1 INT + * | | |IRQ_SRC[22].0 - SC0 INT + * | | |IRQ_SRC[22].1 - SC1 INT + * | | |IRQ_SRC[22].2 - SC2 INT + * | | |IRQ_SRC[23].0 - USB INT + * | | |IRQ_SRC[24].0 - PS2 INT + * | | |IRQ_SRC[25].0 - ACMP INT + * | | |IRQ_SRC[26].0 - PDMA INT + * | | |IRQ_SRC[27].0 - I2S INT + * | | |IRQ_SRC[28].0 - Power Down Wake up INT + * | | |IRQ_SRC[29].0 - ADC INT + * | | |IRQ_SRC[30].0 - IRC INT + * | | |IRQ_SRC[31].0 - RTC INT + * @var GCR_INT_T::NMISEL + * Offset: 0x80 NMI Interrupt Source Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NMI_SEL |NMI interrupt source selection + * | | |The NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number. + * | | |The default NMI interrupt is assigned as IRQ0 interrupt if NMI is enabled by setting NMI_SEL[8]. + * |[8] |NMI_EN |NMI interrupt enable (Write Protect) + * | | |0 = IRQ0~31 assigned to NMI interrupt Disabled. (NMI still can be software triggered by setting its pending flag.) + * | | |1 = IRQ0~31 assigned to NMI interrupt Enabled. + * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register. + * @var GCR_INT_T::MCUIRQ + * Offset: 0x84 MCU Interrupt Request Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MCU_IRQ |MCU IRQ Source Register + * | | |The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. + * | | |When the MCU_IRQ[n] is 0: + * | | |0 = No effect. + * | | |1 = Generate an interrupt to Cortex_M0 NVIC[n]. + * | | |When the MCU_IRQ[n] is 1 (means an interrupt is assert): + * | | |0 = No effect. + * | | |1 = Clear the interrupt and MCU_IRQ[n]. + */ + + __I uint32_t IRQSRC[32]; /* Offset: 0x00-0x7C IRQn(n=0~31) Interrupt Source Identity Register */ + __IO uint32_t NMISEL; /* Offset: 0x80 NMI Interrupt Source Select Control Register */ + __IO uint32_t MCUIRQ; /* Offset: 0x84 MCU Interrupt Request Source Register */ + +} GCR_INT_T; + + + +/* INT IRQSRC Bit Field Definitions */ +#define INT_IRQSRC_INT_SRC_Pos 0 /*!< GCR_INT_T::IRQSRC: INT_SRC Position */ +#define INT_IRQSRC_INT_SRC_Msk (0xFul << INT_IRQSRC_INT_SRC_Pos) + +/* INT NMISEL Bit Field Definitions */ +#define INT_NMISEL_NMI_EN_Pos 8 /*!< GCR_INT_T::NMISEL: NMI_EN Position */ +#define INT_NMISEL_NMI_EN_Msk (1ul << INT_NMISEL_NMI_EN_Pos) /*!< GCR_INT_T::NMISEL: NMI_EN Mask */ + +#define INT_NMISEL_NMI_SEL_Pos 0 /*!< GCR_INT_T::NMISEL: NMI_SEL Position */ +#define INT_NMISEL_NMI_SEL_Msk (0x1Ful << INT_NMISEL_NMI_SEL_Pos) /*!< GCR_INT_T::NMISEL: NMI_SEL Mask */ + +/* INT MCUIRQ Bit Field Definitions */ +#define INT_MCUIRQ_MCU_IRQ_Pos 0 /*!< GCR_INT_T::MCUIRQ: MCU_IRQ Position */ +#define INT_MCUIRQ_MCU_IRQ_Msk (0xFFFFFFFFul << INT_MCUIRQ_MCU_IRQ_Pos) /*!< GCR_INT_T::MCUIRQ: MCU_IRQ Mask */ +/*@}*/ /* end of group SYS_CONST */ +/*@}*/ /* end of group SYS */ + + + + +/*---------------------- Timer Controller -------------------------*/ +/** + @addtogroup TIMER Timer Controller (TIMER) + Memory Mapped Structure for TMR Controller +@{ */ + + +typedef struct +{ + + +/** + * @var TIMER_T::TCSR + * Offset: 0x00 Timer Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PRESCALE |Prescale Counter + * | | |Timer input clock source is divided by (PRESCALE+1) before it is fed to the Timer up + * | | |counter. + * | | |If this field is 0 (PRESCALE = 0), then there is no scaling. + * |[16] |TDR_EN |Data Load Enable Control + * | | |When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit + * | | |up-timer value as the timer is counting. + * | | |0 = Timer Data Register update Disabled. + * | | |1 = Timer Data Register update Enabled while Timer counter is active. + * |[23] |WAKE_EN |Wake Up Function Enable Control + * | | |0 = Wake-up trigger event Disabled. + * | | |1 = Wake-up trigger event Enabled. + * |[24] |CTB |Counter Mode Enable Control + * | | |This bit is for external counting pin function enabled. + * | | |When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer + * | | |clock source. + * | | |Please refer to 5.17.5.6 for detail description. + * | | |0 = External counter mode Disabled. + * | | |1 = External counter mode Enabled. + * |[25] |CACT |Timer Active Status (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * |[26] |CRST |Timer Reset + * | | |0 = No effect. + * | | |1 = Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1. + * |[28:27] |MODE |Timer Operating Mode + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |IE |Interrupt Enable Control + * | | |0 = Timer Interrupt function Disabled. + * | | |1 = Timer Interrupt function Enabled. + * | | |If this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer + * | | |interrupt signal is generated and inform to CPU. + * |[30] |CEN |Timer Enable Control + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CEN to 1 will enable the 24-bit up counter to keep + * | | |counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TCSR [28:27] = 00) when the + * | | |timer interrupt flag (TISR[0] TIF) is generated. + * |[31] |DBGACK_TMR|ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * @var TIMER_T::TCMPR + * Offset: 0x04 Timer Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TCMP |Timer Compared Value + * | | |TCMP is a 24-bit compared value register. + * | | |When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to + * | | |1. + * | | |Time-out period = (Period of Timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP). + * | | |Note1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep + * | | |counting continuously even if user writes a new value into TCMP field. + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting and + * | | |using newest TCMP value to be the timer compared value if user writes a new value into TCMP + * | | |field. + * @var TIMER_T::TISR + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value. + * | | |0 = No effect. + * | | |1 = TDR value matches the TCMP value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWF |Timer Wake-Up Flag + * | | |This bit indicates the interrupt wake-up flag status of Timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::TDR + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TDR |Timer Data Register + * | | |If TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor + * | | |24-bit up counter value. + * @var TIMER_T::TCAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TCAP |Timer Capture Data Register + * | | |When TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed + * | | |immediately. + * @var TIMER_T::TEXCON + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TX_PHASE |Timer External Count Pin Phase Detect Selection + * | | |This bit indicates the detection phase of TMx pin. + * | | |0 = A falling edge of TMx pin will be counted. + * | | |1 = A rising edge of TMx pin will be counted. + * |[2:1] |TEX_EDGE |Timer External Capture Pin Edge Detect Selection + * | | |00 = A 1 to 0 transition on TMx_EXT pin will be detected. + * | | |01 = A 0 to 1 transition on TMx_EXT pin will be detected. + * | | |10 = Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected. + * | | |11 = Reserved. + * |[3] |TEXEN |Timer External Pin Function Enable + * | | |This bit enables the RSTCAPSEL function on the TxEX pin. + * | | |0 = RSTCAPSEL function of TxEX pin will be ignored. + * | | |1 = RSTCAPSEL function of TxEX pin is active. + * |[4] |RSTCAPSEL |Timer External Reset Counter / Timer External Capture Mode Selection + * | | |0 = Transition on TMx_EXT + * | | |pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1. + * | | |1 = Transition on TMx_EXT pin is using to reset the 24-bit up counter. + * |[5] |TEXIEN |Timer External Capture Interrupt Enable Control + * | | |0 = TMx_EXT pin detection Interrupt Disabled. + * | | |1 = TMx_EXT pin detection Interrupt Enabled. + * | | |If TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU + * | | |while TEXIF flag is set to 1. + * |[6] |TEXDB |Timer External Capture Input Pin De-Bounce Enable Control + * | | |0 = TMx_EXT pin de-bounce Disabled. + * | | |1 = TMx_EXT pin de-bounce Enabled. + * | | |If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce + * | | |circuit. + * |[7] |TCDB |Timer External Counter Input Pin De-Bounce Enable Control + * | | |0 = TMx pin de-bounce Disabled. + * | | |1 = TMx pin de-bounce Enabled. + * | | |If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * @var TIMER_T::TEXISR + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TEXIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the external capture interrupt flag status. + * | | |When TEXEN enabled, TMx_EXT pin selected as external capture function, and a transition on + * | | |TMx_EXT pin matched the TEX_EDGE setting, this flag will set to 1 by hardware. + * | | |1 = TMx_EXT + * | | |pin interrupt occurred. + * | | |0 = TMx_EXT + * | | |pin interrupt did not occur. + * | | |Note: This bit is cleared by writing 1 to it. + */ + + __IO uint32_t TCSR; /* Offset: 0x00 Timer Control and Status Register */ + __IO uint32_t TCMPR; /* Offset: 0x04 Timer Compare Register */ + __IO uint32_t TISR; /* Offset: 0x08 Timer Interrupt Status Register */ + __I uint32_t TDR; /* Offset: 0x0C Timer Data Register */ + __I uint32_t TCAP; /* Offset: 0x10 Timer Capture Data Register */ + __IO uint32_t TEXCON; /* Offset: 0x14 Timer External Control Register */ + __IO uint32_t TEXISR; /* Offset: 0x18 Timer External Interrupt Status Register */ + +} TIMER_T; + + + +/** + @addtogroup TIMER_CONST TMR Bit Field Definition + Constant Definitions for TMR Controller +@{ */ + +/* TIMER TCSR Bit Field Definitions */ +#define TIMER_TCSR_DBGACK_TMR_Pos 31 /*!< TIMER_T::TCSR: DBGACK_TMR Position */ +#define TIMER_TCSR_DBGACK_TMR_Msk (1ul << TIMER_TCSR_DBGACK_TMR_Pos) /*!< TIMER_T::TCSR: DBGACK_TMR Mask */ + +#define TIMER_TCSR_CEN_Pos 30 /*!< TIMER_T::TCSR: CEN Position */ +#define TIMER_TCSR_CEN_Msk (1ul << TIMER_TCSR_CEN_Pos) /*!< TIMER_T::TCSR: CEN Mask */ + +#define TIMER_TCSR_IE_Pos 29 /*!< TIMER_T::TCSR: IE Position */ +#define TIMER_TCSR_IE_Msk (1ul << TIMER_TCSR_IE_Pos) /*!< TIMER_T::TCSR: IE Mask */ + +#define TIMER_TCSR_MODE_Pos 27 /*!< TIMER_T::TCSR: MODE Position */ +#define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos) /*!< TIMER_T::TCSR: MODE Mask */ + +#define TIMER_TCSR_CRST_Pos 26 /*!< TIMER_T::TCSR: CRST Position */ +#define TIMER_TCSR_CRST_Msk (1ul << TIMER_TCSR_CRST_Pos) /*!< TIMER_T::TCSR: CRST Mask */ + +#define TIMER_TCSR_CACT_Pos 25 /*!< TIMER_T::TCSR: CACT Position */ +#define TIMER_TCSR_CACT_Msk (1ul << TIMER_TCSR_CACT_Pos) /*!< TIMER_T::TCSR: CACT Mask */ + +#define TIMER_TCSR_CTB_Pos 24 /*!< TIMER_T::TCSR: CTB Position */ +#define TIMER_TCSR_CTB_Msk (1ul << TIMER_TCSR_CTB_Pos) /*!< TIMER_T::TCSR: CTB Mask */ + +#define TIMER_TCSR_WAKE_EN_Pos 23 /*!< TIMER_T::TCSR: WAKE_EN Position */ +#define TIMER_TCSR_WAKE_EN_Msk (1ul << TIMER_TCSR_WAKE_EN_Pos) /*!< TIMER_T::TCSR: WAKE_EN Mask */ + +#define TIMER_TCSR_TDR_EN_Pos 16 /*!< TIMER_T::TCSR: TDR_EN Position */ +#define TIMER_TCSR_TDR_EN_Msk (1ul << TIMER_TCSR_TDR_EN_Pos) /*!< TIMER_T::TCSR: TDR_EN Mask */ + +#define TIMER_TCSR_PRESCALE_Pos 0 /*!< TIMER_T::TCSR: PRESCALE Position */ +#define TIMER_TCSR_PRESCALE_Msk (0xFFul << TIMER_TCSR_PRESCALE_Pos) /*!< TIMER_T::TCSR: PRESCALE Mask */ + +/* TIMER TCMPR Bit Field Definitions */ +#define TIMER_TCMP_TCMP_Pos 0 /*!< TIMER_T::TCMPR: TCMP Position */ +#define TIMER_TCMP_TCMP_Msk (0xFFFFFFul << TIMER_TCMP_TCMP_Pos) /*!< TIMER_T::TCMPR: TCMP Mask */ + +/* TIMER TISR Bit Field Definitions */ +#define TIMER_TISR_TWF_Pos 1 /*!< TIMER_T::TISR: TWF Position */ +#define TIMER_TISR_TWF_Msk (1ul << TIMER_TISR_TWF_Pos) /*!< TIMER_T::TISR: TWF Mask */ + +#define TIMER_TISR_TIF_Pos 0 /*!< TIMER_T::TISR: TIF Position */ +#define TIMER_TISR_TIF_Msk (1ul << TIMER_TISR_TIF_Pos) /*!< TIMER_T::TISR: TIF Mask */ + +/* TIMER TDR Bit Field Definitions */ +#define TIMER_TDR_TDR_Pos 0 /*!< TIMER_T::TDR: TDR Position */ +#define TIMER_TDR_TDR_Msk (0xFFFFFFul << TIMER_TDR_TDR_Pos) /*!< TIMER_T::TDR: TDR Mask */ + +/* TIMER TCAP Bit Field Definitions */ +#define TIMER_TCAP_TCAP_Pos 0 /*!< TIMER_T::TCAP: TCAP Position */ +#define TIMER_TCAP_TCAP_Msk (0xFFFFFFul << TIMER_TCAP_TCAP_Pos) /*!< TIMER_T::TCAP: TCAP Mask */ + +/* TIMER TEXCON Bit Field Definitions */ +#define TIMER_TEXCON_TCDB_Pos 7 /*!< TIMER_T::TEXCON: TCDB Position */ +#define TIMER_TEXCON_TCDB_Msk (1ul << TIMER_TEXCON_TCDB_Pos) /*!< TIMER_T::TEXCON: TCDB Mask */ + +#define TIMER_TEXCON_TEXDB_Pos 6 /*!< TIMER_T::TEXCON: TEXDB Position */ +#define TIMER_TEXCON_TEXDB_Msk (1ul << TIMER_TEXCON_TEXDB_Pos) /*!< TIMER_T::TEXCON: TEXDB Mask */ + +#define TIMER_TEXCON_TEXIEN_Pos 5 /*!< TIMER_T::TEXCON: TEXIEN Position */ +#define TIMER_TEXCON_TEXIEN_Msk (1ul << TIMER_TEXCON_TEXIEN_Pos) /*!< TIMER_T::TEXCON: TEXIEN Mask */ + +#define TIMER_TEXCON_RSTCAPSEL_Pos 4 /*!< TIMER_T::TEXCON: RSTCAPSEL Position */ +#define TIMER_TEXCON_RSTCAPSEL_Msk (1ul << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< TIMER_T::TEXCON: RSTCAPSEL Mask */ + +#define TIMER_TEXCON_TEXEN_Pos 3 /*!< TIMER_T::TEXCON: TEXEN Position */ +#define TIMER_TEXCON_TEXEN_Msk (1ul << TIMER_TEXCON_TEXEN_Pos) /*!< TIMER_T::TEXCON: TEXEN Mask */ + +#define TIMER_TEXCON_TEX_EDGE_Pos 1 /*!< TIMER_T::TEXCON: TEX_EDGE Position */ +#define TIMER_TEXCON_TEX_EDGE_Msk (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos) /*!< TIMER_T::TEXCON: TEX_EDGE Mask */ + +#define TIMER_TEXCON_TX_PHASE_Pos 0 /*!< TIMER_T::TEXCON: TX_PHASE Position */ +#define TIMER_TEXCON_TX_PHASE_Msk (1ul << TIMER_TEXCON_TX_PHASE_Pos) /*!< TIMER_T::TEXCON: TX_PHASE Mask */ + +/* TIMER TEXISR Bit Field Definitions */ +#define TIMER_TEXISR_TEXIF_Pos 0 /*!< TIMER_T::TEXISR: TEXIF Position */ +#define TIMER_TEXISR_TEXIF_Msk (1ul << TIMER_TEXISR_TEXIF_Pos) /*!< TIMER_T::TEXISR: TEXIF Mask */ +/*@}*/ /* end of group TIMER_CONST */ +/*@}*/ /* end of group TIMER */ + + + +/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/ +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller (UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + +/** + * @var UART_T::DATA + * Offset: 0x00 UART Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |Data Register + * | | |By writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first). + * | | |By reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first). + * @var UART_T::THR + * Offset: 0x00 UART Transmit Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |THR |Transmit Holding Register + * | | |By writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first). + * @var UART_T::RBR + * Offset: 0x00 UART Receive Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RBR |Receive Buffer Register (Read Only) + * | | |By reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first). + * @var UART_T::IER + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDA_IEN |Receive Data Available Interrupt Enable Control + * | | |0 = RDA_INT Masked off. + * | | |1 = RDA_INT Enabled. + * |[1] |THRE_IEN |Transmit Holding Register Empty Interrupt Enable Control + * | | |0 = THRE_INT Masked off. + * | | |1 = THRE_INT Enabled. + * |[2] |RLS_IEN |Receive Line Status Interrupt Enable Control + * | | |0 = RLS_INT Masked off. + * | | |1 = RLS_INT Enabled + * |[3] |MODEM_IEN |Modem Status Interrupt Enable Control (Not Available In UART2 Channel) + * | | |0 = MODEM_INT Masked off. + * | | |1 = MODEM_INT Enabled. + * |[4] |TOUT_IEN |RX Time-Out Interrupt Enable Control + * | | |0 = TOUT_INT Masked off. + * | | |1 = TOUT_INT Enabled. + * |[5] |BUF_ERR_IEN|Buffer Error Interrupt Enable Control + * | | |0 = BUF_ERR_INT Masked off. + * | | |1 = BUF_ERR_INT Enabled. + * |[6] |WAKE_EN |UART Wake-Up Function Enable (Not Available In UART2 Channel) + * | | |0 = UART wake-up function Disabled. + * | | |1 = UART wake-up function Enabled, when the chip is in Power-down mode, an external CTS + * | | |change will wake-up chip from Power-down mode. + * |[8] |LIN_IEN |LIN Bus Interrupt Enable + * | | |0 = Lin bus interrupt Disabled. + * | | |1 = Lin bus interrupt Enabled. + * | | |Note: This field is used for LIN function mode. + * |[11] |TIME_OUT_EN|Time-Out Counter Enable + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * |[12] |AUTO_RTS_EN|RTS Auto Flow Control Enable (Not Available in UART2 Channel) + * | | |0 = RTS auto flow control Disabled. + * | | |1 = RTS auto flow control Enabled. + * | | |When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. + * |[13] |AUTO_CTS_EN|CTS Auto Flow Control Enable (Not Available in UART2 Channel) + * | | |0 = CTS auto flow control Disabled. + * | | |1 = CTS auto flow control Enabled. + * | | |When CTS auto-flow is enabled, the UART will send data to external device when CTS input + * | | |assert (UART will not send data to device until CTS is asserted). + * |[14] |DMA_TX_EN |TX DMA Enable (Not Available In UART2 Channel) + * | | |This bit can enable or disable TX DMA service. + * | | |0 = TX DMA Disabled. + * | | |1 = TX DMA Enabled. + * |[15] |DMA_RX_EN |RX DMA Enable (Not Available In UART2 Channel) + * | | |This bit can enable or disable RX DMA service. + * | | |0 = RX DMA Disabled. + * | | |1 = RX DMA Enabled. + * @var UART_T::FCR + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RFR |RX Field Software Reset + * | | |When RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles. + * |[2] |TFR |TX Field Software Reset + * | | |When TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if RDA_IEN (UA_IER[0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |0100 = RX FIFO Interrupt Trigger Level is 30/14 bytes (High Speed/Normal Speed). + * | | |0101 = RX FIFO Interrupt Trigger Level is 46/14 bytes (High Speed/Normal Speed). + * | | |0110 = RX FIFO Interrupt Trigger Level is 62/14 bytes (High Speed/Normal Speed). + * | | |Other = Reserved. + * |[8] |RX_DIS |Receiver Disable Register + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485_NMM (UA_ALT_CSR[8]) is programmed. + * |[19:16] |RTS_TRI_LEV|RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel) + * | | |0000 = RTS Trigger Level is 1 byte. + * | | |0001 = RTS Trigger Level is 4 bytes. + * | | |0010 = RTS Trigger Level is 8 bytes. + * | | |0011 = RTS Trigger Level is 14 bytes. + * | | |0100 = RTS Trigger Level is 30/14 bytes (High Speed/Normal Speed). + * | | |0101 = RTS Trigger Level is 46/14 bytes (High Speed/Normal Speed). + * | | |0110 = RTS Trigger Level is 62/14 bytes (High Speed/Normal Speed). + * | | |Other = Reserved. + * | | |Note: This field is used for RTS auto-flow control. + * @var UART_T::LCR + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |00 = Word length is 5-bit. + * | | |01 = Word length is 6-bit. + * | | |10 = Word length is 7-bit + * | | |11 = Word length is 8-bit + * |[2] |NSB |Number Of "STOP Bit" + * | | |0 = One " STOP bit" is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. + * | | |When select 6-,7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable + * | | |0 = No parity bit. + * | | |1 = Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |This bit has effect only when PBE (UA_LCR[3]) is set. + * |[5] |SPE |Stick Parity Enable + * | | |0 = Stick parity Disabled. + * | | |1 = If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. + * | | |If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). + * | | |This bit acts only on TX and has no effect on the transmitter logic. + * @var UART_T::MCR + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel) + * | | |This bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration. + * | | |0 = RTS signal is active. + * | | |1 = RTS signal is inactive. + * | | |Note1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode. + * | | |Note2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |LEV_RTS |RTS Pin Active Level (Not Available In UART2 Channel) + * | | |This bit defines the active level state of RTS pin output. + * | | |0 = RTS pin output is high level active. + * | | |1 = RTS pin output is low level active. + * |[13] |RTS_ST |RTS Pin State (Read Only) (Not Available In UART2 Channel) + * | | |This bit mirror from RTS pin output of voltage logic status. + * | | |0 = RTS pin output is low level voltage logic state. + * | | |1 = RTS pin output is high level voltage logic state. + * @var UART_T::MSR + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DCTSF |Detect CTS State Change Flag (Not Available In UART2 Channel) + * | | |This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1. + * | | |0 = CTS input has not change state. + * | | |1 = CTS input has change state. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[4] |CTS_ST |CTS Pin Status (Read Only) (Not Available In UART2 Channel) + * | | |This bit mirror from CTS pin input of voltage logic status. + * | | |0 = CTS pin input is low level voltage logic state. + * | | |1 = CTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. + * |[8] |LEV_CTS |CTS Pin Active Level + * | | |This bit defines the active level state of CTS pin input. + * | | |0 = CTS pin input is high level active. + * | | |1 = CTS pin input is low level active. + * @var UART_T::FSR + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RX_OVER_IF|RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[3] |RS485_ADD_DETF|RS-485 Address Byte Detection Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='1'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit. + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[13:8] |RX_POINTER|RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer. + * | | |When UART receives one byte from external device, then RX_POINTER increases one. + * | | |When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one. + * | | |The Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). + * | | |When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. + * | | |As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2). + * |[14] |RX_EMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. + * |[15] |RX_FULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO is full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware. + * |[21:16] |TX_POINTER|TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer. + * | | |When CPU writes one byte into UA_THR, then TX_POINTER increases one. + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one. + * | | |The Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). + * | | |When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2). + * |[22] |TX_EMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). + * |[23] |TX_FULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |This bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware. + * |[24] |TX_OVER_IF|TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[28] |TE_FLAG |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * @var UART_T::ISR + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDA_IF |Receive Data Available Interrupt Flag (Read Only) + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. + * | | |If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). + * |[1] |THRE_IF |Transmit Holding Register Empty Interrupt Flag (Read Only) + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. + * | | |If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). +* |[2] |RLS_IF |Receive Line Interrupt Flag +* | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). +* | | |If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. +* | | |0 = No RLS interrupt flag is generated. +* | | |1 = RLS interrupt flag is generated. +* | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit. At the same time, the bit of RS485_ADD_DETF(UA_FSR[3]) is also set. +* | | |Note2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared. +* | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. + * |[3] |MODEM_IF |MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel) + * | | |This bit is set when the CTS pin has state change (DCTSF (UA_MSR[0]) = 1). + * | | |If MODEM_IEN (UA_IER [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). + * |[4] |TOUT_IF |Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC(UA_TOR[7:0]). + * | | |If TOUT_IEN (UA_IER [4]) is enabled, the Time-out interrupt will be generated. + * | | |0 = No Time-out interrupt flag is generated. + * | | |1 = Time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UA_RBR (RX is in active) to clear it. + * |[5] |BUF_ERR_IF|Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). + * | | |When BUF_ERR_IF (UA_ISR[5])is set, the transfer is not correct. + * | | |If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. + * |[7] |LIN_IF |LIN Bus Flag (Read Only) + * | | |This bit is set when LIN slave header detect (LINS_HDET_F (UA_LIN_SR[0] = 1)), LIN break detect (LIN_BKDET_F(UA_LIN_SR[9]=1)), bit error detect (BIT_ERR_F(UA_LIN_SR[9]=1), LIN slave ID parity error (LINS_IDPERR_F(UA_LIN_SR[2] = 1) or LIN slave header error detect (LINS_HERR_F (UA_LIN_SR[1])). + * | | |If LIN_ IEN (UA_IER [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated. + * | | |1 = At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated. + * | | |Note: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]), LIN_BKDET_F(UA_LIN_SR[9]), BIT_ERR_F(UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared. + * |[8] |RDA_INT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THRE_INT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLS_INT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated + * |[11] |MODEM_INT |MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel) + * | | |This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |TOUT_INT |Time-Out Interrupt Indicator (Read Only) + * | | |This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1. + * | | |0 = No Time-Out interrupt is generated. + * | | |1 = Time-Out interrupt is generated. + * |[13] |BUF_ERR_INT|Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[15] |LIN_INT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[18] |HW_RLS_IF |In DMA Mode, Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). + * | | |If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in DMA mode. + * | | |1 = RLS interrupt flag is generated in DMA mode. + * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit. + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. + * |[19] |HW_MODEM_IF|In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel) + * | | |This bit is set when the CTS pin has state change (DCTSF (US_MSR[0] =1)). + * | | |If MODEM_IEN (UA_IER [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in DMA mode. + * | | |1 = Modem interrupt flag is generated in DMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0]). + * |[20] |HW_TOUT_IF|In DMA Mode, Time-Out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). + * | | |If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated. + * | | |0 = No Time-out interrupt flag is generated in DMA mode. + * | | |1 = Time-out interrupt flag is generated in DMA mode. + * | | |Note: This bit is read only and user can read UA_RBR (RX is in active) to clear it. + * |[21] |HW_BUF_ERR_IF|In DMA Mode, Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). + * | | |When BUF_ERR_IF (UA_ISR[5]) is set, the transfer maybe is not correct. + * | | |If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in DMA mode. + * | | |1 = Buffer error interrupt flag is generated in DMA mode. + * | | |Note: This bit is cleared when both TX_OVER_IF (UA_FSR[24]]) and RX_OVER_IF (UA_FSR[0]) are cleared. + * |[26] |HW_RLS_INT|In DMA Mode, Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in DMA mode. + * | | |1 = RLS interrupt is generated in DMA mode. + * |[27] |HW_MODEM_INT|In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel) + * | | |This bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1. + * | | |0 = No Modem interrupt is generated in DMA mode. + * | | |1 = Modem interrupt is generated in DMA mode. + * |[28] |HW_TOUT_INT|In DMA Mode, Time-Out Interrupt Indicator (Read Only) + * | | |This bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1. + * | | |0 = No Tout interrupt is generated in DMA mode. + * | | |1 = Tout interrupt is generated in DMA mode. + * |[29] |HW_BUF_ERR_INT|In DMA Mode, Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1. + * | | |0 = No buffer error interrupt is generated in DMA mode. + * | | |1 = Buffer error interrupt is generated in DMA mode. + * @var UART_T::TOR + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UA_TOR[7:0])), a receiver time-out interrupt is generated if TOUT_IEN (UA_IER [4]) enabled. + * | | |A new incoming data word or RX FIFO empty will clear TOUT_IF(UA_IER[4]). + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC (UA_TOR[7:0]) value should be set between 40 and 255. + * | | |So, for example, if TOIC (UA_TOR[7:0]) is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divisor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider. + * |[27:24] |DIVIDER_X |Divider X + * | | |The baud rate divider M = X+1. + * |[28] |DIV_X_ONE |Divider X Equal To 1 + * | | |0 = Divider M is X+1 (the equation of M = X+1, but DIVIDER_X[27:24] must >= 8). + * | | |1 = Divider M is 1. + * |[29] |DIV_X_EN |Divider X Enable + * | | |The BRD = Baud Rate Divider, and the baud rate equation is + * | | |Baud Rate = Clock / [M * (BRD + 2)]; The default value of M is 16. + * | | |0 = Divider X Disabled (the equation of M = 16). + * | | |1 = Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must >= 8). + * | | |Note: In IrDA mode, this bit must disable. + * @var UART_T::IRCR + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TX_SELECT |IrDA Receiver/Transmitter Selection Enable Control + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |INV_TX |IrDA inverse Transmitting Output Signal Control + * | | |0 = None inverse transmitting signal. + * | | |1 = Inverse transmitting output signal. + * |[6] |INV_RX |IrDA inverse Receive Input Signal Control + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. + * @var UART_T::ALT_CSR + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LIN_BKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is UA_LIN_BKFL + 1 + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LIN_RX_EN |LIN RX Enable + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LIN_TX_EN |LIN TX Break Mode Enable + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485_NMM |RS-485 Normal Multi-Drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485_AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485_AUD |RS-485 Auto Direction Mode (AUD) + * | | |0 = RS-485 Auto Direction Operation mode (AUO) Disabled. + * | | |1 = RS-485 Auto Direction Operation mode (AUO) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |RS485_ADD_EN|RS-485 Address Detection Enable + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[31:24] |ADDR_MATCH|Address Match Value Register + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUN_SEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FUN_SEL |Function Select Enable + * | | |00 = UART function Enabled. + * | | |01 = LIN function Enabled. + * | | |10 = IrDA function Enabled. + * | | |11 = RS-485 function Enabled. + * @var UART_T::LIN_CTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LINS_EN |LIN Slave Mode Enable Control + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |LINS_HDET_EN|LIN Slave Header Detection Enable Control + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (LINS_EN (UA_LIN_CTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), LINS_HDET_F (UA_LIN_SR [0]) flag will be asserted. If the LIN_IEN (UA_IER[8]) = 1, an interrupt will be generated. + * |[2] |LINS_ARS_EN|LIN Slave Automatic Resynchronization Mode Enable Control + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (LINS_EN (UA_LIN_CTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1). + * | | |(Slave mode with automatic resynchronization). + * |[3] |LINS_DUM_EN|LIN Slave Divider Update Method Enable Control + * | | |0 = UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UA_BAUD is updated at the next received character. User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (LINS_EN (UA_LIN_CTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. + * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared). + * | | |(Slave mode with automatic resynchronization). + * |[4] |LIN_MUTE_EN|LIN Mute Mode Enable Control + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode). + * |[8] |LIN_SHD |LIN TX Send Header Enable Control + * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]). + * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |LIN_IDPEN |LIN ID Parity Enable Control + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (LIN_SHD (UA_LIN_CTL[8])) = 1 and LIN_HEAD_SEL (UA_LIN_CTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only use when the operation header transmitter is in LIN_HEAD_SEL (UA_LIN_CTL[23:22]) = 10. + * |[10] |LIN_BKDET_EN|LIN Break Detection Enable Control + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the LIN_BKDET_F (UA_LIN_SR[8]) flag is set in UA_LIN_SR register at the end of break field. + * | | |If the LIN_IEN (UA_IER [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled. + * | | |1 = LIN break detection Enabled. + * |[11] |LIN_RX_DIS|LIN Receiver Disable Control + * | | |If the receiver is enabled (LIN_RX_DIS (UA_LIN_CTL[11] ) = 0), all received byte data will be accepted and stored in the RX-FIFO, and if the receiver is disabled (LIN_RX_DIS (UA_LIN_CTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUN_SEL (UA_FUN_SEL[1:0]) = 01). + * |[12] |BIT_ERR_EN|Bit Error Detect Enable Control + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BIT_ERR_F (UA_LIN_SR[9]) flag will be asserted. If the LIN_IEN (UA_IER[8]) = 1, an interrupt will be generated. + * |[19:16] |LIN_BKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]. + * | | |Note2: This break field length is LIN_BKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |LIN_BS_LEN|LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1 bit time. + * | | |10 = The LIN break/sync delimiter length is 2 bit time. + * | | |10 = The LIN break/sync delimiter length is 3 bit time. + * | | |11 = The LIN break/sync delimiter length is 4 bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |LIN_HEAD_SEL|LIN Header Select + * | | |00 = The LIN header includes "break field". + * | | |01 = The LIN header includes "break field" and "sync field". + * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field". + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (LIN_SHD (UA_LIN_CTL [8]) = 1) or used to slave to indicates exit from mute mode condition (LIN_MUTE_EN (UA_LIN_CTL[4] = 1). + * |[31:24] |LIN_PID |LIN PID Register + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on LIN_IDPEN (UA_LIN_CTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LIN_SR + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LINS_HDET_F|LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit is can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (LINS_EN (UA_LIN_CTL [0]) = 1) and enable LIN slave header detection function (LINS_HDET_EN (UA_LIN_CTL [1])). + * | | |Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not. + * |[1] |LINS_HERR_F|LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out". + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (LINS_EN (UA_LIN_CTL [0]) = 1) and enables LIN slave header detection function (LINS_HDET_EN (UA_LIN_CTL [1])). + * |[2] |LINS_IDPERR_F|LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit iscan be cleared by writing "1" to it. + * | | |Note2: This bit is only valid when in LIN slave mode (LINS_EN (UA_LIN_CTL [0])= 1) and enable LIN frame ID parity check function LIN_IDPEN (UA_LIN_CTL [9]). + * |[3] |LINS_SYNC_F|LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (LINS_EN(UA_LIN_CTL[0]) = 1). + * | | |Note2: This bitcan be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |LIN_BKDET_F|LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bitcan be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (LIN_BKDET_EN (UA_LIN_CTL[10]) =1). + * |[9] |BIT_ERR_F |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set. + * | | |When occur bit error, if the LIN_IEN (UA_IER[8]) = 1, an interrupt will be generated. + * | | |Note1: This bit iscan be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BIT_ERR_EN (UA_LIN_CTL [12]) = 1). + */ + + union + { + __IO uint32_t DATA; /* Offset: 0x00 UART Data Register */ + __IO uint32_t THR; /* Offset: 0x00 UART Transmit Holding Register */ + __IO uint32_t RBR; /* Offset: 0x00 UART Receive Buffer Register */ + }; + __IO uint32_t IER; /* Offset: 0x04 UART Interrupt Enable Register */ + __IO uint32_t FCR; /* Offset: 0x08 UART FIFO Control Register */ + __IO uint32_t LCR; /* Offset: 0x0C UART Line Control Register */ + __IO uint32_t MCR; /* Offset: 0x10 UART Modem Control Register */ + __IO uint32_t MSR; /* Offset: 0x14 UART Modem Status Register */ + __IO uint32_t FSR; /* Offset: 0x18 UART FIFO Status Register */ + __IO uint32_t ISR; /* Offset: 0x1C UART Interrupt Status Register */ + __IO uint32_t TOR; /* Offset: 0x20 UART Time-out Register */ + __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */ + __IO uint32_t IRCR; /* Offset: 0x28 UART IrDA Control Register */ + __IO uint32_t ALT_CSR; /* Offset: 0x2C UART Alternate Control/Status Register */ + __IO uint32_t FUN_SEL; /* Offset: 0x30 UART Function Select Register */ + __IO uint32_t LIN_CTL; /* Offset: 0x34 UART LIN Control Register */ + __IO uint32_t LIN_SR; /* Offset: 0x38 UART LIN Status Register */ + + +} UART_T; + + + + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +/* UART THR Bit Field Definitions */ +#define UART_THR_THR_Pos 0 /*!< UART_T::THR: THR Position */ +#define UART_THR_THR_Msk (0xFul << UART_THR_THR_Pos) /*!< UART_T::THR: THR Mask */ + +/* UART RBR Bit Field Definitions */ +#define UART_RBR_RBR_Pos 0 /*!< UART_T::RBR: RBR Position */ +#define UART_RBR_RBR_Msk (0xFul << UART_RBR_RBR_Pos) /*!< UART_T::RBR: RBR Mask */ + +/* UART IER Bit Field Definitions */ +#define UART_IER_DMA_RX_EN_Pos 15 /*!< UART_T::IER: RX DMA Enable Position */ +#define UART_IER_DMA_RX_EN_Msk (1ul << UART_IER_DMA_RX_EN_Pos) /*!< UART_T::IER: RX DMA Enable Mask */ + +#define UART_IER_DMA_TX_EN_Pos 14 /*!< UART_T::IER: TX DMA Enable Position */ +#define UART_IER_DMA_TX_EN_Msk (1ul << UART_IER_DMA_TX_EN_Pos) /*!< UART_T::IER: TX DMA Enable Mask */ + +#define UART_IER_AUTO_CTS_EN_Pos 13 /*!< UART_T::IER: AUTO_CTS_EN Position */ +#define UART_IER_AUTO_CTS_EN_Msk (1ul << UART_IER_AUTO_CTS_EN_Pos) /*!< UART_T::IER: AUTO_CTS_EN Mask */ + +#define UART_IER_AUTO_RTS_EN_Pos 12 /*!< UART_T::IER: AUTO_RTS_EN Position */ +#define UART_IER_AUTO_RTS_EN_Msk (1ul << UART_IER_AUTO_RTS_EN_Pos) /*!< UART_T::IER: AUTO_RTS_EN Mask */ + +#define UART_IER_TIME_OUT_EN_Pos 11 /*!< UART_T::IER: TIME_OUT_EN Position */ +#define UART_IER_TIME_OUT_EN_Msk (1ul << UART_IER_TIME_OUT_EN_Pos) /*!< UART_T::IER: TIME_OUT_EN Mask */ + +#define UART_IER_LIN_IEN_Pos 8 /*!< UART_T::IER: LIN_IEN Position */ +#define UART_IER_LIN_IEN_Msk (1ul << UART_IER_LIN_IEN_Pos) /*!< UART_T::IER: LIN_IEN Mask */ + +#define UART_IER_WAKE_EN_Pos 6 /*!< UART_T::IER: WAKE_EN Position */ +#define UART_IER_WAKE_EN_Msk (1ul << UART_IER_WAKE_EN_Pos) /*!< UART_T::IER: WAKE_EN Mask */ + +#define UART_IER_BUF_ERR_IEN_Pos 5 /*!< UART_T::IER: BUF_ERR_IEN Position */ +#define UART_IER_BUF_ERR_IEN_Msk (1ul << UART_IER_BUF_ERR_IEN_Pos) /*!< UART_T::IER: BUF_ERR_IEN Mask */ + +#define UART_IER_TOUT_IEN_Pos 4 /*!< UART_T::IER: TOUT_IEN Position */ +#define UART_IER_TOUT_IEN_Msk (1ul << UART_IER_TOUT_IEN_Pos) /*!< UART_T::IER: TOUT_IEN Mask */ + +#define UART_IER_MODEM_IEN_Pos 3 /*!< UART_T::IER: MODEM_IEN Position */ +#define UART_IER_MODEM_IEN_Msk (1ul << UART_IER_MODEM_IEN_Pos) /*!< UART_T::IER: MODEM_IEN Mask */ + +#define UART_IER_RLS_IEN_Pos 2 /*!< UART_T::IER: RLS_IEN Position */ +#define UART_IER_RLS_IEN_Msk (1ul << UART_IER_RLS_IEN_Pos) /*!< UART_T::IER: RLS_IEN Mask */ + +#define UART_IER_THRE_IEN_Pos 1 /*!< UART_T::IER: THRE_IEN Position */ +#define UART_IER_THRE_IEN_Msk (1ul << UART_IER_THRE_IEN_Pos) /*!< UART_T::IER: THRE_IEN Mask */ + +#define UART_IER_RDA_IEN_Pos 0 /*!< UART_T::IER: RDA_IEN Position */ +#define UART_IER_RDA_IEN_Msk (1ul << UART_IER_RDA_IEN_Pos) /*!< UART_T::IER: RDA_IEN Mask */ + +/* UART FCR Bit Field Definitions */ +#define UART_FCR_RTS_TRI_LEV_Pos 16 /*!< UART_T::FCR: RTS_TRI_LEV Position */ +#define UART_FCR_RTS_TRI_LEV_Msk (0xFul << UART_FCR_RTS_TRI_LEV_Pos) /*!< UART_T::FCR: RTS_TRI_LEV Mask */ + +#define UART_FCR_RX_DIS_Pos 8 /*!< UART_T::FCR: RX_DIS Position */ +#define UART_FCR_RX_DIS_Msk (1ul << UART_FCR_RX_DIS_Pos) /*!< UART_T::FCR: RX_DIS Mask */ + +#define UART_FCR_RFITL_Pos 4 /*!< UART_T::FCR: RFITL Position */ +#define UART_FCR_RFITL_Msk (0xFul << UART_FCR_RFITL_Pos) /*!< UART_T::FCR: RFITL Mask */ + +#define UART_FCR_TFR_Pos 2 /*!< UART_T::FCR: TFR Position */ +#define UART_FCR_TFR_Msk (1ul << UART_FCR_TFR_Pos) /*!< UART_T::FCR: TFR Mask */ + +#define UART_FCR_RFR_Pos 1 /*!< UART_T::FCR: RFR Position */ +#define UART_FCR_RFR_Msk (1ul << UART_FCR_RFR_Pos) /*!< UART_T::FCR: RFR Mask */ + +/* UART LCR Bit Field Definitions */ +#define UART_LCR_BCB_Pos 6 /*!< UART_T::LCR: BCB Position */ +#define UART_LCR_BCB_Msk (1ul << UART_LCR_BCB_Pos) /*!< UART_T::LCR: BCB Mask */ + +#define UART_LCR_SPE_Pos 5 /*!< UART_T::LCR: SPE Position */ +#define UART_LCR_SPE_Msk (1ul << UART_LCR_SPE_Pos) /*!< UART_T::LCR: SPE Mask */ + +#define UART_LCR_EPE_Pos 4 /*!< UART_T::LCR: EPE Position */ +#define UART_LCR_EPE_Msk (1ul << UART_LCR_EPE_Pos) /*!< UART_T::LCR: EPE Mask */ + +#define UART_LCR_PBE_Pos 3 /*!< UART_T::LCR: PBE Position */ +#define UART_LCR_PBE_Msk (1ul << UART_LCR_PBE_Pos) /*!< UART_T::LCR: PBE Mask */ + +#define UART_LCR_NSB_Pos 2 /*!< UART_T::LCR: NSB Position */ +#define UART_LCR_NSB_Msk (1ul << UART_LCR_NSB_Pos) /*!< UART_T::LCR: NSB Mask */ + +#define UART_LCR_WLS_Pos 0 /*!< UART_T::LCR: WLS Position */ +#define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos) /*!< UART_T::LCR: WLS Mask */ + +/* UART MCR Bit Field Definitions */ +#define UART_MCR_RTS_ST_Pos 13 /*!< UART_T::MCR: RTS_ST Position */ +#define UART_MCR_RTS_ST_Msk (1ul << UART_MCR_RTS_ST_Pos) /*!< UART_T::MCR: RTS_ST Mask */ + +#define UART_MCR_LEV_RTS_Pos 9 /*!< UART_T::MCR: LEV_RTS Position */ +#define UART_MCR_LEV_RTS_Msk (1ul << UART_MCR_LEV_RTS_Pos) /*!< UART_T::MCR: LEV_RTS Mask */ + +#define UART_MCR_RTS_Pos 1 /*!< UART_T::MCR: RTS Position */ +#define UART_MCR_RTS_Msk (1ul << UART_MCR_RTS_Pos) /*!< UART_T::MCR: RTS Mask */ + +/* UART MSR Bit Field Definitions */ +#define UART_MSR_LEV_CTS_Pos 8 /*!< UART_T::MSR: LEV_CTS Position */ +#define UART_MSR_LEV_CTS_Msk (1ul << UART_MSR_LEV_CTS_Pos) /*!< UART_T::MSR: LEV_CTS Mask */ + +#define UART_MSR_CTS_ST_Pos 4 /*!< UART_T::MSR: CTS_ST Position */ +#define UART_MSR_CTS_ST_Msk (1ul << UART_MSR_CTS_ST_Pos) /*!< UART_T::MSR: CTS_ST Mask */ + +#define UART_MSR_DCTSF_Pos 0 /*!< UART_T::MSR: DCTST Position */ +#define UART_MSR_DCTSF_Msk (1ul << UART_MSR_DCTSF_Pos) /*!< UART_T::MSR: DCTST Mask */ + + +/* UART FSR Bit Field Definitions */ +#define UART_FSR_TE_FLAG_Pos 28 /*!< UART_T::FSR: TE_FLAG Position */ +#define UART_FSR_TE_FLAG_Msk (1ul << UART_FSR_TE_FLAG_Pos) /*!< UART_T::FSR: TE_FLAG Mask */ + +#define UART_FSR_TX_OVER_IF_Pos 24 /*!< UART_T::FSR: TX_OVER_IF Position */ +#define UART_FSR_TX_OVER_IF_Msk (1ul << UART_FSR_TX_OVER_IF_Pos) /*!< UART_T::FSR: TX_OVER_IF Mask */ + +#define UART_FSR_TX_FULL_Pos 23 /*!< UART_T::FSR: TX_FULL Position */ +#define UART_FSR_TX_FULL_Msk (1ul << UART_FSR_TX_FULL_Pos) /*!< UART_T::FSR: TX_FULL Mask */ + +#define UART_FSR_TX_EMPTY_Pos 22 /*!< UART_T::FSR: TX_EMPTY Position */ +#define UART_FSR_TX_EMPTY_Msk (1ul << UART_FSR_TX_EMPTY_Pos) /*!< UART_T::FSR: TX_EMPTY Mask */ + +#define UART_FSR_TX_POINTER_Pos 16 /*!< UART_T::FSR: TX_POINTER Position */ +#define UART_FSR_TX_POINTER_Msk (0x3Ful << UART_FSR_TX_POINTER_Pos) /*!< UART_T::FSR: TX_POINTER Mask */ + +#define UART_FSR_RX_FULL_Pos 15 /*!< UART_T::FSR: RX_FULL Position */ +#define UART_FSR_RX_FULL_Msk (1ul << UART_FSR_RX_FULL_Pos) /*!< UART_T::FSR: RX_FULL Mask */ + +#define UART_FSR_RX_EMPTY_Pos 14 /*!< UART_T::FSR: RX_EMPTY Position */ +#define UART_FSR_RX_EMPTY_Msk (1ul << UART_FSR_RX_EMPTY_Pos) /*!< UART_T::FSR: RX_EMPTY Mask */ + +#define UART_FSR_RX_POINTER_Pos 8 /*!< UART_T::FSR: RX_POINTERS Position */ +#define UART_FSR_RX_POINTER_Msk (0x3Ful << UART_FSR_RX_POINTER_Pos) /*!< UART_T::FSR: RX_POINTER Mask */ + +#define UART_FSR_BIF_Pos 6 /*!< UART_T::FSR: BIF Position */ +#define UART_FSR_BIF_Msk (1ul << UART_FSR_BIF_Pos) /*!< UART_T::FSR: BIF Mask */ + +#define UART_FSR_FEF_Pos 5 /*!< UART_T::FSR: FEF Position */ +#define UART_FSR_FEF_Msk (1ul << UART_FSR_FEF_Pos) /*!< UART_T::FSR: FEF Mask */ + +#define UART_FSR_PEF_Pos 4 /*!< UART_T::FSR: PEF Position */ +#define UART_FSR_PEF_Msk (1ul << UART_FSR_PEF_Pos) /*!< UART_T::FSR: PEF Mask */ + +#define UART_FSR_RS485_ADD_DETF_Pos 3 /*!< UART_T::FSR: RS485_ADD_DETF Position */ +#define UART_FSR_RS485_ADD_DETF_Msk (1ul << UART_FSR_RS485_ADD_DETF_Pos) /*!< UART_T::FSR: RS485_ADD_DETF Mask */ + +#define UART_FSR_RX_OVER_IF_Pos 0 /*!< UART_T::FSR: RX_OVER_IF Position */ +#define UART_FSR_RX_OVER_IF_Msk (1ul << UART_FSR_RX_OVER_IF_Pos) /*!< UART_T::FSR: RX_OVER_IF Mask */ + +/* UART ISR Bit Field Definitions */ +#define UART_ISR_HW_BUF_ERR_INT_Pos 29 /*!< UART_T::ISR: HW BUF_ERR_INT Position */ +#define UART_ISR_HW_BUF_ERR_INT_Msk (1ul << UART_ISR_HW_BUF_ERR_INT_Pos) /*!< UART_T::ISR: HW BUF_ERR_INT Mask */ + +#define UART_ISR_HW_TOUT_INT_Pos 28 /*!< UART_T::ISR: HW TOUT_INT Position */ +#define UART_ISR_HW_TOUT_INT_Msk (1ul << UART_ISR_HW_TOUT_INT_Pos) /*!< UART_T::ISR: HW TOUT_INT Mask */ + +#define UART_ISR_HW_MODEM_INT_Pos 27 /*!< UART_T::ISR: HW MODEM_INT Position */ +#define UART_ISR_HW_MODEM_INT_Msk (1ul << UART_ISR_HW_MODEM_INT_Pos) /*!< UART_T::ISR: HW MODEM_INT Mask */ + +#define UART_ISR_HW_RLS_INT_Pos 26 /*!< UART_T::ISR: HW RLS_INT Position */ +#define UART_ISR_HW_RLS_INT_Msk (1ul << UART_ISR_HW_RLS_INT_Pos) /*!< UART_T::ISR: HW RLS_INT Position */ + +#define UART_ISR_HW_BUF_ERR_IF_Pos 21 /*!< UART_T::ISR: HW BUF_ERR_IF Position */ +#define UART_ISR_HW_BUF_ERR_IF_Msk (1ul << UART_ISR_HW_BUF_ERR_IF_Pos) /*!< UART_T::ISR: HW BUF_ERR_IF Mask */ + +#define UART_ISR_HW_TOUT_IF_Pos 20 /*!< UART_T::ISR: HW TOUT_IF Position */ +#define UART_ISR_HW_TOUT_IF_Msk (1ul << UART_ISR_HW_TOUT_IF_Pos) /*!< UART_T::ISR: HW TOUT_IF Mask */ + +#define UART_ISR_HW_MODEM_IF_Pos 19 /*!< UART_T::ISR: HW MODEM_IF Position */ +#define UART_ISR_HW_MODEM_IF_Msk (1ul << UART_ISR_HW_MODEM_IF_Pos) /*!< UART_T::ISR: HW MODEM_IF Mask */ + +#define UART_ISR_HW_RLS_IF_Pos 18 /*!< UART_T::ISR: HW RLS_IF Position */ +#define UART_ISR_HW_RLS_IF_Msk (1ul << UART_ISR_HW_RLS_IF_Pos) /*!< UART_T::ISR: HW RLS_IF Mark */ + +#define UART_ISR_LIN_INT_Pos 15 /*!< UART_T::ISR: LIN_INT Position */ +#define UART_ISR_LIN_INT_Msk (1ul << UART_ISR_LIN_INT_Pos) /*!< UART_T::ISR: LIN_INT Mask */ + +#define UART_ISR_BUF_ERR_INT_Pos 13 /*!< UART_T::ISR: BUF_ERR_INT Position */ +#define UART_ISR_BUF_ERR_INT_Msk (1ul << UART_ISR_BUF_ERR_INT_Pos) /*!< UART_T::ISR: BUF_ERR_INT Mask */ + +#define UART_ISR_TOUT_INT_Pos 12 /*!< UART_T::ISR: TOUT_INT Position */ +#define UART_ISR_TOUT_INT_Msk (1ul << UART_ISR_TOUT_INT_Pos) /*!< UART_T::ISR: TOUT_INT Mask */ + +#define UART_ISR_MODEM_INT_Pos 11 /*!< UART_T::ISR: MODEM_INT Position */ +#define UART_ISR_MODEM_INT_Msk (1ul << UART_ISR_MODEM_INT_Pos) /*!< UART_T::ISR: MODEM_INT Mask */ + +#define UART_ISR_RLS_INT_Pos 10 /*!< UART_T::ISR: RLS_INT Position */ +#define UART_ISR_RLS_INT_Msk (1ul << UART_ISR_RLS_INT_Pos) /*!< UART_T::ISR: RLS_INT Mask */ + +#define UART_ISR_THRE_INT_Pos 9 /*!< UART_T::ISR: THRE_INT Position */ +#define UART_ISR_THRE_INT_Msk (1ul << UART_ISR_THRE_INT_Pos) /*!< UART_T::ISR: THRE_INT Mask */ + +#define UART_ISR_RDA_INT_Pos 8 /*!< UART_T::ISR: RDA_INT Position */ +#define UART_ISR_RDA_INT_Msk (1ul << UART_ISR_RDA_INT_Pos) /*!< UART_T::ISR: RDA_INT Mask */ + +#define UART_ISR_LIN_IF_Pos 7 /*!< UART_T::ISR: LIN RX_IF Position */ +#define UART_ISR_LIN_IF_Msk (1ul << UART_ISR_LIN_IF_Pos) /*!< UART_T::ISR: LIN RX_IF Mask */ + +#define UART_ISR_BUF_ERR_IF_Pos 5 /*!< UART_T::ISR: BUF_ERR_IF Position */ +#define UART_ISR_BUF_ERR_IF_Msk (1ul << UART_ISR_BUF_ERR_IF_Pos) /*!< UART_T::ISR: BUF_ERR_IF Mask */ + +#define UART_ISR_TOUT_IF_Pos 4 /*!< UART_T::ISR: TOUT_IF Position */ +#define UART_ISR_TOUT_IF_Msk (1ul << UART_ISR_TOUT_IF_Pos) /*!< UART_T::ISR: TOUT_IF Mask */ + +#define UART_ISR_MODEM_IF_Pos 3 /*!< UART_T::ISR: MODEM_IF Position */ +#define UART_ISR_MODEM_IF_Msk (1ul << UART_ISR_MODEM_IF_Pos) /*!< UART_T::ISR: MODEM_IF Mask */ + +#define UART_ISR_RLS_IF_Pos 2 /*!< UART_T::ISR: RLS_IF Position */ +#define UART_ISR_RLS_IF_Msk (1ul << UART_ISR_RLS_IF_Pos) /*!< UART_T::ISR: RLS_IF Mask */ + +#define UART_ISR_THRE_IF_Pos 1 /*!< UART_T::ISR: THRE_IF Position */ +#define UART_ISR_THRE_IF_Msk (1ul << UART_ISR_THRE_IF_Pos) /*!< UART_T::ISR: THRE_IF Mask */ + +#define UART_ISR_RDA_IF_Pos 0 /*!< UART_T::ISR: RDA_IF Position */ +#define UART_ISR_RDA_IF_Msk (1ul << UART_ISR_RDA_IF_Pos) /*!< UART_T::ISR: RDA_IF Mask */ + + +/* UART TOR Bit Field Definitions */ +#define UART_TOR_DLY_Pos 8 /*!< UART_T::TOR: DLY Position */ +#define UART_TOR_DLY_Msk (0xFFul << UART_TOR_DLY_Pos) /*!< UART_T::TOR: DLY Mask */ + +#define UART_TOR_TOIC_Pos 0 /*!< UART_T::TOR: TOIC Position */ +#define UART_TOR_TOIC_Msk (0xFFul << UART_TOR_TOIC_Pos) + +/* UART BAUD Bit Field Definitions */ +#define UART_BAUD_DIV_X_EN_Pos 29 /*!< UART_T::BAUD: DIV_X_EN Position */ +#define UART_BAUD_DIV_X_EN_Msk (1ul << UART_BAUD_DIV_X_EN_Pos) /*!< UART_T::BAUD: DIV_X_EN Mask */ + +#define UART_BAUD_DIV_X_ONE_Pos 28 /*!< UART_T::BAUD: DIV_X_ONE Position */ +#define UART_BAUD_DIV_X_ONE_Msk (1ul << UART_BAUD_DIV_X_ONE_Pos) /*!< UART_T::BAUD: DIV_X_ONE Mask */ + +#define UART_BAUD_DIVIDER_X_Pos 24 /*!< UART_T::BAUD: DIVIDER_X Position */ +#define UART_BAUD_DIVIDER_X_Msk (0xFul << UART_BAUD_DIVIDER_X_Pos) /*!< UART_T::BAUD: DIVIDER_X Mask */ + +#define UART_BAUD_BRD_Pos 0 /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xFFFFul << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +/* UART IRCR Bit Field Definitions */ +#define UART_IRCR_INV_RX_Pos 6 /*!< UART_T::IRCR: INV_RX Position */ +#define UART_IRCR_INV_RX_Msk (1ul << UART_IRCR_INV_RX_Pos) /*!< UART_T::IRCR: INV_RX Mask */ + +#define UART_IRCR_INV_TX_Pos 5 /*!< UART_T::IRCR: INV_TX Position */ +#define UART_IRCR_INV_TX_Msk (1ul << UART_IRCR_INV_TX_Pos) /*!< UART_T::IRCR: INV_TX Mask */ + +#define UART_IRCR_TX_SELECT_Pos 1 /*!< UART_T::IRCR: TX_SELECT Position */ +#define UART_IRCR_TX_SELECT_Msk (1ul << UART_IRCR_TX_SELECT_Pos) /*!< UART_T::IRCR: TX_SELECT Mask */ + +/* UART ALT_CSR Bit Field Definitions */ +#define UART_ALT_CSR_ADDR_MATCH_Pos 24 /*!< UART_T::ALT_CSR: ADDR_MATCH Position */ +#define UART_ALT_CSR_ADDR_MATCH_Msk (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos) /*!< UART_T::ALT_CSR: ADDR_MATCH Mask */ + +#define UART_ALT_CSR_RS485_ADD_EN_Pos 15 /*!< UART_T::ALT_CSR: RS485_ADD_EN Position */ +#define UART_ALT_CSR_RS485_ADD_EN_Msk (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos) /*!< UART_T::ALT_CSR: RS485_ADD_EN Mask */ + +#define UART_ALT_CSR_RS485_AUD_Pos 10 /*!< UART_T::ALT_CSR: RS485_AUD Position */ +#define UART_ALT_CSR_RS485_AUD_Msk (1ul << UART_ALT_CSR_RS485_AUD_Pos) /*!< UART_T::ALT_CSR: RS485_AUD Mask */ + +#define UART_ALT_CSR_RS485_AAD_Pos 9 /*!< UART_T::ALT_CSR: RS485_AAD Position */ +#define UART_ALT_CSR_RS485_AAD_Msk (1ul << UART_ALT_CSR_RS485_AAD_Pos) /*!< UART_T::ALT_CSR: RS485_AAD Mask */ + +#define UART_ALT_CSR_RS485_NMM_Pos 8 /*!< UART_T::ALT_CSR: RS485_NMM Position */ +#define UART_ALT_CSR_RS485_NMM_Msk (1ul << UART_ALT_CSR_RS485_NMM_Pos) /*!< UART_T::ALT_CSR: RS485_NMM Mask */ + +#define UART_ALT_CSR_LIN_TX_EN_Pos 7 /*!< UART_T::ALT_CSR: LIN TX Break Mode Enable Position */ +#define UART_ALT_CSR_LIN_TX_EN_Msk (1ul << UART_ALT_CSR_LIN_TX_EN_Pos) /*!< UART_T::ALT_CSR: LIN TX Break Mode Enable Mask */ + +#define UART_ALT_CSR_LIN_RX_EN_Pos 6 /*!< UART_T::ALT_CSR: LIN RX Enable Position */ +#define UART_ALT_CSR_LIN_RX_EN_Msk (1ul << UART_ALT_CSR_LIN_RX_EN_Pos) /*!< UART_T::ALT_CSR: LIN RX Enable Mask */ + +#define UART_ALT_CSR_UA_LIN_BKFL_Pos 0 /*!< UART_T::ALT_CSR: UART LIN Break Field Length Position */ +#define UART_ALT_CSR_UA_LIN_BKFL_Msk (0xFul << UART_ALT_CSR_UA_LIN_BKFL_Pos) /*!< UART_T::ALT_CSR: UART LIN Break Field Length Mask */ + +/* UART FUN_SEL Bit Field Definitions */ +#define UART_FUN_SEL_FUN_SEL_Pos 0 /*!< UART_T::FUN_SEL: FUN_SEL Position */ +#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_T::FUN_SEL: FUN_SEL Mask */ + +/* UART LIN_CTL Bit Field Definitions */ +#define UART_LIN_CTL_LIN_PID_Pos 24 /*!< UART_T::LIN_CTL: LIN_PID Position */ +#define UART_LIN_CTL_LIN_PID_Msk (0xFFul << UART_LIN_CTL_LIN_PID_Pos) /*!< UART_T::LIN_CTL: LIN_PID Mask */ + +#define UART_LIN_CTL_LIN_HEAD_SEL_Pos 22 /*!< UART_T::LIN_CTL: LIN_HEAD_SEL Position */ +#define UART_LIN_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_LIN_CTL_LIN_HEAD_SEL_Pos) /*!< UART_T::LIN_CTL: LIN_HEAD_SEL Mask */ + +#define UART_LIN_CTL_LIN_BS_LEN_Pos 20 /*!< UART_T::LIN_CTL: LIN_BS_LEN Position */ +#define UART_LIN_CTL_LIN_BS_LEN_Msk (0x3ul << UART_LIN_CTL_LIN_BS_LEN_Pos) /*!< UART_T::LIN_CTL: LIN_BS_LEN Mask */ + +#define UART_LIN_CTL_LIN_BKFL_Pos 16 /*!< UART_T::LIN_CTL: LIN_BKFL Position */ +#define UART_LIN_CTL_LIN_BKFL_Msk (0xFul << UART_LIN_CTL_LIN_BKFL_Pos) /*!< UART_T::LIN_CTL: LIN_BKFL Mask */ + +#define UART_LIN_CTL_BIT_ERR_EN_Pos 12 /*!< UART_T::LIN_CTL: BIT_ERR_EN Position */ +#define UART_LIN_CTL_BIT_ERR_EN_Msk (1ul << UART_LIN_CTL_BIT_ERR_EN_Pos) /*!< UART_T::LIN_CTL: BIT_ERR_EN Mask */ + +#define UART_LIN_CTL_LIN_RX_DIS_Pos 11 /*!< UART_T::LIN_CTL: LIN_RX_DIS Position */ +#define UART_LIN_CTL_LIN_RX_DIS_Msk (1ul << UART_LIN_CTL_LIN_RX_DIS_Pos) /*!< UART_T::LIN_CTL: LIN_RX_DIS Mask */ + +#define UART_LIN_CTL_LIN_BKDET_EN_Pos 10 /*!< UART_T::LIN_CTL: LIN_BKDET_EN Position */ +#define UART_LIN_CTL_LIN_BKDET_EN_Msk (1ul << UART_LIN_CTL_LIN_BKDET_EN_Pos) /*!< UART_T::LIN_CTL: LIN_BKDET_EN Mask */ + +#define UART_LIN_CTL_LIN_IDPEN_Pos 9 /*!< UART_T::LIN_CTL: LIN_IDPEN Position */ +#define UART_LIN_CTL_LIN_IDPEN_Msk (1ul << UART_LIN_CTL_LIN_IDPEN_Pos) /*!< UART_T::LIN_CTL: LIN_IDPEN Mask */ + +#define UART_LIN_CTL_LIN_SHD_Pos 8 /*!< UART_T::LIN_CTL: LIN_SHD Position */ +#define UART_LIN_CTL_LIN_SHD_Msk (1ul << UART_LIN_CTL_LIN_SHD_Pos) /*!< UART_T::LIN_CTL: LIN_SHD Mask */ + +#define UART_LIN_CTL_LIN_MUTE_EN_Pos 4 /*!< UART_T::LIN_CTL: LIN_MUTE_EN Position */ +#define UART_LIN_CTL_LIN_MUTE_EN_Msk (1ul << UART_LIN_CTL_LIN_MUTE_EN_Pos) /*!< UART_T::LIN_CTL: LIN_MUTE_EN Mask */ + +#define UART_LIN_CTL_LINS_DUM_EN_Pos 3 /*!< UART_T::LIN_CTL: LINS_DUM_EN Position */ +#define UART_LIN_CTL_LINS_DUM_EN_Msk (1ul << UART_LIN_CTL_LINS_DUM_EN_Pos) /*!< UART_T::LIN_CTL: LINS_DUM_EN Mask */ + +#define UART_LIN_CTL_LINS_ARS_EN_Pos 2 /*!< UART_T::LIN_CTL: LINS_ARS_EN Position */ +#define UART_LIN_CTL_LINS_ARS_EN_Msk (1ul << UART_LIN_CTL_LINS_ARS_EN_Pos) /*!< UART_T::LIN_CTL: LINS_ARS_EN Mask */ + +#define UART_LIN_CTL_LINS_HDET_EN_Pos 1 /*!< UART_T::LIN_CTL: LINS_HDET_EN Position */ +#define UART_LIN_CTL_LINS_HDET_EN_Msk (1ul << UART_LIN_CTL_LINS_HDET_EN_Pos) /*!< UART_T::LIN_CTL: LINS_HDET_EN Mask */ + +#define UART_LIN_CTL_LINS_EN_Pos 0 /*!< UART_T::LIN_CTL: LINS_EN Position */ +#define UART_LIN_CTL_LINS_EN_Msk (1ul << UART_LIN_CTL_LINS_EN_Pos) /*!< UART_T::LIN_CTL: LINS_EN Mask */ + +/* UART LIN_SR Bit Field Definitions */ +#define UART_LIN_SR_BIT_ERR_F_Pos 9 /*!< UART_T::LIN_SR: BIT_ERR_F Position */ +#define UART_LIN_SR_BIT_ERR_F_Msk (1ul << UART_LIN_SR_BIT_ERR_F_Pos) /*!< UART_T::LIN_SR: BIT_ERR_F Mask */ + +#define UART_LIN_SR_LINS_BKDET_F_Pos 8 /*!< UART_T::LIN_SR: LINS_BKDET_F Position */ +#define UART_LIN_SR_LINS_BKDET_F_Msk (1ul << UART_LIN_SR_LINS_BKDET_F_Pos) /*!< UART_T::LIN_SR: LINS_BKDET_F Mask */ + +#define UART_LIN_SR_LINS_SYNC_F_Pos 3 /*!< UART_T::LIN_SR: LINS_SYNC_F Position */ +#define UART_LIN_SR_LINS_SYNC_F_Msk (1ul << UART_LIN_SR_LINS_SYNC_F_Pos) /*!< UART_T::LIN_SR: LINS_SYNC_F Mask */ + +#define UART_LIN_SR_LINS_IDPERR_F_Pos 2 /*!< UART_T::LIN_SR: LINS_IDPERR_F Position */ +#define UART_LIN_SR_LINS_IDPERR_F_Msk (1ul << UART_LIN_SR_LINS_IDPERR_F_Pos) /*!< UART_T::LIN_SR: LINS_IDPERR_F Mask */ + +#define UART_LIN_SR_LINS_HERR_F_Pos 1 /*!< UART_T::LIN_SR: LINS_HERR_F Position */ +#define UART_LIN_SR_LINS_HERR_F_Msk (1ul << UART_LIN_SR_LINS_HERR_F_Pos) /*!< UART_T::LIN_SR: LINS_HERR_F Mask */ + +#define UART_LIN_SR_LINS_HDET_F_Pos 0 /*!< UART_T::LIN_SR: LINS_HDET_F Position */ +#define UART_LIN_SR_LINS_HDET_F_Msk (1ul << UART_LIN_SR_LINS_HDET_F_Pos) /*!< UART_T::LIN_SR: LINS_HDET_F Mask */ +/*@}*/ /* end of group UART_CONST */ +/*@}*/ /* end of group UART */ + + + +/*---------------------- Universal Serial Bus Device Controller -------------------------*/ +/** + @addtogroup USBD Universal Serial Bus Device Controller (USBD) + Memory Mapped Structure for USBD Controller +@{ */ + + + +typedef struct +{ + + +/* + * @var USBD_EP_T::BUFSEG + * Offset: 0x20/0x30/0x40/0x50/0x60/0x70 Endpoint 0~5 Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting + * | | |address The effective starting address of the endpoint is + * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000} + * | | |Where the USB_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x24/0x34/0x44/0x54/0x64/0x74 Endpoint 0~5 Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length + * | | |which is received from the host (OUT token). + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or + * | | |received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and + * | | |indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the + * | | |value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after + * | | |IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x28/0x38/0x48/0x58/0x68/0x78 Endpoint 0~5 Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EP_NUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint. + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQ_SYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. + * | | |Hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x2C/0x3C/0x4C/0x5C/0x6C/0x7C Endpoint 0~5 Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit + * | | |or receive data. + * | | |If the user wants to turn off this transaction before the transaction start, users can set + * | | |this bit to 1 to turn it off and it will be cleared to 0 automatically. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + + __IO uint32_t BUFSEG; /* Offset: 0x20/0x30/0x40/0x50/0x60/0x70 Endpoint 0~5 Buffer Segmentation Register */ + __IO uint32_t MXPLD; /* Offset: 0x24/0x34/0x44/0x54/0x64/0x74 Endpoint 0~5 Maximal Payload Register */ + __IO uint32_t CFG; /* Offset: 0x28/0x38/0x48/0x58/0x68/0x78 Endpoint 0~5 Configuration Register */ + __IO uint32_t CFGP; /* Offset: 0x2C/0x3C/0x4C/0x5C/0x6C/0x7C Endpoint 0~5 Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + + +typedef struct +{ + + +/** + * @var USBD_T::INTEN + * Offset: 0x00 USB Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUS_IE |Bus Event Interrupt Enable + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USB_IE |USB Event Interrupt Enable + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |FLDET_IE |Floating Detection Interrupt Enable + * | | |0 = Floating detection Interrupt Disabled. + * | | |1 = Floating detection Interrupt Enabled. + * |[3] |WAKEUP_IE |USB Wake-Up Interrupt Enable + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |WAKEUP_EN |Wake-Up Function Enable + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAK_EN |Active NAK Function And Its Status In IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be + * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event + * | | | will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUS_STS |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, + * | | |cleared by write 1 to USB_INTSTS[0]. + * |[1] |USB_STS |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the + * | | |bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred. + * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]). + * |[2] |FLDET_STS |Floating Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to + * | | |USB_INTSTS[2]. + * |[3] |WAKEUP_STS|Wake-Up Interrupt Status + * | | |0 = No Wake-up event occurred. + * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred on endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred on endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred on endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred on endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred on endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred on endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred on endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred on endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event + * | | |was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OVERRUN |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 + * | | |Bytes. + * |[10:8] |EPSTS0 |Endpoint 0 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[13:11] |EPSTS1 |Endpoint 1 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[16:14] |EPSTS2 |Endpoint 2 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[19:17] |EPSTS3 |Endpoint 3 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[22:20] |EPSTS4 |Endpoint 4 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[25:23] |EPSTS5 |Endpoint 5 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[28:26] |EPSTS6 |Endpoint 6 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * |[31:29] |EPSTS7 |Endpoint 7 Bus Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |000 = In ACK. + * | | |001 = In NAK. + * | | |010 = Out Packet Data0 ACK. + * | | |110 = Out Packet Data1 ACK. + * | | |011 = Setup ACK. + * | | |111 = Isochronous transfer end. + * @var USBD_T::ATTR + * Offset: 0x10 USB Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TIMEOUT |Time-Out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * | | |Note: This bit is read only. + * |[4] |PHY_EN |PHY Transceiver Function Enable + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-Up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up. + * |[7] |USB_EN |USB Controller Enable + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPU_EN |Pull-Up Resistor On USB_D+ Enable + * | | |0 = Pull-up resistor in USB_D+ pin Disabled. + * | | |1 = Pull-up resistor in USB_D+ pin Enabled. + * |[9] |PWRDN |Power-Down PHY Transceiver, Low Active + * | | |0 = Power-down related circuit of PHY transceiver. + * | | |1 = Turn-on related circuit of PHY transceiver. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * @var USBD_T::FLDET + * Offset: 0x14 USB Floating Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLDET |Device Floating Detected + * | | |0 = Controller is not attached into the USB host. + * | | |1 =Controller is attached into the BUS. + * @var USBD_T::STBUFSEG + * Offset: 0x18 Setup Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM + * | | |starting address The effective starting address is + * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000} + * | | |Where the USB_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::DRVSE0 + * Offset: 0x90 USB Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = None. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + + __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */ + __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */ + __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */ + __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */ + __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */ + __I uint32_t FLDET; /* Offset: 0x14 USB Floating Detection Register */ + __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */ + __I uint32_t RESERVE0; + USBD_EP_T EP[6]; /* Offset: 0x20 Endpoint Related Configuration Registers */ + __I uint32_t RESERVE1[4]; + __IO uint32_t DRVSE0; /* Offset: 0x90 USB Drive SE0 Control Register */ + +} USBD_T; + + + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +/* USBD INTEN Bit Field Definitions */ +#define USBD_INTEN_INNAK_EN_Pos 15 /*!< USBD_T::INTEN: INNAK_EN Position */ +#define USBD_INTEN_INNAK_EN_Msk (1ul << USBD_INTEN_INNAK_EN_Pos) /*!< USBD_T::INTEN: INNAK_EN Mask */ + +#define USBD_INTEN_WAKEUP_EN_Pos 8 /*!< USBD_T::INTEN: RWAKEUP Position */ +#define USBD_INTEN_WAKEUP_EN_Msk (1ul << USBD_INTEN_WAKEUP_EN_Pos) /*!< USBD_T::INTEN: RWAKEUP Mask */ + +#define USBD_INTEN_WAKEUP_IE_Pos 3 /*!< USBD_T::INTEN: WAKEUP_IE Position */ +#define USBD_INTEN_WAKEUP_IE_Msk (1ul << USBD_INTEN_WAKEUP_IE_Pos) /*!< USBD_T::INTEN: WAKEUP_IE Mask */ + +#define USBD_INTEN_FLDET_IE_Pos 2 /*!< USBD_T::INTEN: FLDET_IE Position */ +#define USBD_INTEN_FLDET_IE_Msk (1ul << USBD_INTEN_FLDET_IE_Pos) /*!< USBD_T::INTEN: FLDET_IE Mask */ + +#define USBD_INTEN_USB_IE_Pos 1 /*!< USBD_T::INTEN: USB_IE Position */ +#define USBD_INTEN_USB_IE_Msk (1ul << USBD_INTEN_USB_IE_Pos) /*!< USBD_T::INTEN: USB_IE Mask */ + +#define USBD_INTEN_BUS_IE_Pos 0 /*!< USBD_T::INTEN: BUS_IE Position */ +#define USBD_INTEN_BUS_IE_Msk (1ul << USBD_INTEN_BUS_IE_Pos) /*!< USBD_T::INTEN: BUS_IE Mask */ + +/* USBD INTSTS Bit Field Definitions */ +#define USBD_INTSTS_SETUP_Pos 31 /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_INTSTS_EPEVT_Pos 16 /*!< USBD_T::INTSTS: EPEVT Position */ +#define USBD_INTSTS_EPEVT_Msk (0x3Ful << USBD_INTSTS_EPEVT_Pos) /*!< USBD_T::INTSTS: EPEVT Mask */ + +#define USBD_INTSTS_WAKEUP_STS_Pos 3 /*!< USBD_T::INTSTS: WAKEUP_STS Position */ +#define USBD_INTSTS_WAKEUP_STS_Msk (1ul << USBD_INTSTS_WAKEUP_STS_Pos) /*!< USBD_T::INTSTS: WAKEUP_STS Mask */ + +#define USBD_INTSTS_FLDET_STS_Pos 2 /*!< USBD_T::INTSTS: FLDET_STS Position */ +#define USBD_INTSTS_FLDET_STS_Msk (1ul << USBD_INTSTS_FLDET_STS_Pos) /*!< USBD_T::INTSTS: FLDET_STS Mask */ + +#define USBD_INTSTS_USB_STS_Pos 1 /*!< USBD_T::INTSTS: USB_STS Position */ +#define USBD_INTSTS_USB_STS_Msk (1ul << USBD_INTSTS_USB_STS_Pos) /*!< USBD_T::INTSTS: USB_STS Mask */ + +#define USBD_INTSTS_BUS_STS_Pos 0 /*!< USBD_T::INTSTS: BUS_STS Position */ +#define USBD_INTSTS_BUS_STS_Msk (1ul << USBD_INTSTS_BUS_STS_Pos) /*!< USBD_T::INTSTS: BUS_STS Mask */ + +/* USBD FADDR Bit Field Definitions */ +#define USBD_FADDR_FADDR_Pos 0 /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7Ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +/* USBD EPSTS Bit Field Definitions */ +#define USBD_EPSTS_EPSTS5_Pos 23 /*!< USBD_T::EPSTS: EPSTS5 Position */ +#define USBD_EPSTS_EPSTS5_Msk (7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */ + +#define USBD_EPSTS_EPSTS4_Pos 20 /*!< USBD_T::EPSTS: EPSTS4 Position */ +#define USBD_EPSTS_EPSTS4_Msk (7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */ + +#define USBD_EPSTS_EPSTS3_Pos 17 /*!< USBD_T::EPSTS: EPSTS3 Position */ +#define USBD_EPSTS_EPSTS3_Msk (7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */ + +#define USBD_EPSTS_EPSTS2_Pos 14 /*!< USBD_T::EPSTS: EPSTS2 Position */ +#define USBD_EPSTS_EPSTS2_Msk (7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */ + +#define USBD_EPSTS_EPSTS1_Pos 11 /*!< USBD_T::EPSTS: EPSTS1 Position */ +#define USBD_EPSTS_EPSTS1_Msk (7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */ + +#define USBD_EPSTS_EPSTS0_Pos 8 /*!< USBD_T::EPSTS: EPSTS0 Position */ +#define USBD_EPSTS_EPSTS0_Msk (7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */ + +#define USBD_EPSTS_OVERRUN_Pos 7 /*!< USBD_T::EPSTS: OVERRUN Position */ +#define USBD_EPSTS_OVERRUN_Msk (1ul << USBD_EPSTS_OVERRUN_Pos) /*!< USBD_T::EPSTS: OVERRUN Mask */ + +/* USBD ATTR Bit Field Definitions */ +#define USBD_ATTR_BYTEM_Pos 10 /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_PWRDN_Pos 9 /*!< USBD_T::ATTR: PWRDN Position */ +#define USBD_ATTR_PWRDN_Msk (1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */ + +#define USBD_ATTR_DPPU_EN_Pos 8 /*!< USBD_T::ATTR: DPPU_EN Position */ +#define USBD_ATTR_DPPU_EN_Msk (1ul << USBD_ATTR_DPPU_EN_Pos) /*!< USBD_T::ATTR: DPPU_EN Mask */ + +#define USBD_ATTR_USB_EN_Pos 7 /*!< USBD_T::ATTR: USB_EN Position */ +#define USBD_ATTR_USB_EN_Msk (1ul << USBD_ATTR_USB_EN_Pos) /*!< USBD_T::ATTR: USB_EN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos 5 /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_PHY_EN_Pos 4 /*!< USBD_T::ATTR: PHY_EN Position */ +#define USBD_ATTR_PHY_EN_Msk (1ul << USBD_ATTR_PHY_EN_Pos) /*!< USBD_T::ATTR: PHY_EN Mask */ + +#define USBD_ATTR_TIMEOUT_Pos 3 /*!< USBD_T::ATTR: TIMEOUT Position */ +#define USBD_ATTR_TIMEOUT_Msk (1ul << USBD_ATTR_TIMEOUT_Pos) /*!< USBD_T::ATTR: TIMEOUT Mask */ + +#define USBD_ATTR_RESUME_Pos 2 /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_SUSPEND_Pos 1 /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_USBRST_Pos 0 /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +/* USBD FLDET Bit Field Definitions */ +#define USBD_FLDET_FLDET_Pos 0 /*!< USBD_T::FLDET: FLDET Position */ +#define USBD_FLDET_FLDET_Msk (1ul << USBD_FLDET_FLDET_Pos) /*!< USBD_T::FLDET: FLDET Mask */ + +/* USBD STBUFSEG Bit Field Definitions */ +#define USBD_STBUFSEG_STBUFSEG_Pos 3 /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3Ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +/* USBD BUFSEG Bit Field Definitions */ +#define USBD_BUFSEG_BUFSEG_Pos 3 /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3Ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +/* USBD MXPLD Bit Field Definitions */ +#define USBD_MXPLD_MXPLD_Pos 0 /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1FFul << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +/* USBD CFG Bit Field Definitions */ +#define USBD_CFG_CSTALL_Pos 9 /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFG_DSQ_SYNC_Pos 7 /*!< USBD_EP_T::CFG: DSQ_SYNC Position */ +#define USBD_CFG_DSQ_SYNC_Msk (1ul << USBD_CFG_DSQ_SYNC_Pos) /*!< USBD_EP_T::CFG: DSQ_SYNC Mask */ + +#define USBD_CFG_STATE_Pos 5 /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_ISOCH_Pos 4 /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_EP_NUM_Pos 0 /*!< USBD_EP_T::CFG: EP_NUM Position */ +#define USBD_CFG_EP_NUM_Msk (0xFul << USBD_CFG_EP_NUM_Pos) /*!< USBD_EP_T::CFG: EP_NUM Mask */ + +/* USBD CFGP Bit Field Definitions */ +#define USBD_CFGP_SSTALL_Pos 1 /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +#define USBD_CFGP_CLRRDY_Pos 0 /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +/* USBD DRVSE0 Bit Field Definitions */ +#define USBD_DRVSE0_DRVSE0_Pos 0 /*!< USBD_T::DRVSE0: DRVSE0 Position */ +#define USBD_DRVSE0_DRVSE0_Msk (1ul << USBD_DRVSE0_DRVSE0_Pos) /*!< USBD_T::DRVSE0: DRVSE0 Mask */ + +/*@}*/ /* end of group USBD_CONST */ +/*@}*/ /* end of group USBD */ + + + + +/*---------------------- Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup WDT Watch Dog Timer Controller (WDT) + Memory Mapped Structure for WDT Controller +@{ */ + + +typedef struct +{ + + +/** + * @var WDT_T::WTCR + * Offset: 0x00 Watchdog Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WTR |Reset Watchdog Timer Up Counter (Write Protect) + * | | |0 = No effect. + * | | |1 = Reset the internal 18-bit WDT up counter value. + * | | |Note: This bit will be automatically cleared by hardware. + * |[1] |WTRE |Watchdog Timer Reset Enable (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function if the WDT up counter value has + * | | |not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * |[2] |WTRF |Watchdog Timer Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |WTIF |Watchdog Timer Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out + * | | |interval. + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WTWKE |Watchdog Timer Time-out Wake-Up Function Control + * | | |(Write Protect) + * | | |If this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out + * | | |interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock + * | | |source is selected to 10 kHz oscillator. + * |[5] |WTWKF |Watchdog Timer Time-out Wake-Up Flag + * | | |This bit indicates the interrupt wake-up flag status of WDT. + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |WTIE |Watchdog Timer Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * |[7] |WTE |Watchdog Timer Enable Control (Write Protect) + * | | |0 = WDT Disabled. (This action will reset the internal up counter value.) + * | | |1 = WDT Enabled. + * | | |Note: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0, this bit is forced as 1 and + * | | | user cannot change this bit to 0. + * |[10:8] |WTIS |Watchdog Timer Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |000 = 24 *TWDT. + * | | |001 = 26 * TWDT. + * | | |010 = 28 * TWDT. + * | | |011 = 210 * TWDT. + * | | |100 = 212 * TWDT. + * | | |101 = 214 * TWDT. + * | | |110 = 216 * TWDT. + * | | |111 = 218 * TWDT. + * |[31] |DBGACK_WDT|ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * @var WDT_T::WTCRALT + * Offset: 0x04 Watchdog Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WTRDSEL |Watchdog Timer Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT + * | | |counter to prevent WDT time-out reset happened. + * | | |User can select a suitable value of WDT Reset Delay Period for different WDT time-out + * | | |period. + * | | |These bits are protected bit. + * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to + * | | |disable register protection. + * | | |Reference the register REGWRPROT at address GCR_BA+0x100. + * | | |00 = Watchdog Timer Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = Watchdog Timer Reset Delay Period is 130 * WDT_CLK. + * | | |10 = Watchdog Timer Reset Delay Period is 18 * WDT_CLK. + * | | |11 = Watchdog Timer Reset Delay Period is 3 * WDT_CLK. + * | | |Note: This register will be reset to 0 if WDT time-out reset happened. + */ + + __IO uint32_t WTCR; /* Offset: 0x00 Watchdog Timer Control Register */ + __IO uint32_t WTCRALT; /* Offset: 0x04 Watchdog Timer Alternative Control Register */ + +} WDT_T; + + + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +/* WDT WTCR Bit Field Definitions */ +#define WDT_WTCR_DBGACK_WDT_Pos 31 /*!< WDT_T::WTCR: DBGACK_WDT Position */ +#define WDT_WTCR_DBGACK_WDT_Msk (1ul << WDT_WTCR_DBGACK_WDT_Pos) /*!< WDT_T::WTCR: DBGACK_WDT Mask */ + +#define WDT_WTCR_WTIS_Pos 8 /*!< WDT_T::WTCR: WTIS Position */ +#define WDT_WTCR_WTIS_Msk (0x7ul << WDT_WTCR_WTIS_Pos) /*!< WDT_T::WTCR: WTIS Mask */ + +#define WDT_WTCR_WTE_Pos 7 /*!< WDT_T::WTCR: WTE Position */ +#define WDT_WTCR_WTE_Msk (1ul << WDT_WTCR_WTE_Pos) /*!< WDT_T::WTCR: WTE Mask */ + +#define WDT_WTCR_WTIE_Pos 6 /*!< WDT_T::WTCR: WTIE Position */ +#define WDT_WTCR_WTIE_Msk (1ul << WDT_WTCR_WTIE_Pos) /*!< WDT_T::WTCR: WTIE Mask */ + +#define WDT_WTCR_WTWKF_Pos 5 /*!< WDT_T::WTCR: WTWKF Position */ +#define WDT_WTCR_WTWKF_Msk (1ul << WDT_WTCR_WTWKF_Pos) /*!< WDT_T::WTCR: WTWKF Mask */ + +#define WDT_WTCR_WTWKE_Pos 4 /*!< WDT_T::WTCR: WTWKE Position */ +#define WDT_WTCR_WTWKE_Msk (1ul << WDT_WTCR_WTWKE_Pos) /*!< WDT_T::WTCR: WTWKE Mask */ + +#define WDT_WTCR_WTIF_Pos 3 /*!< WDT_T::WTCR: WTIF Position */ +#define WDT_WTCR_WTIF_Msk (1ul << WDT_WTCR_WTIF_Pos) /*!< WDT_T::WTCR: WTIF Mask */ + +#define WDT_WTCR_WTRF_Pos 2 /*!< WDT_T::WTCR: WTRF Position */ +#define WDT_WTCR_WTRF_Msk (1ul << WDT_WTCR_WTRF_Pos) /*!< WDT_T::WTCR: WTRF Mask */ + +#define WDT_WTCR_WTRE_Pos 1 /*!< WDT_T::WTCR: WTRE Position */ +#define WDT_WTCR_WTRE_Msk (1ul << WDT_WTCR_WTRE_Pos) /*!< WDT_T::WTCR: WTRE Mask */ + +#define WDT_WTCR_WTR_Pos 0 /*!< WDT_T::WTCR: WTR Position */ +#define WDT_WTCR_WTR_Msk (1ul << WDT_WTCR_WTR_Pos) /*!< WDT_T::WTCR: WTR Mask */ + +/* WDT WTCRALT Bit Field Definitions */ +#define WDT_WTCRALT_WTRDSEL_Pos 0 /*!< WDT_T::WTCRALT: WTRDSEL Position */ +#define WDT_WTCRALT_WTRDSEL_Msk (0x3ul << WDT_WTCRALT_WTRDSEL_Pos) /*!< WDT_T::WTCRALT: WTRDSEL Mask */ +/*@}*/ /* end of group WDT_CONST */ +/*@}*/ /* end of group WDT */ + + +/*---------------------- Window Watchdog Timer -------------------------*/ +/** + @addtogroup WWDT Window Watchdog Timer (WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + + +typedef struct +{ + + +/** + * @var WWDT_T::WWDTRLD + * Offset: 0x00 Window Watchdog Timer Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WWDTRLD |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDTRLD to reload WWDT counter value when current WWDT + * | | | counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT + * | | | counter value is larger than WINCMP, WWDT reset signal will generate immediately. + * @var WWDT_T::WWDTCR + * Offset: 0x04 Window Watchdog Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |WWDTIE |WWDT Interrupt Enable Control + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and + * | | |inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PERIODSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT. + * |[21:16] |WINCMP |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter + * | | |value between 0 and WINCMP. + * | | |If user writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal + * | | |will generate immediately. + * |[31] |DBGACK_WWDT|ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgment effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::WWDTSR + * Offset: 0x08 Window Watchdog Timer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP + * | | |value. + * | | |0 = No effect. + * | | |1 = WWDT counter value matches WINCMP value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::WWDTCVR + * Offset: 0x0C Window Watchdog Timer Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |WWDTCVAL |WWDT Counter Value + * | | |WWDTCVAL will be updated continuously to monitor 6-bit down counter value. + */ + + __IO uint32_t WWDTRLD; /* Offset: 0x00 Window Watchdog Timer Reload Counter Register */ + __IO uint32_t WWDTCR; /* Offset: 0x04 Window Watchdog Timer Control Register */ + __IO uint32_t WWDTSR; /* Offset: 0x08 Window Watchdog Timer Status Register */ + __I uint32_t WWDTCVR; /* Offset: 0x0C Window Watchdog Timer Counter Value Register */ + +} WWDT_T; + + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +/* WWDT WWDTRLD Bit Field Definitions */ +#define WWDT_WWDTRLD_WWDTRLD_Pos 0 /*!< WWDT_T::WWDTRLD: WWDTRLD Position */ +#define WWDT_WWDTRLD_WWDTRLD_Msk (0xFFFFFFFFul << WWDT_WWDTRLD_WWDTRLD_Pos) /*!< WWDT_T::WWDTRLD: WWDTRLD Mask */ + +/* WWDT WWDTCR Bit Field Definitions */ +#define WWDT_WWDTCR_DBGACK_WWDT_Pos 31 /*!< WWDT_T::WWDTCR: DBGACK_WWDT Position */ +#define WWDT_WWDTCR_DBGACK_WWDT_Msk (1ul << WWDT_WWDTCR_DBGACK_WWDT_Pos) /*!< WWDT_T::WWDTCR: DBGACK_WWDT Mask */ + +#define WWDT_WWDTCR_WINCMP_Pos 16 /*!< WWDT_T::WWDTCR: WINCMP Position */ +#define WWDT_WWDTCR_WINCMP_Msk (0x3Ful << WWDT_WWDTCR_WINCMP_Pos) /*!< WWDT_T::WWDTCR: WINCMP Mask */ + +#define WWDT_WWDTCR_PERIODSEL_Pos 8 /*!< WWDT_T::WWDTCR: PERIODSEL Position */ +#define WWDT_WWDTCR_PERIODSEL_Msk (0xFul << WWDT_WWDTCR_PERIODSEL_Pos) /*!< WWDT_T::WWDTCR: PERIODSEL Mask */ + +#define WWDT_WWDTCR_WWDTIE_Pos 1 /*!< WWDT_T::WWDTCR: WWDTIE Position */ +#define WWDT_WWDTCR_WWDTIE_Msk (1ul << WWDT_WWDTCR_WWDTIE_Pos) /*!< WWDT_T::WWDTCR: WWDTIE Mask */ + +#define WWDT_WWDTCR_WWDTEN_Pos 0 /*!< WWDT_T::WWDTCR: WWDTEN Position */ +#define WWDT_WWDTCR_WWDTEN_Msk (1ul << WWDT_WWDTCR_WWDTEN_Pos) /*!< WWDT_T::WWDTCR: WWDTEN Mask */ + +/* WWDT WWDTSR Bit Field Definitions */ +#define WWDT_WWDTSR_WWDTRF_Pos 1 /*!< WWDT_T::WWDTSR: WWDTRF Position */ +#define WWDT_WWDTSR_WWDTRF_Msk (1ul << WWDT_WWDTSR_WWDTRF_Pos) /*!< WWDT_T::WWDTSR: WWDTRF Mask */ + +#define WWDT_WWDTSR_WWDTIF_Pos 0 /*!< WWDT_T::WWDTSR: WWDTIF Position */ +#define WWDT_WWDTSR_WWDTIF_Msk (1ul << WWDT_WWDTSR_WWDTIF_Pos) /*!< WWDT_T::WWDTSR: WWDTIF Mask */ + +/* WWDT WWDTCVR Bit Field Definitions */ +#define WWDT_WWDTCVR_WWDTCVAL_Pos 0 /*!< WWDT_T::WWDTCVR: WWDTRF Position */ +#define WWDT_WWDTCVR_WWDTCVAL_Msk (0x3Ful << WWDT_WWDTCVR_WWDTCVAL_Pos) /*!< WWDT_T::WWDTCVR: WWDTRF Mask */ +/*@}*/ /* end of group WWDT_CONST */ +/*@}*/ /* end of group WWDT */ +/*@}*/ /* end of group REGISTER */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Map + Memory Mapped Structure for Series Peripheral + @{ + */ +/* Peripheral and SRAM base address */ +#define FLASH_BASE (( uint32_t)0x00000000) +#define SRAM_BASE (( uint32_t)0x20000000) +#define AHB_BASE (( uint32_t)0x50000000) +#define APB1_BASE (( uint32_t)0x40000000) +#define APB2_BASE (( uint32_t)0x40100000) + +/* Peripheral memory map */ +#define GPIO_BASE (AHB_BASE + 0x4000) /*!< GPIO Base Address */ +#define PA_BASE (GPIO_BASE ) /*!< GPIO PORTA Base Address */ +#define PB_BASE (GPIO_BASE + 0x0040) /*!< GPIO PORTB Base Address */ +#define PC_BASE (GPIO_BASE + 0x0080) /*!< GPIO PORTC Base Address */ +#define PD_BASE (GPIO_BASE + 0x00C0) /*!< GPIO PORTD Base Address */ +#define PE_BASE (GPIO_BASE + 0x0100) /*!< GPIO PORTE Base Address */ +#define PF_BASE (GPIO_BASE + 0x0140) /*!< GPIO PORTF Base Address */ +#define GPIO_DBNCECON_BASE (GPIO_BASE + 0x0180) /*!< GPIO De-bounce Cycle Control Base Address */ +#define GPIO_PIN_DATA_BASE (GPIO_BASE + 0x0200) /*!< GPIO Pin Data Input/Output Control Base Address */ + + +#define UART0_BASE (APB1_BASE + 0x50000) +#define UART1_BASE (APB2_BASE + 0x50000) +#define UART2_BASE (APB2_BASE + 0x54000) + + +#define TIMER0_BASE (APB1_BASE + 0x10000) /*!< Timer0 Base Address */ +#define TIMER1_BASE (APB1_BASE + 0x10020) /*!< Timer1 Base Address */ +#define TIMER2_BASE (APB2_BASE + 0x10000) /*!< Timer2 Base Address */ +#define TIMER3_BASE (APB2_BASE + 0x10020) /*!< Timer3 Base Address */ + +#define WDT_BASE (APB1_BASE + 0x4000) /*!< Watchdog Timer Base Address */ + +#define WWDT_BASE (APB1_BASE + 0x4100) /*!< Window Watchdog Timer Base Address */ + +#define SPI0_BASE (APB1_BASE + 0x30000) /*!< SPI0 Base Address */ +#define SPI1_BASE (APB1_BASE + 0x34000) /*!< SPI1 Base Address */ +#define SPI2_BASE (APB2_BASE + 0x30000) /*!< SPI2 Base Address */ +#define SPI3_BASE (APB2_BASE + 0x34000) /*!< SPI3 Base Address */ + +#define I2C0_BASE (APB1_BASE + 0x20000) /*!< I2C0 Base Address */ +#define I2C1_BASE (APB2_BASE + 0x20000) /*!< I2C1 Base Address */ + +#define RTC_BASE (APB1_BASE + 0x08000) /*!< RTC Base Address */ + +#define ADC_BASE (APB1_BASE + 0xE0000) /*!< ADC Base Address */ + +#define ACMP_BASE (APB1_BASE + 0xD0000) /*!< ACMP Base Address */ + +#define CLK_BASE (AHB_BASE + 0x00200) /*!< System Clock Controller Base Address */ + +#define GCR_BASE (AHB_BASE + 0x00000) /*!< System Global Controller Base Address */ + +#define INT_BASE (AHB_BASE + 0x00300) /*!< Interrupt Source Controller Base Address */ + +#define FMC_BASE (AHB_BASE + 0x0C000) + +#define PS2_BASE (APB2_BASE + 0x00000) /*!< PS/2 Base Address */ + +#define USBD_BASE (APB1_BASE + 0x60000) /*!< USBD Base Address */ + +#define PDMA0_BASE (AHB_BASE + 0x08000) /*!< PDMA0 Base Address */ +#define PDMA1_BASE (AHB_BASE + 0x08100) /*!< PDMA1 Base Address */ +#define PDMA2_BASE (AHB_BASE + 0x08200) /*!< PDMA2 Base Address */ +#define PDMA3_BASE (AHB_BASE + 0x08300) /*!< PDMA3 Base Address */ +#define PDMA4_BASE (AHB_BASE + 0x08400) /*!< PDMA4 Base Address */ +#define PDMA5_BASE (AHB_BASE + 0x08500) /*!< PDMA5 Base Address */ +#define PDMA6_BASE (AHB_BASE + 0x08600) /*!< PDMA6 Base Address */ +#define PDMA7_BASE (AHB_BASE + 0x08700) /*!< PDMA7 Base Address */ +#define PDMA8_BASE (AHB_BASE + 0x08800) /*!< PDMA8 Base Address */ + +#define PDMA_GCR_BASE (AHB_BASE + 0x08F00) /*!< PDMA Global Base Address */ + +#define CRC_BASE (AHB_BASE + 0x08E00) /*!< CRC Base Address */ + +#define PWMA_BASE (APB1_BASE + 0x40000) /*!< PWMA Base Address */ +#define PWMB_BASE (APB2_BASE + 0x40000) /*!< PWMB Base Address */ + +#define SC0_BASE (APB2_BASE + 0x90000) /*!< SC0 Base Address */ +#define SC1_BASE (APB2_BASE + 0x94000) /*!< SC1 Base Address */ +#define SC2_BASE (APB2_BASE + 0x98000) /*!< SC2 Base Address */ + +#define I2S_BASE (APB2_BASE + 0xA0000) /*!< I2S Base Address */ + +#define EBI_BASE (AHB_BASE + 0x10000) /*!< EBI Base Address */ +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + +/******************************************************************************/ +/* Peripheral Definitions */ +/******************************************************************************/ + +/** @addtogroup PERIPHERAL Peripheral Definitions + The Definitions of Series Peripheral + @{ + */ +#define PA ((GPIO_T *) PA_BASE) /*!< GPIO PORTA Configuration Struct */ +#define PB ((GPIO_T *) PB_BASE) /*!< GPIO PORTB Configuration Struct */ +#define PC ((GPIO_T *) PC_BASE) /*!< GPIO PORTC Configuration Struct */ +#define PD ((GPIO_T *) PD_BASE) /*!< GPIO PORTD Configuration Struct */ +#define PE ((GPIO_T *) PE_BASE) /*!< GPIO PORTE Configuration Struct */ +#define PF ((GPIO_T *) PF_BASE) /*!< GPIO PORTF Configuration Struct */ +#define GPIO ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE) /*!< Interrupt De-bounce Cycle Control Configuration Struct */ + +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) + +#define TIMER0 ((TIMER_T *) TIMER0_BASE) /*!< Timer0 Configuration Struct */ +#define TIMER1 ((TIMER_T *) TIMER1_BASE) /*!< Timer1 Configuration Struct */ +#define TIMER2 ((TIMER_T *) TIMER2_BASE) /*!< Timer2 Configuration Struct */ +#define TIMER3 ((TIMER_T *) TIMER3_BASE) /*!< Timer3 Configuration Struct */ + +#define WDT ((WDT_T *) WDT_BASE) /*!< Watchdog Timer Configuration Struct */ + +#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watchdog Timer Configuration Struct */ + +#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Configuration Struct */ +#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Configuration Struct */ +#define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Configuration Struct */ +#define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Configuration Struct */ + +#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Configuration Struct */ +#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Configuration Struct */ + +#define I2S ((I2S_T *) I2S_BASE) /*!< I2S Configuration Struct */ + +#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Configuration Struct */ + +#define ADC ((ADC_T *) ADC_BASE) /*!< ADC Configuration Struct */ + +#define ACMP ((ACMP_T *) ACMP_BASE) /*!< ACMP Configuration Struct */ + +#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Configuration Struct */ + +#define SYS ((GCR_T *) GCR_BASE) /*!< System Global Controller Configuration Struct */ + +#define SYSINT ((GCR_INT_T *) INT_BASE) /*!< Interrupt Source Controller Configuration Struct */ + +#define FMC ((FMC_T *) FMC_BASE) + +#define PS2 ((PS2_T *) PS2_BASE) /*!< PS/2 Configuration Struct */ + +#define USBD ((USBD_T *) USBD_BASE) /*!< USBD Configuration Struct */ + +#define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Configuration Struct */ +#define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Configuration Struct */ +#define PDMA2 ((PDMA_T *) PDMA2_BASE) /*!< PDMA2 Configuration Struct */ +#define PDMA3 ((PDMA_T *) PDMA3_BASE) /*!< PDMA3 Configuration Struct */ +#define PDMA4 ((PDMA_T *) PDMA4_BASE) /*!< PDMA4 Configuration Struct */ +#define PDMA5 ((PDMA_T *) PDMA5_BASE) /*!< PDMA5 Configuration Struct */ +#define PDMA6 ((PDMA_T *) PDMA6_BASE) /*!< PDMA6 Configuration Struct */ +#define PDMA7 ((PDMA_T *) PDMA7_BASE) /*!< PDMA7 Configuration Struct */ +#define PDMA8 ((PDMA_T *) PDMA8_BASE) /*!< PDMA8 Configuration Struct */ + +#define PDMA_GCR ((PDMA_GCR_T *) PDMA_GCR_BASE) /*!< PDMA Global Configuration Struct */ + +#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Configuration Struct */ + +#define PWMA ((PWM_T *) PWMA_BASE) /*!< PWMA Configuration Struct */ +#define PWMB ((PWM_T *) PWMB_BASE) /*!< PWMB Configuration Struct */ + +#define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Configuration Struct */ +#define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Configuration Struct */ +#define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Configuration Struct */ + +#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Configuration Struct */ + +/*@}*/ /* end of group PERIPHERAL */ + +#define UNLOCKREG(x) do{*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88;}while(*((__IO uint32_t *)(GCR_BASE + 0x100))==0) +#define LOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00 + +#define REGCOPY(dest, src) *((uint32_t *)&(dest)) = *((uint32_t *)&(src)) +#define CLEAR(dest) *((uint32_t *)&(dest)) = 0 + +//============================================================================= +/** @addtogroup IO_ROUTINE I/O routines + The Declaration of I/O routines + @{ + */ + +typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((volatile unsigned int *)(port)) = value + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((volatile unsigned short *)(port)) = value + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((volatile unsigned char *)(port)) = value + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((volatile unsigned char *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((volatile unsigned int *)(port)) = value + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((volatile unsigned short *)(port)) = value + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((volatile unsigned char *)(port)) = value + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((volatile unsigned char *)(port))) + +/*@}*/ /* end of group IO_ROUTINE */ + + + + +/** @addtogroup legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + + +#define E_SUCCESS 0 +#ifndef NULL +#define NULL 0 +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ENABLE 1 +#define DISABLE 0 + +/* Define one bit mask */ +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FF) +#define BYTE1_Msk (0x0000FF00) +#define BYTE2_Msk (0x00FF0000) +#define BYTE3_Msk (0xFF000000) + +#define _GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define _GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define _GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define _GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group legacy_Constants */ + +/*@}*/ /* end of group Definitions */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "sys.h" +#include "adc.h" +#include "fmc.h" +#include "gpio.h" +#include "i2c.h" +#include "pwm.h" +#include "spi.h" +#include "crc.h" +#include "timer.h" +#include "wdt.h" +#include "wwdt.h" +#include "rtc.h" +#include "uart.h" +#include "i2s.h" +#include "usbd.h" +#include "pdma.h" +#include "sc.h" +#include "ps2.h" +#include "clk.h" +#include "acmp.h" +#endif + + + + diff --git a/BSP/Device/Nuvoton/NUC200Series/Include/system_NUC200Series.h b/BSP/Device/Nuvoton/NUC200Series/Include/system_NUC200Series.h new file mode 100644 index 0000000..ae97a09 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Include/system_NUC200Series.h @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file system_NUC200Series.h + * @version V3.0 + * $Revision: 6 $ + * $Date: 14/11/27 5:30p $ + * @brief NUC200 Series CMSIS System Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __SYSTEM_NUC2xx_H +#define __SYSTEM_NUC2xx_H + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Using UART0 or UART1 */ +#define DEBUG_PORT UART0 + +/*---------------------------------------------------------------------------- + Define SYSCLK + *----------------------------------------------------------------------------*/ +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */ +#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __HSI (50000000UL) /*!< PLL default output is 50MHz */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + +/** + * Initialize the system + * + * @param None + * @return None + * + * @brief Setup the microcontroller system + * Initialize GPIO directions and values + */ +extern void SystemInit(void); + + +/** + * Update SystemCoreClock variable + * + * @param None + * @return None + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from CPU registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/ARM/startup_NUC200Series.s b/BSP/Device/Nuvoton/NUC200Series/Source/ARM/startup_NUC200Series.s new file mode 100644 index 0000000..e6b7708 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/ARM/startup_NUC200Series.s @@ -0,0 +1,410 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* */ +;/* SPDX-License-Identifier: Apache-2.0 */ +;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */ +;/* */ +;/*---------------------------------------------------------------------------------------------------------*/ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +CLK_BA_base EQU 0x50000200 +PWRCON EQU 0x00 +AHBCLK EQU 0x04 +APBCLK EQU 0x08 +CLKSEL0 EQU 0x10 +CLKSEL1 EQU 0x14 +CLKDIV EQU 0x18 +PLLCON EQU 0x20 +TEST_S EQU 0x30 + +CLK_BA_APBCLK EQU 0x50000208 + +;// Define clock enable registers + +ADC_COMP_CLK EQU 0x50000208 +ADC_enable EQU 0x10000000 +COMP_enable EQU 0x40000000 + +PDMA_CLK EQU 0x50000204 +PDMA_enable EQU 0x00000003 + +;; bit 0 CPU_EN +;; bit 1 PDMA_EN + + + + +;// Define COMP registers base +COMP_base EQU 0x400D0000 +CMP1CR EQU 0x00 +CMP2CR EQU 0x04 +CMPSR EQU 0x08 + +;// Define ADC registers base +ADC_base EQU 0x400E0000 +ADDR0 EQU 0x00 +ADDR1 EQU 0x04 +ADDR2 EQU 0x08 +ADDR3 EQU 0x0c +ADDR4 EQU 0x10 +ADDR5 EQU 0x14 +ADDR6 EQU 0x18 +ADDR7 EQU 0x1c +ADCR EQU 0x20 +ADCHER EQU 0x24 +ADCMPR0 EQU 0x28 +ADCMPR1 EQU 0x2c +ADSR EQU 0x30 +ADCALR EQU 0x34 +ADCFCR EQU 0x38 +ADCALD EQU 0x3c + +;// Pattern Table +pattern_55555555 EQU 0x55555555 +pattern_aaaaaaaa EQU 0xaaaaaaaa +pattern_00005555 EQU 0x00005555 +pattern_0000aaaa EQU 0x0000aaaa +pattern_05550515 EQU 0x05550515 +pattern_0aaa0a2a EQU 0x0aaa0a2a + +;// Define PDMA regsiter base +PDMA_BA_ch0_base EQU 0x50008000 +PDMA_BA_ch1_base EQU 0x50008100 +PDMA_BA_ch2_base EQU 0x50008200 +PDMA_BA_ch3_base EQU 0x50008300 +PDMA_BA_ch4_base EQU 0x50008400 +PDMA_BA_ch5_base EQU 0x50008500 +PDMA_BA_ch6_base EQU 0x50008600 +PDMA_BA_ch7_base EQU 0x50008700 + +PDMA_BA_GCR EQU 0x50008F00 +PDMA_BA_GCR_base EQU 0x50008F00 + +PDMA_GCRCSR EQU 0X00 +PDMA_PDSSR2 EQU 0X04 +PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000 +PDMA_GCRISR EQU 0X0C + +PDMA_GLOBAL_enable EQU 0x0000FF00 + + +PDMA_CSR EQU 0X00 +PDMA_SAR EQU 0X04 +PDMA_DAR EQU 0X08 +PDMA_BCR EQU 0X0C +PDMA_CSAR EQU 0X14 +PDMA_CDAR EQU 0X18 +PDMA_CBSR EQU 0X1C +PDMA_IER EQU 0X20 +PDMA_ISR EQU 0X24 +PDMA_CTCSR EQU 0X28 +PDMA_SASOCR EQU 0X2C +PDMA_DASOCR EQU 0X30 +PDMA_SBUF0 EQU 0X80 +PDMA_SBUF1 EQU 0X84 +PDMA_SBUF2 EQU 0X88 +PDMA_SBUF3 EQU 0X8C + + +;// Define VIC control register +VIC_base EQU 0xFFFF0000 +VIC_SCR15 EQU 0x003c +VIC_SVR15 EQU 0x00bc +VIC_SCR16 EQU 0x0040 +VIC_SVR16 EQU 0x00c0 +VIC_SCR30 EQU 0x0078 +VIC_SVR30 EQU 0x00f8 +VIC_MECR EQU 0x0318 +VIC_MDCR EQU 0x031c +VIC_EOSCR EQU 0x0130 + +;//================================== +INT_BA_base EQU 0x50000300 + + +;// Parameter table +ADC_PDMA_CFG EQU 0x00002980 +ADC_PDMA_DST EQU 0xC0000000 +ADC_PDMA_SRC EQU 0xE0024200 +ADC_PDMA_TCBL EQU 0x00030008 + +;//================================== + + +GPIO_base EQU 0x50004000 +GPIOB_PMD EQU 0x0040 +GPIOB_OFFD EQU 0x0044 +GPIOB_DOUT EQU 0x0048 +GPIOB_DMASK EQU 0x004C +GPIOB_PIN EQU 0x0050 +GPIOB_DBEN EQU 0x0054 +GPIOB_IMD EQU 0x0058 +GPIOB_IEN EQU 0x005C +GPIOB_ISRC EQU 0x0060 + +;//================================== + + +GCR_base EQU 0x50000000 +GPB_MFP EQU 0x0034 + + + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + + + + + + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00000400 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000000 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; maximum of 32 External Interrupts are possible + DCD BOD_IRQHandler + DCD WDT_IRQHandler + DCD EINT0_IRQHandler + DCD EINT1_IRQHandler + DCD GPAB_IRQHandler + DCD GPCDEF_IRQHandler + DCD PWMA_IRQHandler + DCD PWMB_IRQHandler + DCD TMR0_IRQHandler + DCD TMR1_IRQHandler + DCD TMR2_IRQHandler + DCD TMR3_IRQHandler + DCD UART02_IRQHandler + DCD UART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD SPI2_IRQHandler + DCD SPI3_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD CAN0_IRQHandler + DCD CAN1_IRQHandler + DCD SC012_IRQHandler + DCD USBD_IRQHandler + DCD PS2_IRQHandler + DCD ACMP_IRQHandler + DCD PDMA_IRQHandler + DCD I2S_IRQHandler + DCD PWRWU_IRQHandler + DCD ADC_IRQHandler + DCD Default_Handler + DCD RTC_IRQHandler + + + + + + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + + ENTRY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =0x50000100 + ; Unlock Register + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + ; Init POR + LDR R2, =0x50000024 + LDR R1, =0x00005AA5 + STR R1, [R2] + + ; Lock register + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT GPAB_IRQHandler [WEAK] + EXPORT GPCDEF_IRQHandler [WEAK] + EXPORT PWMA_IRQHandler [WEAK] + EXPORT PWMB_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART02_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT SC012_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT PS2_IRQHandler [WEAK] + EXPORT ACMP_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + +BOD_IRQHandler +WDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +GPAB_IRQHandler +GPCDEF_IRQHandler +PWMA_IRQHandler +PWMB_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART02_IRQHandler +UART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC012_IRQHandler +USBD_IRQHandler +PS2_IRQHandler +ACMP_IRQHandler +PDMA_IRQHandler +I2S_IRQHandler +PWRWU_IRQHandler +ADC_IRQHandler +RTC_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/GCC/_syscalls.c b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/_syscalls.c new file mode 100644 index 0000000..fcb8dd0 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/_syscalls.c @@ -0,0 +1,1168 @@ +// +// This file is part of the uOS++ III distribution +// Parts of this file are from the newlib sources, issued under GPL. +// Copyright (c) 2014 Liviu Ionescu +// + +// ---------------------------------------------------------------------------- + +int errno; +void *__dso_handle __attribute__ ((weak)); + +// ---------------------------------------------------------------------------- + +#if !defined(OS_USE_SEMIHOSTING) + +#include <_ansi.h> +#include <_syslist.h> +#include +//#include +#include +#include +#include +#include +#include + +void +__initialize_args(int* p_argc, char*** p_argv); + +// This is the standard default implementation for the routine to +// process args. It returns a single empty arg. +// For semihosting applications, this is redefined to get the real +// args from the debugger. You can also use it if you decide to keep +// some args in a non-volatile memory. + +void __attribute__((weak)) +__initialize_args(int* p_argc, char*** p_argv) +{ + // By the time we reach this, the data and bss should have been initialised. + + // The strings pointed to by the argv array shall be modifiable by the + // program, and retain their last-stored values between program startup + // and program termination. (static, no const) + static char name[] = ""; + + // The string pointed to by argv[0] represents the program name; + // argv[0][0] shall be the null character if the program name is not + // available from the host environment. argv[argc] shall be a null pointer. + // (static, no const) + static char* argv[2] = + { name, NULL }; + + *p_argc = 1; + *p_argv = &argv[0]; + return; +} + +// These functions are defined here to avoid linker errors in freestanding +// applications. They might be called in some error cases from library +// code. +// +// If you detect other functions to be needed, just let us know +// and we'll add them. + +int +raise(int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int +kill(pid_t pid, int sig); + +int +kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +#endif // !defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +// If you need the empty definitions, remove the -ffreestanding option. + +#if __STDC_HOSTED__ == 1 + +char* __env[1] = +{ 0 }; +char** environ = __env; + +#if !defined(OS_USE_SEMIHOSTING) + +// Forward declarations + +int +_chown(const char* path, uid_t owner, gid_t group); + +int +_close(int fildes); + +int +_execve(char* name, char** argv, char** env); + +int +_fork(void); + +int +_fstat(int fildes, struct stat* st); + +int +_getpid(void); + +int +_gettimeofday(struct timeval* ptimeval, void* ptimezone); + +int +_isatty(int file); + +int +_kill(int pid, int sig); + +int +_link(char* existing, char* _new); + +int +_lseek(int file, int ptr, int dir); + +int +_open(char* file, int flags, int mode); + +int +_read(int file, char* ptr, int len); + +int +_readlink(const char* path, char* buf, size_t bufsize); + +int +_stat(const char* file, struct stat* st); + +int +_symlink(const char* path1, const char* path2); + +clock_t +_times(struct tms* buf); + +int +_unlink(char* name); + +int +_wait(int* status); + +int +_write(int file, char* ptr, int len); + +// Definitions + +int __attribute__((weak)) +_chown(const char* path __attribute__((unused)), + uid_t owner __attribute__((unused)), gid_t group __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_close(int fildes __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)), + char** env __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fork(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fstat(int fildes __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_getpid(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_gettimeofday(struct timeval* ptimeval __attribute__((unused)), + void* ptimezone __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_isatty(int file __attribute__((unused))) +{ + errno = ENOSYS; + return 0; +} + +int __attribute__((weak)) +_kill(int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_link(char* existing __attribute__((unused)), + char* _new __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)), + int dir __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_open(char* file __attribute__((unused)), int flags __attribute__((unused)), + int mode __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_read(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_readlink(const char* path __attribute__((unused)), + char* buf __attribute__((unused)), size_t bufsize __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_stat(const char* file __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_symlink(const char* path1 __attribute__((unused)), + const char* path2 __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +clock_t __attribute__((weak)) +_times(struct tms* buf __attribute__((unused))) +{ + errno = ENOSYS; + return ((clock_t) -1); +} + +int __attribute__((weak)) +_unlink(char* name __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_wait(int* status __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_write(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#else // defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "semihosting.h" + +int _kill (int pid, int sig); + +void __attribute__((noreturn)) _exit (int status); + +// Forward declarations. +int _system (const char*); +int _rename (const char*, const char*); +int _isatty (int); +clock_t _times (struct tms*); +int _gettimeofday (struct timeval *, void*); +int _unlink (const char*); +int _link (void); + +int _stat (const char*, struct stat*); + +int _fstat (int, struct stat*); +int _swistat (int fd, struct stat* st); +int _getpid (int); +int _close (int); +clock_t _clock (void); +int _swiclose (int); +int _open (const char*, int, ...); +int _swiopen (const char*, int); +int _write (int, char*, int); +int _swiwrite (int, char*, int); +int _lseek (int, int, int); +int _swilseek (int, int, int); +int _read (int, char*, int); +int _swiread (int, char*, int); + +void initialise_monitor_handles (void); + +void __initialize_args (int* p_argc, char*** p_argv); + +static int +checkerror (int); +static int +error (int); +static int +get_errno (void); + +// ---------------------------------------------------------------------------- + +#define ARGS_BUF_ARRAY_SIZE 80 +#define ARGV_BUF_ARRAY_SIZE 10 + +typedef struct +{ + char* pCommandLine; + int size; +} CommandLineBlock; + +void __initialize_args (int* p_argc, char*** p_argv) +{ + // Array of chars to receive the command line from the host + static char args_buf[ARGS_BUF_ARRAY_SIZE]; + + // Array of pointers to store the final argv pointers (pointing + // in the above array). + static char* argv_buf[ARGV_BUF_ARRAY_SIZE]; + + int argc = 0; + int isInArgument = 0; + + CommandLineBlock cmdBlock; + cmdBlock.pCommandLine = args_buf; + cmdBlock.size = sizeof(args_buf) - 1; + + int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock); + if (ret == 0) + { + + // In case the host send more than we can chew, limit the + // string to our buffer. + args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0'; + + // The command line is a null terminated string + char* p = cmdBlock.pCommandLine; + + int delim = '\0'; + int ch; + + while ((ch = *p) != '\0') + { + if (isInArgument == 0) + { + if (!isblank(ch)) + { + if (argc >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1)) + break; + + if (ch == '"' || ch == '\'') + { + // Remember the delimiter to search for the + // corresponding terminator + delim = ch; + ++p; // skip the delimiter + ch = *p; + } + // Remember the arg beginning address + argv_buf[argc++] = p; + isInArgument = 1; + } + } + else if (delim != '\0') + { + if ((ch == delim)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + } + else if (isblank(ch)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + ++p; + } + } + + if (argc == 0) + { + // No args found in string, return a single empty name. + args_buf[0] = '\0'; + argv_buf[0] = &args_buf[0]; + ++argc; + } + + // Must end the array with a null pointer. + argv_buf[argc] = NULL; + + *p_argc = argc; + *p_argv = &argv_buf[0]; + + // temporary here + initialise_monitor_handles (); + + return; +} + +// ---------------------------------------------------------------------------- + +void _exit (int status) +{ + /* There is only one SWI for both _exit and _kill. For _exit, call + the SWI with the second argument set to -1, an invalid value for + signum, so that the SWI handler can distinguish the two calls. + Note: The RDI implementation of _kill throws away both its + arguments. */ + report_exception (status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError); +} + +// ---------------------------------------------------------------------------- + +int __attribute__((weak)) +_kill (int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +struct fdent +{ + int handle; + int pos; +}; + +#define MAX_OPEN_FILES 20 + +/* User file descriptors (fd) are integer indexes into + the openfiles[] array. Error checking is done by using + findslot(). + + This openfiles array is manipulated directly by only + these 5 functions: + + findslot() - Translate entry. + newslot() - Find empty entry. + initilise_monitor_handles() - Initialize entries. + _swiopen() - Initialize entry. + _close() - Handle stdout == stderr case. + + Every other function must use findslot(). */ + +static struct fdent openfiles[MAX_OPEN_FILES]; + +static struct fdent* findslot (int); +static int newslot (void); + +/* Register name faking - works in collusion with the linker. */ +register char* stack_ptr asm ("sp"); + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void __sinit(struct _reent*); +#define CHECK_INIT(ptr) \ + do \ + { \ + if ((ptr) && !(ptr)->__sdidinit) \ + __sinit (ptr); \ + } \ + while (0) + +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Return a pointer to the structure associated with + the user file descriptor fd. */ +static struct fdent* +findslot (int fd) +{ + CHECK_INIT(_REENT); + + /* User file descriptor is out of range. */ + if ((unsigned int) fd >= MAX_OPEN_FILES) + { + return NULL; + } + + /* User file descriptor is open? */ + if (openfiles[fd].handle == -1) + { + return NULL; + } + + /* Valid. */ + return &openfiles[fd]; +} + +/* Return the next lowest numbered free file + structure, or -1 if we can't find one. */ +static int +newslot (void) +{ + int i; + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + if (openfiles[i].handle == -1) + { + break; + } + } + + if (i == MAX_OPEN_FILES) + { + return -1; + } + + return i; +} + +void +initialise_monitor_handles (void) +{ + int i; + + /* Open the standard file descriptors by opening the special + * teletype device, ":tt", read-only to obtain a descriptor for + * standard input and write-only to obtain a descriptor for standard + * output. Finally, open ":tt" in append mode to obtain a descriptor + * for standard error. Since this is a write mode, most kernels will + * probably return the same value as for standard output, but the + * kernel can differentiate the two using the mode flag and return a + * different descriptor for standard error. + */ + + int volatile block[3]; + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 0; /* mode "r" */ + monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 4; /* mode "w" */ + monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 8; /* mode "a" */ + monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + /* If we failed to open stderr, redirect to stdout. */ + if (monitor_stderr == -1) + { + monitor_stderr = monitor_stdout; + } + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + openfiles[i].handle = -1; + } + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; + openfiles[2].handle = monitor_stderr; + openfiles[2].pos = 0; +} + +static int +get_errno (void) +{ + return call_host (SEMIHOSTING_SYS_ERRNO, NULL); +} + +/* Set errno and return result. */ +static int +error (int result) +{ + errno = get_errno (); + return result; +} + +/* Check the return and set errno appropriately. */ +static int +checkerror (int result) +{ + if (result == -1) + { + return error (-1); + } + + return result; +} + +/* fh, is a valid internal file handle. + ptr, is a null terminated string. + len, is the length in bytes to read. + Returns the number of bytes *not* written. */ +int +_swiread (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_READ, block)); +} + +/* fd, is a valid user file handle. + Translates the return of _swiread into + bytes read. */ +int +_read (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiread (pfd->handle, ptr, len); + + if (res == -1) + { + return res; + } + + pfd->pos += len - res; + + /* res == len is not an error, + at least if we want feof() to work. */ + return len - res; +} + +/* fd, is a user file descriptor. */ +int _swilseek (int fd, int ptr, int dir) +{ + int res; + struct fdent *pfd; + + /* Valid file descriptor? */ + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Valid whence? */ + if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END)) + { + errno = EINVAL; + return -1; + } + + /* Convert SEEK_CUR to SEEK_SET */ + if (dir == SEEK_CUR) + { + ptr = pfd->pos + ptr; + /* The resulting file offset would be negative. */ + if (ptr < 0) + { + errno = EINVAL; + if ((pfd->pos > 0) && (ptr > 0)) + { + errno = EOVERFLOW; + } + return -1; + } + dir = SEEK_SET; + } + + int block[2]; + if (dir == SEEK_END) + { + block[0] = pfd->handle; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block)); + if (res == -1) + { + return -1; + } + ptr += res; + } + + /* This code only does absolute seeks. */ + block[0] = pfd->handle; + block[1] = ptr; + res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block)); + + /* At this point ptr is the current file position. */ + if (res >= 0) + { + pfd->pos = ptr; + return ptr; + } + else + { + return -1; + } +} + +int _lseek (int fd, int ptr, int dir) +{ + return _swilseek (fd, ptr, dir); +} + +/* fh, is a valid internal file handle. + Returns the number of bytes *not* written. */ +int _swiwrite (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block)); +} + +/* fd, is a user file descriptor. */ +int _write (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiwrite (pfd->handle, ptr, len); + + /* Clearly an error. */ + if (res < 0) + { + return -1; + } + + pfd->pos += len - res; + + /* We wrote 0 bytes? + Retrieve errno just in case. */ + if ((len - res) == 0) + { + return error (0); + } + + return (len - res); +} + +int _swiopen (const char* path, int flags) +{ + int aflags = 0, fh; + uint32_t block[3]; + + int fd = newslot (); + + if (fd == -1) + { + errno = EMFILE; + return -1; + } + + /* It is an error to open a file that already exists. */ + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + struct stat st; + int res; + res = _stat (path, &st); + if (res != -1) + { + errno = EEXIST; + return -1; + } + } + + /* The flags are Unix-style, so we need to convert them. */ +#ifdef O_BINARY + if (flags & O_BINARY) + { + aflags |= 1; + } +#endif + + /* In O_RDONLY we expect aflags == 0. */ + + if (flags & O_RDWR) + { + aflags |= 2; + } + + if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY)) + { + aflags |= 4; + } + + if (flags & O_APPEND) + { + /* Can't ask for w AND a; means just 'a'. */ + aflags &= ~4; + aflags |= 8; + } + + block[0] = (uint32_t) path; + block[2] = strlen (path); + block[1] = (uint32_t) aflags; + + fh = call_host (SEMIHOSTING_SYS_OPEN, block); + + /* Return a user file descriptor or an error. */ + if (fh >= 0) + { + openfiles[fd].handle = fh; + openfiles[fd].pos = 0; + return fd; + } + else + { + return error (fh); + } +} + +int _open (const char* path, int flags, ...) +{ + return _swiopen (path, flags); +} + +/* fh, is a valid internal file handle. */ +int _swiclose (int fh) +{ + return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh)); +} + +/* fd, is a user file descriptor. */ +int _close (int fd) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Handle stderr == stdout. */ + if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle)) + { + pfd->handle = -1; + return 0; + } + + /* Attempt to close the handle. */ + res = _swiclose (pfd->handle); + + /* Reclaim handle? */ + if (res == 0) + { + pfd->handle = -1; + } + + return res; +} + +int __attribute__((weak)) +_getpid (int n __attribute__ ((unused))) +{ + return 1; +} + +int +_swistat (int fd, struct stat* st) +{ + struct fdent *pfd; + int res; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Always assume a character device, + with 1024 byte blocks. */ + st->st_mode |= S_IFCHR; + st->st_blksize = 1024; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle)); + if (res == -1) + { + return -1; + } + + /* Return the file size. */ + st->st_size = res; + return 0; +} + +int __attribute__((weak)) +_fstat (int fd, struct stat* st) +{ + memset (st, 0, sizeof(*st)); + return _swistat (fd, st); +} + +int __attribute__((weak)) +_stat (const char*fname, struct stat *st) +{ + int fd, res; + memset (st, 0, sizeof(*st)); + /* The best we can do is try to open the file readonly. + If it exists, then we can guess a few things about it. */ + if ((fd = _open (fname, O_RDONLY)) == -1) + { + return -1; + } + st->st_mode |= S_IFREG | S_IREAD; + res = _swistat (fd, st); + /* Not interested in the error. */ + _close (fd); + return res; +} + +int __attribute__((weak)) +_link (void) +{ + errno = ENOSYS; + return -1; +} + +int _unlink (const char* path) +{ + int res; + uint32_t block[2]; + block[0] = (uint32_t) path; + block[1] = strlen (path); + res = call_host (SEMIHOSTING_SYS_REMOVE, block); + + if (res == -1) + { + return error (res); + } + return 0; +} + +int _gettimeofday (struct timeval* tp, void* tzvp) +{ + struct timezone* tzp = tzvp; + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL); + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t _clock (void) +{ + clock_t timeval; + + timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL); + return timeval; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_times (struct tms* tp) +{ + clock_t timeval = _clock (); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +} + +int _isatty (int fd) +{ + struct fdent *pfd; + int tty; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return 0; + } + + tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle); + + if (tty == 1) + { + return 1; + } + + errno = get_errno (); + return 0; +} + +int _system (const char* s) +{ + uint32_t block[2]; + int e; + + /* Hmmm. The ARM debug interface specification doesn't say whether + SYS_SYSTEM does the right thing with a null argument, or assign any + meaning to its return value. Try to do something reasonable.... */ + if (!s) + { + return 1; /* maybe there is a shell available? we can hope. :-P */ + } + block[0] = (uint32_t) s; + block[1] = strlen (s); + e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block)); + if ((e >= 0) && (e < 256)) + { + /* We have to convert e, an exit status to the encoded status of + the command. To avoid hard coding the exit status, we simply + loop until we find the right position. */ + int exit_code; + + for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1) + { + continue; + } + } + return e; +} + +int _rename (const char* oldpath, const char* newpath) +{ + uint32_t block[4]; + block[0] = (uint32_t) oldpath; + block[1] = strlen (oldpath); + block[2] = (uint32_t) newpath; + block[3] = strlen (newpath); + return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0; +} + +// ---------------------------------------------------------------------------- +// Required by Google Tests + +int mkdir (const char *path __attribute__((unused)), mode_t mode __attribute__((unused))) +{ +#if 0 + // always return true + return 0; +#else + errno = ENOSYS; + return -1; +#endif +} + +char *getcwd (char *buf, size_t size) +{ + // no cwd available via semihosting, so we use the temporary folder + strncpy (buf, "/tmp", size); + return buf; +} + +#endif // defined OS_USE_SEMIHOSTING + +#endif // __STDC_HOSTED__ == 1 diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/GCC/gcc_arm.ld b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/gcc_arm.ld new file mode 100644 index 0000000..f25b967 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/gcc_arm.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 128k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/GCC/semihosting.h b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/semihosting.h new file mode 100644 index 0000000..798746a --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/semihosting.h @@ -0,0 +1,116 @@ + +#ifndef ARM_SEMIHOSTING_H_ +#define ARM_SEMIHOSTING_H_ + +// ---------------------------------------------------------------------------- + +// Semihosting operations. +enum OperationNumber +{ + // Regular operations + SEMIHOSTING_EnterSVC = 0x17, + SEMIHOSTING_ReportException = 0x18, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + + // Codes returned by SEMIHOSTING_ReportException + ADP_Stopped_ApplicationExit = ((2 << 16) + 38), + ADP_Stopped_RunTimeError = ((2 << 16) + 35), + +}; + +// ---------------------------------------------------------------------------- + +// SWI numbers and reason codes for RDI (Angel) monitors. +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +// For thumb only architectures use the BKPT instruction instead of SWI. +#if defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) \ + || defined(__ARM_ARCH_6M__) +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +// Testing the local semihosting handler cannot use another BKPT, since this +// configuration cannot trigger HaedFault exceptions while the debugger is +// connected, so we use an illegal op code, that will trigger an +// UsageFault exception. +#define AngelSWITestFault "setend be" +#define AngelSWITestFaultOpCode (0xB658) +#endif + +static inline int +__attribute__ ((always_inline)) +call_host (int reason, void* arg) +{ + int value; + asm volatile ( + + " mov r0, %[rsn] \n" + " mov r1, %[arg] \n" +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + " " AngelSWITestFault " \n" +#else + " " AngelSWIInsn " %[swi] \n" +#endif + " mov %[val], r0" + + : [val] "=r" (value) /* Outputs */ + : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + // Clobbers r0 and r1, and lr if in supervisor mode + ); + + // Accordingly to page 13-77 of ARM DUI 0040D other registers + // can also be clobbered. Some memory positions may also be + // changed by a system call, so they should not be kept in + // registers. Note: we are assuming the manual is right and + // Angel is respecting the APCS. + return value; +} + +// ---------------------------------------------------------------------------- + +// Function used in _exit() to return the status code as Angel exception. +static inline void +__attribute__ ((always_inline,noreturn)) +report_exception (int reason) +{ + call_host (SEMIHOSTING_ReportException, (void*) reason); + + for (;;) + ; +} + +// ---------------------------------------------------------------------------- + +#endif // ARM_SEMIHOSTING_H_ diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/GCC/startup_NUC200Series.S b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/startup_NUC200Series.S new file mode 100644 index 0000000..3314787 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/GCC/startup_NUC200Series.S @@ -0,0 +1,316 @@ +/****************************************************************************//** + * @file startup_NUC200Series.S + * @version V1.00 + * @brief CMSIS Device Startup File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .global __StackTop + .global __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000100 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved*/ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long BOD_IRQHandler + .long WDT_IRQHandler + .long EINT0_IRQHandler + .long EINT1_IRQHandler + .long GPAB_IRQHandler + .long GPCDEF_IRQHandler + .long PWMA_IRQHandler + .long PWMB_IRQHandler + .long TMR0_IRQHandler + .long TMR1_IRQHandler + .long TMR2_IRQHandler + .long TMR3_IRQHandler + .long UART02_IRQHandler + .long UART1_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long SPI2_IRQHandler + .long SPI3_IRQHandler + .long I2C0_IRQHandler + .long I2C1_IRQHandler + .long CAN0_IRQHandler + .long CAN1_IRQHandler + .long SC012_IRQHandler + .long USBD_IRQHandler + .long PS2_IRQHandler + .long ACMP_IRQHandler + .long PDMA_IRQHandler + .long I2S_IRQHandler + .long PWRWU_IRQHandler + .long ADC_IRQHandler + .long Default_Handler + .long RTC_IRQHandler + + + .size __Vectors, . - __Vectors + + + .text + .thumb + .thumb_func + .align 2 + .global Reset_Handler + .type Reset_Handler, % function + + +Reset_Handler: + /* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, = __copy_table_start__ + ldr r5, = __copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else + /* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, = __etext + ldr r2, = __data_start__ + ldr r3, = __data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, = __zero_table_start__ + ldr r4, = __zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + +#elif defined (__STARTUP_CLEAR_BSS) + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, = __bss_start__ + ldr r2, = __bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, % function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + /* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + + def_irq_handler BOD_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler GPAB_IRQHandler + def_irq_handler GPCDEF_IRQHandler + def_irq_handler PWMA_IRQHandler + def_irq_handler PWMB_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART02_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC012_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler PS2_IRQHandler + def_irq_handler ACMP_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler I2S_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler ADC_IRQHandler + def_irq_handler RTC_IRQHandler + + + .end diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/IAR/startup_NUC200Series.s b/BSP/Device/Nuvoton/NUC200Series/Source/IAR/startup_NUC200Series.s new file mode 100644 index 0000000..9f43361 --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/IAR/startup_NUC200Series.s @@ -0,0 +1,184 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* */ +;/* SPDX-License-Identifier: Apache-2.0 */ +;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */ +;/* */ +;/*---------------------------------------------------------------------------------------------------------*/ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment + + SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment + + EXTERN SystemInit + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD BOD_IRQHandler ; Brownout low voltage detected interrupt + DCD WDT_IRQHandler ; Watch Dog Timer interrupt + DCD EINT0_IRQHandler ; External signal interrupt from PB.14 pin + DCD EINT1_IRQHandler ; External signal interrupt from PB.15 pin + DCD GPAB_IRQHandler ; GPIO interrupt from PA[15:0]/PB[13:0] + DCD GPCDEF_IRQHandler ; GPIO interrupt from PC[15:0]/PD[15:0]/PE[15:0]//PF[3:0] + DCD PWMA_IRQHandler ; PWM0 or PWM2 interrupt + DCD PWMB_IRQHandler ; PWM1 or PWM3 interrupt + DCD TMR0_IRQHandler ; Timer 0 interrupt + DCD TMR1_IRQHandler ; Timer 1 interrupt + DCD TMR2_IRQHandler ; Timer 2 interrupt + DCD TMR3_IRQHandler ; Timer 3 interrupt + DCD UART02_IRQHandler ; UART0 interrupt + DCD UART1_IRQHandler ; UART1 interrupt + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD SPI1_IRQHandler ; SPI1 interrupt + DCD SPI2_IRQHandler ; SPI2 interrupt + DCD SPI3_IRQHandler ; SPI3 interrupt + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C1 interrupt + DCD CAN0_IRQHandler ; CAN0 interrupt + DCD CAN1_IRQHandler ; CAN1 interrupt + DCD SC012_IRQHandler ; SC0/1/2 interrupt + DCD USBD_IRQHandler ; USB FS Device interrupt + DCD PS2_IRQHandler ; PS2 interrupt + DCD ACMP_IRQHandler ; Analog Comparator-0 or Comaprator-1 interrupt + DCD PDMA_IRQHandler ; PDMA interrupt + DCD I2S_IRQHandler ; I2S interrupt + DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power- + DCD ADC_IRQHandler ; ADC interrupt + DCD Default_Handler ; Reserved + DCD RTC_IRQHandler ; Real time clock interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) ; 4 bytes alignment +Reset_Handler + LDR R0, =0x50000100 + ; Unlock Register + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + ; Init POR + LDR R2, =0x50000024 + LDR R1, =0x00005AA5 + STR R1, [R2] + + ; Lock register + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK HardFault_Handler + PUBWEAK NMI_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK BOD_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK GPAB_IRQHandler + PUBWEAK GPCDEF_IRQHandler + PUBWEAK PWMA_IRQHandler + PUBWEAK PWMB_IRQHandler + PUBWEAK TMR0_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK UART02_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK SPI3_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + PUBWEAK SC012_IRQHandler + PUBWEAK USBD_IRQHandler + PUBWEAK PS2_IRQHandler + PUBWEAK ACMP_IRQHandler + PUBWEAK PDMA_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK PWRWU_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HardFault_Handler +NMI_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +BOD_IRQHandler +WDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +GPAB_IRQHandler +GPCDEF_IRQHandler +PWMA_IRQHandler +PWMB_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART02_IRQHandler +UART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC012_IRQHandler +USBD_IRQHandler +PS2_IRQHandler +ACMP_IRQHandler +PDMA_IRQHandler +I2S_IRQHandler +PWRWU_IRQHandler +ADC_IRQHandler +RTC_IRQHandler +Default_Handler + B Default_Handler + + + END + diff --git a/BSP/Device/Nuvoton/NUC200Series/Source/system_NUC200Series.c b/BSP/Device/Nuvoton/NUC200Series/Source/system_NUC200Series.c new file mode 100644 index 0000000..a2ec8fb --- /dev/null +++ b/BSP/Device/Nuvoton/NUC200Series/Source/system_NUC200Series.c @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file system_NUC200Series.c + * @version V3.0 + * $Revision: 5 $ + * $Date: 14/11/21 5:08p $ + * @brief NUC200 Series CMSIS System File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#include +#include "NUC200Series.h" + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */ +uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, NULL, NULL, NULL, __HIRC}; + + +/*---------------------------------------------------------------------------- + Clock functions + This function is used to update the variable SystemCoreClock + and must be called whenever the core clock is changed. + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk; + + if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL) + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + else + { + /* Use PLL clock */ + u32Freq = PllClock; + } + + u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + CyclesPerUs = (SystemCoreClock + 500000) / 1000000; +} + +/*---------------------------------------------------------------------------------------------------------*/ +/* Function: SystemInit */ +/* */ +/* Parameters: */ +/* None */ +/* */ +/* Returns: */ +/* None */ +/* */ +/* Description: */ +/* The necessary initialization of system. */ +/* */ +/*---------------------------------------------------------------------------------------------------------*/ +void SystemInit(void) +{ +} diff --git a/BSP/README.md b/BSP/README.md new file mode 100644 index 0000000..86aac40 --- /dev/null +++ b/BSP/README.md @@ -0,0 +1,58 @@ +# NUC200 CMSIS BSP + +This BSP folder + +## .\Document\ + + +- Release Note
+ Show all the revision history about specific BSP. + +- Driver Reference Guide
+ Describe the definition, input and output of each API. + +## .\Library\ + + +- CMSIS
+ CMSIS definitions by ARM® Corp. + +- Device
+ CMSIS compliant device header file. + +- StdDriver
+ All peripheral driver header and source files. + +## .\Sample Code\ + + +- CardReader
+ CCID Smart Card reader Sample Code. + +- Hard\_Fault\_Sample
+ Show hard fault information when hard fault happened. + +- ISP
+ Sample codes for In-System-Programming. + +- Template
+ Software Development Template. + +- Semihost
+ Show how to debug with semi-host message print. + +- RegBased
+ The sample codes which access control registers directly. + +- StdDriver
+ NUC200 Series Driver Samples. + + +# Licesne + +**SPDX-License-Identifier: Apache-2.0** + +Copyright in some of the content available in this BSP belongs to third parties. +Third parties license is specified in a file header or license file. +NUC200 BSP files are provided under the Apache-2.0 license. + diff --git a/BSP/SmartcardLib/Include/sclib.h b/BSP/SmartcardLib/Include/sclib.h new file mode 100644 index 0000000..df686b6 --- /dev/null +++ b/BSP/SmartcardLib/Include/sclib.h @@ -0,0 +1,307 @@ +/**************************************************************************//** + * @file sclib.h + * @version V1.00 + * $Revision: 6 $ + * $Date: 15/05/18 10:11a $ + * @brief Smartcard library header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCLIB_H__ +#define __SCLIB_H__ + +#include "NUC200Series.h" + +/** @addtogroup Library Library + @{ +*/ + +/** @addtogroup SCLIB Smartcard Library + @{ +*/ + +/** @addtogroup SCLIB_EXPORTED_CONSTANTS Smartcard Library Exported Constants + @{ +*/ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define SCLIB_MAX_ATR_LEN 32 ///< Max ATR length. ISO-7816 8.2.1 +#define SCLIB_MIN_ATR_LEN 2 ///< Min ATR length, TS and T0 + +// Protocol +#define SCLIB_PROTOCOL_UNDEFINED 0x00000000 ///< There is no active protocol. +#define SCLIB_PROTOCOL_T0 0x00000001 ///< T=0 is the active protocol. +#define SCLIB_PROTOCOL_T1 0x00000002 ///< T=1 is the active protocol. + +#define SCLIB_SUCCESS 0x00000000 ///< Command successful without error +// error code generate by interrupt handler +#define SCLIB_ERR_CARD_REMOVED 0x00000001 ///< Smartcard removed +#define SCLIB_ERR_OVER_RUN 0x00000002 ///< Rx FIFO over run +#define SCLIB_ERR_PARITY_ERROR 0x00000003 ///< Tx/Rx parity error +#define SCLIB_ERR_NO_STOP 0x00000004 ///< Stop bit not found +#define SCLIB_ERR_SILENT_BYTE 0x00000005 ///< I/O pin stay at low for longer than 1 character time +#define SCLIB_ERR_CMD 0x00000006 +#define SCLIB_ERR_UNSUPPORTEDCARD 0x00000007 +#define SCLIB_ERR_READ 0x00000008 +#define SCLIB_ERR_WRITE 0x00000009 +#define SCLIB_ERR_TIME0OUT 0x0000000A ///< Smartcard timer 0 timeout +#define SCLIB_ERR_TIME1OUT 0x0000000B ///< Smartcard timer 1 timeout +#define SCLIB_ERR_TIME2OUT 0x0000000C ///< Smartcard timer 2 timeout +#define SCLIB_ERR_AUTOCONVENTION 0x0000000D ///< Smartcard is neither direct nor inverse convention +#define SCLIB_ERR_CLOCK 0x0000000E ///< Smartcard clock frequency is not between 1MHz and 5 MHz +#define SCLIB_ERR_BGTIMEOUT 0x0000000E +// error code generate while parsing ATR and process PPS +#define SCLIB_ERR_ATR_UNRECOGNIZED 0x00001001 ///< Unrecognized ATR +#define SCLIB_ERR_ATR_INVALID_PARAM 0x00001002 ///< ATR parsing interface bytes error +#define SCLIB_ERR_ATR_INVALID_TCK 0x00001003 ///< TCK check byte error +#define SCLIB_ERR_PPS 0x00001004 +// error code for T=1 protocol +#define SCLIB_ERR_T1_PARITY 0x00002001 ///< T=1 Parity Error Notice +#define SCLIB_ERR_T1_ICC 0x00002002 ///< ICC communication error +#define SCLIB_ERR_T1_PROTOCOL 0x00002003 ///< T=1 Protocol Error +#define SCLIB_ERR_T1_ABORT_RECEIVED 0x00002004 ///< Received ABORT request +#define SCLIB_ERR_T1_RESYNCH_RECEIVED 0x00002005 ///< Received RESYNCH request +#define SCLIB_ERR_T1_VPP_ERROR_RECEIVED 0x00002006 ///< Received VPP error +#define SCLIB_ERR_T1_WTXRES_RECEIVED 0x00002007 ///< Received BWT extension request +#define SCLIB_ERR_T1_IFSRES_RECEIVED 0x00002008 ///< Received max IFS offer +#define SCLIB_ERR_T1_ABORTRES_RECEIVED 0x00002009 ///< Received ABORT response +#define SCLIB_ERR_T1_CHECKSUM 0x0000200A ///< T=1 block check sum error + +// error code for T=0 protocol +#define SCLIB_ERR_T0_PROTOCOL 0x00003003 ///< T=0 Protocol Error + +// error code indicates application control flow error +#define SCLIB_ERR_DEACTIVE 0x0000F001 ///< Smartcard is deactivation +#define SCLIB_ERR_CARDBUSY 0x0000F002 ///< Smartcard is busy, previous transmission is not complete yet + +/*@}*/ /* end of group NUC400_SCLIB_EXPORTED_CONSTANTS */ + +/** @addtogroup NUC400_SCLIB_EXPORTED_STRUCTS Smartcard Library Exported Structs + @{ +*/ + +/** + * @brief A structure holds smartcard information + */ +typedef struct { + uint32_t T; ///< Protocol, ether \ref SCLIB_PROTOCOL_T0 or \ref SCLIB_PROTOCOL_T1. + uint32_t ATR_Len; ///< ATR length, between SCLIB_MAX_ATR_LEN and SCLIB_MIN_ATR_LEN + uint8_t ATR_Buf[SCLIB_MAX_ATR_LEN]; ///< Buffer holds ATR answered by smartcard +} SCLIB_CARD_INFO_T; + +/** + * @brief A structure holds smartcard attribute, including convention, guard time, waiting time, IFCS... etc. + */ +typedef struct +{ + uint8_t Fi; ///< Findex; + uint8_t Di; ///< Dindex; + uint8_t conv; ///< Convention, direct or inverse. 0 direct, 1 inverse + uint8_t chksum; ///< Checksum type + uint8_t GT; ///< Guard Time + uint8_t WI; ///< Wait integer for T0 + uint8_t BWI; ///< Block waiting integer for T1; + uint8_t CWI; ///< Character waiting integer for T1; + uint8_t clkStop; ///< Card clock stop status. 00 Not allowed, 01 low, 02, high, 03 ether high or low + uint8_t IFSC; ///< size of negotiated IFCS + uint8_t NAD; ///< NAD value +} SCLIB_CARD_ATTRIB_T; + + +/*@}*/ /* end of group NUC400_SCLIB_EXPORTED_STRUCTS */ + +/** @addtogroup NUC400_SCLIB_EXPORTED_FUNCTIONS Smartcard Library Exported Functions + @{ +*/ + +/** + * @brief Activate a smartcard + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[in] u32EMVCheck Enable EMV error check or not. Valid setting are \ref TRUE and \ref FALSE. + * By enable EMV error checking, this library will perform ATR checking according to + * EMV book 1 specification. Otherwise, the error checking follows ISO 7816-3 + * @return Smartcard successfully activated or not + * @retval SCLIB_SUCCESS Smartcard activated successfully + * @retval Others Smartcard activation failed + * @note It is required to set smartcard interface clock between 1 MHz and 5 MHz before + * calling this API, otherwise this API return with \ref SCLIB_ERR_CLOCK error code. + * @note EMV book 1 is stricter than ISO-7816 on ATR checking. Enable EMV check iff the + * application supports EMV cards only. + */ +int32_t SCLIB_Activate(uint32_t num, uint32_t u32EMVCheck); + +/** + * @brief Activate a smartcard with large delay between set VCC high and start CLK output + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[in] u32EMVCheck Enable EMV error check or not. Valid setting are \ref TRUE and \ref FALSE. + * By enable EMV error checking, this library will perform ATR checking according to + * EMV book 1 specification. Otherwise, the error checking follows ISO 7816-3 + * @param[in] u32Delay Extra delay time between set VCC high and start CLK output, using ETU as time unit. + * @return Smartcard successfully activated or not + * @retval SCLIB_SUCCESS Smartcard activated successfully + * @retval Others Smartcard activation failed + * @note It is required to set smartcard interface clock between 1 MHz and 5 MHz before + * calling this API, otherwise this API return with \ref SCLIB_ERR_CLOCK error code. + * @note EMV book 1 is stricter than ISO-7816 on ATR checking. Enable EMV check iff the + * application supports EMV cards only. + * @note Only use this function instead of \ref SCLIB_Activate if there's large capacitor on VCC pin and + * VCC raise slowly. + */ +int32_t SCLIB_ActivateDelay(uint32_t num, uint32_t u32EMVCheck, uint32_t u32Delay); + + + +/** + * @brief Cold reset a smartcard + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Smartcard cold reset success or not + * @retval SCLIB_SUCCESS Smartcard cold reset success + * @retval Others Smartcard cold reset failed + */ +int32_t SCLIB_ColdReset(uint32_t num); + +/** + * @brief Warm reset a smartcard + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Smartcard warm reset success or not + * @retval SCLIB_SUCCESS Smartcard warm reset success + * @retval Others Smartcard warm reset failed + */ +int32_t SCLIB_WarmReset(uint32_t num); + +/** + * @brief Deactivate a smartcard + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return None + */ +void SCLIB_Deactivate(uint32_t num); + +/** + * @brief Get the card information (e.g., protocol selected, ATR...) after activation success + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[out] s_info A pointer to \ref SCLIB_CARD_INFO_T holds the card information + * @return Success or not + * @retval SCLIB_SUCCESS Success, s_info contains card information + * @retval SCLIB_ERR_CARD_REMOVED Card removed, s_info does not contains card information + * @retval SCLIB_ERR_DEACTIVE Card is deactivated, s_info does not contains card information + */ +int32_t SCLIB_GetCardInfo(uint32_t num, SCLIB_CARD_INFO_T *s_info); + + +/** + * @brief Get the card attribute (e.g., Fi, Di, convention, guard time... etc. ) after activation success + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[out] s_attrib A pointer to \ref SCLIB_CARD_ATTRIB_T holds the card information + * @return Success or not + * @retval SCLIB_SUCCESS Success, s_info contains card information + * @retval SCLIB_ERR_CARD_REMOVED Card removed, s_info does not contains card information + * @retval SCLIB_ERR_DEACTIVE Card is deactivated, s_info does not contains card information + */ +int32_t SCLIB_GetCardAttrib(uint32_t num, SCLIB_CARD_ATTRIB_T *s_attrib); + +/** + * @brief Start a smartcard transmission. + * @details SCLIB will start a transmission according to the protocol selected + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[in] cmdBuf Command buffer pointer + * @param[in] cmdLen Command length + * @param[out] rspBuf Buffer to holds card response + * @param[out] rspLen Response length received + * @return Smartcard transmission success or failed + * @retval SCLIB_SUCCESS Transmission success. rspBuf and rspLen holds response data and length + * @retval Others Transmission failed + * @note This API supports case 1, 2S, 3S, and 4S defined in ISO-7816, but does \b NOT support case 2E, 3E, and 4E. + */ +int32_t SCLIB_StartTransmission(uint32_t num, uint8_t *cmdBuf, uint32_t cmdLen, uint8_t *rspBuf, uint32_t *rspLen); + +/** + * @brief Set interface device max information field size (IFSD) + * @details This function sends S block to notify card about the max size of information filed blocks that + * can be received by the interface device. According to EMV 9.2.4.3, this should be the first + * block transmitted by terminal to ICC after ATR. + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @param[in] size IFSD size. According to EMV spec 9.2.4.3 Error Free Operation, this field must be 0xFE. + * @return Smartcard transmission success or failed + * @retval SCLIB_SUCCESS Smartcard warm reset success + * @retval Others Smartcard warm reset failed + */ +int32_t SCLIB_SetIFSD(uint32_t num, uint8_t size); + + +/** + * @brief A callback called by library while smartcard request for a time extension + * @param[in] u32Protocol What protocol the card is using while it requested for a time extension. + * Could be ether \ref SCLIB_PROTOCOL_T0 or \ref SCLIB_PROTOCOL_T1 + * @return None + * @note This function is defined with __weak attribute and does nothing in library. + * Application can provide its own time extension function. For example, and CCID reader + * can use this function to report this status to PC. See CCID rev 1.1 Table 6.2-3 + */ +#if defined (__GNUC__) +void SCLIB_RequestTimeExtension () __attribute__ ((weak)); +void SCLIB_RequestTimeExtension(uint32_t u32Protocol); +#else +__weak void SCLIB_RequestTimeExtension(uint32_t u32Protocol); +#endif + +/** + * @brief Process card detect event in IRQ handler + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Card detect event occur or not + * @retval 1 Card detect event occurred + * @retval 0 Card detect event did not occur + * @note Smartcard IRQ handler shall call this function with correct interface number as parameter + */ +uint32_t SCLIB_CheckCDEvent(uint32_t num); + +/** + * @brief Process time out event in IRQ handler + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Time out event occur or not + * @retval 1 Time out event occurred + * @retval 0 Time out event did not occur + * @note Smartcard IRQ handler shall call this function with correct interface number as parameter + */ +uint32_t SCLIB_CheckTimeOutEvent(uint32_t num); + +/** + * @brief Process card transmission event in IRQ handler + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Transmission event occur or not + * @retval 1 Transmission event occurred + * @retval 0 Transmission event did not occur + * @note Smartcard IRQ handler shall call this function with correct interface number as parameter + */ +uint32_t SCLIB_CheckTxRxEvent(uint32_t num); + +/** + * @brief Process error event in IRQ handler + * @param[in] num Smartcard interface number. From 0 ~ ( \ref SC_INTERFACE_NUM - 1) + * @return Error event occur or not + * @retval 1 Error event occurred + * @retval 0 Error event did not occur + * @note Smartcard IRQ handler shall call this function with correct interface number as parameter + */ +uint32_t SCLIB_CheckErrorEvent(uint32_t num); + + +#ifdef __cplusplus +} +#endif + +#endif //__SCLIB_H__ + +/*@}*/ /* end of group SCLIB_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Library */ + +/*@}*/ /* end of group Library */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/SmartcardLib/SmartCardLib.lib b/BSP/SmartcardLib/SmartCardLib.lib new file mode 100644 index 0000000000000000000000000000000000000000..f6d5bb3b2a0b283739e0fa69c1254b4e49f838b0 GIT binary patch literal 40904 zcmeHw3wRsVnf95{UA|u+b|TV|?Idz8j_usct;mw2Smc6ZJ2WAt9@&;7C62Aw3RNHh zg@$fm({7+_>j1k=fNs;v-#=wZOD}X23N7if`;P+YLSc86mafxoFVM0r?Di-B`^`n3 znOLa<<$22U_dJ%*yytt*cdm0ZbIzx8yw^lV`(qz;FBXihQ3sW4{eMAdYHnGgP((Ll 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+/**************************************************************************//** + * @file acmp.h + * @version V3.00 + * $Revision: 11 $ + * $Date: 15/05/20 8:50p $ + * @brief Analog Comparator (ACMP) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CMPCR constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CR_VNEG_BANDGAP (1UL << ACMP_CMPCR_CMPCN_Pos) /*!< CMPCR setting for selecting band-gap voltage as the source of ACMP V-. */ +#define ACMP_CR_VNEG_PIN (0UL << ACMP_CMPCR_CMPCN_Pos) /*!< CMPCR setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */ +#define ACMP_CR_HYSTERESIS_ENABLE (1UL << ACMP_CMPCR_CMP_HYSEN_Pos) /*!< CMPCR setting for enabling the hysteresis function. */ +#define ACMP_CR_HYSTERESIS_DISABLE (0UL << ACMP_CMPCR_CMP_HYSEN_Pos) /*!< CMPCR setting for disabling the hysteresis function. */ +#define ACMP_CR_INT_ENABLE (1UL << ACMP_CMPCR_CMPIE_Pos) /*!< CMPCR setting for enabling the interrupt function. */ +#define ACMP_CR_INT_DISABLE (0UL << ACMP_CMPCR_CMPIE_Pos) /*!< CMPCR setting for disabling the interrupt function. */ +#define ACMP_CR_ACMP_ENABLE (1UL << ACMP_CMPCR_CMPEN_Pos) /*!< CMPCR setting for enabling the ACMP analog circuit. */ +#define ACMP_CR_ACMP_DISABLE (0UL << ACMP_CMPCR_CMPEN_Pos) /*!< CMPCR setting for disabling the ACMP analog circuit. */ + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src Comparator negative input selection. Including: + * - \ref ACMP_CR_VNEG_PIN + * - \ref ACMP_CR_VNEG_BANDGAP + * @return None + * @details This macro will set CMPCN bit of CMPCR register to determine the source of negative input. + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CMPCR[(u32ChNum)%2] = ((acmp)->CMPCR[(u32ChNum)%2] & ~ACMP_CMPCR_CMPCN_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set HYSEN bit of CMPCR register to enable hysteresis function. + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] |= ACMP_CMPCR_CMP_HYSEN_Msk) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEN bit of CMPCR register to disable hysteresis function. + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] &= ~ACMP_CMPCR_CMP_HYSEN_Msk) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set CMPIE bit of CMPCR register to enable interrupt function. + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] |= ACMP_CMPCR_CMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear CMPIE bit of CMPCR register to disable interrupt function. + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] &= ~ACMP_CMPCR_CMPIE_Msk) + + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set CMPEN bit of CMPCR register to enable analog comparator. + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] |= ACMP_CMPCR_CMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear CMPEN bit of CMPCR register to disable analog comparator. + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CMPCR[(u32ChNum)%2] &= ~ACMP_CMPCR_CMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->CMPSR & (ACMP_CMPSR_CO0_Msk<<(u32ChNum)))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred or not + * @details This macro will return the ACMP interrupt flag. + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->CMPSR & (ACMP_CMPSR_CMPF0_Msk<<(u32ChNum)))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to CMPFn bit of CMPSR register to clear interrupt flag. + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->CMPSR = (ACMP_CMPSR_CMPF0_Msk<<(u32ChNum))) + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn); +void ACMP_Close(ACMP_T *, uint32_t u32ChNum); + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__ACMP_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/adc.h b/BSP/StdDriver/inc/adc.h new file mode 100644 index 0000000..e594354 --- /dev/null +++ b/BSP/StdDriver/inc/adc.h @@ -0,0 +1,362 @@ +/**************************************************************************//** + * @file adc.h + * @version V3.00 + * $Revision: 14 $ + * $Date: 15/05/06 4:39p $ + * @brief ADC Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __ADC_H__ +#define __ADC_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_EXPORTED_CONSTANTS ADC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* ADCR Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ADC_ADCR_ADEN_CONVERTER_DISABLE (0UL<ADCHER = ((adc)->ADCHER & ~ADC_ADCHER_PRESEL_Msk) | (u32Source)) + +/** + * @brief Enable PDMA transfer. + * @param[in] adc The pointer of the specified ADC module + * @return None + * @details Enable PDMA to transfer the conversion data. + * @note While enable PDMA transfer, software must set ADIE = 0 to disable interrupt. + */ +#define ADC_ENABLE_PDMA(adc) ((adc)->ADCR |= ADC_ADCR_PTEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] adc The pointer of the specified ADC module + * @return None + * @details Disable PDMA to transfer the conversion data. + */ +#define ADC_DISABLE_PDMA(adc) ((adc)->ADCR &= ~ADC_ADCR_PTEN_Msk) + +/** + * @brief Get conversion data of specified channel. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32ChNum ADC Channel, valid value are from 0 to 7. + * @return 16-bit data. + * @details Read RSLT bit field to get conversion data. + */ +#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->ADDR[(u32ChNum)] & ADC_ADDR_RSLT_Msk) + +/** + * @brief Return the user-specified interrupt flags. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status. + * Valid values are: + * - \ref ADC_ADF_INT :Convert complete interrupt flag. + * - \ref ADC_CMP0_INT :Comparator 0 interrupt flag. + * - \ref ADC_CMP1_INT :Comparator 1 interrupt flag. + * @return User specified interrupt flags. + * @details Get the status of the ADC interrupt flag. + */ +#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->ADSR & (u32Mask)) + +/** + * @brief This macro clear the selected interrupt status bits. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status. + * Valid values are: + * - \ref ADC_ADF_INT :Convert complete interrupt flag. + * - \ref ADC_CMP0_INT :Comparator 0 interrupt flag. + * - \ref ADC_CMP1_INT :Comparator 1 interrupt flag. + * @return None + * @details ADF (ADSR[0])/CMPF0 (ADSR[1])/CMPF0 (ADSR[2]) can be cleared by writing 1 to itself. + */ +#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->ADSR = (u32Mask)) + +/** + * @brief Get the busy state of ADC. + * @param[in] adc The pointer of the specified ADC module. + * @retval 0 ADC is not busy. + * @retval 1 ADC is busy. + * @details BUSY(ADSR[3])is mirror of as ADST bit (ADCR[11]). + */ +#define ADC_IS_BUSY(adc) ((adc)->ADSR & ADC_ADSR_BUSY_Msk ? 1 : 0) + +/** + * @brief Check if the ADC conversion data is over written or not. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32ChNum ADC Channel, valid value are from 0 to 7. + * @retval 0 ADC data is not overrun. + * @retval 1 ADC data is overrun. + * @details OVERRUN (ADSR[23:16]) is a mirror to OVERRUN (ADDR0~7[16]). + */ +#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((adc)->ADSR & (0x1 << (ADC_ADSR_OVERRUN_Pos + (u32ChNum))) ? 1 : 0) + +/** + * @brief Check if the ADC conversion data is valid or not. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32ChNum ADC Channel, valid value are from 0 to 7. + * @retval 0 ADC data is not valid. + * @retval 1 ADC data is valid. + * @details VALID (ADDR0~7[17]) is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read. + */ +#define ADC_IS_DATA_VALID(adc, u32ChNum) ((adc)->ADSR & (0x1<<(ADC_ADSR_VALID_Pos+(u32ChNum))) ? 1 : 0) + +/** + * @brief Power down ADC module. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Disable A/D converter analog circuit for saving power consumption. + * @note None + */ +#define ADC_POWER_DOWN(adc) ((adc)->ADCR &= ~ADC_ADCR_ADEN_Msk) + +/** + * @brief Power on ADC module. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Before starting A/D conversion function, ADEN bit (ADCR[0]) should be set to 1. + */ +#define ADC_POWER_ON(adc) ((adc)->ADCR |= ADC_ADCR_ADEN_Msk) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7. + * @param[in] u32Condition Specifies the compare condition. Valid values are: + * - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value". + * - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value. + * @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF. + * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16. + * @return None + * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means ADC will assert comparator 0 flag if channel 5 conversion result is greater or + * equal to 0x800 for 10 times continuously. + * \hideinitializer + */ +#define ADC_ENABLE_CMP0(adc, \ + u32ChNum, \ + u32Condition, \ + u32Data, \ + u32MatchCount) ((adc)->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \ + (u32Condition) | \ + ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \ + (((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\ + ADC_ADCMPR_CMPEN_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Set CMPEN (ADCMPR0[0]) to 0 to disable ADC controller to compare CMPD (ADCMPR0[27:16]). + */ +#define ADC_DISABLE_CMP0(adc) ((adc)->ADCMPR[0] = 0) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7. + * @param[in] u32Condition Specifies the compare condition. Valid values are: + * - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value". + * - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value. + * @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF. + * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16. + * @return None + * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means ADC will assert comparator 1 flag if channel 5 conversion result is greater or + * equal to 0x800 for 10 times continuously. + * \hideinitializer + */ +#define ADC_ENABLE_CMP1(adc, \ + u32ChNum, \ + u32Condition, \ + u32Data, \ + u32MatchCount) ((adc)->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \ + (u32Condition) | \ + ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \ + (((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\ + ADC_ADCMPR_CMPEN_Msk) + +/** + * @brief Disable comparator 1. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Set CMPEN (ADCMPR1[0]) to 0 to disable ADC controller to compare CMPD (ADCMPR1[27:16]). + */ +#define ADC_DISABLE_CMP1(adc) ((adc)->ADCMPR[1] = 0) + +/** + * @brief Set ADC input channel. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7. + * @return None + * @details Enabled channel will be converted while ADC starts. + * @note NUC200 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel + * with smallest number will be convert. + */ +#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) ((adc)->ADCHER = ((adc)->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask)) + +/** + * @brief Set the output format mode. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - \ref ADC_ADCR_DMOF_UNSIGNED_OUTPUT :Select the straight binary format as the output format of the conversion result. + * - \ref ADC_ADCR_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D differential input mode output format. + */ +#define ADC_SET_DMOF(adc, u32Format) ((adc)->ADCR = ((adc)->ADCR & ~ADC_ADCR_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details ADST (ADCR[11]) can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. + */ +#define ADC_START_CONV(adc) ((adc)->ADCR |= ADC_ADCR_ADST_Msk) + +/** + * @brief Stop the A/D conversion. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details ADST (ADCR[11]) will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. + * In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset. + */ +#define ADC_STOP_CONV(adc) ((adc)->ADCR &= ~ADC_ADCR_ADST_Msk) + +void ADC_Open(ADC_T *adc, + uint32_t u32InputMode, + uint32_t u32OpMode, + uint32_t u32ChMask); +void ADC_Close(ADC_T *adc); +void ADC_EnableHWTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32Param); +void ADC_DisableHWTrigger(ADC_T *adc); +void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask); +void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask); + + + +/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ADC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__ADC_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/clk.h b/BSP/StdDriver/inc/clk.h new file mode 100644 index 0000000..73efccb --- /dev/null +++ b/BSP/StdDriver/inc/clk.h @@ -0,0 +1,561 @@ +/**************************************************************************//** + * @file clk.h + * @version V3.0 + * $Revision: 42 $ + * $Date: 17/07/20 1:59p $ + * @brief Clock Control Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + +#define FREQ_25MHZ 25000000 +#define FREQ_50MHZ 50000000 +#define FREQ_100MHZ 100000000 +#define FREQ_200MHZ 200000000 + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLK_S_HXT (0x0UL<>30) & 0x3) /*!< Calculate APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK, 0x2:APBCLK1 */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK, 0x2:APBCLK1 */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */ + + +#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMA_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ +#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISP_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ +#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_WDT_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */ +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_TMR0_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */ +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_TMR1_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */ +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_TMR2_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */ +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_TMR3_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */ +#define FDIV_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_FDIV_EN_Pos) |\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FDIV Module */ +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_I2C0_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_I2C1_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ +#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_SPI0_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 4)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */ +#define SPI1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_SPI1_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 5)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI1 Module */ +#define SPI2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_SPI2_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 6)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI2 Module */ +#define SPI3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_SPI3_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 7)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ +#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_UART0_EN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */ +#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_UART1_EN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART1 Module */ +#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_UART2_EN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART2 Module */ +#define PWM01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_PWM01_EN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM01 Module */ +#define PWM23_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_PWM23_EN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM23 Module */ +#define PWM45_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_PWM45_EN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM45 Module */ +#define PWM67_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_PWM67_EN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 6)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM67 Module */ +#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_USBD_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */ +#define ADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_ADC_EN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< ADC Module */ +#define I2S_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_I2S_EN_Pos) |\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2S Module */ +#define ACMP_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_ACMP_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP Module */ +#define PS2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_PS2_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PS2 Module */ +#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0_EN_Pos) |\ + MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */ +#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC1_EN_Pos) |\ + MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\ + MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< SC1 Module */ +#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC2_EN_Pos) |\ + MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\ + MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< SC2 Module */ +#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_RTC_EN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK_WDT_EN_Pos) |\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(16)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */ + + +#define CLK_CLKSEL_PWM01_HXT (CLK_CLKSEL1_PWM01_S_HXT |CLK_CLKSEL2_PWM01_EXT_HXT) /*!< HXT Clock selection setting for PWM01 */ +#define CLK_CLKSEL_PWM01_LXT (CLK_CLKSEL1_PWM01_S_LXT |CLK_CLKSEL2_PWM01_EXT_LXT) /*!< LXT Clock selection setting for PWM01 */ +#define CLK_CLKSEL_PWM01_HCLK (CLK_CLKSEL1_PWM01_S_HCLK|CLK_CLKSEL2_PWM01_EXT_HCLK) /*!< HCLK Clock selection setting for PWM01 */ +#define CLK_CLKSEL_PWM01_HIRC (CLK_CLKSEL1_PWM01_S_HIRC|CLK_CLKSEL2_PWM01_EXT_HIRC) /*!< HIRC Clock selection setting for PWM01 */ +#define CLK_CLKSEL_PWM01_LIRC (CLK_CLKSEL1_PWM01_S_LIRC|CLK_CLKSEL2_PWM01_EXT_LIRC) /*!< LIRC Clock selection setting for PWM01 */ +#define CLK_CLKSEL_PWM23_HXT (CLK_CLKSEL1_PWM23_S_HXT |CLK_CLKSEL2_PWM23_EXT_HXT) /*!< HXT Clock selection setting for PWM23 */ +#define CLK_CLKSEL_PWM23_LXT (CLK_CLKSEL1_PWM23_S_LXT |CLK_CLKSEL2_PWM23_EXT_LXT) /*!< LXT Clock selection setting for PWM23 */ +#define CLK_CLKSEL_PWM23_HCLK (CLK_CLKSEL1_PWM23_S_HCLK|CLK_CLKSEL2_PWM23_EXT_HCLK) /*!< HCLK Clock selection setting for PWM23 */ +#define CLK_CLKSEL_PWM23_HIRC (CLK_CLKSEL1_PWM23_S_HIRC|CLK_CLKSEL2_PWM23_EXT_HIRC) /*!< HIRC Clock selection setting for PWM23 */ +#define CLK_CLKSEL_PWM23_LIRC (CLK_CLKSEL1_PWM23_S_LIRC|CLK_CLKSEL2_PWM23_EXT_LIRC) /*!< LIRC Clock selection setting for PWM23 */ +#define CLK_CLKSEL_PWM45_HXT (CLK_CLKSEL2_PWM45_S_HXT |CLK_CLKSEL2_PWM45_EXT_HXT) /*!< HXT Clock selection setting for PWM45 */ +#define CLK_CLKSEL_PWM45_LXT (CLK_CLKSEL2_PWM45_S_LXT |CLK_CLKSEL2_PWM45_EXT_LXT) /*!< LXT Clock selection setting for PWM45 */ +#define CLK_CLKSEL_PWM45_HCLK (CLK_CLKSEL2_PWM45_S_HCLK|CLK_CLKSEL2_PWM45_EXT_HCLK) /*!< HCLK Clock selection setting for PWM45 */ +#define CLK_CLKSEL_PWM45_HIRC (CLK_CLKSEL2_PWM45_S_HIRC|CLK_CLKSEL2_PWM45_EXT_HIRC) /*!< HIRC Clock selection setting for PWM45 */ +#define CLK_CLKSEL_PWM45_LIRC (CLK_CLKSEL2_PWM45_S_LIRC|CLK_CLKSEL2_PWM45_EXT_LIRC) /*!< LIRC Clock selection setting for PWM45 */ +#define CLK_CLKSEL_PWM67_HXT (CLK_CLKSEL2_PWM67_S_HXT |CLK_CLKSEL2_PWM67_EXT_HXT) /*!< HXT Clock selection setting for PWM67 */ +#define CLK_CLKSEL_PWM67_LXT (CLK_CLKSEL2_PWM67_S_LXT |CLK_CLKSEL2_PWM67_EXT_LXT) /*!< LXT Clock selection setting for PWM67 */ +#define CLK_CLKSEL_PWM67_HCLK (CLK_CLKSEL2_PWM67_S_HCLK|CLK_CLKSEL2_PWM67_EXT_HCLK) /*!< HCLK Clock selection setting for PWM67 */ +#define CLK_CLKSEL_PWM67_HIRC (CLK_CLKSEL2_PWM67_S_HIRC|CLK_CLKSEL2_PWM67_EXT_HIRC) /*!< HIRC Clock selection setting for PWM67 */ +#define CLK_CLKSEL_PWM67_LIRC (CLK_CLKSEL2_PWM67_S_LIRC|CLK_CLKSEL2_PWM67_EXT_LIRC) /*!< LIRC Clock selection setting for PWM67 */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1, 2, 2, 4}; + + u32PllReg = CLK->PLLCON; + + if(u32PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) + return 0; /* PLL is in power down mode or fix low */ + + if(u32PllReg & CLK_PLLCON_PLL_SRC_HIRC) + u32FIN = __HIRC; /* PLL source clock from HIRC */ + else + u32FIN = __HXT; /* PLL source clock from HXT */ + + if(u32PllReg & CLK_PLLCON_BP_Msk) + return u32FIN; /* PLL is in bypass mode */ + + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; + u32NR = ((u32PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2); + + return u32PllFreq; +} + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x00); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); + + /* Disable SysTick counter */ + SysTick->CTRL = 0; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ + +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t delay; + + /* It should <= 335544us for each delay loop */ + delay = 335544UL; + + do + { + if(us > delay) + { + us -= delay; + } + else + { + delay = us; + us = 0UL; + } + + SysTick->LOAD = delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + }while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLKFreq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Device_Driver */ + + + +#endif //__CLK_H__ + + + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/crc.h b/BSP/StdDriver/inc/crc.h new file mode 100644 index 0000000..38e375a --- /dev/null +++ b/BSP/StdDriver/inc/crc.h @@ -0,0 +1,160 @@ +/**************************************************************************//** + * @file crc.h + * @version V3.00 + * $Revision: 6 $ + * $Date: 15/05/04 3:58p $ + * @brief CRC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT 0x00000000UL /*!DMAIER |= (u32Mask)) + +/** + * @brief Disable CRC Interrupt + * + * @param[in] u32Mask Interrupt mask + * + * @return None + * + * @details This macro disable the specify CRC interrupt function by u32Mask setting. + */ +#define CRC_DISABLE_INT(u32Mask) (CRC->DMAIER &= ~(u32Mask)) + +/** + * @brief Get CRC Interrupt Flag + * + * @param None + * + * @return Interrupt Flag Status + * + * @details This macro gets the CRC interrupt flags. + */ +#define CRC_GET_INT_FLAG() ((uint32_t)(CRC->DMAISR)) + +/** + * @brief Clear CRC Interrupt Flag + * + * @param[in] u32Mask Interrupt mask + * + * @return None + * + * @details This macro clear the specify CRC interrupt flag by u32Mask setting. + */ +#define CRC_CLR_INT_FLAG(u32Mask) (CRC->DMAISR = (u32Mask)) + +/** + * @brief Set CRC seed value + * + * @param[in] u32Seed Seed value + * + * @return None + * + * @details This macro set CRC seed value. + * + * @note User must to setting CRC_RST (CRC_CTL[1] CRC Engine Reset) to reload the new seed value + * to CRC controller. + */ +#define CRC_SET_SEED(u32Seed) { CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CRC_RST_Msk; } + +/** + * @brief Get CRC Seed value + * + * @param None + * + * @return Seed Value + * + * @details This macro gets the current CRC seed value. + */ +#define CRC_GET_SEED() ((uint32_t)(CRC->SEED)) + +/** + * @brief CRC write data + * + * @param[in] u32Data write data + * + * @return None + * + * @details User can write data directly by this macro to perform CRC operation. + */ +#define CRC_WRITE_DATA(u32Data) (CRC->WDATA = (u32Data)) + + +/*********************************************************************/ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__CRC_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/fmc.h b/BSP/StdDriver/inc/fmc.h new file mode 100644 index 0000000..474ba75 --- /dev/null +++ b/BSP/StdDriver/inc/fmc.h @@ -0,0 +1,456 @@ +/**************************************************************************//** + * @file FMC.h + * @version V3.0 + * $Revision: 13 $ + * $Date: 15/05/19 3:38p $ + * @brief Flash Memory Controller Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ + +#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 Bytes) */ +#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4K Bytes) */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCON constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCON_BS_LDROM 0x2 /*!< ISPCON setting to select to boot from LDROM */ +#define FMC_ISPCON_BS_APROM 0x0 /*!< ISPCON setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */ +#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Program Flash */ +#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_VECMAP 0x2e /*!< ISP Command: Set VECMAP */ +#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */ + + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* FMC Macro Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable ISP Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCON control register to enable ISP function. + * + */ +#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk) + + +/** + * @brief Disable ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCON control register to disable ISP function. + * + */ +#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk) + + +/** + * @brief Enable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set LDUEN bit of ISPCON control register to enable LDROM update function. + * User needs to set LDUEN bit before they can update LDROM. + * + */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk) + + + +/** + * @brief Disable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCON control register to disable LDROM update function. + * + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk) /*!< Disable LDROM Update Function */ + + + +/** + * @brief Enable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will set CFGUEN bit of ISPCON control register to enable User Configuration update function. + * User needs to set CFGUEN bit before they can update User Configuration area. + * + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk) + +/** + * @brief Disable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will clear CFGUEN bit of ISPCON control register to disable User Configuration update function. + * + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ + + +/** + * @brief Enable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set APUEN bit of ISPCON control register to enable APROM update function. + * User needs to set APUEN bit before they can update APROM in APROM boot mode. + * + */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk) + + +/** + * @brief Disable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will clear APUEN bit of ISPCON control register to disable APROM update function. + * + */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk) /*!< Disable APROM Update Function */ + +/** + * @brief Get ISP fail flag + * + * @param None + * + * @retval 0 Previous ISP command execution result is successful + * @retval 1 Previous ISP command execution result is fail + * + * @details ISPFF flag of ISPCON is used to indicate ISP command success or fail. + * This function will return the ISPFF flag to identify ISP command OK or fail. + * + */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0) + + +/** + * @brief Select booting from APROM + * + * @param None + * + * @return None + * + * @details If MCU is working without IAP, user need to set BS bit of ISPCON and reset CPU to execute the code of LDROM/APROM. + * This function is used to set BS bit of ISPCON to boot to APROM. + * + * @note To valid new BS bit setting, user also need to trigger CPU reset or System Reset Request after setting BS bit. + * + */ +#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk) + +/** + * @brief Select booting from APROM + * + * @param None + * + * @return None + * + * @details If MCU is working without IAP, user need to set/clear BS bit of ISPCON and reset CPU to execute the code of APROM/LDROM. + * This function is used to clear BS bit of ISPCON to boot to LDROM. + * + * @note To valid new BS bit setting, user also need to trigger CPU reset or System Reset Request after clear BS bit. + * + */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Program 32-bit data into specified address of flash + * + * @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG + * @param[in] u32data 32-bit Data to program + * + * @return None + * + * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG. + * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual. + * + */ +static __INLINE void FMC_Write(uint32_t u32addr, uint32_t u32data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; /* Set ISP Command Code */ + FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */ + FMC->ISPDAT = u32data; /* Set Data to Program */ + FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG); /* Waiting for ISP Done */ +} + +/** + * @brief Read 32-bit Data from specified address of flash + * + * @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG + * + * @return The data of specified address + * + * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG. + * + */ +static __INLINE uint32_t FMC_Read(uint32_t u32addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; /* Set ISP Command Code */ + FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */ + FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG); /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + + +/** + * @brief Flash page erase + * + * @param[in] u32addr Flash address including APROM, LDROM, Data Flash, and CONFIG + * + * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG. + * The page size is 512 bytes. + * + * @retval 0 Success + * @retval -1 Erase failed + * + */ +static __INLINE int32_t FMC_Erase(uint32_t u32addr) +{ + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; /* Set ISP Command Code */ + FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be page alignment. */ + FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG); /* Waiting for ISP Done */ + + /* Check ISPFF flag to know whether erase OK or fail. */ + if(FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) + { + FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk; + return -1; + } + return 0; +} + +/** + * @brief Read Unique ID + * + * @param[in] u8index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * + * @return The 32-bit unique ID data of specified UID index. + * + * @details To read out 96-bit Unique ID. + * + */ +static __INLINE uint32_t FMC_ReadUID(uint8_t u8index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADR = (u8index << 2); /* Set UID Address. It must be word alignment. */ + FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG); /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + + +/** + * @brief Read company ID + * + * @param None + * + * @return The company ID (32-bit) + * + * @details The company ID of Nuvoton is fixed to be 0xDA + * + */ +static __INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADR = 0x0; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * + * @param None + * + * @return The product ID (32-bit) + * + * @details This function is used to read product ID. + * + */ +static __INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADR = 0x04; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * + * @return The UCID of specified index + * + * @details This function is used to read unique chip ID (UCID). + * + */ +static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + + + +/** + * @brief Set vector mapping address + * + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * + * @return None + * + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + * + */ +static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ + __ISB(); /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG); /* Waiting for ISP Done */ +} + + +/** + * @brief Get current vector mapping address. + * + * @param None + * + * @return The current vector mapping address. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + * + */ +static __INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTA & FMC_ISPSTA_VECMAP_Msk); +} + +extern void FMC_Open(void); +extern void FMC_Close(void); +extern void FMC_EnableAPUpdate(void); +extern void FMC_DisableAPUpdate(void); +extern void FMC_EnableConfigUpdate(void); +extern void FMC_DisableConfigUpdate(void); +extern void FMC_EnableLDUpdate(void); +extern void FMC_DisableLDUpdate(void); +extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern int32_t FMC_GetBootSource(void); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/BSP/StdDriver/inc/gpio.h b/BSP/StdDriver/inc/gpio.h new file mode 100644 index 0000000..87d7660 --- /dev/null +++ b/BSP/StdDriver/inc/gpio.h @@ -0,0 +1,441 @@ +/**************************************************************************//** + * @file GPIO.h + * @version V3.00 + * $Revision: 14 $ + * $Date: 15/05/04 3:58p $ + * @brief General Purpose I/O Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ +#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PMD Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define GPIO_PMD_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* IMD Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */ +#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DBNCECON Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_CLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_INT_CLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCLKSRC_LIRC 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */ +#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the HCLK */ + +#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */ +#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */ +#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */ +#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */ +#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */ +#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */ +#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */ +#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */ +#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */ +#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */ +#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */ +#define PC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ + + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->ISRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->ISRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be \n + * GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, GPIO_DBCLKSEL_8, \n + * GPIO_DBCLKSEL_16, GPIO_DBCLKSEL_32, GPIO_DBCLKSEL_64, GPIO_DBCLKSEL_128, \n + * GPIO_DBCLKSEL_256, GPIO_DBCLKSEL_512, GPIO_DBCLKSEL_1024, GPIO_DBCLKSEL_2048, \n + * GPIO_DBCLKSEL_4096, GPIO_DBCLKSEL_8192, GPIO_DBCLKSEL_16384, GPIO_DBCLKSEL_32768. + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCLKSRC_LIRC, GPIO_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 400 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GPIO_DBNCECON_ICLK_ON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + +/** + * @brief Enable External GPIO Interrupt 0 + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT0 GPIO_EnableInt + + +/** + * @brief Disable External GPIO Interrupt 0 + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT0 GPIO_DisableInt + + +/** + * @brief Enable External GPIO Interrupt 1 + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT1 GPIO_EnableInt + + +/** + * @brief Disable External GPIO Interrupt 1 + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT1 GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__GPIO_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/i2c.h b/BSP/StdDriver/inc/i2c.h new file mode 100644 index 0000000..92df958 --- /dev/null +++ b/BSP/StdDriver/inc/i2c.h @@ -0,0 +1,206 @@ +/**************************************************************************//** + * @file i2c.h + * @version V3.0 + * $Revision: 16 $ + * $Date: 15/05/22 11:23a $ + * @brief I2C Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __I2C_H__ +#define __I2C_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2CON constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_I2CON_STA_SI 0x28UL /*!< I2CON setting for I2C control bits. It would set STA and SI bits */ +#define I2C_I2CON_STA_SI_AA 0x2CUL /*!< I2CON setting for I2C control bits. It would set STA, SI and AA bits */ +#define I2C_I2CON_STO_SI 0x18UL /*!< I2CON setting for I2C control bits. It would set STO and SI bits */ +#define I2C_I2CON_STO_SI_AA 0x1CUL /*!< I2CON setting for I2C control bits. It would set STO, SI and AA bits */ +#define I2C_I2CON_SI 0x08UL /*!< I2CON setting for I2C control bits. It would set SI bit */ +#define I2C_I2CON_SI_AA 0x0CUL /*!< I2CON setting for I2C control bits. It would set SI and AA bits */ +#define I2C_I2CON_STA 0x20UL /*!< I2CON setting for I2C control bits. It would set STA bit */ +#define I2C_I2CON_STO 0x10UL /*!< I2CON setting for I2C control bits. It would set STO bit */ +#define I2C_I2CON_AA 0x04UL /*!< I2CON setting for I2C control bits. It would set AA bit */ + +#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */ + +/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2CON register to control I2C bus conditions of START, STOP, SI, ACK. + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->I2CON = ((i2c)->I2CON & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2CON register. + */ +#define I2C_START(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2CON register. + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->I2CON & I2C_I2CON_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + */ +#define I2C_GET_DATA(i2c) ((i2c)->I2CDAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2CDAT register, the I2C controller will shift it to I2C bus. + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->I2CDAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + */ +#define I2C_GET_STATUS(i2c) ((i2c)->I2CSTATUS) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->I2CTOC & I2C_I2CTOC_TIF_Msk) == I2C_I2CTOC_TIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->I2CWKUPSTS & I2C_I2CWKUPSTS_WKUPIF_Msk) == I2C_I2CWKUPSTS_WKUPIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->I2CWKUPSTS |= I2C_I2CWKUPSTS_WKUPIF_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2CON register and wait STOP condition finish. + */ +static __INLINE void I2C_STOP(I2C_T *i2c) +{ + (i2c)->I2CON |= (I2C_I2CON_SI_Msk | I2C_I2CON_STO_Msk); + while((i2c)->I2CON & I2C_I2CON_STO_Msk); +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif +#endif //__I2C_H__ diff --git a/BSP/StdDriver/inc/i2s.h b/BSP/StdDriver/inc/i2s.h new file mode 100644 index 0000000..64ddb99 --- /dev/null +++ b/BSP/StdDriver/inc/i2s.h @@ -0,0 +1,300 @@ +/**************************************************************************//** + * @file i2s.h + * @version V3.0 + * $Revision: 12 $ + * $Date: 15/05/04 3:58p $ + * @brief I2S driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0 << I2S_CON_WORDWIDTH_Pos) /*!< I2S data width is 8-bit */ +#define I2S_DATABIT_16 (1 << I2S_CON_WORDWIDTH_Pos) /*!< I2S data width is 16-bit */ +#define I2S_DATABIT_24 (2 << I2S_CON_WORDWIDTH_Pos) /*!< I2S data width is 24-bit */ +#define I2S_DATABIT_32 (3 << I2S_CON_WORDWIDTH_Pos) /*!< I2S data width is 32-bit */ + +/* Audio Format */ +#define I2S_MONO I2S_CON_MONO_Msk /*!< Mono channel */ +#define I2S_STEREO 0 /*!< Stereo channel */ + +/* I2S Data Format */ +#define I2S_FORMAT_MSB I2S_CON_FORMAT_Msk /*!< MSB data format */ +#define I2S_FORMAT_I2S 0 /*!< I2S data format */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CON_SLAVE_Msk /*!< As slave mode */ +#define I2S_MODE_MASTER 0 /*!< As master mode */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CON_TXTH_Pos) /*!< TX threshold is 1 word */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CON_TXTH_Pos) /*!< TX threshold is 2 words */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CON_TXTH_Pos) /*!< TX threshold is 3 words */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CON_TXTH_Pos) /*!< TX threshold is 4 words */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CON_TXTH_Pos) /*!< TX threshold is 5 words */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CON_TXTH_Pos) /*!< TX threshold is 6 words */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CON_TXTH_Pos) /*!< TX threshold is 7 words */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CON_RXTH_Pos) /*!< RX threshold is 2 words */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CON_RXTH_Pos) /*!< RX threshold is 3 words */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CON_RXTH_Pos) /*!< RX threshold is 4 words */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CON_RXTH_Pos) /*!< RX threshold is 5 words */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CON_RXTH_Pos) /*!< RX threshold is 6 words */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CON_RXTH_Pos) /*!< RX threshold is 7 words */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CON_RXTH_Pos) /*!< RX threshold is 8 words */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT 0 /*!< Record mono right channel */ +#define I2S_MONO_LEFT I2S_CON_RXLCH_Msk /*!< Record mono left channel */ + +/* I2S Channel */ +#define I2S_RIGHT 0 /*!< Select right channel */ +#define I2S_LEFT 1 /*!< Select left channel */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref I2S_RIGHT + * - \ref I2S_LEFT + * @return None + * @details This function will set RCHZCEN or LCHZCEN bit of I2SCON register to enable zero cross detection function. + */ +static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == I2S_RIGHT) + i2s->CON |= I2S_CON_RCHZCEN_Msk; + else + i2s->CON |= I2S_CON_LCHZCEN_Msk; +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref I2S_RIGHT + * - \ref I2S_LEFT + * @return None + * @details This function will clear RCHZCEN or LCHZCEN bit of I2SCON register to disable zero cross detection function. + */ +static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == I2S_RIGHT) + i2s->CON &= ~I2S_CON_RCHZCEN_Msk; + else + i2s->CON &= ~I2S_CON_LCHZCEN_Msk; +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXDMA bit of I2SCON register to transmit data with PDMA. + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CON |= I2S_CON_TXDMA_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXDMA bit of I2SCON register to disable TX DMA function. + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CON &= ~I2S_CON_TXDMA_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXDMA bit of I2SCON register to receive data with PDMA. + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CON |= I2S_CON_RXDMA_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXDMA bit of I2SCON register to disable RX DMA function. + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CON &= ~I2S_CON_RXDMA_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of I2SCON register to enable I2S TX function. + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CON |= I2S_CON_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of I2SCON register to disable I2S TX function. + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CON &= ~I2S_CON_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of I2SCON register to enable I2S RX function. + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CON |= I2S_CON_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of I2SCON register to disable I2S RX function. + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CON &= ~I2S_CON_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of I2SCON register to enable I2S TX mute function. + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CON |= I2S_CON_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of I2SCON register to disable I2S TX mute function. + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CON &= ~I2S_CON_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CON |= I2S_CON_CLR_TXFIFO_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CON |= I2S_CON_CLR_RXFIFO_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch Left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + */ +static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CON |= I2S_CON_RXLCH_Msk) : + (i2s->CON &= ~I2S_CON_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination flags of I2SSTATUS register. The flags are specified by the u32mask parameter. + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_TX_LEVEL_Msk) >> I2S_STATUS_TX_LEVEL_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_RX_LEVEL_Msk) >> I2S_STATUS_RX_LEVEL_Pos) & 0xF ) + + +/* Function prototype declaration */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#endif + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + diff --git a/BSP/StdDriver/inc/pdma.h b/BSP/StdDriver/inc/pdma.h new file mode 100644 index 0000000..c939b39 --- /dev/null +++ b/BSP/StdDriver/inc/pdma.h @@ -0,0 +1,197 @@ +/**************************************************************************//** + * @file pdma.h + * @version V1.00 + * $Revision: 14 $ + * $Date: 15/05/04 3:58p $ + * @brief PDMA Controller Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + + + +/** @addtogroup Standard_Driver Standard Driver + * @{ + */ + +/** @addtogroup PDMA_Driver PDMA Driver + * @{ + */ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Data Width Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_WIDTH_8 0x00080000UL /*!GCRISR)) + +/** + * @brief Get PDMA Channel Interrupt Status + * + * @param[in] u32Ch Selected DMA channel + * + * @return Interrupt Status + * + * @details This macro gets the channel interrupt status. + */ +#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA0->ISR + (uint32_t)((u32Ch)*0x100)))) + +/** + * @brief Clear PDMA Channel Interrupt Flag + * + * @param[in] u32Ch Selected DMA channel + * @param[in] u32Mask Interrupt Mask + * + * @return None + * + * @details This macro clear the channel interrupt flag. + */ +#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA0->ISR + (uint32_t)((u32Ch)*0x100))) = (u32Mask)) + +/** + * @brief Check Channel Status + * + * @param[in] u32Ch The selected channel + * + * @retval 0 The selected channel is idle + * @retval 1 The selected channel is busy + * + * @details Check the selected channel is busy or not. + */ +#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA0->CSR +(uint32_t)((u32Ch)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + */ +#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA0->SAR + (uint32_t)((u32Ch)*0x100))) = (u32Addr)) + +/** + * @brief Set Destination Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + */ +#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA0->DAR + (uint32_t)((u32Ch)*0x100))) = (u32Addr)) + +/** + * @brief Set Transfer Count + * + * @param[in] u32Ch The selected channel + * @param[in] u32Count Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) { \ + if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA0->CSR + (uint32_t)((u32Ch)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \ + *((__IO uint32_t *)((uint32_t)&PDMA0->BCR + (uint32_t)((u32Ch)*0x100))) = ((u32Count) << 2); \ + else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA0->CSR + (uint32_t)((u32Ch)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \ + *((__IO uint32_t *)((uint32_t)&PDMA0->BCR + (uint32_t)((u32Ch)*0x100))) = (u32Count); \ + else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA0->CSR + (uint32_t)((u32Ch)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \ + *((__IO uint32_t *)((uint32_t)&PDMA0->BCR + (uint32_t)((u32Ch)*0x100))) = ((u32Count) << 1); \ +} + +/** + * @brief Stop the channel + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + */ +#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA0->CSR + (uint32_t)((u32Ch)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk) + +void PDMA_Open(uint32_t u32Mask); +void PDMA_Close(void); +void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_Trigger(uint32_t u32Ch); +void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask); + + +/** + * @} End of PDMA Device Function Interface + */ + +/** + * @} End of Function Interface + */ + +/** + * @} End of Device_Driver + */ + + + +#endif // __PDMA_H__ diff --git a/BSP/StdDriver/inc/ps2.h b/BSP/StdDriver/inc/ps2.h new file mode 100644 index 0000000..16242de --- /dev/null +++ b/BSP/StdDriver/inc/ps2.h @@ -0,0 +1,250 @@ +/**************************************************************************//** + * @file ps2.h + * @version V3.00 + * $Revision: 16 $ + * $Date: 15/05/20 11:39a $ + * @brief NUC200 PS/2 Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __PS2_H__ +#define __PS2_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PS2_Driver PS2 Driver + @{ +*/ + + +/** @addtogroup PS2_EXPORTED_FUNCTIONS PS2 Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @brief To Set PS/2 Tx FIFO length + * + * @param[in] u32Count Tx FIFO length + * + * @return None + * + * @details Before PS/2 data transmit, program needs to set the FIFO depth. + * \hideinitializer + */ +#define PS2_SET_TX_BYTE_CNT(u32Count) (PS2->PS2CON = (PS2->PS2CON & ~PS2_PS2CON_TXFIFO_DEPTH_Msk) \ + | (((u32Count)-1) << PS2_PS2CON_TXFIFO_DEPTH_Pos)) + +/** + * @brief This function use to Get PS/2 Status + * + * @param None + * + * @return PS/2 bus status + * + * @details To get PS/2 bus status which are about Byte index, Tx/Rx status, Error status and PS/2 line status. + */ +#define PS2_GET_STATUS() (PS2->PS2STATUS) + +/** + * @brief This function is used to Clear PS/2 Status + * + * @param[in] u32Mask Clear the specified status of PS/2 module: + * 1. PS2D_PS2STATUS_FRAMERR_Msk 2. PS2D_PS2STATUS_RXOVF_Msk + * + * @return None + * + * @details To clear PS/2 bus status which are about Byte index, TX/RX status, Error status, PS/2 line status. + */ +#define PS2_CLR_STATUS(u32Mask) (PS2->PS2STATUS = (u32Mask)) + +/** + * @brief This function is used to Clear PS/2 Tx FIFO + * + * @param None + * + * @return None + * + * @details Write 1 to terminate PS/2 device to host transmission. + * + * @note Write 1 is always clear Tx FIFO, and need write 0 to STOP the clear action. + */ +__STATIC_INLINE void PS2_CLEAR_TX_FIFO(void) +{ + PS2->PS2CON |= PS2_PS2CON_CLRFIFO_Msk; + PS2->PS2CON &= ~PS2_PS2CON_CLRFIFO_Msk; +} + +/** + * @brief This function is used to Clear PS2 Rx interrupt + * + * @param None + * + * @return None + * + * @details To disable PS/2 receive interrupt occurs. + */ +#define PS2_CLR_RX_INT_FLAG() (PS2->PS2INTID = PS2_PS2INTID_RXINT_Msk) + +/** + * @brief This function is used to Clear PS/2 Tx Interrupt + * + * @param None + * + * @return None + * + * @details To disable PS/2 transmit interrupt occurs. + */ +#define PS2_CLR_TX_INT_FLAG() (PS2->PS2INTID = PS2_PS2INTID_TXINT_Msk) + +/** + * @brief This function is used to Get PS/2 Interrupt + * + * @param[in] u32IntFlag Interrupt flag of PS2_PS2INTID_TXINT_Msk, PS2_PS2INTID_RXINT_Msk + * + * @retval 1 Interrupt occurs + * @retval 0 Interrupt not occurs + * + * @details To check PS/2 bus interrupt occur from TX or RX + */ +#define PS2_GET_INT_FLAG(u32IntFlag) ((PS2->PS2INTID & (u32IntFlag))?1:0) + +/** + * @brief Disable PS2CLK and PS2DATA pins override. + * + * @param None + * + * @return None + * + * @details To disable the override control of PS2CLK and PS2DATA pins. + */ +#define PS2_DISABLE_OVERRIDE() (PS2->PS2CON &= ~PS2_PS2CON_OVERRIDE_Msk) + +/** + * @brief Enable PS2CLK and PS2DATA pins Override. + * + * @param None + * + * @return None + * + * @details TO enable the override control of PS2CLK and PS2DATA pins. + */ +#define PS2_ENABLE_OVERRIDE() (PS2->PS2CON |= PS2_PS2CON_OVERRIDE_Msk) + +/** + * @brief This function is used to Get Indicates which data byte in transmit data shift register + * + * @param None + * + * @return The indicates which data byte in transmit data shift register. + * + * @details To get a indication which a data byte in the data shift register. + */ +#define PS2_GET_TX_BYTE_INDEX() ((PS2->PS2STATUS & PS2_PS2STATUS_BYTEIDX_Msk) >> PS2_PS2STATUS_BYTEIDX_Pos) + +/** + * @brief This function is used to set PS2DATA Pin low. + * + * @param None + * + * @return None + * + * @details To control the PS2DATA pin state to low. + */ +#define PS2_SET_DATA_LOW() (PS2->PS2CON &= ~PS2_PS2CON_FPS2DAT_Msk) + +/** + * @brief This function is used to set PS2DATA Pin high + * + * @param None + * + * @return None + * + * @details To control the PS2DATA pin state to high. + */ +#define PS2_SET_DATA_HIGH() (PS2->PS2CON |= PS2_PS2CON_FPS2DAT_Msk) + +/** + * @brief This function is used to set PS2CLK Pin low. + * + * @param None + * + * @return None + * + * @details To control the PS2CLK pin state to low. + */ +#define PS2_SET_CLK_LOW() (PS2->PS2CON &= ~PS2_PS2CON_FPS2CLK_Msk) + +/** + * @brief This function is used to set PS2CLK Pin high. + * + * @param None + * + * @return None + * + * @details To control the PS2CLK pin state to high. + */ +#define PS2_SET_CLK_HIGH() (PS2->PS2CON |= PS2_PS2CON_FPS2CLK_Msk) + +/** + * @brief Disable always sends acknowledge + * + * @param None + * + * @return None + * + * @details If parity error or Stop bit is not received correctly, acknowledge will not be sent to host at 12th clock. + */ +#define PS2_DISABLE_ACK_ALWAYS() (PS2->PS2CON |= PS2_PS2CON_ACK_Msk) + +/** + * @brief Always sends acknowledge + * + * @param None + * + * @return None + * + * @details Always send acknowledge to host at 12th clock for host to device communication. + */ +#define PS2_ENABLE_ACK_ALWAYS() (PS2->PS2CON &= ~PS2_PS2CON_ACK_Msk) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PS2_Open(void); +void PS2_Close(void); +uint8_t PS2_Read(void); +int32_t PS2_Write(uint32_t *pu32Buf, uint32_t u32ByteCount); +void PS2_EnableInt(uint32_t u32Mask); +void PS2_DisableInt(uint32_t u32Mask); + + +/*@}*/ /* end of group PS2_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PS2_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__PS2_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + diff --git a/BSP/StdDriver/inc/pwm.h b/BSP/StdDriver/inc/pwm.h new file mode 100644 index 0000000..14a9e1a --- /dev/null +++ b/BSP/StdDriver/inc/pwm.h @@ -0,0 +1,237 @@ +/**************************************************************************//** + * @file pwm.h + * @version V3.00 + * $Revision: 12 $ + * $Date: 15/05/06 2:33p $ + * @brief PWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PWM_Driver PWM Driver + @{ +*/ + +/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants + @{ +*/ +#define PWM_CHANNEL_NUM (4) /*!< PWM channel number */ +#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */ +#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */ +#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */ +#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */ +#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */ +#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */ +#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type */ +#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt triggered if counter underflow */ +#define PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT01TYPE_Msk) /*!< PWM period interrupt triggered if counter match CNR */ +#define PWM_CAPTURE_INT_RISING_LATCH (PWM_CCR0_CRL_IE0_Msk) /*!< PWM capture interrupt if channel has rising transition */ +#define PWM_CAPTURE_INT_FALLING_LATCH (PWM_CCR0_CFL_IE0_Msk) /*!< PWM capture interrupt if channel has falling transition */ +/*---------------------------------------------------------------------------------------------------------*/ +/* PWM Group channel number constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PWM_CH0 0x0 /*!< PWM Group A/B channel 0 */ +#define PWM_CH1 0x1 /*!< PWM Group A/B channel 1 */ +#define PWM_CH2 0x2 /*!< PWM Group A/B channel 2 */ +#define PWM_CH3 0x3 /*!< PWM Group A/B channel 3 */ +#define PWM_CCR_MASK 0x000F000F /*!< PWM CCR0/CCR2 bit0~3 and bit16~19 mask */ + +/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */ + + +/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief Enable output inverter of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable capture input inverter for specified channel(s). + * \hideinitializer + */ +#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \ + do{ \ + int i;\ + (pwm)->PCR &= ~(PWM_PCR_CH0INV_Msk|PWM_PCR_CH1INV_Msk|PWM_PCR_CH2INV_Msk|PWM_PCR_CH3INV_Msk);\ + for(i = 0; i < 4; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (pwm)->PCR |= (PWM_PCR_CH0INV_Msk << (PWM_PCR_CH0INV_Pos * (i * 4))); \ + } \ + }while(0) + +/** + * @brief Get captured rising data of specified channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return The timer counter, 0~0xFFFF + * @details This macro is used to get captured rising data for specified channel. + */ +#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CRLR0)) + (u32ChannelNum) * 8)))) + +/** + * @brief Get captured falling data of specified channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return The timer counter, 0~0xFFFF + * @details This macro is used to get captured falling data for specified channel. + */ +#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CFLR0)) + (u32ChannelNum) * 8)))) + +/** + * @brief Set the prescaler of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF + * @return None + * @details This macro is used to set timer pre-scale for specified channel. + * @note If u32Prescaler = 0, corresponding PWM-timer will be stopped. + * @note If u32Prescaler = x (x not equal to 0), it means Clock input is divided by (x + 1) before it is fed to the corresponding PWM counter. + */ +#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \ + ((pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8))) + +/** + * @brief Set the divider of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Divider Clock divider of specified channel. Valid values are + * - \ref PWM_CLK_DIV_1 + * - \ref PWM_CLK_DIV_2 + * - \ref PWM_CLK_DIV_4 + * - \ref PWM_CLK_DIV_8 + * - \ref PWM_CLK_DIV_16 + * @return None + * @details This macro is used to set Timer clock source divider selection for specified channel. + */ +#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \ + ((pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4))) + +/** + * @brief Set the duty of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set PWM Comparator value for specified channel. + * @note This new setting will take effect on next PWM period. + */ +#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CMR0)) + (u32ChannelNum) * 12))) = (u32CMR)) + +/** + * @brief Set the period of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set timer loaded value(CNR) for specified channel.\n + * Loaded value determines the PWM period. + * @note This new setting will take effect on next PWM period. + * @note PWM counter will stop if period length set to 0. + */ +#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CNR0)) + (u32ChannelNum) * 12))) = (u32CNR)) + +/** + * @brief Set the PWM aligned type + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType PWM aligned type, valid values are: + * - \ref PWM_EDGE_ALIGNED + * - \ref PWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the PWM aligned type. + * @note PWM trigger ADC function is only supported when PWM operating at Center-aligned type. + * \hideinitializer + */ +#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 4; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (pwm)->PCR = ((pwm)->PCR & ~(PWM_PCR_PWM01TYPE_Msk << (i >> 1))) | ((u32AlignedType) << (PWM_PCR_PWM01TYPE_Pos + (i >> 1))); \ + } \ + }while(0) + + +uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32UnitTimeNsec, + uint32_t u32CaptureEdge); +uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32Frequncy, + uint32_t u32DutyCycle); +void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); + + + +/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PWM_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__PWM_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/rtc.h b/BSP/StdDriver/inc/rtc.h new file mode 100644 index 0000000..fe45650 --- /dev/null +++ b/BSP/StdDriver/inc/rtc.h @@ -0,0 +1,258 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * $Revision: 13 $ + * $Date: 15/05/08 2:51p $ + * @brief RTC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ + +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state */ +#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Access Key to enable RTC read/write accessible and kept 1024 RTC clock */ + +#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time-out Value */ + +#define RTC_YEAR2000 2000 /*!< RTC Reference for compute year data */ +#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference for frequency compensation */ + +#define RTC_CLOCK_12 0 /*!< RTC as 12-hour time scale with AM and PM indication */ +#define RTC_CLOCK_24 1 /*!< RTC as 24-hour time scale */ + +#define RTC_AM 1 /*!< RTC as AM indication */ +#define RTC_PM 2 /*!< RTC as PM indication */ + +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick is 1 second */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick is 1/2 second */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick is 1/4 second */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick is 1/8 second */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick is 1/16 second */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick is 1/32 second */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick is 1/64 second */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick is 1/128 second */ + +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday */ + +#define RTC_SNOOPER_LOW_LEVEL 0x0UL /*!< Snooper pin detected is low-level trigger */ +#define RTC_SNOOPER_HIGH_LEVEL 0x2UL /*!< Snooper pin detected is high-level trigger */ +#define RTC_SNOOPER_FALLING_EDGE 0x8UL /*!< Snooper pin detected is falling-edge trigger */ +#define RTC_SNOOPER_RISING_EDGE 0xAUL /*!< Snooper pin detected is rising-edge trigger */ +#define RTC_SNOOPER_DETECT_Msk 0xAUL /*!< Snooper pin detected mask bits */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + */ +#define RTC_IS_LEAP_YEAR() ((RTC->LIR & RTC_LIR_LIR_Msk)? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->RIIR = RTC_RIIR_AIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->RIIR = RTC_RIIR_TIF_Msk) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicate RTC alarm interrupt occurred or not. + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->RIIR & RTC_RIIR_AIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicate RTC time tick interrupt occurred or not. + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->RIIR & RTC_RIIR_TIF_Msk)? 1:0) + +/** + * @brief Clear RTC Snooper Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clear RTC snooper pin interrupt flag. + */ +#define RTC_CLEAR_SNOOPER_INT_FLAG() (RTC->RIIR = RTC_RIIR_SNOOPIF_Msk) + +/** + * @brief Get RTC Snooper Pin Flag + * + * @param None + * + * @retval 0 RTC snooper pin interrupt did not occur + * @retval 1 RTC snooper pin interrupt occurred + * + * @details This macro indicate RTC snooper pin interrupt occurred or not. + */ +#define RTC_GET_SNPPOER_INT_FLAG() ((RTC->RIIR & RTC_RIIR_SNOOPIF_Msk)? 1:0) + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +static __INLINE void RTC_WaitAccessEnable(void) +{ + /* To wait AER bit is cleared and enable AER bit (Access bit) again */ + while((RTC->AER & RTC_AER_ENF_Msk) == RTC_AER_ENF_Msk); + RTC->AER = RTC_WRITE_KEY; + + /* To wait AER bit is set and user can access the RTC registers from now on */ + while((RTC->AER & RTC_AER_ENF_Msk) == 0x0); +} + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX100); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareRegister(void); +void RTC_DisableSpareRegister(void); +void RTC_EnableSnooperDetection(uint32_t u32PinCondition); +void RTC_DisableSnooperDetection(void); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__RTC_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/sc.h b/BSP/StdDriver/inc/sc.h new file mode 100644 index 0000000..d393f28 --- /dev/null +++ b/BSP/StdDriver/inc/sc.h @@ -0,0 +1,275 @@ +/**************************************************************************//** + * @file sc.h + * @version V3.00 + * $Revision: 11 $ + * $Date: 15/05/12 2:18p $ + * @brief Smartcard (SC) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */ +#define SC_CLK_ON 1 /*!< Smartcard clock on */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off */ + +#define SC_TMR_MODE_0 (0ul << SC_TMR0_MODE_Pos) /*!IER |= (u32Mask)) + +/** + * @brief Disable smartcard interrupt. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_IER_ACON_ERR_IE_Msk + * - \ref SC_IER_RTMR_IE_Msk + * - \ref SC_IER_INIT_IE_Msk + * - \ref SC_IER_CD_IE_Msk + * - \ref SC_IER_BGT_IE_Msk + * - \ref SC_IER_TMR2_IE_Msk + * - \ref SC_IER_TMR1_IE_Msk + * - \ref SC_IER_TMR0_IE_Msk + * - \ref SC_IER_TERR_IE_Msk + * - \ref SC_IER_TBE_IE_Msk + * - \ref SC_IER_RDA_IE_Msk + * @return None + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of VCC pin, valid parameters are: + * \ref SC_PIN_STATE_HIGH :Smartcard pin status high. + * \ref SC_PIN_STATE_LOW :Smartcard pin status low. + * @return None + * @details User can set POW_EN (SC_PINCSR[0]) and POW_INV (SC_PINCSR[11])to decide SC_PWR pin is in high or low level. + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCSR & SC_PINCSR_SYNC_Msk);\ + if((u32State))\ + (sc)->PINCSR |= SC_PINCSR_POW_EN_Msk;\ + else\ + (sc)->PINCSR &= ~SC_PINCSR_POW_EN_Msk;\ + }while(0) + + +/** + * @brief Set CLK output status. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are: + * \ref SC_CLK_ON :Smartcard clock on. + * \ref SC_CLK_OFF :Smartcard clock off. + * @return None + * @details User can set CLK_KEEP (SC_PINCSR[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCSR & SC_PINCSR_SYNC_Msk);\ + if((u32OnOff))\ + (sc)->PINCSR |= SC_PINCSR_CLK_KEEP_Msk;\ + else\ + (sc)->PINCSR &= ~(SC_PINCSR_CLK_KEEP_Msk);\ + }while(0) + +/** + * @brief Set I/O pin state. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of I/O pin, valid parameters are: + * \ref SC_PIN_STATE_HIGH :Smartcard pin status high. + * \ref SC_PIN_STATE_LOW :Smartcard pin status low. + * @return None + * @details User can set SC_DATA_O(SC_PINCSR[9]) to decide SC_DATA_O pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCSR & SC_PINCSR_SYNC_Msk);\ + if((u32State))\ + (sc)->PINCSR |= SC_PINCSR_SC_DATA_O_Msk;\ + else\ + (sc)->PINCSR &= ~SC_PINCSR_SC_DATA_O_Msk;\ + }while(0) + +/** + * @brief Set RST pin state. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of RST pin, valid parameters are: + * \ref SC_PIN_STATE_HIGH :Smartcard pin status high. + * \ref SC_PIN_STATE_LOW :Smartcard pin status low. + * @return None + * @details User can set SC_RST(SC_PINCSR[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCSR & SC_PINCSR_SYNC_Msk);\ + if((u32State))\ + (sc)->PINCSR |= SC_PINCSR_SC_RST_Msk;\ + else\ + (sc)->PINCSR &= ~SC_PINCSR_SC_RST_Msk;\ + }while(0) + +/** + * @brief Read one byte from smartcard module receive FIFO. + * @param[in] sc The pointer of smartcard module. + * @return One byte read from receive FIFO. + * @details By reading RBR register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->RBR)) + +/** + * @brief Write one byte to smartcard module transmit FIFO. + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * @return None + * @details By writing data to THR register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->THR = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_SLEN_Msk) | ((u32Len) == 1 ? SC_CTL_SLEN_Msk : 0)) + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry. + * @return None + * @details This macro enable/disable transmitter retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk); + if((u32Count) == 0) // disable Tx error retry + { + (sc)->CTL &= ~(SC_CTL_TX_ERETRY_Msk | SC_CTL_TX_ERETRY_EN_Msk); + } + else + { + (sc)->CTL = ((sc)->CTL & ~SC_CTL_TX_ERETRY_Msk) | (((u32Count) - 1) << SC_CTL_TX_ERETRY_Pos) | SC_CTL_TX_ERETRY_EN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry. + * @return None + * @details This macro enable/disable receiver retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk); + if((u32Count) == 0) // disable Rx error retry + { + (sc)->CTL &= ~(SC_CTL_RX_ERETRY_Msk | SC_CTL_RX_ERETRY_EN_Msk); + } + else + { + (sc)->CTL = ((sc)->CTL & ~SC_CTL_RX_ERETRY_Msk) | (((u32Count) - 1) << SC_CTL_RX_ERETRY_Pos) | SC_CTL_RX_ERETRY_EN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__SC_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/spi.h b/BSP/StdDriver/inc/spi.h new file mode 100644 index 0000000..ef87081 --- /dev/null +++ b/BSP/StdDriver/inc/spi.h @@ -0,0 +1,392 @@ +/**************************************************************************//** + * @file spi.h + * @version V3.0 + * $Revision: 15 $ + * $Date: 15/05/28 9:45p $ + * @brief SPI Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */ +#define SPI_MODE_1 (SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */ +#define SPI_MODE_2 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */ +#define SPI_MODE_3 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */ + +#define SPI_SLAVE (SPI_CNTRL_SLAVE_Msk) /*!< Set as slave */ +#define SPI_MASTER (0x0) /*!< Set as master */ + +#define SPI_SS0 (1<CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk) + +/** + * @brief Clear the Slave 3-wire mode start interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Write 1 to SLV_START_INTSTS bit of SPI_STATUS register to clear the Slave 3-wire mode start interrupt flag. + */ +#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk) + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Write 1 to IF bit of SPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_IF_Msk) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TWOB bit of SPI_CNTRL register to disable 2-bit Transfer mode. + */ +#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CNTRL &= ~SPI_CNTRL_TWOB_Msk) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear NOSLVSEL bit of SPI_CNTRL2 register to disable Slave 3-wire mode. + */ +#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk) + +/** + * @brief Disable Dual I/O mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear DUAL_IO_EN bit of SPI_CNTRL2 register to disable Dual I/O mode. + */ +#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_DUAL_IO_EN_Msk) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TWOB bit of SPI_CNTRL register to enable 2-bit Transfer mode. + */ +#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CNTRL |= SPI_CNTRL_TWOB_Msk) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set NOSLVSEL bit of SPI_CNTRL2 register to enable Slave 3-wire mode. + * Only available in Slave mode. + */ +#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk) + +/** + * @brief Enable Dual input mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear DUAL_IO_DIR bit and set DUAL_IO_EN bit of SPI_CNTRL2 register to enable Dual input mode. + */ +#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CNTRL2 = ((spi)->CNTRL2 & (~SPI_CNTRL2_DUAL_IO_DIR_Msk)) | SPI_CNTRL2_DUAL_IO_EN_Msk) + +/** + * @brief Enable Dual output mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set DUAL_IO_DIR bit and DUAL_IO_EN bit of SPI_CNTRL2 register to enable Dual output mode. + */ +#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CNTRL2 |= (SPI_CNTRL2_DUAL_IO_EN_Msk | SPI_CNTRL2_DUAL_IO_DIR_Msk)) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RX_DMA_GO bit of SPI_DMA register to enable RX PDMA transfer function. + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->DMA |= SPI_DMA_RX_DMA_GO_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TX_DMA_GO bit of SPI_DMA register to enable TX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->DMA |= SPI_DMA_TX_DMA_GO_Msk) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TX_DMA_GO bit and RX_DMA_GO bit of SPI_DMA register to enable TX and RX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->DMA |= (SPI_DMA_TX_DMA_GO_Msk | SPI_DMA_RX_DMA_GO_Msk)) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RX_FIFO_COUNT (SPI_STATUS[15:12]) to get the count of available data in RX FIFO. + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RX_EMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk)>>SPI_STATUS_RX_EMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TX_EMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk)>>SPI_STATUS_TX_EMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TX_FULL bit of SPI_STATUS register to get the TX FIFO full flag. + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_FULL_Msk)>>SPI_STATUS_TX_FULL_Pos) + +/** + * @brief Get the datum read from RX0 register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX0 register. + * @details Read SPI_RX0 register to get the received datum. + */ +#define SPI_READ_RX0(spi) ((spi)->RX[0]) + +/** + * @brief Get the datum read from RX1 register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX1 register. + * @details Read SPI_RX1 register to get the received datum. + */ +#define SPI_READ_RX1(spi) ((spi)->RX[1]) + +/** + * @brief Write datum to TX0 register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to TX0 register. + */ +#define SPI_WRITE_TX0(spi, u32TxData) ((spi)->TX[0] = (u32TxData)) + +/** + * @brief Write datum to TX1 register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to TX1 register. + */ +#define SPI_WRITE_TX1(spi, u32TxData) ((spi)->TX[1] = (u32TxData)) + +/** + * @brief Set SPIn_SS0, SPIn_SS1 pin to high or low state. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] ss0 0 = Set SPIn_SS0 to low. 1 = Set SPIn_SS0 to high. + * @param[in] ss1 0 = Set SPIn_SS1 to low. 1 = Set SPIn_SS1 to high. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0/SPIn_SS1 pin to specified high/low state. + * Only available in Master mode. + */ +#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1)) + +/** + * @brief Set SPIn_SS0 pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode. + */ +#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0))) + +/** + * @brief Set SPIn_SS1 pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode. + */ +#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1))) + +/** + * @brief Set SPIn_SS0 pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode. + */ +#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0) + +/** + * @brief Set SPIn_SS1 pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode. + */ +#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set REORDER bit of SPI_CNTRL register to enable Byte Reorder function. + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CNTRL |= SPI_CNTRL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit of SPI_CNTRL register to disable Byte Reorder function. + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * Only available in Master mode. + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | ((u32SuspCycle) << SPI_CNTRL_SP_CYCLE_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CNTRL register to set the SPI transfer sequence with LSB first. + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CNTRL |= SPI_CNTRL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CNTRL register to set the SPI transfer sequence with MSB first. + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of transfer data. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_TX_BIT_LEN_Msk) | (((u32Width)&0x1F) << SPI_CNTRL_TX_BIT_LEN_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + */ +#define SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk)>>SPI_CNTRL_GO_BUSY_Pos ) + +/** + * @brief Set the GO_BUSY bit to trigger SPI transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details If FIFO mode is disabled, user can use this macro to trigger the data transfer after all configuration is ready. + * If FIFO mode is enabled, user should not use this macro to trigger the data transfer. SPI controller will trigger the data transfer + * automatically after user write to SPI_TX0/1 register. + */ +#define SPI_TRIGGER(spi) ((spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void SPI_DisableFIFO(SPI_T *spi); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + + + +/** + * @} End of SPI Device Function Interface + */ + +/** + * @} End of Function Interface + */ + +/** + * @} End of Device_Driver + */ + + +#endif + diff --git a/BSP/StdDriver/inc/sys.h b/BSP/StdDriver/inc/sys.h new file mode 100644 index 0000000..974f539 --- /dev/null +++ b/BSP/StdDriver/inc/sys.h @@ -0,0 +1,1462 @@ +/**************************************************************************//** + * @file sys.h + * @version V3.00 + * $Revision: 30 $ + * $Date: 15/05/20 3:25p $ + * @brief SYS Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __SYS_H__ +#define __SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_RST ((0x0<<24) | SYS_IPRSTC1_PDMA_RST_Pos ) /*!< PDMA reset is one of the SYS_ResetModule parameter */ +#define GPIO_RST ((0x4<<24) | SYS_IPRSTC2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4<<24) | SYS_IPRSTC2_TMR0_RST_Pos ) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4<<24) | SYS_IPRSTC2_TMR1_RST_Pos ) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4<<24) | SYS_IPRSTC2_TMR2_RST_Pos ) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4<<24) | SYS_IPRSTC2_TMR3_RST_Pos ) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4<<24) | SYS_IPRSTC2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4<<24) | SYS_IPRSTC2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4<<24) | SYS_IPRSTC2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI1_RST ((0x4<<24) | SYS_IPRSTC2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ +#define SPI2_RST ((0x4<<24) | SYS_IPRSTC2_SPI2_RST_Pos ) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ +#define SPI3_RST ((0x4<<24) | SYS_IPRSTC2_SPI3_RST_Pos ) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4<<24) | SYS_IPRSTC2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4<<24) | SYS_IPRSTC2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART2_RST ((0x4<<24) | SYS_IPRSTC2_UART2_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define PWM03_RST ((0x4<<24) | SYS_IPRSTC2_PWM03_RST_Pos ) /*!< PWM03 reset is one of the SYS_ResetModule parameter */ +#define PWM47_RST ((0x4<<24) | SYS_IPRSTC2_PWM47_RST_Pos ) /*!< PWM47 reset is one of the SYS_ResetModule parameter */ +#define ACMP_RST ((0x4<<24) | SYS_IPRSTC2_ACMP_RST_Pos ) /*!< ACMP reset is one of the SYS_ResetModule parameter */ +#define PS2_RST ((0x4<<24) | SYS_IPRSTC2_PS2_RST_Pos ) /*!< PS2 reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4<<24) | SYS_IPRSTC2_USBD_RST_Pos ) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define ADC_RST ((0x4<<24) | SYS_IPRSTC2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */ +#define I2S_RST ((0x4<<24) | SYS_IPRSTC2_I2S_RST_Pos ) /*!< I2S reset is one of the SYS_ResetModule parameter */ +#define SC0_RST ((0x8<<24) | SYS_IPRSTC3_SC0_RST_Pos ) /*!< SC0 reset is one of the SYS_ResetModule parameter */ +#define SC1_RST ((0x8<<24) | SYS_IPRSTC3_SC1_RST_Pos ) /*!< SC1 reset is one of the SYS_ResetModule parameter */ +#define SC2_RST ((0x8<<24) | SYS_IPRSTC3_SC2_RST_Pos ) /*!< SC2 reset is one of the SYS_ResetModule parameter */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCR_BOD_RST_EN (1UL<GPA_MFP = SYS_GPA_MFP_PA0_ADC0 | SYS_GPA_MFP_PA1_ADC1; + SYS->ALT_MFP1 = SYS_ALT_MFP1_PA0_ADC0| SYS_ALT_MFP1_PA1_ADC1; +*/ + +//PA.0 +#define SYS_GPA_MFP_PA0_GPIO 0x00000000UL /*!< GPA_MFP PA.0 setting for GPIO */ +#define SYS_ALT_MFP_PA0_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.0 */ +#define SYS_ALT_MFP1_PA0_GPIO 0x00000000UL /*!< ALT_MFP1 PA.0 setting for GPIO */ +#define SYS_ALT_MFP2_PA0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.0 */ + +#define SYS_GPA_MFP_PA0_ADC0 (1UL<<0) /*!< GPA_MFP PA.0 setting for ADC0 */ +#define SYS_ALT_MFP_PA0_ADC0 (uint32_t)NULL /*!< No ALT_MFP setting for PA.0 */ +#define SYS_ALT_MFP1_PA0_ADC0 0x00000000UL /*!< ALT_MFP1 PA.0 setting for ADC0 */ +#define SYS_ALT_MFP2_PA0_ADC0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.0 */ + +#define SYS_GPA_MFP_PA0_SC0_PWR (1UL<<0) /*!< GPA_MFP PA.0 setting for SC0_PWR */ +#define SYS_ALT_MFP_PA0_SC0_PWR (uint32_t)NULL /*!< No ALT_MFP setting for PA.0 */ +#define SYS_ALT_MFP1_PA0_SC0_PWR (1UL<<2) /*!< ALT_MFP1 PA.0 setting for SC0_PWR */ +#define SYS_ALT_MFP2_PA0_SC0_PWR (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.0 */ + +#define SYS_GPA_MFP_PA0_Msk (1UL<<0) /*!< GPA_MFP PA.0 mask */ +#define SYS_ALT_MFP1_PA0_Msk (1UL<<2) /*!< ALT_MFP1 PA.0 mask */ + +//PA.1 +#define SYS_GPA_MFP_PA1_GPIO 0x00000000UL /*!< GPA_MFP PA.1 setting for GPIO */ +#define SYS_ALT_MFP_PA1_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.1 */ +#define SYS_ALT_MFP1_PA1_GPIO 0x00000000UL /*!< ALT_MFP1 PA.1 setting for GPIO */ +#define SYS_ALT_MFP2_PA1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.1 */ + +#define SYS_GPA_MFP_PA1_ADC1 (1UL<<1) /*!< GPA_MFP PA.1 setting for ADC1 */ +#define SYS_ALT_MFP_PA1_ADC1 (uint32_t)NULL /*!< No ALT_MFP setting for PA.1 */ +#define SYS_ALT_MFP1_PA1_ADC1 0x00000000UL /*!< ALT_MFP1 PA.1 setting for ADC1 */ +#define SYS_ALT_MFP2_PA1_ADC1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.1 */ + +#define SYS_GPA_MFP_PA1_SC0_RST (1UL<<1) /*!< GPA_MFP PA.1 setting for SC0_RST */ +#define SYS_ALT_MFP_PA1_SC0_RST (uint32_t)NULL /*!< No ALT_MFP setting for PA.1 */ +#define SYS_ALT_MFP1_PA1_SC0_RST (1UL<<3) /*!< ALT_MFP1 PA.1 setting for SC0_RST */ +#define SYS_ALT_MFP2_PA1_SC0_RST (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.1 */ + +#define SYS_GPA_MFP_PA1_Msk (1UL<<1) /*!< GPA_MFP PA.1 mask */ +#define SYS_ALT_MFP1_PA1_Msk (1UL<<3) /*!< ALT_MFP1 PA.1 mask */ + +//PA.2 +#define SYS_GPA_MFP_PA2_GPIO 0x00000000UL /*!< GPA_MFP PA.2 setting for GPIO */ +#define SYS_ALT_MFP_PA2_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.2 */ +#define SYS_ALT_MFP1_PA2_GPIO 0x00000000UL /*!< ALT_MFP1 PA.2 setting for GPIO */ +#define SYS_ALT_MFP2_PA2_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.2 */ + +#define SYS_GPA_MFP_PA2_ADC2 (1UL<<2) /*!< GPA_MFP PA.2 setting for ADC2 */ +#define SYS_ALT_MFP_PA2_ADC2 (uint32_t)NULL /*!< Mp ALT_MFP setting for PA.2 */ +#define SYS_ALT_MFP1_PA2_ADC2 0x00000000UL /*!< ALT_MFP1 PA.2 setting for ADC2 */ +#define SYS_ALT_MFP2_PA2_ADC2 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.2 */ + +#define SYS_GPA_MFP_PA2_SC0_CLK (1UL<<2) /*!< GPA_MFP PA.2 setting for SC0_CLK */ +#define SYS_ALT_MFP_PA2_SC0_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PA.2 */ +#define SYS_ALT_MFP1_PA2_SC0_CLK (1UL<<0) /*!< ALT_MFP1 PA.2 setting for SC0_CLK */ +#define SYS_ALT_MFP2_PA2_SC0_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.2 */ + +#define SYS_GPA_MFP_PA2_Msk (1UL<<2) /*!< GPA_MFP PA.2 mask */ +#define SYS_ALT_MFP1_PA2_Msk (1UL<<0) /*!< ALT_MFP1 PA.2 mask */ + +//PA.3 +#define SYS_GPA_MFP_PA3_GPIO 0x00000000UL /*!< GPA_MFP PA.3 setting for GPIO */ +#define SYS_ALT_MFP_PA3_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.3 */ +#define SYS_ALT_MFP1_PA3_GPIO 0x00000000UL /*!< ALT_MFP1 PA.3 setting for GPIO */ +#define SYS_ALT_MFP2_PA3_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.3 */ + +#define SYS_GPA_MFP_PA3_ADC3 (1UL<<3) /*!< GPA_MFP PA.3 setting for ADC3 */ +#define SYS_ALT_MFP_PA3_ADC3 (uint32_t)NULL /*!< No ALT_MFP setting for PA.3 */ +#define SYS_ALT_MFP1_PA3_ADC3 0x00000000UL /*!< ALT_MFP1 PA.3 setting for ADC3 */ +#define SYS_ALT_MFP2_PA3_ADC3 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.3 */ + +#define SYS_GPA_MFP_PA3_SC0_DAT (1UL<<3) /*!< GPA_MFP PA.3 setting for SC0_DAT */ +#define SYS_ALT_MFP_PA3_SC0_DAT (uint32_t)NULL /*!< No ALT_MFP setting for PA.3 */ +#define SYS_ALT_MFP1_PA3_SC0_DAT (1UL<<1) /*!< ALT_MFP1 PA.3 setting for SC0_DAT */ +#define SYS_ALT_MFP2_PA3_SC0_DAT (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.3 */ + +#define SYS_GPA_MFP_PA3_Msk (1UL<<3) /*!< GPA_MFP PA.3 mask */ +#define SYS_ALT_MFP1_PA3_Msk (1UL<<1) /*!< ALT_MFP1 PA.3 mask */ + +//PA.4 +#define SYS_GPA_MFP_PA4_GPIO 0x00000000UL /*!< GPA_MFP PA.4 setting for GPIO */ +#define SYS_ALT_MFP_PA4_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.4 */ +#define SYS_ALT_MFP1_PA4_GPIO 0x00000000UL /*!< ALT_MFP1 PA.4 setting for GPIO */ +#define SYS_ALT_MFP2_PA4_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.4 */ + +#define SYS_GPA_MFP_PA4_ADC4 (1UL<<4) /*!< GPA_MFP PA.4 setting for ADC4 */ +#define SYS_ALT_MFP_PA4_ADC4 (uint32_t)NULL /*!< No ALT_MFP setting for PA.4 */ +#define SYS_ALT_MFP1_PA4_ADC4 0x00000000UL /*!< ALT_MFP1 PA.4 setting for ADC4 */ +#define SYS_ALT_MFP2_PA4_ADC4 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.4 */ + +#define SYS_GPA_MFP_PA4_SC1_PWR (1UL<<4) /*!< GPA_MFP PA.4 setting for SC1_PWR */ +#define SYS_ALT_MFP_PA4_SC1_PWR (uint32_t)NULL /*!< No ALT_MFP setting for PA.4 */ +#define SYS_ALT_MFP1_PA4_SC1_PWR (1UL<<7) /*!< ALT_MFP1 PA.4 setting for SC1_PWR */ +#define SYS_ALT_MFP2_PA4_SC1_PWR (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.4 */ + +#define SYS_GPA_MFP_PA4_Msk (1UL<<4) /*!< GPA_MFP PA.4 mask */ +#define SYS_ALT_MFP1_PA4_Msk (1UL<<7) /*!< ALT_MFP1 PA.4 mask */ + +//PA.5 +#define SYS_GPA_MFP_PA5_GPIO 0x00000000UL /*!< GPA_MFP PA.5 setting for GPIO */ +#define SYS_ALT_MFP_PA5_GPIO (uint32_t) /*!< No ALT_MFP setting for PA.5 */ +#define SYS_ALT_MFP1_PA5_GPIO 0x00000000UL /*!< ALT_MFP1 PA.5 setting for GPIO */ +#define SYS_ALT_MFP2_PA5_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.5 */ + +#define SYS_GPA_MFP_PA5_ADC5 (1UL<<5) /*!< GPA_MFP PA.5 setting for ADC5 */ +#define SYS_ALT_MFP_PA5_ADC5 (uint32_t)NULL /*!< No ALT_MFP setting for PA.5 */ +#define SYS_ALT_MFP1_PA5_ADC5 0x00000000UL /*!< ALT_MFP1 PA.5 setting for ADC5 */ +#define SYS_ALT_MFP2_PA5_ADC5 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.5 */ + +#define SYS_GPA_MFP_PA5_SC1_RST (1UL<<5) /*!< GPA_MFP PA.5 setting for SC1_RST */ +#define SYS_ALT_MFP_PA5_SC1_RST (uint32_t)NULL /*!< No ALT_MFP setting for PA.5 */ +#define SYS_ALT_MFP1_PA5_SC1_RST (1UL<<8) /*!< ALT_MFP1 PA.5 setting for SC1_RST */ +#define SYS_ALT_MFP2_PA5_SC1_RST (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.5 */ + +#define SYS_GPA_MFP_PA5_Msk (1UL<<5) /*!< GPA_MFP PA.5 mask */ +#define SYS_ALT_MFP1_PA5_Msk (1UL<<8) /*!< ALT_MFP1 PA.5 mask */ + +//PA.6 +#define SYS_GPA_MFP_PA6_GPIO 0x00000000UL /*!< GPA_MFP PA.6 setting for GPIO */ +#define SYS_ALT_MFP_PA6_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.6 */ +#define SYS_ALT_MFP1_PA6_GPIO 0x00000000UL /*!< ALT_MFP1 PA.6 setting for GPIO */ +#define SYS_ALT_MFP2_PA6_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.6 */ + +#define SYS_GPA_MFP_PA6_ADC6 (1UL<<6) /*!< GPA_MFP PA.6 setting for ADC6 */ +#define SYS_ALT_MFP_PA6_ADC6 (uint32_t)NULL /*!< No ALT_MFP setting for PA.6 */ +#define SYS_ALT_MFP1_PA6_ADC6 0x00000000UL /*!< ALT_MFP1 PA.6 setting for ADC6 */ +#define SYS_ALT_MFP2_PA6_ADC6 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.6 */ + +#define SYS_GPA_MFP_PA6_SC1_CLK (1UL<<6) /*!< GPA_MFP PA.6 setting for SC1_CLK */ +#define SYS_ALT_MFP_PA6_SC1_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PA.6 */ +#define SYS_ALT_MFP1_PA6_SC1_CLK (1UL<<5) /*!< ALT_MFP1 PA.6 setting for SC1_CLK */ +#define SYS_ALT_MFP2_PA6_SC1_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.6 */ + +#define SYS_GPA_MFP_PA6_Msk (1UL<<6) /*!< GPA_MFP PA.6 mask */ +#define SYS_ALT_MFP1_PA6_Msk (1UL<<5) /*!< ALT_MFP1 PA.6 mask */ + +//PA.7 +#define SYS_GPA_MFP_PA7_GPIO 0x00000000UL /*!< GPA_MFP PA.7 setting for GPIO */ +#define SYS_ALT_MFP_PA7_GPIO 0x00000000UL /*!< ALT_MFP PA.7 setting for GPIO */ +#define SYS_ALT_MFP1_PA7_GPIO 0x00000000UL /*!< ALT_MFP1 PA.7 setting for GPIO */ +#define SYS_ALT_MFP2_PA7_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.7 */ + +#define SYS_GPA_MFP_PA7_ADC7 (1UL<<7) /*!< GPA_MFP PA.7 setting for ADC7 */ +#define SYS_ALT_MFP_PA7_ADC7 0x00000000UL /*!< ALT_MFP PA.7 setting for ADC7 */ +#define SYS_ALT_MFP1_PA7_ADC7 0x00000000UL /*!< ALT_MFP1 PA.7 setting for ADC7 */ +#define SYS_ALT_MFP2_PA7_ADC7 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.7 */ + +#define SYS_GPA_MFP_PA7_SPI2_SS1 (1UL<<7) /*!< GPA_MFP PA.7 setting for SPI2_SS1 */ +#define SYS_ALT_MFP_PA7_SPI2_SS1 (1UL<<2) /*!< ALT_MFP PA.7 setting for SPI2_SS1 */ +#define SYS_ALT_MFP1_PA7_SPI2_SS1 0x00000000UL /*!< ALT_MFP1 PA.7 setting for SPI2_SS1 */ +#define SYS_ALT_MFP2_PA7_SPI2_SS1 (uint32_t)LL /*!< No ALT_MFP2 setting for PA.7 */ + +#define SYS_GPA_MFP_PA7_SC1_DAT (1UL<<7) /*!< GPA_MFP PA.7 setting for SC1_DAT */ +#define SYS_ALT_MFP_PA7_SC1_DAT 0x00000000UL /*!< ALT_MFP PA.7 setting for SC1_DAT */ +#define SYS_ALT_MFP1_PA7_SC1_DAT (1UL<<6) /*!< ALT_MFP1 PA.7 setting for SC1_DAT */ +#define SYS_ALT_MFP2_PA7_SC1_DAT (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.7 */ + +#define SYS_GPA_MFP_PA7_Msk (1UL<<7) /*!< GPA_MFP PA.7 mask */ +#define SYS_ALT_MFP_PA7_Msk (1UL<<2) /*!< ALT_MFP PA.7 mask */ +#define SYS_ALT_MFP1_PA7_Msk (1UL<<6) /*!< ALT_MFP1 PA.7 mask */ + +//PA.8 +#define SYS_GPA_MFP_PA8_GPIO 0x00000000UL /*!< GPA_MFP PA.8 setting for GPIO */ +#define SYS_ALT_MFP_PA8_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.8 */ +#define SYS_ALT_MFP1_PA8_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.8 */ +#define SYS_ALT_MFP2_PA8_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.8 */ + +#define SYS_GPA_MFP_PA8_I2C0_SDA (1UL<<8) /*!< GPA_MFP PA.8 setting for I2C0_SDA */ +#define SYS_ALT_MFP_PA8_I2C0_SDA (uint32_t)NULL /*!< No ALT_MFP setting for PA.8 */ +#define SYS_ALT_MFP1_PA8_I2C0_SDA (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.8 */ +#define SYS_ALT_MFP2_PA8_I2C0_SDA (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.8 */ + +#define SYS_GPA_MFP_PA8_Msk (1UL<<8) /*!< GPA_MFP PA.8 mask */ + +//PA.9 +#define SYS_GPA_MFP_PA9_GPIO 0x00000000UL /*!< GPA_MFP PA.9 setting for GPIO */ +#define SYS_ALT_MFP_PA9_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.9 */ +#define SYS_ALT_MFP1_PA9_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.9 */ +#define SYS_ALT_MFP2_PA9_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.9 */ + +#define SYS_GPA_MFP_PA9_I2C0_SCL (1UL<<9) /*!< GPA_MFP PA.9 setting for I2C0_SCL */ +#define SYS_ALT_MFP_PA9_I2C0_SCL (uint32_t)NULL /*!< No ALT_MFP setting for PA.9 */ +#define SYS_ALT_MFP1_PA9_I2C0_SCL (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.9 */ +#define SYS_ALT_MFP2_PA9_I2C0_SCL (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.9 */ + +#define SYS_GPA_MFP_PA9_Msk (1UL<<9) /*!< GPA_MFP PA.9 mask */ + +//PA.10 +#define SYS_GPA_MFP_PA10_GPIO 0x00000000UL /*!< GPA_MFP PA.10 setting for GPIO */ +#define SYS_ALT_MFP_PA10_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.10 */ +#define SYS_ALT_MFP1_PA10_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.10 */ +#define SYS_ALT_MFP2_PA10_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.10 */ + +#define SYS_GPA_MFP_PA10_I2C1_SDA (1UL<<10) /*!< GPA_MFP PA.10 setting for I2C1_SDA */ +#define SYS_ALT_MFP_PA10_I2C1_SDA (uint32_t)NULL /*!< No ALT_MFP setting for PA.10 */ +#define SYS_ALT_MFP1_PA10_I2C1_SDA (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.10 */ +#define SYS_ALT_MFP2_PA10_I2C1_SDA (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.10 */ + +#define SYS_GPA_MFP_PA10_Msk (1UL<<10) /*!< GPA_MFP PA.10 mask */ + +//PA.11 +#define SYS_GPA_MFP_PA11_GPIO 0x00000000UL /*!< GPA_MFP PA.11 setting for GPIO */ +#define SYS_ALT_MFP_PA11_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.11 */ +#define SYS_ALT_MFP1_PA11_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.11 */ +#define SYS_ALT_MFP2_PA11_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.11 */ + +#define SYS_GPA_MFP_PA11_I2C1_SCL (1UL<<11) /*!< GPA_MFP PA.11 setting for I2C1_SCL */ +#define SYS_ALT_MFP_PA11_I2C1_SCL (uint32_t)NULL /*!< No ALT_MFP setting for PA.11 */ +#define SYS_ALT_MFP1_PA11_I2C1_SCL (uint32_t)NULL /*!< No ALT_MFP1 setting for PA.11 */ +#define SYS_ALT_MFP2_PA11_I2C1_SCL (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.11 */ + +#define SYS_GPA_MFP_PA11_Msk (1UL<<11) /*!< GPA_MFP PA.11 mask */ + +//PA.12 +#define SYS_GPA_MFP_PA12_GPIO 0x00000000UL /*!< GPA_MFP PA.12 setting for GPIO */ +#define SYS_ALT_MFP_PA12_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.12 */ +#define SYS_ALT_MFP1_PA12_GPIO 0x00000000UL /*!< ALT_MFP1 PA.12 setting for GPIO */ +#define SYS_ALT_MFP2_PA12_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.12 */ + +#define SYS_GPA_MFP_PA12_PWM0 (1UL<<12) /*!< GPA_MFP PA.12 setting for PWM0 */ +#define SYS_ALT_MFP_PA12_PWM0 (uint32_t)NULL /*!< No ALT_MFP setting for PA.12 */ +#define SYS_ALT_MFP1_PA12_PWM0 0x00000000UL /*!< ALT_MFP1 PA.12 setting for PWM0 */ +#define SYS_ALT_MFP2_PA12_PWM0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.12 */ + +#define SYS_GPA_MFP_PA12_SC2_DAT (1UL<<12) /*!< GPA_MFP PA.12 setting for SC2_DAT */ +#define SYS_ALT_MFP_PA12_SC2_DAT (uint32_t)NULL /*!< No ALT_MFP setting for PA.12 */ +#define SYS_ALT_MFP1_PA12_SC2_DAT (1UL<<11) /*!< ALT_MFP1 PA.12 setting for SC2_DAT */ +#define SYS_ALT_MFP2_PA12_SC2_DAT (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.12 */ + +#define SYS_GPA_MFP_PA12_Msk (1UL<<12) /*!< GPA_MFP PA.12 mask */ +#define SYS_ALT_MFP1_PA12_Msk (1UL<<11) /*!< ALT_MFP1 PA.12 mask */ + +//PA.13 +#define SYS_GPA_MFP_PA13_GPIO 0x00000000UL /*!< GPA_MFP PA.13 setting for GPIO */ +#define SYS_ALT_MFP_PA13_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.13 */ +#define SYS_ALT_MFP1_PA13_GPIO 0x00000000UL /*!< ALT_MFP1 PA.13 setting for GPIO */ +#define SYS_ALT_MFP2_PA13_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.13 */ + +#define SYS_GPA_MFP_PA13_PWM1 (1UL<<13) /*!< GPA_MFP PA.13 setting for PWM1 */ +#define SYS_ALT_MFP_PA13_PWM1 (uint32_t)NULL /*!< No ALT_MFP setting for PA.13 */ +#define SYS_ALT_MFP1_PA13_PWM1 0x00000000UL /*!< ALT_MFP1 PA.13 setting for PWM1 */ +#define SYS_ALT_MFP2_PA13_PWM1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.13 */ + +#define SYS_GPA_MFP_PA13_SC2_CLK (1UL<<13) /*!< GPA_MFP PA.13 setting for SC2_CLK */ +#define SYS_ALT_MFP_PA13_SC2_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PA.13 */ +#define SYS_ALT_MFP1_PA13_SC2_CLK (1UL<<10) /*!< ALT_MFP1 PA.13 setting for SC2_CLK */ +#define SYS_ALT_MFP2_PA13_SC2_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.13 */ + +#define SYS_GPA_MFP_PA13_Msk (1UL<<13) /*!< GPA_MFP PA.13 mask */ +#define SYS_ALT_MFP1_PA13_Msk (1UL<<10) /*!< ALT_MFP1 PA.13 mask */ + +//PA.14 +#define SYS_GPA_MFP_PA14_GPIO 0x00000000UL /*!< GPA_MFP PA.14 setting for GPIO */ +#define SYS_ALT_MFP_PA14_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PA.14 */ +#define SYS_ALT_MFP1_PA14_GPIO 0x00000000UL /*!< ALT_MFP1 PA.14 setting for GPIO */ +#define SYS_ALT_MFP2_PA14_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.14 */ + +#define SYS_GPA_MFP_PA14_PWM2 (1UL<<14) /*!< GPA_MFP PA.14 setting for PWM2 */ +#define SYS_ALT_MFP_PA14_PWM2 (uint32_t) /*!< No ALT_MFP setting for PA.14 */ +#define SYS_ALT_MFP1_PA14_PWM2 0x00000000UL /*!< ALT_MFP1 PA.14 setting for PWM2 */ +#define SYS_ALT_MFP2_PA14_PWM2 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.14 */ + +#define SYS_GPA_MFP_PA14_SC2_RST (1UL<<14) /*!< GPA_MFP PA.14 setting for SC2_RST */ +#define SYS_ALT_MFP_PA14_SC2_RST (uint32_t)NULL /*!< No ALT_MFP setting for PA.14 */ +#define SYS_ALT_MFP1_PA14_SC2_RST (1UL<<13) /*!< ALT_MFP1 PA.14 setting for SC2_RST */ +#define SYS_ALT_MFP2_PA14_SC2_RST (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.14 */ + +#define SYS_GPA_MFP_PA14_Msk (1UL<<14) /*!< GPA_MFP PA.14 mask */ +#define SYS_ALT_MFP1_PA14_Msk (1UL<<13) /*!< ALT_MFP1 PA.14 mask */ + +//PA.15 +#define SYS_GPA_MFP_PA15_GPIO 0x00000000UL /*!< GPA_MFP PA.15 setting for GPIO */ +#define SYS_ALT_MFP_PA15_GPIO 0x00000000UL /*!< ALT_MFP PA.15 setting for GPIO */ +#define SYS_ALT_MFP1_PA15_GPIO 0x00000000UL /*!< ALT_MFP1 PA.15 setting for GPIO */ +#define SYS_ALT_MFP2_PA15_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.15 */ + +#define SYS_GPA_MFP_PA15_PWM3 (1UL<<15) /*!< GPA_MFP PA.15 setting for PWM3 */ +#define SYS_ALT_MFP_PA15_PWM3 0x00000000UL /*!< ALT_MFP PA.15 setting for PWM3 */ +#define SYS_ALT_MFP1_PA15_PWM3 0x00000000UL /*!< ALT_MFP1 PA.15 setting for PWM3 */ +#define SYS_ALT_MFP2_PA15_PWM3 (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.15 */ + +#define SYS_GPA_MFP_PA15_I2S_MCLK (1UL<<15) /*!< GPA_MFP PA.15 setting for I2S_MCLK */ +#define SYS_ALT_MFP_PA15_I2S_MCLK (1UL<<9) /*!< ALT_MFP PA.15 setting for I2S_MCLK */ +#define SYS_ALT_MFP1_PA15_I2S_MCLK 0x00000000UL /*!< ALT_MFP1 PA.15 setting for I2S_MCLK */ +#define SYS_ALT_MFP2_PA15_I2S_MCLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.15 */ + +#define SYS_GPA_MFP_PA15_SC2_PWR (1UL<<15) /*!< GPA_MFP PA.15 setting for SC2_PWR */ +#define SYS_ALT_MFP_PA15_SC2_PWR 0x00000000UL /*!< ALT_MFP PA.15 setting for SC2_PWR */ +#define SYS_ALT_MFP1_PA15_SC2_PWR (1UL<<12) /*!< ALT_MFP1 PA.15 setting for SC2_PWR */ +#define SYS_ALT_MFP2_PA15_SC2_PWR (uint32_t)NULL /*!< No ALT_MFP2 setting for PA.15 */ + +#define SYS_GPA_MFP_PA15_Msk (1UL<<15) /*!< GPA_MFP PA.15 mask */ +#define SYS_ALT_MFP_PA15_Msk (1UL<<9) /*!< ALT_MFP PA.15 mask */ +#define SYS_ALT_MFP1_PA15_Msk (1UL<<12) /*!< ALT_MFP1 PA.15 mask */ + +//PB.0 +#define SYS_GPB_MFP_PB0_GPIO 0x00000000UL /*!< GPB_MFP PB.0 setting for GPIO */ +#define SYS_ALT_MFP_PB0_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.0 */ +#define SYS_ALT_MFP1_PB0_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.0 */ +#define SYS_ALT_MFP2_PB0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.0 */ + +#define SYS_GPB_MFP_PB0_UART0_RXD (1UL<<0) /*!< GPB_MFP PB.0 setting for UART0_RXD */ +#define SYS_ALT_MFP_PB0_UART0_RXD (uint32_t)NULL /*!< No ALT_MFP setting for PB.0 */ +#define SYS_ALT_MFP1_PB0_UART0_RXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.0 */ +#define SYS_ALT_MFP2_PB0_UART0_RXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.0 */ + +#define SYS_GPB_MFP_PB0_Msk (1UL<<0) /*!< GPB_MFP PB.0 mask */ + +//PB.1 +#define SYS_GPB_MFP_PB1_GPIO 0x00000000UL /*!< GPB_MFP PB.1 setting for GPIO */ +#define SYS_ALT_MFP_PB1_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.1 */ +#define SYS_ALT_MFP1_PB1_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.1 */ +#define SYS_ALT_MFP2_PB1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.1 */ + +#define SYS_GPB_MFP_PB1_UART0_TXD (1UL<<1) /*!< GPB_MFP PB.1 setting for UART0_TXD */ +#define SYS_ALT_MFP_PB1_UART0_TXD (uint32_t)NULL /*!< No ALT_MFP setting for PB.1 */ +#define SYS_ALT_MFP1_PB1_UART0_TXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.1 */ +#define SYS_ALT_MFP2_PB1_UART0_TXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.1 */ + +#define SYS_GPB_MFP_PB1_Msk (1UL<<1) /*!< GPB_MFP PB.1 mask */ + +//PB.2 +#define SYS_GPB_MFP_PB2_GPIO 0x00000000UL /*!< GPB_MFP PB.2 setting for GPIO */ +#define SYS_ALT_MFP_PB2_GPIO 0x00000000UL /*!< ALT_MFP PB.2 setting for GPIO */ +#define SYS_ALT_MFP1_PB2_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.2 */ +#define SYS_ALT_MFP2_PB2_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.2 */ + +#define SYS_GPB_MFP_PB2_UART0_nRTS (1UL<<2) /*!< GPB_MFP PB.2 setting for UART0_nRTS */ +#define SYS_ALT_MFP_PB2_UART0_nRTS 0x00000000UL /*!< ALT_MFP PB.2 setting for UART0_nRTS */ +#define SYS_ALT_MFP1_PB2_UART0_nRTS (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.2 */ +#define SYS_ALT_MFP2_PB2_UART0_nRTS (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.2 */ + +#define SYS_GPB_MFP_PB2_TM2_EXT (1UL<<2) /*!< GPB_MFP PB.2 setting for TM2_EXT */ +#define SYS_ALT_MFP_PB2_TM2_EXT (1UL<<26) /*!< ALT_MFP PB.2 setting for TM2_EXT */ +#define SYS_ALT_MFP1_PB2_TM2_EXT (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.2 */ +#define SYS_ALT_MFP2_PB2_TM2_EXT (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.2 */ + +#define SYS_GPB_MFP_PB2_ACMP0_O (1UL<<2) /*!< GPB_MFP PB.2 setting for ACMP0_O */ +#define SYS_ALT_MFP_PB2_ACMP0_O (1UL<<30) /*!< ALT_MFP PB.2 setting for ACMP0_O */ +#define SYS_ALT_MFP1_PB2_ACMP0_O (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.2 */ +#define SYS_ALT_MFP2_PB2_ACMP0_O (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.2 */ + +#define SYS_GPB_MFP_PB2_CMP0_O (1UL<<2) /*!< GPB_MFP PB.2 setting for CMP0_O */ +#define SYS_ALT_MFP_PB2_CMP0_O (1UL<<30) /*!< ALT_MFP PB.2 setting for CMP0_O */ +#define SYS_ALT_MFP1_PB2_CMP0_O (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.2 */ +#define SYS_ALT_MFP2_PB2_CMP0_O (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.2 */ + +#define SYS_GPB_MFP_PB2_Msk (1UL<<2) /*!< GPB_MFP PB.2 mask */ +#define SYS_ALT_MFP_PB2_Msk ((1UL<<30)|(1UL<<26)) /*!< ALT_MFP PB.2 mask */ + +//PB.3 +#define SYS_GPB_MFP_PB3_GPIO 0x00000000UL /*!< GPB_MFP PB.3 setting for GPIO */ +#define SYS_ALT_MFP_PB3_GPIO 0x00000000UL /*!< ALT_MFP PB.3 setting for GPIO */ +#define SYS_ALT_MFP1_PB3_GPIO 0x00000000UL /*!< ALT_MFP1 PB.3 setting for GPIO */ +#define SYS_ALT_MFP2_PB3_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.3 */ + +#define SYS_GPB_MFP_PB3_UART0_nCTS (1UL<<3) /*!< GPB_MFP PB.3 setting for UART0_nCTS */ +#define SYS_ALT_MFP_PB3_UART0_nCTS 0x00000000UL /*!< ALT_MFP PB.3 setting for UART0_nCTS */ +#define SYS_ALT_MFP1_PB3_UART0_nCTS 0x00000000UL /*!< ALT_MFP1 PB.3 setting for UART0_nCTS */ +#define SYS_ALT_MFP2_PB3_UART0_nCTS (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.3 */ + +#define SYS_GPB_MFP_PB3_TM3_EXT (1UL<<3) /*!< GPB_MFP PB.3 setting for TM3_EXT */ +#define SYS_ALT_MFP_PB3_TM3_EXT (1UL<<27) /*!< ALT_MFP PB.3 setting for TM3_EXT */ +#define SYS_ALT_MFP1_PB3_TM3_EXT 0x00000000UL /*!< ALT_MFP1 PB.3 setting for TM3_EXT */ +#define SYS_ALT_MFP2_PB3_TM3_EXT (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.3 */ + +#define SYS_GPB_MFP_PB3_SC2_CD (1UL<<3) /*!< GPB_MFP PB.3 setting for SC2_CD */ +#define SYS_ALT_MFP_PB3_SC2_CD 0x00000000UL /*!< ALT_MFP PB.3 setting for SC2_CD */ +#define SYS_ALT_MFP1_PB3_SC2_CD (1UL<<14) /*!< ALT_MFP1 PB.3 setting for SC2_CD */ +#define SYS_ALT_MFP2_PB3_SC2_CD (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.3 */ + +#define SYS_GPB_MFP_PB3_Msk (1UL<<3) /*!< GPB_MFP PB.3 mask */ +#define SYS_ALT_MFP_PB3_Msk (1UL<<27) /*!< ALT_MFP PB.3 mask */ +#define SYS_ALT_MFP1_PB3_Msk (1UL<<14) /*!< ALT_MFP1 PB.3 mask */ + + +//PB.4 +#define SYS_GPB_MFP_PB4_GPIO 0x00000000UL /*!< GPA_MFP PB.4 setting for GPIO */ +#define SYS_ALT_MFP_PB4_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.4 */ +#define SYS_ALT_MFP1_PB4_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.4 */ +#define SYS_ALT_MFP2_PB4_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.4 */ + +#define SYS_GPB_MFP_PB4_UART1_RXD (1UL<<4) /*!< GPA_MFP PB.4 setting for UART1_RXD */ +#define SYS_ALT_MFP_PB4_UART1_RXD (uint32_t)NULL /*!< No ALT_MFP setting for PB.4 */ +#define SYS_ALT_MFP1_PB4_UART1_RXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.4 */ +#define SYS_ALT_MFP2_PB4_UART1_RXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.4 */ + +#define SYS_GPB_MFP_PB4_Msk (1UL<<4) /*!< GPA_MFP PB.4 mask */ + +//PB.5 +#define SYS_GPB_MFP_PB5_GPIO 0x00000000UL /*!< GPA_MFP PB.5 setting for GPIO */ +#define SYS_ALT_MFP_PB5_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.5 */ +#define SYS_ALT_MFP1_PB5_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.5 */ +#define SYS_ALT_MFP2_PB5_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.5 */ + +#define SYS_GPB_MFP_PB5_UART1_TXD (1UL<<5) /*!< GPA_MFP PB.5 setting for UART1_TXD */ +#define SYS_ALT_MFP_PB5_UART1_TXD (uint32_t)NULL /*!< No ALT_MFP setting for PB.5 */ +#define SYS_ALT_MFP1_PB5_UART1_TXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.5 */ +#define SYS_ALT_MFP2_PB5_UART1_TXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.5 */ + +#define SYS_GPB_MFP_PB5_Msk (1UL<<5) /*!< GPA_MFP PB.5 mask */ + +//PB.6 +#define SYS_GPB_MFP_PB6_GPIO 0x00000000UL /*!< GPB_MFP PB.6 setting for GPIO */ +#define SYS_ALT_MFP_PB6_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.6 */ +#define SYS_ALT_MFP1_PB6_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.6 */ +#define SYS_ALT_MFP2_PB6_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.6 */ + +#define SYS_GPB_MFP_PB6_UART1_nRTS (1UL<<6) /*!< GPB_MFP PB.6 setting for UART1_nRTS */ +#define SYS_ALT_MFP_PB6_UART1_nRTS (uint32_t)NULL /*!< No ALT_MFP setting for PB.6 */ +#define SYS_ALT_MFP1_PB6_UART1_nRTS (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.6 */ +#define SYS_ALT_MFP2_PB6_UART1_nRTS (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.6 */ + +#define SYS_GPB_MFP_PB6_Msk (1UL<<6) /*!< GPB_MFP PB.6 mask */ + +//PB.7 +#define SYS_GPB_MFP_PB7_GPIO 0x00000000UL /*!< GPB_MFP PB.7 setting for GPIO */ +#define SYS_ALT_MFP_PB7_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.7 */ +#define SYS_ALT_MFP1_PB7_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.7 */ +#define SYS_ALT_MFP2_PB7_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.7 */ + +#define SYS_GPB_MFP_PB7_UART1_nCTS (1UL<<7) /*!< GPB_MFP PB.7 setting for UART1_nCTS */ +#define SYS_ALT_MFP_PB7_UART1_nCTS (uint32_t)NULL /*!< No ALT_MFP setting for PB.7 */ +#define SYS_ALT_MFP1_PB7_UART1_nCTS (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.7 */ +#define SYS_ALT_MFP2_PB7_UART1_nCTS (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.7 */ + +#define SYS_GPB_MFP_PB7_Msk (1UL<<7) /*!< GPB_MFP PB.7 mask */ + +//PB.8 +#define SYS_GPB_MFP_PB8_GPIO 0x00000000UL /*!< GPA_MFP PB.8 setting for GPIO */ +#define SYS_ALT_MFP_PB8_GPIO 0x00000000UL /*!< ALT_MFP PB.8 setting for GPIO */ +#define SYS_ALT_MFP1_PB8_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.8 */ +#define SYS_ALT_MFP2_PB8_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.8 */ + +#define SYS_GPB_MFP_PB8_TM0 (1UL<<8) /*!< GPA_MFP PB.8 setting for TM0 */ +#define SYS_ALT_MFP_PB8_TM0 0x00000000UL /*!< ALT_MFP PB.8 setting for TM0 */ +#define SYS_ALT_MFP1_PB8_TM0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.8 */ +#define SYS_ALT_MFP2_PB8_TM0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.8 */ + +#define SYS_GPB_MFP_PB8_CLKO (1UL<<8) /*!< GPA_MFP PB.8 setting for CLKO */ +#define SYS_ALT_MFP_PB8_CLKO (1UL<<29) /*!< ALT_MFP PB.8 setting for CLKO */ +#define SYS_ALT_MFP1_PB8_CLKO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.8 */ +#define SYS_ALT_MFP2_PB8_CLKO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.8 */ + +#define SYS_GPB_MFP_PB8_Msk (1UL<<8) /*!< GPA_MFP PB.8 mask */ +#define SYS_ALT_MFP_PB8_Msk (1UL<<29) /*!< ALT_MFP PB.8 mask */ + +//PB.9 +#define SYS_GPB_MFP_PB9_GPIO 0x00000000UL /*!< GPB_MFP PB.9 setting for GPIO */ +#define SYS_ALT_MFP_PB9_GPIO 0x00000000UL /*!< ALT_MFP PB.9 setting for GPIO */ +#define SYS_ALT_MFP1_PB9_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.9 */ +#define SYS_ALT_MFP2_PB9_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.9 */ + +#define SYS_GPB_MFP_PB9_TM1 (1UL<<9) /*!< GPB_MFP PB.9 setting for TM1 */ +#define SYS_ALT_MFP_PB9_TM1 0x00000000UL /*!< ALT_MFP PB.9 setting for TM1 */ +#define SYS_ALT_MFP1_PB9_TM1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.9 */ +#define SYS_ALT_MFP2_PB9_TM1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.9 */ + +#define SYS_GPB_MFP_PB9_SPI1_SS1 (1UL<<9) /*!< GPB_MFP PB.9 setting for SPI1_SS1 */ +#define SYS_ALT_MFP_PB9_SPI1_SS1 (1UL<<1) /*!< ALT_MFP PB.9 setting for SPI1_SS1 */ +#define SYS_ALT_MFP1_PB9_SPI1_SS1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.9 */ +#define SYS_ALT_MFP2_PB9_SPI1_SS1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.9 */ + +#define SYS_GPB_MFP_PB9_Msk (1UL<<9) /*!< GPB_MFP PB.9 mask */ +#define SYS_ALT_MFP_PB9_Msk (1UL<<1) /*!< ALT_MFP PB.9 mask */ + +//PB.10 +#define SYS_GPB_MFP_PB10_GPIO 0x00000000UL /*!< GPB_MFP PB.10 setting for GPIO */ +#define SYS_ALT_MFP_PB10_GPIO 0x00000000UL /*!< ALT_MFP PB.10 setting for GPIO */ +#define SYS_ALT_MFP1_PB10_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.10 */ +#define SYS_ALT_MFP2_PB10_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.10 */ + +#define SYS_GPB_MFP_PB10_TM2 (1UL<<10) /*!< GPB_MFP PB.10 setting for TM2 */ +#define SYS_ALT_MFP_PB10_TM2 0x00000000UL /*!< ALT_MFP PB.10 setting for TM2 */ +#define SYS_ALT_MFP1_PB10_TM2 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.10 */ +#define SYS_ALT_MFP2_PB10_TM2 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.10 */ + +#define SYS_GPB_MFP_PB10_SPI0_SS1 (1UL<<10) /*!< GPB_MFP PB.10 setting for SPI0_SS1 */ +#define SYS_ALT_MFP_PB10_SPI0_SS1 (1UL<<0) /*!< ALT_MFP PB.10 setting for SPI0_SS1 */ +#define SYS_ALT_MFP1_PB10_SPI0_SS1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.10 */ +#define SYS_ALT_MFP2_PB10_SPI0_SS1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.10 */ + +#define SYS_GPB_MFP_PB10_Msk (1UL<<10) /*!< GPB_MFP PB.10 mask */ +#define SYS_ALT_MFP_PB10_Msk (1UL<<0) /*!< ALT_MFP PB.10 mask */ + +//PB.11 +#define SYS_GPB_MFP_PB11_GPIO 0x00000000UL /*!< GPB_MFP PB.11 setting for GPIO */ +#define SYS_ALT_MFP_PB11_GPIO 0x00000000UL /*!< ALT_MFP PB.11 setting for GPIO */ +#define SYS_ALT_MFP1_PB11_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.11 */ +#define SYS_ALT_MFP2_PB11_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.11 */ + +#define SYS_GPB_MFP_PB11_TM3 (1UL<<11) /*!< GPB_MFP PB.11 setting for TM3 */ +#define SYS_ALT_MFP_PB11_TM3 0x00000000UL /*!< ALT_MFP PB.11 setting for TM3 */ +#define SYS_ALT_MFP1_PB11_TM3 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.11 */ +#define SYS_ALT_MFP2_PB11_TM3 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.11 */ + +#define SYS_GPB_MFP_PB11_PWM4 (1UL<<11) /*!< GPB_MFP PB.11 setting for PWM4 */ +#define SYS_ALT_MFP_PB11_PWM4 (1UL<<4) /*!< ALT_MFP PB.11 setting for PWM4 */ +#define SYS_ALT_MFP1_PB11_PWM4 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.11 */ +#define SYS_ALT_MFP2_PB11_PWM4 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.11 */ + +#define SYS_GPB_MFP_PB11_Msk (1UL<<11) /*!< GPB_MFP PB.11 mask */ +#define SYS_ALT_MFP_PB11_Msk (1UL<<4) /*!< ALT_MFP PB.11 mask */ + +//PB.12 is reserved + +//PB.13 +#define SYS_GPB_MFP_PB13_GPIO 0x00000000UL /*!< GPB_MFP PB.13 setting for GPIO */ +#define SYS_ALT_MFP_PB13_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PB.13 */ +#define SYS_ALT_MFP1_PB13_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.13 */ +#define SYS_ALT_MFP2_PB13_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.13 */ + +#define SYS_GPB_MFP_PB13_ACMP1_O (1UL<<13) /*!< GPB_MFP PB.13 setting for ACMP1_O */ +#define SYS_ALT_MFP_PB13_ACMP1_O (uint32_t)NULL /*!< No ALT_MFP setting for PB.13 */ +#define SYS_ALT_MFP1_PB13_ACMP1_O (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.13 */ +#define SYS_ALT_MFP2_PB13_ACMP1_O (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.13 */ + +#define SYS_GPB_MFP_PB13_CMP1_O (1UL<<13) /*!< GPB_MFP PB.13 setting for CMP1_O */ +#define SYS_ALT_MFP_PB13_CMP1_O (uint32_t)NULL /*!< No ALT_MFP setting for PB.13 */ +#define SYS_ALT_MFP1_PB13_CMP1_O (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.13 */ +#define SYS_ALT_MFP2_PB13_CMP1_O (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.13 */ + +#define SYS_GPB_MFP_PB13_Msk (1UL<<13) /*!< GPB_MFP PB.13 mask */ + +//PB.14 +#define SYS_GPB_MFP_PB14_GPIO 0x00000000UL /*!< GPB_MFP PB.14 setting for GPIO */ +#define SYS_ALT_MFP_PB14_GPIO 0x00000000UL /*!< ALT_MFP PB.14 setting for GPIO */ +#define SYS_ALT_MFP1_PB14_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.14 */ +#define SYS_ALT_MFP2_PB14_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.14 */ + +#define SYS_GPB_MFP_PB14_INT0 (1UL<<14) /*!< GPB_MFP PB.14 setting for INT0 */ +#define SYS_ALT_MFP_PB14_INT0 0x00000000UL /*!< ALT_MFP PB.14 setting for INT0 */ +#define SYS_ALT_MFP1_PB14_INT0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.14 */ +#define SYS_ALT_MFP2_PB14_INT0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.14 */ + +#define SYS_GPB_MFP_PB14_SPI3_SS1 (1UL<<14) /*!< GPB_MFP PB.14 setting for SPI3_SS1 */ +#define SYS_ALT_MFP_PB14_SPI3_SS1 (1UL<<3) /*!< ALT_MFP PB.14 setting for SPI3_SS1 */ +#define SYS_ALT_MFP1_PB14_SPI3_SS1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.14 */ +#define SYS_ALT_MFP2_PB14_SPI3_SS1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.14 */ + +#define SYS_GPB_MFP_PB14_Msk (1UL<<14) /*!< GPB_MFP PB.14 mask */ +#define SYS_ALT_MFP_PB14_Msk (1UL<<3) /*!< ALT_MFP PB.14 mask */ + +//PB.15 +#define SYS_GPB_MFP_PB15_GPIO 0x00000000UL /*!< GPB_MFP PB.15 setting for GPIO */ +#define SYS_ALT_MFP_PB15_GPIO 0x00000000UL /*!< ALT_MFP PB.15 setting for GPIO */ +#define SYS_ALT_MFP1_PB15_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.15 */ +#define SYS_ALT_MFP2_PB15_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.15 */ + +#define SYS_GPB_MFP_PB15_INT1 (1UL<<15) /*!< GPB_MFP PB.15 setting for INT1 */ +#define SYS_ALT_MFP_PB15_INT1 0x00000000UL /*!< ALT_MFP PB.15 setting for INT1 */ +#define SYS_ALT_MFP1_PB15_INT1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.15 */ +#define SYS_ALT_MFP2_PB15_INT1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.15 */ + +#define SYS_GPB_MFP_PB15_TM0_EXT (1UL<<15) /*!< GPB_MFP PB.15 setting for TM0_EXT */ +#define SYS_ALT_MFP_PB15_TM0_EXT (1UL<<24) /*!< ALT_MFP PB.15 setting for TM0_EXT */ +#define SYS_ALT_MFP1_PB15_TM0_EXT (uint32_t)NULL /*!< No ALT_MFP1 setting for PB.15 */ +#define SYS_ALT_MFP2_PB15_TM0_EXT (uint32_t)NULL /*!< No ALT_MFP2 setting for PB.15 */ + +#define SYS_GPB_MFP_PB15_Msk (1UL<<15) /*!< GPB_MFP PB.15 mask */ +#define SYS_ALT_MFP_PB15_Msk (1UL<<24) /*!< ALT_MFP PB.15 mask */ + + +//PC.0 +#define SYS_GPC_MFP_PC0_GPIO 0x00000000UL /*!< GPC_MFP PC.0 setting for GPIO */ +#define SYS_ALT_MFP_PC0_GPIO 0x00000000UL /*!< ALT_MFP PC.0 setting for GPIO */ +#define SYS_ALT_MFP1_PC0_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.0 */ +#define SYS_ALT_MFP2_PC0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.0 */ + +#define SYS_GPC_MFP_PC0_SPI0_SS0 (1UL<<0) /*!< GPC_MFP PC.0 setting for SPI0_SS0 */ +#define SYS_ALT_MFP_PC0_SPI0_SS0 0x00000000UL /*!< ALT_MFP PC.0 setting for SPI0_SS0 */ +#define SYS_ALT_MFP1_PC0_SPI0_SS0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.0 */ +#define SYS_ALT_MFP2_PC0_SPI0_SS0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.0 */ + +#define SYS_GPC_MFP_PC0_I2S_LRCLK (1UL<<0) /*!< GPC_MFP PC.0 setting for I2S_LRCLK */ +#define SYS_ALT_MFP_PC0_I2S_LRCLK (1UL<<5) /*!< ALT_MFP PC.0 setting for I2S_LRCLK */ +#define SYS_ALT_MFP1_PC0_I2S_LRCLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.0 */ +#define SYS_ALT_MFP2_PC0_I2S_LRCLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.0 */ + +#define SYS_GPC_MFP_PC0_I2S_LRCK (1UL<<0) /*!< GPC_MFP PC.0 setting for I2S_LRCK */ +#define SYS_ALT_MFP_PC0_I2S_LRCK (1UL<<5) /*!< ALT_MFP PC.0 setting for I2S_LRCK */ +#define SYS_ALT_MFP1_PC0_I2S_LRCK (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.0 */ +#define SYS_ALT_MFP2_PC0_I2S_LRCK (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.0 */ + +#define SYS_GPC_MFP_PC0_Msk (1UL<<0) /*!< GPC_MFP PC.0 mask */ +#define SYS_ALT_MFP_PC0_Msk (1UL<<5) /*!< ALT_MFP PC.0 mask */ + +//PC.1 +#define SYS_GPC_MFP_PC1_GPIO 0x00000000UL /*!< GPC_MFP PC.1 setting for GPIO */ +#define SYS_ALT_MFP_PC1_GPIO 0x00000000UL /*!< ALT_MFP PC.1 setting for GPIO */ +#define SYS_ALT_MFP1_PC1_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.1 */ +#define SYS_ALT_MFP2_PC1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.1 */ + +#define SYS_GPC_MFP_PC1_SPI0_CLK (1UL<<1) /*!< GPC_MFP PC.1 setting for SPI0_CLK */ +#define SYS_ALT_MFP_PC1_SPI0_CLK 0x00000000UL /*!< ALT_MFP PC.1 setting for SPI0_CLK */ +#define SYS_ALT_MFP1_PC1_SPI0_CLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.1 */ +#define SYS_ALT_MFP2_PC1_SPI0_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.1 */ + +#define SYS_GPC_MFP_PC1_I2S_BCLK (1UL<<1) /*!< GPC_MFP PC.1 setting for I2S_BCLK */ +#define SYS_ALT_MFP_PC1_I2S_BCLK (1UL<<6) /*!< ALT_MFP PC.1 setting for I2S_BCLK */ +#define SYS_ALT_MFP1_PC1_I2S_BCLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.1 */ +#define SYS_ALT_MFP2_PC1_I2S_BCLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.1 */ + +#define SYS_GPC_MFP_PC1_Msk (1UL<<1) /*!< GPC_MFP PC.1 mask */ +#define SYS_ALT_MFP_PC1_Msk (1UL<<6) /*!< ALT_MFP PC.1 mask */ + +//PC.2 +#define SYS_GPC_MFP_PC2_GPIO 0x00000000UL /*!< GPC_MFP PC.2 setting for GPIO */ +#define SYS_ALT_MFP_PC2_GPIO 0x00000000UL /*!< ALT_MFP PC.2 setting for GPIO */ +#define SYS_ALT_MFP1_PC2_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.2 */ +#define SYS_ALT_MFP2_PC2_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.2 */ + +#define SYS_GPC_MFP_PC2_SPI0_MISO0 (1UL<<2) /*!< GPC_MFP PC.2 setting for SPI0_MISO0 */ +#define SYS_ALT_MFP_PC2_SPI0_MISO0 0x00000000UL /*!< ALT_MFP PC.2 setting for SPI0_MISO0 */ +#define SYS_ALT_MFP1_PC2_SPI0_MISO0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.2 */ +#define SYS_ALT_MFP2_PC2_SPI0_MISO0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.2 */ + +#define SYS_GPC_MFP_PC2_I2S_DI (1UL<<2) /*!< GPC_MFP PC.2 setting for I2S_DI */ +#define SYS_ALT_MFP_PC2_I2S_DI (1UL<<7) /*!< ALT_MFP PC.2 setting for I2S_DI */ +#define SYS_ALT_MFP1_PC2_I2S_DI (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.2 */ +#define SYS_ALT_MFP2_PC2_I2S_DI (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.2 */ + +#define SYS_GPC_MFP_PC2_Msk (1UL<<2) /*!< GPC_MFP PC.2 mask */ +#define SYS_ALT_MFP_PC2_Msk (1UL<<7) /*!< ALT_MFP PC.2 mask */ + +//PC.3 +#define SYS_GPC_MFP_PC3_GPIO 0x00000000UL /*!< GPC_MFP PC.3 setting for GPIO */ +#define SYS_ALT_MFP_PC3_GPIO 0x00000000UL /*!< ALT_MFP PC.3 setting for GPIO */ +#define SYS_ALT_MFP1_PC3_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.3 */ +#define SYS_ALT_MFP2_PC3_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.3 */ + +#define SYS_GPC_MFP_PC3_SPI0_MOSI0 (1UL<<3) /*!< GPC_MFP PC.3 setting for SPI0_MOSI0 */ +#define SYS_ALT_MFP_PC3_SPI0_MOSI0 0x00000000UL /*!< ALT_MFP PC.3 setting for SPI0_MOSI0 */ +#define SYS_ALT_MFP1_PC3_SPI0_MOSI0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.3 */ +#define SYS_ALT_MFP2_PC3_SPI0_MOSI0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.3 */ + +#define SYS_GPC_MFP_PC3_I2S_DO (1UL<<3) /*!< GPC_MFP PC.3 setting for I2S_DO */ +#define SYS_ALT_MFP_PC3_I2S_DO (1UL<<8) /*!< ALT_MFP PC.3 setting for I2S_DO */ +#define SYS_ALT_MFP1_PC3_I2S_DO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.3 */ +#define SYS_ALT_MFP2_PC3_I2S_DO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.3 */ + +#define SYS_GPC_MFP_PC3_Msk (1UL<<3) /*!< GPC_MFP PC.3 mask */ +#define SYS_ALT_MFP_PC3_Msk (1UL<<8) /*!< ALT_MFP PC.3 mask */ + +//PC.4 +#define SYS_GPC_MFP_PC4_GPIO 0x00000000UL /*!< GPC_MFP PC.4 setting for GPIO */ +#define SYS_ALT_MFP_PC4_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.4 */ +#define SYS_ALT_MFP1_PC4_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.4 */ +#define SYS_ALT_MFP2_PC4_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.4 */ + +#define SYS_GPC_MFP_PC4_SPI0_MISO1 (1UL<<4) /*!< GPC_MFP PC.4 setting for SPI0_MISO1 */ +#define SYS_ALT_MFP_PC4_SPI0_MISO1 (uint32_t)NULL /*!< No ALT_MFP setting for PC.4 */ +#define SYS_ALT_MFP1_PC4_SPI0_MISO1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.4 */ +#define SYS_ALT_MFP2_PC4_SPI0_MISO1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.4 */ + +#define SYS_GPC_MFP_PC4_Msk (1UL<<4) /*!< GPC_MFP PC.4 mask */ + +//PC.5 +#define SYS_GPC_MFP_PC5_GPIO 0x00000000UL /*!< GPC_MFP PC.5 setting for GPIO */ +#define SYS_ALT_MFP_PC5_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.5 */ +#define SYS_ALT_MFP1_PC5_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.5 */ +#define SYS_ALT_MFP2_PC5_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.5 */ + +#define SYS_GPC_MFP_PC5_SPI0_MOSI1 (1UL<<5) /*!< GPC_MFP PC.5 setting for SPI0_MOSI1 */ +#define SYS_ALT_MFP_PC5_SPI0_MOSI1 (uint32_t)NULL /*!< No ALT_MFP setting for PC.5 */ +#define SYS_ALT_MFP1_PC5_SPI0_MOSI1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.5 */ +#define SYS_ALT_MFP2_PC5_SPI0_MOSI1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.5 */ + +#define SYS_GPC_MFP_PC5_Msk (1UL<<5) /*!< GPC_MFP PC.5 mask */ + +//PC.6 +#define SYS_GPC_MFP_PC6_GPIO 0x00000000UL /*!< GPC_MFP PC.6 setting for GPIO */ +#define SYS_ALT_MFP_PC6_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.6 */ +#define SYS_ALT_MFP1_PC6_GPIO 0x00000000UL /*!< ALT_MFP1 PC.6 setting for GPIO */ +#define SYS_ALT_MFP2_PC6_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.6 */ + +#define SYS_GPC_MFP_PC6_ACMP0_P (1UL<<6) /*!< GPC_MFP PC.6 setting for ACMP0_P */ +#define SYS_ALT_MFP_PC6_ACMP0_P (uint32_t)NULL /*!< No ALT_MFP setting for PC.6 */ +#define SYS_ALT_MFP1_PC6_ACMP0_P 0x00000000UL /*!< ALT_MFP1 PC.6 setting for ACMP0_P */ +#define SYS_ALT_MFP2_PC6_ACMP0_P (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.6 */ + +#define SYS_GPC_MFP_PC6_CMP0_P (1UL<<6) /*!< GPC_MFP PC.6 setting for CMP0_P */ +#define SYS_ALT_MFP_PC6_CMP0_P (uint32_t)NULL /*!< No ALT_MFP setting for PC.6 */ +#define SYS_ALT_MFP1_PC6_CMP0_P 0x00000000UL /*!< ALT_MFP1 PC.6 setting for CMP0_P */ +#define SYS_ALT_MFP2_PC6_CMP0_P (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.6 */ + +#define SYS_GPC_MFP_PC6_SC0_CD (1UL<<6) /*!< GPC_MFP PC.6 setting for SC0_CD */ +#define SYS_ALT_MFP_PC6_SC0_CD (uint32_t)NULL /*!< No ALT_MFP setting for PC.6 */ +#define SYS_ALT_MFP1_PC6_SC0_CD (1UL<<4) /*!< ALT_MFP1 PC.6 setting for SC0_CD */ +#define SYS_ALT_MFP2_PC6_SC0_CD (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.6 */ + +#define SYS_GPC_MFP_PC6_Msk (1UL<<6) /*!< GPC_MFP PC.6 mask */ +#define SYS_ALT_MFP1_PC6_Msk (1UL<<4) /*!< ALT_MFP1 PC.6 mask */ + +//PC.7 +#define SYS_GPC_MFP_PC7_GPIO 0x00000000UL /*!< GPC_MFP PC.7 setting for GPIO */ +#define SYS_ALT_MFP_PC7_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.7 */ +#define SYS_ALT_MFP1_PC7_GPIO 0x00000000UL /*!< ALT_MFP1 PC.7 setting for GPIO */ +#define SYS_ALT_MFP2_PC7_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.7 */ + +#define SYS_GPC_MFP_PC7_ACMP0_N (1UL<<7) /*!< GPC_MFP PC.7 setting for ACMP0_N */ +#define SYS_ALT_MFP_PC7_ACMP0_N (uint32_t)NULL /*!< No ALT_MFP setting for PC.7 */ +#define SYS_ALT_MFP1_PC7_ACMP0_N 0x00000000UL /*!< ALT_MFP1 PC.7 setting for ACMP0_N */ +#define SYS_ALT_MFP2_PC7_ACMP0_N (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.7 */ + +#define SYS_GPC_MFP_PC7_CMP0_N (1UL<<7) /*!< GPC_MFP PC.7 setting for CMP0_N */ +#define SYS_ALT_MFP_PC7_CMP0_N (uint32_t)NULL /*!< No ALT_MFP setting for PC.7 */ +#define SYS_ALT_MFP1_PC7_CMP0_N 0x00000000UL /*!< ALT_MFP1 PC.7 setting for CMP0_N */ +#define SYS_ALT_MFP2_PC7_CMP0_N (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.7 */ + +#define SYS_GPC_MFP_PC7_SC1_CD (1UL<<7) /*!< GPC_MFP PC.7 setting for SC1_CD */ +#define SYS_ALT_MFP_PC7_SC1_CD (uint32_t)NULL /*!< No ALT_MFP setting for PC.7 */ +#define SYS_ALT_MFP1_PC7_SC1_CD (1UL<<9) /*!< ALT_MFP1 PC.7 setting for SC1_CD */ +#define SYS_ALT_MFP2_PC7_SC1_CD (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.7 */ + +#define SYS_GPC_MFP_PC7_Msk (1UL<<7) /*!< GPC_MFP PC.7 mask */ +#define SYS_ALT_MFP1_PC7_Msk (1UL<<9) /*!< ALT_MFP1 PC.7 mask */ + +//PC.8 +#define SYS_GPC_MFP_PC8_GPIO 0x00000000UL /*!< GPC_MFP PC.8 setting for GPIO */ +#define SYS_ALT_MFP_PC8_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.8 */ +#define SYS_ALT_MFP1_PC8_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.8 */ +#define SYS_ALT_MFP2_PC8_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.8 */ + +#define SYS_GPC_MFP_PC8_SPI1_SS0 (1UL<<8) /*!< GPC_MFP PC.8 setting for SPI1_SS0 */ +#define SYS_ALT_MFP_PC8_SPI1_SS0 (uint32_t)NULL /*!< No ALT_MFP setting for PC.8 */ +#define SYS_ALT_MFP1_PC8_SPI1_SS0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.8 */ +#define SYS_ALT_MFP2_PC8_SPI1_SS0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.8 */ + +#define SYS_GPC_MFP_PC8_Msk (1UL<<8) /*!< GPC_MFP PC.8 mask */ + +//PC.9 +#define SYS_GPC_MFP_PC9_GPIO 0x00000000UL /*!< GPC_MFP PC.9 setting for GPIO */ +#define SYS_ALT_MFP_PC9_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.9 */ +#define SYS_ALT_MFP1_PC9_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.9 */ +#define SYS_ALT_MFP2_PC9_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.9 */ + +#define SYS_GPC_MFP_PC9_SPI1_CLK (1UL<<9) /*!< GPC_MFP PC.9 setting for SPI1_CLK */ +#define SYS_ALT_MFP_PC9_SPI1_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PC.9 */ +#define SYS_ALT_MFP1_PC9_SPI1_CLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.9 */ +#define SYS_ALT_MFP2_PC9_SPI1_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.9 */ + +#define SYS_GPC_MFP_PC9_Msk (1UL<<9) /*!< GPC_MFP PC.9 mask */ + +//PC.10 +#define SYS_GPC_MFP_PC10_GPIO 0x00000000UL /*!< GPC_MFP PC.10 setting for GPIO */ +#define SYS_ALT_MFP_PC10_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.10 */ +#define SYS_ALT_MFP1_PC10_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.10 */ +#define SYS_ALT_MFP2_PC10_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.10 */ + +#define SYS_GPC_MFP_PC10_SPI1_MISO0 (1UL<<10) /*!< GPC_MFP PC.10 setting for SPI1_MISO0 */ +#define SYS_ALT_MFP_PC10_SPI1_MISO0 (uint32_t)NULL /*!< No ALT_MFP setting for PC.10 */ +#define SYS_ALT_MFP1_PC10_SPI1_MISO0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.10 */ +#define SYS_ALT_MFP2_PC10_SPI1_MISO0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.10 */ + +#define SYS_GPC_MFP_PC10_Msk (1UL<<10) /*!< GPC_MFP PC.10 mask */ + +//PC.11 +#define SYS_GPC_MFP_PC11_GPIO 0x00000000UL /*!< GPC_MFP PC.11 setting for GPIO */ +#define SYS_ALT_MFP_PC11_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.11 */ +#define SYS_ALT_MFP1_PC11_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.11 */ +#define SYS_ALT_MFP2_PC11_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.11 */ + +#define SYS_GPC_MFP_PC11_SPI1_MOSI0 (1UL<<11) /*!< GPC_MFP PC.11 setting for SPI1_MOSI0 */ +#define SYS_ALT_MFP_PC11_SPI1_MOSI0 (uint32_t)NULL /*!< No ALT_MFP setting for PC.11 */ +#define SYS_ALT_MFP1_PC11_SPI1_MOSI0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.11 */ +#define SYS_ALT_MFP2_PC11_SPI1_MOSI0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.11 */ + +#define SYS_GPC_MFP_PC11_Msk (1UL<<11) /*!< GPC_MFP PC.11 mask */ + + +//PC.12 +#define SYS_GPC_MFP_PC12_GPIO 0x00000000UL /*!< GPC_MFP PC.12 setting for GPIO */ +#define SYS_ALT_MFP_PC12_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.12 */ +#define SYS_ALT_MFP1_PC12_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.12 */ +#define SYS_ALT_MFP2_PC12_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.12 */ + +#define SYS_GPC_MFP_PC12_SPI1_MISO1 (1UL<<12) /*!< GPC_MFP PC.12 setting for SPI1_MISO1 */ +#define SYS_ALT_MFP_PC12_SPI1_MISO1 (uint32_t)NULL /*!< No ALT_MFP setting for PC.12 */ +#define SYS_ALT_MFP1_PC12_SPI1_MISO1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.12 */ +#define SYS_ALT_MFP2_PC12_SPI1_MISO1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.12 */ + +#define SYS_GPC_MFP_PC12_Msk (1UL<<12) /*!< GPC_MFP PC.12 mask */ + +//PC.13 +#define SYS_GPC_MFP_PC13_GPIO 0x00000000UL /*!< GPC_MFP PC.13 setting for GPIO */ +#define SYS_ALT_MFP_PC13_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.13 */ +#define SYS_ALT_MFP1_PC13_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.13 */ +#define SYS_ALT_MFP2_PC13_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.13 */ + +#define SYS_GPC_MFP_PC13_SPI1_MOSI1 (1UL<<13) /*!< GPC_MFP PC.13 setting for SPI1_MOSI1 */ +#define SYS_ALT_MFP_PC13_SPI1_MOSI1 (uint32_t)NULL /*!< No ALT_MFP setting for PC.13 */ +#define SYS_ALT_MFP1_PC13_SPI1_MOSI1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.13 */ +#define SYS_ALT_MFP2_PC13_SPI1_MOSI1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.13 */ + +#define SYS_GPC_MFP_PC13_Msk (1UL<<13) /*!< GPC_MFP PC.13 mask */ + +//PC.14 +#define SYS_GPC_MFP_PC14_GPIO 0x00000000UL /*!< GPC_MFP PC.14 setting for GPIO */ +#define SYS_ALT_MFP_PC14_GPIO (uint32_t)NULL /*!< No LT_MFP setting for PC.14 */ +#define SYS_ALT_MFP1_PC14_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.14 */ +#define SYS_ALT_MFP2_PC14_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.14 */ + +#define SYS_GPC_MFP_PC14_ACMP1_P (1UL<<14) /*!< GPC_MFP PC.14 setting for ACMP1_P */ +#define SYS_ALT_MFP_PC14_ACMP1_P (uint32_t)NULL /*!< No ALT_MFP setting for PC.14 */ +#define SYS_ALT_MFP1_PC14_ACMP1_P (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.14 */ +#define SYS_ALT_MFP2_PC14_ACMP1_P (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.14 */ + +#define SYS_GPC_MFP_PC14_CMP1_P (1UL<<14) /*!< GPC_MFP PC.14 setting for CMP1_P */ +#define SYS_ALT_MFP_PC14_CMP1_P (uint32_t)NULL /*!< No ALT_MFP setting for PC.14 */ +#define SYS_ALT_MFP1_PC14_CMP1_P (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.14 */ +#define SYS_ALT_MFP2_PC14_CMP1_P (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.14 */ + +#define SYS_GPC_MFP_PC14_Msk (1UL<<14) /*!< GPC_MFP PC.14 mask */ + +//PC.15 +#define SYS_GPC_MFP_PC15_GPIO 0x00000000UL /*!< GPC_MFP PC.15 setting for GPIO */ +#define SYS_ALT_MFP_PC15_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PC.15 */ +#define SYS_ALT_MFP1_PC15_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.15 */ +#define SYS_ALT_MFP2_PC15_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.15 */ + +#define SYS_GPC_MFP_PC15_ACMP1_N (1UL<<15) /*!< GPC_MFP PC.15 setting for ACMP1_N */ +#define SYS_ALT_MFP_PC15_ACMP1_N (uint32_t)NULL /*!< No ALT_MFP setting for PC.15 */ +#define SYS_ALT_MFP1_PC15_ACMP1_N (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.15 */ +#define SYS_ALT_MFP2_PC15_ACMP1_N (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.15 */ + +#define SYS_GPC_MFP_PC15_CMP1_N (1UL<<15) /*!< GPC_MFP PC.15 setting for CMP1_N */ +#define SYS_ALT_MFP_PC15_CMP1_N (uint32_t)NULL /*!< No ALT_MFP setting for PC.15 */ +#define SYS_ALT_MFP1_PC15_CMP1_N (uint32_t)NULL /*!< No ALT_MFP1 setting for PC.15 */ +#define SYS_ALT_MFP2_PC15_CMP1_N (uint32_t)NULL /*!< No ALT_MFP2 setting for PC.15 */ + +#define SYS_GPC_MFP_PC15_Msk (1UL<<15) /*!< GPC_MFP PC.15 mask */ + +//PD.0 +#define SYS_GPD_MFP_PD0_GPIO 0x00000000UL /*!< GPD_MFP PD.0 setting for GPIO */ +#define SYS_ALT_MFP_PD0_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.0 */ +#define SYS_ALT_MFP1_PD0_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.0 */ +#define SYS_ALT_MFP2_PD0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.0 */ + +#define SYS_GPD_MFP_PD0_SPI2_SS0 (1UL<<0) /*!< GPD_MFP PD.0 setting for SPI2_SS0 */ +#define SYS_ALT_MFP_PD0_SPI2_SS0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.0 */ +#define SYS_ALT_MFP1_PD0_SPI2_SS0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.0 */ +#define SYS_ALT_MFP2_PD0_SPI2_SS0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.0 */ + +#define SYS_GPD_MFP_PD0_Msk (1UL<<0) /*!< GPD_MFP PD.0 mask */ + +//PD.1 +#define SYS_GPD_MFP_PD1_GPIO 0x00000000UL /*!< GPD_MFP PD.1 setting for GPIO */ +#define SYS_ALT_MFP_PD1_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.1 */ +#define SYS_ALT_MFP1_PD1_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.1 */ +#define SYS_ALT_MFP2_PD1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.1 */ + +#define SYS_GPD_MFP_PD1_SPI2_CLK (1UL<<1) /*!< GPD_MFP PD.1 setting for SPI2_CLK */ +#define SYS_ALT_MFP_PD1_SPI2_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PD.1 */ +#define SYS_ALT_MFP1_PD1_SPI2_CLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.1 */ +#define SYS_ALT_MFP2_PD1_SPI2_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.1 */ + +#define SYS_GPD_MFP_PD1_Msk (1UL<<1) /*!< GPD_MFP PD.1 mask */ + +//PD.2 +#define SYS_GPD_MFP_PD2_GPIO 0x00000000UL /*!< GPD_MFP PD.2 setting for GPIO */ +#define SYS_ALT_MFP_PD2_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.2 */ +#define SYS_ALT_MFP1_PD2_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.2 */ +#define SYS_ALT_MFP2_PD2_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.2 */ + +#define SYS_GPD_MFP_PD2_SPI2_MISO0 (1UL<<2) /*!< GPD_MFP PD.2 setting for SPI2_MISO0 */ +#define SYS_ALT_MFP_PD2_SPI2_MISO0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.2 */ +#define SYS_ALT_MFP1_PD2_SPI2_MISO0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.2 */ +#define SYS_ALT_MFP2_PD2_SPI2_MISO0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.2 */ + +#define SYS_GPD_MFP_PD2_Msk (1UL<<2) /*!< GPD_MFP PD.2 mask */ + +//PD.3 +#define SYS_GPD_MFP_PD3_GPIO 0x00000000UL /*!< GPD_MFP PD.3 setting for GPIO */ +#define SYS_ALT_MFP_PD3_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.3 */ +#define SYS_ALT_MFP1_PD3_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.3 */ +#define SYS_ALT_MFP2_PD3_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.3 */ + +#define SYS_GPD_MFP_PD3_SPI2_MOSI0 (1UL<<3) /*!< GPD_MFP PD.3 setting for SPI2_MOSI0 */ +#define SYS_ALT_MFP_PD3_SPI2_MOSI0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.3 */ +#define SYS_ALT_MFP1_PD3_SPI2_MOSI0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.3 */ +#define SYS_ALT_MFP2_PD3_SPI2_MOSI0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.3 */ + +#define SYS_GPD_MFP_PD3_Msk (1UL<<3) /*!< GPD_MFP PD.3 mask */ + +//PD.4 +#define SYS_GPD_MFP_PD4_GPIO 0x00000000UL /*!< GPD_MFP PD.4 setting for GPIO */ +#define SYS_ALT_MFP_PD4_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.4 */ +#define SYS_ALT_MFP1_PD4_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.4 */ +#define SYS_ALT_MFP2_PD4_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.4 */ + +#define SYS_GPD_MFP_PD4_SPI2_MISO1 (1UL<<4) /*!< GPD_MFP PD.4 setting for SPI2_MISO1 */ +#define SYS_ALT_MFP_PD4_SPI2_MISO1 (uint32_t)NULL /*!< No ALT_MFP setting for PD.4 */ +#define SYS_ALT_MFP1_PD4_SPI2_MISO1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.4 */ +#define SYS_ALT_MFP2_PD4_SPI2_MISO1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.4 */ + +#define SYS_GPD_MFP_PD4_Msk (1UL<<4) /*!< GPD_MFP PD.4 mask */ + +//PD.5 +#define SYS_GPD_MFP_PD5_GPIO 0x00000000UL /*!< GPD_MFP PD.5 setting for GPIO */ +#define SYS_ALT_MFP_PD5_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.5 */ +#define SYS_ALT_MFP1_PD5_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.5 */ +#define SYS_ALT_MFP2_PD5_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.5 */ + +#define SYS_GPD_MFP_PD5_SPI2_MOSI1 (1UL<<5) /*!< GPD_MFP PD.5 setting for SPI2_MOSI1 */ +#define SYS_ALT_MFP_PD5_SPI2_MOSI1 (uint32_t)NULL /*!< No ALT_MFP setting for PD.5 */ +#define SYS_ALT_MFP1_PD5_SPI2_MOSI1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.5 */ +#define SYS_ALT_MFP2_PD5_SPI2_MOSI1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.5 */ + +#define SYS_GPD_MFP_PD5_Msk (1UL<<5) /*!< GPD_MFP PD.5 mask */ + +//PD.6 is reserved + +//PD.7 is reserved + +//PD.8 +#define SYS_GPD_MFP_PD8_GPIO 0x00000000UL /*!< GPD_MFP PD.8 setting for GPIO */ +#define SYS_ALT_MFP_PD8_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.8 */ +#define SYS_ALT_MFP1_PD8_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.8 */ +#define SYS_ALT_MFP2_PD8_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.8 */ + +#define SYS_GPD_MFP_PD8_SPI3_SS0 (1UL<<8) /*!< GPD_MFP PD.8 setting for SPI3_SS0 */ +#define SYS_ALT_MFP_PD8_SPI3_SS0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.8 */ +#define SYS_ALT_MFP1_PD8_SPI3_SS0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.8 */ +#define SYS_ALT_MFP2_PD8_SPI3_SS0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.8 */ + +#define SYS_GPD_MFP_PD8_Msk (1UL<<8) /*!< GPD_MFP PD.8 mask */ + +//PD.9 +#define SYS_GPD_MFP_PD9_GPIO 0x00000000UL /*!< GPD_MFP PD.9 setting for GPIO */ +#define SYS_ALT_MFP_PD9_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.9 */ +#define SYS_ALT_MFP1_PD9_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.9 */ +#define SYS_ALT_MFP2_PD9_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.9 */ + +#define SYS_GPD_MFP_PD9_SPI3_CLK (1UL<<9) /*!< GPD_MFP PD.9 setting for SPI3_CLK */ +#define SYS_ALT_MFP_PD9_SPI3_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PD.9 */ +#define SYS_ALT_MFP1_PD9_SPI3_CLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.9 */ +#define SYS_ALT_MFP2_PD9_SPI3_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.9 */ + +#define SYS_GPD_MFP_PD9_Msk (1UL<<9) /*!< GPD_MFP PD.9 mask */ + +//PD.10 +#define SYS_GPD_MFP_PD10_GPIO 0x00000000UL /*!< GPD_MFP PD.10 setting for GPIO */ +#define SYS_ALT_MFP_PD10_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.10 */ +#define SYS_ALT_MFP1_PD10_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.10 */ +#define SYS_ALT_MFP2_PD10_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.10 */ + +#define SYS_GPD_MFP_PD10_SPI3_MISO0 (1UL<<10) /*!< GPD_MFP PD.10 setting for SPI3_MISO0 */ +#define SYS_ALT_MFP_PD10_SPI3_MISO0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.10 */ +#define SYS_ALT_MFP1_PD10_SPI3_MISO0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.10 */ +#define SYS_ALT_MFP2_PD10_SPI3_MISO0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.10 */ + +#define SYS_GPD_MFP_PD10_Msk (1UL<<10) /*!< GPD_MFP PD.10 mask */ + +//PD.11 +#define SYS_GPD_MFP_PD11_GPIO 0x00000000UL /*!< GPD_MFP PD.11 setting for GPIO */ +#define SYS_ALT_MFP_PD11_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.11 */ +#define SYS_ALT_MFP1_PD11_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.11 */ +#define SYS_ALT_MFP2_PD11_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.11 */ + +#define SYS_GPD_MFP_PD11_SPI3_MOSI0 (1UL<<11) /*!< GPD_MFP PD.11 setting for SPI3_MOSI0 */ +#define SYS_ALT_MFP_PD11_SPI3_MOSI0 (uint32_t)NULL /*!< No ALT_MFP setting for PD.11 */ +#define SYS_ALT_MFP1_PD11_SPI3_MOSI0 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.11 */ +#define SYS_ALT_MFP2_PD11_SPI3_MOSI0 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.11 */ + +#define SYS_GPD_MFP_PD11_Msk (1UL<<11) /*!< GPD_MFP PD.11 mask */ + +//PD.12 +#define SYS_GPD_MFP_PD12_GPIO 0x00000000UL /*!< GPD_MFP PD.12 setting for GPIO */ +#define SYS_ALT_MFP_PD12_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.12 */ +#define SYS_ALT_MFP1_PD12_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.12 */ +#define SYS_ALT_MFP2_PD12_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.12 */ + +#define SYS_GPD_MFP_PD12_SPI3_MISO1 (1UL<<12) /*!< GPD_MFP PD.12 setting for SPI3_MISO1 */ +#define SYS_ALT_MFP_PD12_SPI3_MISO1 (uint32_t)NULL /*!< No ALT_MFP setting for PD.12 */ +#define SYS_ALT_MFP1_PD12_SPI3_MISO1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.12 */ +#define SYS_ALT_MFP2_PD12_SPI3_MISO1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.12 */ + +#define SYS_GPD_MFP_PD12_Msk (1UL<<12) /*!< GPD_MFP PD.12 mask */ + +//PD.13 +#define SYS_GPD_MFP_PD13_GPIO 0x00000000UL /*!< GPD_MFP PD.13 setting for GPIO */ +#define SYS_ALT_MFP_PD13_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.13 */ +#define SYS_ALT_MFP1_PD13_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.13 */ +#define SYS_ALT_MFP2_PD13_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.13 */ + +#define SYS_GPD_MFP_PD13_SPI3_MOSI1 (1UL<<13) /*!< GPD_MFP PD.13 setting for SPI3_MOSI1 */ +#define SYS_ALT_MFP_PD13_SPI3_MOSI1 (uint32_t)NULL /*!< No ALT_MFP setting for PD.13 */ +#define SYS_ALT_MFP1_PD13_SPI3_MOSI1 (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.13 */ +#define SYS_ALT_MFP2_PD13_SPI3_MOSI1 (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.13 */ + +#define SYS_GPD_MFP_PD13_Msk (1UL<<13) /*!< GPD_MFP PD.13 mask */ + +//PD.14 +#define SYS_GPD_MFP_PD14_GPIO 0x00000000UL /*!< GPD_MFP PD.14 setting for GPIO */ +#define SYS_ALT_MFP_PD14_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.14 */ +#define SYS_ALT_MFP1_PD14_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.14 */ +#define SYS_ALT_MFP2_PD14_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.14 */ + +#define SYS_GPD_MFP_PD14_UART2_RXD (1UL<<14) /*!< GPD_MFP PD.14 setting for UART2_RXD */ +#define SYS_ALT_MFP_PD14_UART2_RXD (uint32_t)NULL /*!< No ALT_MFP setting for PD.14 */ +#define SYS_ALT_MFP1_PD14_UART2_RXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.14 */ +#define SYS_ALT_MFP2_PD14_UART2_RXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.14 */ + +#define SYS_GPD_MFP_PD14_Msk (1UL<<14) /*!< GPD_MFP PD.14 mask */ + +//PD.15 +#define SYS_GPD_MFP_PD15_GPIO 0x00000000UL /*!< GPD_MFP PD.15 setting for GPIO */ +#define SYS_ALT_MFP_PD15_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PD.15 */ +#define SYS_ALT_MFP1_PD15_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.15 */ +#define SYS_ALT_MFP2_PD15_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.15 */ + +#define SYS_GPD_MFP_PD15_UART2_TXD (1UL<<15) /*!< GPD_MFP PD.15 setting for UART2_TXD */ +#define SYS_ALT_MFP_PD15_UART2_TXD (uint32_t)NULL /*!< No ALT_MFP setting for PD.15 */ +#define SYS_ALT_MFP1_PD15_UART2_TXD (uint32_t)NULL /*!< No ALT_MFP1 setting for PD.15 */ +#define SYS_ALT_MFP2_PD15_UART2_TXD (uint32_t)NULL /*!< No ALT_MFP2 setting for PD.15 */ + +#define SYS_GPD_MFP_PD15_Msk (1UL<<15) /*!< GPD_MFP PD.15 mask */ + +//PE.0 +#define SYS_GPE_MFP_PE0_GPIO 0x00000000UL /*!< GPE_MFP PE.0 setting for GPIO */ +#define SYS_ALT_MFP_PE0_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PE.0 */ +#define SYS_ALT_MFP1_PE0_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.0 */ +#define SYS_ALT_MFP2_PE0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.0 */ + +#define SYS_GPE_MFP_PE0_PWM6 (1UL<<0) /*!< GPE_MFP PE.0 setting for PWM6 */ +#define SYS_ALT_MFP_PE0_PWM6 (uint32_t)NULL /*!< No ALT_MFP setting for PE.0 */ +#define SYS_ALT_MFP1_PE0_PWM6 (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.0 */ +#define SYS_ALT_MFP2_PE0_PWM6 (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.0 */ + +#define SYS_GPE_MFP_PE0_Msk (1UL<<0) /*!< GPE_MFP PE.0 mask */ + +//PE.1 +#define SYS_GPE_MFP_PE1_GPIO 0x00000000UL /*!< GPE_MFP PE.1 setting for GPIO */ +#define SYS_ALT_MFP_PE1_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PE.1 */ +#define SYS_ALT_MFP1_PE1_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.1 */ +#define SYS_ALT_MFP2_PE1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.1 */ + +#define SYS_GPE_MFP_PE1_PWM7 (1UL<<1) /*!< GPE_MFP PE.1 setting for PWM7 */ +#define SYS_ALT_MFP_PE1_PWM7 (uint32_t)NULL /*!< No ALT_MFP setting for PE.1 */ +#define SYS_ALT_MFP1_PE1_PWM7 (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.1 */ +#define SYS_ALT_MFP2_PE1_PWM7 (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.1 */ + +#define SYS_GPE_MFP_PE1_Msk (1UL<<1) /*!< GPE_MFP PE.1 mask */ + +//PE.5 +#define SYS_GPE_MFP_PE5_GPIO 0x00000000UL /*!< GPE_MFP PE.5 setting for GPIO */ +#define SYS_ALT_MFP_PE5_GPIO 0x00000000UL /*!< ALT_MFP PE.5 setting for GPIO */ +#define SYS_ALT_MFP1_PE5_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.5 */ +#define SYS_ALT_MFP2_PE5_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.5 */ + +#define SYS_GPE_MFP_PE5_PWM5 (1UL<<5) /*!< GPE_MFP PE.5 setting for PWM5 */ +#define SYS_ALT_MFP_PE5_PWM5 0x00000000UL /*!< ALT_MFP PE.5 setting for PWM5 */ +#define SYS_ALT_MFP1_PE5_PWM5 (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.5 */ +#define SYS_ALT_MFP2_PE5_PWM5 (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.5 */ + +#define SYS_GPE_MFP_PE5_TM1_EXT (1UL<<5) /*!< GPE_MFP PE.5 setting for TM1_EXT */ +#define SYS_ALT_MFP_PE5_TM1_EXT (1UL<<25) /*!< ALT_MFP PE.5 setting for TM1_EXT */ +#define SYS_ALT_MFP1_PE5_TM1_EXT (uint32_t)NULL /*!< No ALT_MFP1 setting for PE.5 */ +#define SYS_ALT_MFP2_PE5_TM1_EXT (uint32_t)NULL /*!< No ALT_MFP2 setting for PE.5 */ + +#define SYS_GPE_MFP_PE5_Msk (1UL<<5) /*!< GPE_MFP PE.5 mask */ +#define SYS_ALT_MFP_PE5_Msk (1UL<<25) /*!< ALT_MFP PE.5 mask */ + +//PF.0 +#define SYS_GPF_MFP_PF0_GPIO 0x00000000UL /*!< GPF_MFP PF.0 setting for GPIO */ +#define SYS_ALT_MFP_PF0_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PF.0 */ +#define SYS_ALT_MFP1_PF0_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.0 */ +#define SYS_ALT_MFP2_PF0_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.0 */ + +#define SYS_GPF_MFP_PF0_XT1_OUT (1UL<<0) /*!< GPF_MFP PF.0 setting for XT1_OUT */ +#define SYS_ALT_MFP_PF0_XT1_OUT (uint32_t)NULL /*!< No ALT_MFP setting for PF.0 */ +#define SYS_ALT_MFP1_PF0_XT1_OUT (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.0 */ +#define SYS_ALT_MFP2_PF0_XT1_OUT (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.0 */ + +#define SYS_GPF_MFP_PF0_Msk (1UL<<0) /*!< GPF_MFP PF.0 mask */ + +//PF.1 +#define SYS_GPF_MFP_PF1_GPIO 0x00000000UL /*!< GPF_MFP PF.1 setting for GPIO */ +#define SYS_ALT_MFP_PF1_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PF.1 */ +#define SYS_ALT_MFP1_PF1_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.1 */ +#define SYS_ALT_MFP2_PF1_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.1 */ + +#define SYS_GPF_MFP_PF1_XT1_IN (1UL<<1) /*!< GPF_MFP PF.1 setting for XT1_IN */ +#define SYS_ALT_MFP_PF1_XT1_IN (uint32_t)NULL /*!< No ALT_MFP setting for PF.1 */ +#define SYS_ALT_MFP1_PF1_XT1_IN (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.1 */ +#define SYS_ALT_MFP2_PF1_XT1_IN (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.1 */ + +#define SYS_GPF_MFP_PF1_Msk (1UL<<1) /*!< GPF_MFP PF.1 mask */ + +//PF.2 +#define SYS_GPF_MFP_PF2_GPIO 0x00000000UL /*!< GPF_MFP PF.2 setting for GPIO */ +#define SYS_ALT_MFP_PF2_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PF.2 */ +#define SYS_ALT_MFP1_PF2_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.2 */ +#define SYS_ALT_MFP2_PF2_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.2 */ + +#define SYS_GPF_MFP_PF2_PS2_DAT (1UL<<2) /*!< GPF_MFP PF.2 setting for PS2_DAT */ +#define SYS_ALT_MFP_PF2_PS2_DAT (uint32_t)NULL /*!< No ALT_MFP setting for PF.2 */ +#define SYS_ALT_MFP1_PF2_PS2_DAT (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.2 */ +#define SYS_ALT_MFP2_PF2_PS2_DAT (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.2 */ + +#define SYS_GPF_MFP_PF2_Msk (1UL<<2) /*!< GPF_MFP PF.2 mask */ + +//PF.3 +#define SYS_GPF_MFP_PF3_GPIO 0x00000000UL /*!< GPF_MFP PF.3 setting for GPIO */ +#define SYS_ALT_MFP_PF3_GPIO (uint32_t)NULL /*!< No ALT_MFP setting for PF.3 */ +#define SYS_ALT_MFP1_PF3_GPIO (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.3 */ +#define SYS_ALT_MFP2_PF3_GPIO (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.3 */ + +#define SYS_GPF_MFP_PF3_PS2_CLK (1UL<<3) /*!< GPF_MFP PF.3 setting for PS2_CLK */ +#define SYS_ALT_MFP_PF3_PS2_CLK (uint32_t)NULL /*!< No ALT_MFP setting for PF.3 */ +#define SYS_ALT_MFP1_PF3_PS2_CLK (uint32_t)NULL /*!< No ALT_MFP1 setting for PF.3 */ +#define SYS_ALT_MFP2_PF3_PS2_CLK (uint32_t)NULL /*!< No ALT_MFP2 setting for PF.3 */ + +#define SYS_GPF_MFP_PF3_Msk (1UL<<3) /*!< GPF_MFP PF.3 mask */ + + +/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */ + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + + +/** + * @brief Clear Brown-out detector interrupt flag + * @param None + * @return None + * @details This macro clear Brown-out detector interrupt flag. + */ +#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCR |= SYS_BODCR_BOD_INTF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCR &= ~SYS_BODCR_BOD_LPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + */ +#define SYS_DISABLE_BOD() (SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + */ +#define SYS_ENABLE_BOD() (SYS->BODCR |= SYS_BODCR_BOD_EN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCR & SYS_BODCR_BOD_INTF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0. + * @retval >=1 System voltage is lower than BOD_VL setting. + * @details This macro get Brown-out detector output status. + * If the BOD_EN is 0, this function always return 0. + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCR & SYS_BODCR_BOD_OUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCR &= ~SYS_BODCR_BOD_RSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCR |= SYS_BODCR_BOD_RSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + */ +#define SYS_SET_BOD_LPM() (SYS->BODCR |= SYS_BODCR_BOD_LPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCR_BOD_VL_4_4V + * - \ref SYS_BODCR_BOD_VL_3_7V + * - \ref SYS_BODCR_BOD_VL_2_7V + * - \ref SYS_BODCR_BOD_VL_2_2V + * @return None + * @details This macro set Brown-out detector voltage level. + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + */ +#define SYS_IS_BOD_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_BOD_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + */ +#define SYS_IS_CPU_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_CPU_Msk) + +/** + * @brief Get reset source is from Low-Voltage-Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + */ +#define SYS_IS_LVR_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_LVR_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + */ +#define SYS_IS_POR_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_POR_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_RESET_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_SYS_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + */ +#define SYS_IS_WDT_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_WDT_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + */ +#define SYS_DISABLE_LVR() (SYS->BODCR &= ~SYS_BODCR_LVR_EN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + */ +#define SYS_ENABLE_LVR() (SYS->BODCR |= SYS_BODCR_LVR_EN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + */ +#define SYS_DISABLE_POR() (SYS->PORCR = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + */ +#define SYS_ENABLE_POR() (SYS->PORCR = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including: + * - \ref SYS_RSTSRC_RSTS_CPU_Msk + * - \ref SYS_RSTSRC_RSTS_SYS_Msk + * - \ref SYS_RSTSRC_RSTS_BOD_Msk + * - \ref SYS_RSTSRC_RSTS_LVR_Msk + * - \ref SYS_RSTSRC_RSTS_WDT_Msk + * - \ref SYS_RSTSRC_RSTS_RESET_Msk + * - \ref SYS_RSTSRC_RSTS_POR_Msk + * @return None + * @details This macro clear reset source flag. + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSRC = (u32RstSrc) ) + + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function enable register write-protection function. + * To lock the protected register to forbid write access. + */ +static __INLINE void SYS_LockReg(void) +{ + SYS->REGWRPROT = 0; +} + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + * + */ +static __INLINE void SYS_UnlockReg(void) +{ + while(SYS->REGWRPROT != SYS_REGWRPROT_REGPROTDIS_Msk) + { + SYS->REGWRPROT = 0x59; + SYS->REGWRPROT = 0x16; + SYS->REGWRPROT = 0x88; + } +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Device_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif //__SYS_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/timer.h b/BSP/StdDriver/inc/timer.h new file mode 100644 index 0000000..a994d95 --- /dev/null +++ b/BSP/StdDriver/inc/timer.h @@ -0,0 +1,394 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * $Revision: 11 $ + * $Date: 15/05/04 3:58p $ + * @brief Timer driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ + +#define TIMER_ONESHOT_MODE (0UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in one-shot mode */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in periodic mode */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in toggle-output mode */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in continuous counting mode */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to get timer counter value */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to reset timer counter */ +#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Falling edge trigger timer capture */ +#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Rising edge trigger timer capture */ +#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Both falling and rising edge trigger timer capture */ +#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on falling edge */ +#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on rising edge */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compare Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set new Timer compared value. + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->TCMPR = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set new Timer prescale value. + * @note Clock input is divided by (prescale + 1) before it is fed into timer. + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->TCSR = ((timer)->TCSR & ~TIMER_TCSR_PRESCALE_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer channel is inactive or active. + */ +#define TIMER_IS_ACTIVE(timer) ((timer)->TCSR & TIMER_TCSR_CACT_Msk ? 1 : 0) + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +static __INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->TCSR |= TIMER_TCSR_CEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +static __INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->TCSR &= ~TIMER_TCSR_CEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wakeup Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the Timer interrupt wake-up function. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +static __INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->TCSR |= TIMER_TCSR_WAKE_EN_Msk; +} + +/** + * @brief Disable Timer Wakeup Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the Timer interrupt wake-up function. + */ +static __INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->TCSR &= ~TIMER_TCSR_WAKE_EN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the capture pin detection de-bounce function. + */ +static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->TEXCON |= TIMER_TEXCON_TEXDB_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the capture pin detection de-bounce function. + */ +static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->TEXCON &= ~TIMER_TEXCON_TEXDB_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the counter pin detection de-bounce function. + */ +static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->TEXCON |= TIMER_TEXCON_TCDB_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the counter pin detection de-bounce function. + */ +static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->TEXCON &= ~TIMER_TEXCON_TCDB_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the Timer time-out interrupt function. + */ +static __INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->TCSR |= TIMER_TCSR_IE_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the Timer time-out interrupt function. + */ +static __INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->TCSR &= ~TIMER_TCSR_IE_Msk; +} + +/** + * @brief Enable Capture Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the Timer capture trigger interrupt function. + */ +static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->TEXCON |= TIMER_TEXCON_TEXIEN_Msk; +} + +/** + * @brief Disable Capture Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the Timer capture trigger interrupt function. + */ +static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->TEXCON &= ~TIMER_TEXCON_TEXIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates Timer time-out interrupt occurred or not. + */ +static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return (timer->TISR & TIMER_TISR_TIF_Msk ? 1 : 0); +} + +/** + * @brief Clear Timer time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears Timer time-out interrupt flag. + */ +static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->TISR = TIMER_TISR_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates Timer capture interrupt occurred or not. + */ +static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->TEXISR; +} + +/** + * @brief Clear Timer capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears Timer capture interrupt flag. + */ +static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->TEXISR = TIMER_TEXISR_TEXIF_Msk; +} + +/** + * @brief Get Timer Wakeup Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer did not wake up system + * @retval 1 Timer Timer wake up system + * + * @details This function indicates Timer has waked up system or not. + */ +static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->TISR & TIMER_TISR_TWF_Msk ? 1 : 0); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the Timer wake-up system flag. + */ +static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->TISR = TIMER_TISR_TWF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Capture Value + * + * @details This function reports the current timer capture data value. + */ +static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->TCAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->TDR; +} + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__TIMER_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/uart.h b/BSP/StdDriver/inc/uart.h new file mode 100644 index 0000000..b83c38d --- /dev/null +++ b/BSP/StdDriver/inc/uart.h @@ -0,0 +1,460 @@ +/**************************************************************************//** + * @file UART.h + * @version V3.0 + * $Revision: 27 $ + * $Date: 15/06/04 11:16a $ + * @brief UART Interface Controller Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __UART_H__ +#define __UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART FIFO size constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define UART0_FIFO_SIZE 64 /*!< UART0 supports separated receive/transmit 64/64 bytes entry FIFO */ +#define UART1_FIFO_SIZE 16 /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART2_FIFO_SIZE 16 /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_FCR constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define UART_FCR_RFITL_1BYTE (0x0 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 1 byte */ +#define UART_FCR_RFITL_4BYTES (0x1 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 4 bytes */ +#define UART_FCR_RFITL_8BYTES (0x2 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 8 bytes */ +#define UART_FCR_RFITL_14BYTES (0x3 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 14 bytes */ +#define UART_FCR_RFITL_30BYTES (0x4 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 30 bytes */ +#define UART_FCR_RFITL_46BYTES (0x5 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 46 bytes */ +#define UART_FCR_RFITL_62BYTES (0x6 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 62 bytes */ + +#define UART_FCR_RTS_TRI_LEV_1BYTE (0x0 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 1 byte */ +#define UART_FCR_RTS_TRI_LEV_4BYTES (0x1 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 4 bytes */ +#define UART_FCR_RTS_TRI_LEV_8BYTES (0x2 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 8 bytes */ +#define UART_FCR_RTS_TRI_LEV_14BYTES (0x3 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 14 bytes */ +#define UART_FCR_RTS_TRI_LEV_30BYTES (0x4 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 30 bytes */ +#define UART_FCR_RTS_TRI_LEV_46BYTES (0x5 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 46 bytes */ +#define UART_FCR_RTS_TRI_LEV_62BYTES (0x6 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 62 bytes */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_LCR constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_WORD_LEN_5 (0) /*!< UA_LCR setting to set UART word length to 5 bits */ +#define UART_WORD_LEN_6 (1) /*!< UA_LCR setting to set UART word length to 6 bits */ +#define UART_WORD_LEN_7 (2) /*!< UA_LCR setting to set UART word length to 7 bits */ +#define UART_WORD_LEN_8 (3) /*!< UA_LCR setting to set UART word length to 8 bits */ + +#define UART_PARITY_NONE (0x0 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as no parity */ +#define UART_PARITY_ODD (0x1 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as odd parity */ +#define UART_PARITY_EVEN (0x3 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as even parity */ +#define UART_PARITY_MARK (0x5 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '1' */ +#define UART_PARITY_SPACE (0x7 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '0' */ + +#define UART_STOP_BIT_1 (0x0 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for one stop bit */ +#define UART_STOP_BIT_1_5 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for 1.5 stop bit when 5-bit word length */ +#define UART_STOP_BIT_2 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for two stop bit when 6, 7, 8-bit word length */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART RTS LEVEL TRIGGER constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is Low Level Active */ +#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is High Level Active */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_IRCR constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_IRCR_TX_SELECT (0x1 << UART_IRCR_TX_SELECT_Pos) /*!< Set IrDA function Tx mode */ +#define UART_IRCR_RX_SELECT (0x0 << UART_IRCR_TX_SELECT_Pos) /*!< Set IrDA function Rx mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_FUNC_SEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set UART Function (Default) */ +#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set LIN Function */ +#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set IrDA Function */ +#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set RS485 Function */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_LIN_CTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_LIN_CTL_LINS_EN (0x1UL << UART_LIN_CTL_LINS_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Slave Mode Enable */ +#define UART_LIN_CTL_LINS_HDET_EN (0x1UL << UART_LIN_CTL_LINS_HDET_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Slave Header Detection Enable */ +#define UART_LIN_CTL_LINS_ARS_EN (0x1UL << UART_LIN_CTL_LINS_ARS_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Slave Automatic Resynchronization Mode Enable */ +#define UART_LIN_CTL_LINS_DUM_EN (0x1UL << UART_LIN_CTL_LINS_DUM_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Slave Divider Update Method Enable */ +#define UART_LIN_CTL_LIN_MUTE_EN (0x1UL << UART_LIN_CTL_LIN_MUTE_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Mute Mode Enable */ +#define UART_LIN_CTL_LIN_SHD (0x1UL << UART_LIN_CTL_LIN_SHD_Pos) /*!< UA_LIN_CTL setting to set LIN TX Send Header Enable */ +#define UART_LIN_CTL_LIN_IDPEN (0x1UL << UART_LIN_CTL_LIN_IDPEN_Pos) /*!< UA_LIN_CTL setting to set LIN ID Parity Enable */ +#define UART_LIN_CTL_LIN_BKDET_EN (0x1UL << UART_LIN_CTL_LIN_BKDET_EN_Pos) /*!< UA_LIN_CTL setting to set LIN Break Detection Enable */ +#define UART_LIN_CTL_LIN_RX_DIS (0x1UL << UART_LIN_CTL_LIN_RX_DIS_Pos) /*!< UA_LIN_CTL setting to set LIN Receiver Disable */ +#define UART_LIN_CTL_BIT_ERR_EN (0x1UL << UART_LIN_CTL_BIT_ERR_EN_Pos) /*!< UA_LIN_CTL setting to set Bit Error Detect Enable */ +#define UART_LIN_CTL_LIN_BKFL(x) (((x)-1) << UART_LIN_CTL_LIN_BKFL_Pos) /*!< UA_LIN_CTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */ +#define UART_LIN_CTL_LIN_BS_LEN(x) (((x)-1) << UART_LIN_CTL_LIN_BS_LEN_Pos)/*!< UA_LIN_CTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */ +#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK (0x0UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos) /*!< UA_LIN_CTL setting to set LIN Header Select to break field */ +#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK_SYNC (0x1UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos) /*!< UA_LIN_CTL setting to set LIN Header Select to break field and sync field */ +#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK_SYNC_ID (0x2UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos) /*!< UA_LIN_CTL setting to set LIN Header Select to break field, sync field and ID field*/ +#define UART_LIN_CTL_LIN_LIN_PID(x) ((x) << UART_LIN_CTL_LIN_PID_Pos) /*!< UA_LIN_CTL setting to set LIN PID value */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART BAUDRATE MODE constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */ +#define UART_BAUD_MODE2 (UART_BAUD_DIV_X_EN_Msk | UART_BAUD_DIV_X_ONE_Msk) /*!< Set UART Baudrate Mode is Mode2 */ + + +/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode0 divider + * + * @details This macro calculate UART baudrate mode0 divider. + */ +#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8)) / (u32BaudRate) >> 4)-2) + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2)) / (u32BaudRate))-2) + + +/** + * @brief Write data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UART_WRITE(uart, u8Data) ((uart)->THR = (u8Data)) + +/** + * @brief Read data + * + * @param[in] uart The pointer of the specified UART module. + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + */ +#define UART_READ(uart) ((uart)->RBR) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Tx empty register value. + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FSR & UART_FSR_TX_EMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Rx empty register value. + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FSR & UART_FSR_RX_EMPTY_Msk) + +/** + * @brief Check specified uart port transmission is over. + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Transmission is not over. + * @retval 1 Transmission is over. + * + * @details This macro return if Tx FIFO is empty and specified uart port transmission is over nor not. + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FSR & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos) + + +/** + * @brief Wait specified uart port transmission is over + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details This macro wait specified uart port transmission is over. + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FSR) & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos)) + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + */ +#define UART_IS_RX_READY(uart) (((uart)->ISR & UART_ISR_RDA_IF_Msk)>>UART_ISR_RDA_IF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + */ +#define UART_IS_TX_FULL(uart) (((uart)->FSR & UART_FSR_TX_FULL_Msk)>>UART_FSR_TX_FULL_Pos) + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + */ +#define UART_IS_RX_FULL(uart) (((uart)->FSR & UART_FSR_RX_FULL_Msk)>>UART_FSR_RX_FULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + */ +#define UART_GET_TX_FULL(uart) ((uart)->FSR & UART_FSR_TX_FULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + */ +#define UART_GET_RX_FULL(uart) ((uart)->FSR & UART_FSR_RX_FULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32eIntSel Interrupt type select + * - UART_IER_LIN_IEN_Msk : Lin bus interrupt + * - UART_IER_WAKE_EN_Msk : Wakeup interrupt + * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt + * - UART_IER_TOUT_IEN_Msk : Rx time-out interrupt + * - UART_IER_MODEM_IEN_Msk : Modem interrupt + * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt + * - UART_IER_THRE_IEN_Msk : Tx empty interrupt + * - UART_IER_RDA_IEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->IER |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32eIntSel Interrupt type select + * - UART_IER_LIN_IEN_Msk : Lin bus interrupt + * - UART_IER_WAKE_EN_Msk : Wakeup interrupt + * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt + * - UART_IER_TOUT_IEN_Msk : Rx time-out interrupt + * - UART_IER_MODEM_IEN_Msk : Modem interrupt + * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt + * - UART_IER_THRE_IEN_Msk : Tx empty interrupt + * - UART_IER_RDA_IEN_Msk : Rx ready interrupt + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->IER &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt indicator status + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - UART_ISR_HW_BUF_ERR_INT_Msk : In DMA Mode, Buffer Error Interrupt Indicator + * - UART_ISR_HW_TOUT_INT_Msk : In DMA Mode, Rx Time-out Interrupt Indicator + * - UART_ISR_HW_MODEM_INT_Msk : In DMA Mode, MODEM Status Interrupt Indicator + * - UART_ISR_HW_RLS_INT_Msk : In DMA Mode, Rx Line Status Interrupt Indicator + * - UART_ISR_HW_BUF_ERR_IF_Msk : In DMA Mode, Buffer Error Interrupt Flag + * - UART_ISR_HW_TOUT_IF_Msk : In DMA Mode, Rx Time-out Interrupt Flag + * - UART_ISR_HW_MODEM_IF_Msk : In DMA Mode, MODEM Status Interrupt Flag + * - UART_ISR_HW_RLS_IF_Msk : In DMA Mode, Rx Line Status Interrupt Flag + * - UART_ISR_LIN_INT_Msk : LIN Bus Interrupt Indicator + * - UART_ISR_BUF_ERR_INT_Msk : Buffer Error Interrupt Indicator + * - UART_ISR_TOUT_INT_Msk : Rx Time-out Interrupt Indicator + * - UART_ISR_MODEM_INT_Msk : MODEM Status Interrupt Indicator + * - UART_ISR_RLS_INT_Msk : Rx Line Status Interrupt Indicator + * - UART_ISR_THRE_INT_Msk : Tx Empty Interrupt Indicator + * - UART_ISR_RDA_INT_Msk : Rx Ready Interrupt Indicator + * - UART_ISR_LIN_IF_Msk : LIN Bus Interrupt Flag + * - UART_ISR_BUF_ERR_IF_Msk : Buffer Error Interrupt Flag + * - UART_ISR_TOUT_IF_Msk : Rx Time-out Interrupt Flag + * - UART_ISR_MODEM_IF_Msk : MODEM Status Interrupt Flag + * - UART_ISR_RLS_IF_Msk : Rx Line Status Interrupt Flag + * - UART_ISR_THRE_IF_Msk : Tx Empty Interrupt Flag + * - UART_ISR_RDA_IF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * @retval 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->ISR & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + (uart)->MCR |= UART_MCR_LEV_RTS_Msk; + (uart)->MCR &= ~UART_MCR_RTS_Msk; +} + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + (uart)->MCR |= UART_MCR_LEV_RTS_Msk | UART_MCR_RTS_Msk; +} + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FSR = UART_FSR_RS485_ADD_DETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module. + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FSR & UART_FSR_RS485_ADD_DETF_Msk) >> UART_FSR_RS485_ADD_DETF_Pos) + + +void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes); +void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes); + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__UART_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + diff --git a/BSP/StdDriver/inc/usbd.h b/BSP/StdDriver/inc/usbd.h new file mode 100644 index 0000000..8e30c0b --- /dev/null +++ b/BSP/StdDriver/inc/usbd.h @@ -0,0 +1,668 @@ +/**************************************************************************//** + * @file usbd.h + * @version V3.0 + * $Revision: 17 $ + * $Date: 15/05/28 8:42p $ + * @brief USB driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef __USBD_H__ +#define __USBD_H__ + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ + + +typedef struct s_usbd_info +{ + const uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + const uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + const uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + const uint8_t *gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + +} S_USBD_INFO_T; + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */ + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ + +#define USBD_BUF_BASE (USBD_BASE+0x100) + + + +#define USBD_MAX_EP 6 + +#define EP0 0 /*!< Endpoint 0 */ +#define EP1 1 /*!< Endpoint 1 */ +#define EP2 2 /*!< Endpoint 2 */ +#define EP3 3 /*!< Endpoint 3 */ +#define EP4 4 /*!< Endpoint 4 */ +#define EP5 5 /*!< Endpoint 5 */ + + +/*! b, then return a. Otherwise, return b. + */ +#define Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= (USBD_USB_EN|USBD_PHY_EN))) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->DRVSE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->DRVSE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * + * @details Return USB_ATTR[3:0] for USB bus events. + * + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf)) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->FLDET & USBD_FLDET_FLDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint + * + * @param[in] ep The USB endpoint buffer number. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint. + * + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint + * + * @param[in] ep The USB endpoint buffer number. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQ_SYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint + * + * @param[in] ep The USB endpoint buffer number. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQ_SYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint buffer number. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint buffer number. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint buffer number. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint. + * + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint buffer number. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint. + * + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint buffer number. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint. + * + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID (USB endpoint buffer number). + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID (USB endpoint buffer number). + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID (USB endpoint buffer number). + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size) +{ + while(size--) *dest++ = *src++; +} + + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +static __INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for(i = 0; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +static __INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for(i = 0; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +static __INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for(i = 0; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + + +extern volatile uint8_t g_usbd_RemoteWakeupEn; +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type declaration for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type definition for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type definition for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Device_Driver */ + + +#endif //__USBD_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/wdt.h b/BSP/StdDriver/inc/wdt.h new file mode 100644 index 0000000..682a564 --- /dev/null +++ b/BSP/StdDriver/inc/wdt.h @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * $Revision: 8 $ + * $Date: 15/05/04 3:58p $ + * @brief WDT driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WTCR Constants Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WTCRALT Constants Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clear WDT time-out reset system flag. + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTRF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clear WDT time-out interrupt flag. + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTIF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clear WDT time-out wake-up system flag. + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk)) | WDT_WTCR_WTWKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT did not cause system reset + * @retval 1 WDT caused system reset + * + * @details This macro indicate WDT time-out to reset system or not. + */ +#define WDT_GET_RESET_FLAG() ((WDT->WTCR & WDT_WTCR_WTRF_Msk)? 1 : 0) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicate WDT time-out interrupt occurred or not. + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->WTCR & WDT_WTCR_WTIF_Msk)? 1 : 0) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT did not wake up system + * @retval 1 WDT waked up system + * + * @details This macro indicate WDT time-out waked system up or not + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->WTCR & WDT_WTCR_WTWKF_Msk)? 1 : 0) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset 18-bit WDT counter. + * @note If WDT is activated and enabled to reset system, user must reset WDT counter \n + * before WDT time-out plus reset delay reached. Or WDT generate a reset signal. + */ +#define WDT_RESET_COUNTER() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk | WDT_WTCR_WTRF_Msk)) | WDT_WTCR_WTR_Msk) + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function stops WDT counting and disable WDT module. + */ +static __INLINE void WDT_Close(void) +{ + WDT->WTCR = 0; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function enable the WDT time-out interrupt. + */ +static __INLINE void WDT_EnableInt(void) +{ + WDT->WTCR |= WDT_WTCR_WTIE_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function disables the WDT time-out interrupt. + */ +static __INLINE void WDT_DisableInt(void) +{ + // Do not touch write 1 clear bits + WDT->WTCR &= ~(WDT_WTCR_WTIE_Msk | WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk); + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__WDT_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/inc/wwdt.h b/BSP/StdDriver/inc/wwdt.h new file mode 100644 index 0000000..b4aea7c --- /dev/null +++ b/BSP/StdDriver/inc/wwdt.h @@ -0,0 +1,145 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * $Revision: 9 $ + * $Date: 15/05/04 3:58p $ + * @brief WWDT driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDTCR Constants Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_2 (1 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_4 (2 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_8 (3 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_16 (4 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_32 (5 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_64 (6 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_128 (7 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_192 (8 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_256 (9 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_384 (10 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_512 (11 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_768 (12 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_1024 (13 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_1536 (14 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_2048 (15 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */ + +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDTRLD register to reload WWDT counter */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT counter time-out reset system flag. + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT counter compare match interrupt flag. + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset Flag + * + * @param None + * + * @retval 0 WWDT did not cause system reset + * @retval 1 WWDT counter time-out caused system reset + * + * @details This macro is used to indicate WWDT counter time-out reset system flag. + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->WWDTSR & WWDT_WWDTSR_WWDTRF_Msk)? 1:0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT counter compare match interrupt did not occur + * @retval 1 WWDT counter compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter compare match interrupt occurred or not. + */ +#define WWDT_GET_INT_FLAG() ((WWDT->WWDTSR & WWDT_WWDTSR_WWDTIF_Msk)? 1:0) + +/** + * @brief Get WWDT Counter value + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro to reflects the current WWDT counter value. + */ +#define WWDT_GET_COUNTER() (WWDT->WWDTCVR) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note After WWDT enabled, user must reload WWDT counter while current counter is less than compare value \n + * and larger than 0, otherwise WWDT will cause system reset immediately. + */ +#define WWDT_RELOAD_COUNTER() (WWDT->WWDTRLD = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__WWDT_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/acmp.c b/BSP/StdDriver/src/acmp.c new file mode 100644 index 0000000..ccac17e --- /dev/null +++ b/BSP/StdDriver/src/acmp.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file acmp.c + * @version V3.00 + * $Revision: 8 $ + * $Date: 15/05/04 3:58p $ + * @brief Analog Comparator(ACMP) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NUC200Series.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] Acmp The pointer of the specified ACMP module. + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CR_VNEG_PIN + * - \ref ACMP_CR_VNEG_BANDGAP + * @param[in] u32HysteresisEn The hysteresis function option. Including: + * - \ref ACMP_CR_HYSTERESIS_ENABLE + * - \ref ACMP_CR_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn) +{ + Acmp->CMPCR[u32ChNum] = (Acmp->CMPCR[u32ChNum] & (~(ACMP_CMPCR_CMPCN_Msk | ACMP_CMPCR_CMP_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CMPCR_CMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] Acmp The pointer of the specified ACMP module. + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear CMPEN bit of CMPCR register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum) +{ + Acmp->CMPCR[u32ChNum] &= (~ACMP_CMPCR_CMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + diff --git a/BSP/StdDriver/src/adc.c b/BSP/StdDriver/src/adc.c new file mode 100644 index 0000000..6950163 --- /dev/null +++ b/BSP/StdDriver/src/adc.c @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file adc.c + * @version V3.00 + * $Revision: 10 $ + * $Date: 15/05/04 3:59p $ + * @brief ADC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions + @{ +*/ + +/** + * @brief This function configures ADC module to be ready for convert the input from selected channel. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32InputMode Decides the ADC analog input mode. Valid values are: + * - \ref ADC_ADCR_DIFFEN_SINGLE_END :Single end input mode. + * - \ref ADC_ADCR_DIFFEN_DIFFERENTIAL :Differential input type. + * @param[in] u32OpMode Decides the ADC operation mode. Valid values are: + * - \ref ADC_ADCR_ADMD_SINGLE :Single mode. + * - \ref ADC_ADCR_ADMD_SINGLE_CYCLE :Single cycle scan mode. + * - \ref ADC_ADCR_ADMD_CONTINUOUS :Continuous scan mode. + * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7. + * @return None + * @details Before starting A/D conversion function, ADEN(ADCR[0]) should be set to 1. + * @note NUC200 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel + * with smallest number will be convert. + * @note This function does not turn on ADC power nor does trigger ADC conversion. + */ +void ADC_Open(ADC_T *adc, + uint32_t u32InputMode, + uint32_t u32OpMode, + uint32_t u32ChMask) +{ + (adc)->ADCR = ((adc)->ADCR & (~(ADC_ADCR_DIFFEN_Msk | ADC_ADCR_ADMD_Msk))) | \ + (u32InputMode) | \ + (u32OpMode); + + (adc)->ADCHER = ((adc)->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32ChMask); + + return; +} + +/** + * @brief Disable ADC module. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Disable A/D converter analog circuit for saving power consumption. + */ +void ADC_Close(ADC_T *adc) +{ + (adc)->ADCR &= (~ADC_ADCR_ADEN_Msk); + return; +} + +/** + * @brief Configure the hardware trigger condition and enable hardware trigger. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Source Decides the hardware trigger source. Valid values are: + * - \ref ADC_ADCR_TRGS_STADC :A/D conversion is started by external STADC pin. + * - \ref ADC_ADCR_TRGS_PWM :A/D conversion is started by PWM. + * @param[in] u32Param ADC trigger by external pin, this parameter is used to set trigger condition. Valid values are: + * - \ref ADC_ADCR_TRGCOND_LOW_LEVEL :STADC Low level active. + * - \ref ADC_ADCR_TRGCOND_HIGH_LEVEL :STADC High level active. + * - \ref ADC_ADCR_TRGCOND_FALLING_EDGE :STADC Falling edge active. + * - \ref ADC_ADCR_TRGCOND_RISING_EDGE :STADC Rising edge active. + * @return None + * @details Software should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS(ADCR[5:4]). + */ +void ADC_EnableHWTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32Param) +{ + (adc)->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk); + + (adc)->ADCR |= (u32Source) | (u32Param) | ADC_ADCR_TRGEN_Msk; + + return; +} + +/** + * @brief Disable hardware trigger ADC function. + * @param[in] adc The pointer of the specified ADC module. + * @return None + * @details Disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger). + */ +void ADC_DisableHWTrigger(ADC_T *adc) +{ + (adc)->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk); + return; +} + +/** + * @brief Enable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit + * corresponds to a interrupt status. This parameter decides which + * interrupts will be enabled. + * - \ref ADC_ADF_INT :ADC convert complete interrupt. + * - \ref ADC_CMP0_INT :ADC comparator 0 interrupt. + * - \ref ADC_CMP1_INT :ADC comparator 1 interrupt. + * @return None + * @details A/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1. + * If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) + * and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, in the meanwhile, + * if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is generated. + */ +void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask) +{ + if((u32Mask) & ADC_ADF_INT) + (adc)->ADCR |= ADC_ADCR_ADIE_Msk; + if((u32Mask) & ADC_CMP0_INT) + (adc)->ADCMPR[0] |= ADC_ADCMPR_CMPIE_Msk; + if((u32Mask) & ADC_CMP1_INT) + (adc)->ADCMPR[1] |= ADC_ADCMPR_CMPIE_Msk; + + return; +} + +/** + * @brief Disable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc The pointer of the specified ADC module. + * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit + * corresponds to a interrupt status. This parameter decides which + * interrupts will be disabled. + * - \ref ADC_ADF_INT :ADC convert complete interrupt. + * - \ref ADC_CMP0_INT :ADC comparator 0 interrupt. + * - \ref ADC_CMP1_INT :ADC comparator 1 interrupt. + * @return None + * @details The function is used to disable convert complete interrupt, comparator 0 interrupt or comparator 1 interrupt. + */ +void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask) +{ + if((u32Mask) & ADC_ADF_INT) + (adc)->ADCR &= ~ADC_ADCR_ADIE_Msk; + if((u32Mask) & ADC_CMP0_INT) + (adc)->ADCMPR[0] &= ~ADC_ADCMPR_CMPIE_Msk; + if((u32Mask) & ADC_CMP1_INT) + (adc)->ADCMPR[1] &= ~ADC_ADCMPR_CMPIE_Msk; + + return; +} + + + +/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ADC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/clk.c b/BSP/StdDriver/src/clk.c new file mode 100644 index 0000000..a142dc0 --- /dev/null +++ b/BSP/StdDriver/src/clk.c @@ -0,0 +1,749 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * $Revision: 49 $ + * $Date: 15/10/20 8:30a $ + * @brief CLK driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable frequency output function + * @param None + * @return None + * @details This function disable frequency output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK_DisableModuleClock(FDIV_MODULE); +} + +/** + * @brief This function enable frequency divider module clock. + * enable frequency divider clock function and configure frequency divider. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL2_FRQDIV_S_HXT + * - \ref CLK_CLKSEL2_FRQDIV_S_LXT + * - \ref CLK_CLKSEL2_FRQDIV_S_HCLK + * - \ref CLK_CLKSEL2_FRQDIV_S_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. + * @param[in] u32ClkDivBy1En is not supported. + * @return None + * + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. + * The formula is: + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | u32ClkDiv; + + /* Enable CKO clock source */ + CLK_EnableModuleClock(FDIV_MODULE); + + /* Select CKO clock source */ + CLK_SetModuleClock(FDIV_MODULE, u32ClkSrc, 0); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function let system enter to Power-down mode. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled and Power-down entry condition */ + CLK->PWRCON |= (CLK_PWRCON_PWR_DOWN_EN_Msk | CLK_PWRCON_PD_WAIT_CPU_Msk); + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Enter to Idle mode. + * @param None + * @return None + * @details This function let system enter to Idle mode. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCON &= ~CLK_PWRCON_PWR_DOWN_EN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk) + return __HXT; + else + return 0; +} + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + if(CLK->PWRCON & CLK_PWRCON_XTL32K_EN_Msk) + return __LXT; + else + return 0; +} + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Get PCLK frequency + * @param None + * @return PCLK frequency + * @details This function get PCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency + * @return HCLK frequency + * @details This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 25 MHz ~ 50 MHz. + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + + /* Boundary Check */ + if(u32Hclk > FREQ_50MHZ) + u32Hclk = FREQ_50MHZ; + if(u32Hclk < FREQ_25MHZ) + u32Hclk = FREQ_25MHZ; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + while((CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk) == 0); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC; + + /* Disable PLL to Avoid PLL Unstable while Setting */ + CLK->PLLCON |= CLK_PLLCON_PD_Msk; + + /* Configure PLL setting if HXT clock is stable */ + if(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not stable */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + } + + CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0) + CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk; + + return u32Hclk; +} + +/** + * @brief Set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLK_S_HXT + * - \ref CLK_CLKSEL0_HCLK_S_LXT + * - \ref CLK_CLKSEL0_HCLK_S_PLL + * - \ref CLK_CLKSEL0_HCLK_S_LIRC + * - \ref CLK_CLKSEL0_HCLK_S_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + while((CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk) == 0); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC; + + /* Apply new Divider */ + CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | u32ClkDiv; + + /* Switch to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0) + CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk; +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :---------------------------------- | :--------------------- | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_LIRC | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_HCLK_DIV2048 | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_LXT | x | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HXT |\ref CLK_CLKDIV_ADC(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_PLL |\ref CLK_CLKDIV_ADC(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HCLK |\ref CLK_CLKDIV_ADC(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HIRC |\ref CLK_CLKDIV_ADC(x) | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_HCLK | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_HCLK | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2_S_HCLK | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2_S_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3_S_HCLK | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3_S_PLL | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HCLK | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_EXT_TRG | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HCLK | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_EXT_TRG | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HCLK | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_EXT_TRG | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HCLK | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_EXT_TRG | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HIRC | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) | + * |\ref PWM01_MODULE |\ref CLK_CLKSEL_PWM01_HXT | x | + * |\ref PWM01_MODULE |\ref CLK_CLKSEL_PWM01_LXT | x | + * |\ref PWM01_MODULE |\ref CLK_CLKSEL_PWM01_HCLK | x | + * |\ref PWM01_MODULE |\ref CLK_CLKSEL_PWM01_HIRC | x | + * |\ref PWM01_MODULE |\ref CLK_CLKSEL_PWM01_LIRC | x | + * |\ref PWM23_MODULE |\ref CLK_CLKSEL_PWM23_HXT | x | + * |\ref PWM23_MODULE |\ref CLK_CLKSEL_PWM23_LXT | x | + * |\ref PWM23_MODULE |\ref CLK_CLKSEL_PWM23_HCLK | x | + * |\ref PWM23_MODULE |\ref CLK_CLKSEL_PWM23_HIRC | x | + * |\ref PWM23_MODULE |\ref CLK_CLKSEL_PWM23_LIRC | x | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HXT | x | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_PLL | x | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HCLK | x | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HIRC | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HXT | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_LXT | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HCLK | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HIRC | x | + * |\ref PWM45_MODULE |\ref CLK_CLKSEL_PWM45_HXT | x | + * |\ref PWM45_MODULE |\ref CLK_CLKSEL_PWM45_LXT | x | + * |\ref PWM45_MODULE |\ref CLK_CLKSEL_PWM45_HCLK | x | + * |\ref PWM45_MODULE |\ref CLK_CLKSEL_PWM45_HIRC | x | + * |\ref PWM45_MODULE |\ref CLK_CLKSEL_PWM45_LIRC | x | + * |\ref PWM67_MODULE |\ref CLK_CLKSEL_PWM67_HXT | x | + * |\ref PWM67_MODULE |\ref CLK_CLKSEL_PWM67_LXT | x | + * |\ref PWM67_MODULE |\ref CLK_CLKSEL_PWM67_HCLK | x | + * |\ref PWM67_MODULE |\ref CLK_CLKSEL_PWM67_HIRC | x | + * |\ref PWM67_MODULE |\ref CLK_CLKSEL_PWM67_LIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL2_WWDT_S_HCLK_DIV2048 | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL2_WWDT_S_LIRC | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0_S_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0_S_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0_S_HCLK |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0_S_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1_S_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1_S_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1_S_HCLK |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1_S_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2_S_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2_S_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2_S_HCLK |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2_S_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref USBD_MODULE | x |\ref CLK_CLKDIV_USB(x) | + */ + +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32sel = 0, u32div = 0; + uint32_t u32SelTbl[4] = {0x0, 0x4, 0xC, 0x24}; + uint32_t u32DivTbl[2] = {0x0, 0x20}; + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Set new clock selection setting */ + M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + + /* We need to set CLKSEL2 ext control bit for PWM */ + if(u32ModuleIdx == PWM01_MODULE) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM01_S_E_Msk)) | (u32ClkSrc & CLK_CLKSEL2_PWM01_S_E_Msk); + else if(u32ModuleIdx == PWM23_MODULE) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM23_S_E_Msk)) | (u32ClkSrc & CLK_CLKSEL2_PWM23_S_E_Msk); + else if(u32ModuleIdx == PWM45_MODULE) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM45_S_E_Msk)) | (u32ClkSrc & CLK_CLKSEL2_PWM45_S_E_Msk); + else if(u32ModuleIdx == PWM67_MODULE) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM67_S_E_Msk)) | (u32ClkSrc & CLK_CLKSEL2_PWM67_S_E_Msk); + } + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32div = (uint32_t)&CLK->CLKDIV + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Apply new divider */ + M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLK_S_HXT + * - \ref CLK_CLKSEL0_STCLK_S_LXT + * - \ref CLK_CLKSEL0_STCLK_S_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLK_S_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLK_S_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCON_XTL12M_EN_Msk + * - \ref CLK_PWRCON_XTL32K_EN_Msk + * - \ref CLK_PWRCON_OSC22M_EN_Msk + * - \ref CLK_PWRCON_OSC10K_EN_Msk + * @return None + * @details This function enable clock source. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCON |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCON_XTL12M_EN_Msk + * - \ref CLK_PWRCON_XTL32K_EN_Msk + * - \ref CLK_PWRCON_OSC22M_EN_Msk + * - \ref CLK_PWRCON_OSC10K_EN_Msk + * @return None + * @details This function disable clock source. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCON &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref FDIV_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref PWM01_MODULE + * - \ref PWM23_MODULE + * - \ref PWM45_MODULE + * - \ref PWM67_MODULE + * - \ref USBD_MODULE + * - \ref ADC_MODULE + * - \ref I2S_MODULE + * - \ref ACMP_MODULE + * - \ref PS2_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * @return None + * @details This function enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32OffsetTbl[4] = {0x0, 0x4, 0x2C, 0x0}; + + *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + u32OffsetTbl[MODULE_APBCLK(u32ModuleIdx)]) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx); +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref FDIV_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref PWM01_MODULE + * - \ref PWM23_MODULE + * - \ref PWM45_MODULE + * - \ref PWM67_MODULE + * - \ref USBD_MODULE + * - \ref ADC_MODULE + * - \ref I2S_MODULE + * - \ref ACMP_MODULE + * - \ref PS2_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * @return None + * @details This function disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32OffsetTbl[4] = {0x0, 0x4, 0x2C, 0x0}; + + *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + u32OffsetTbl[MODULE_APBCLK(u32ModuleIdx)]) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx)); +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCON_PLL_SRC_HXT + * - \ref CLK_PLLCON_PLL_SRC_HIRC + * @param[in] u32PllFreq is PLL frequency + * @return PLL frequency + * @details This function set PLL frequency. + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; + + /* Disable PLL first to avoid unstable when setting PLL. */ + CLK->PLLCON = CLK_PLLCON_PD_Msk; + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); + + /* Select PLL source clock from HXT */ + u32CLK_SRC = CLK_PLLCON_PLL_SRC_HXT; + u32PllSrcClk = __HXT; + + /* u32NR start from 2 */ + u32NR = 2; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); + + /* Select PLL source clock from HIRC */ + u32CLK_SRC = CLK_PLLCON_PLL_SRC_HIRC; + u32PllSrcClk = __HIRC; + + /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ + u32NR = 4; + } + + /* Select "NO" according to request frequency */ + if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq > FREQ_100MHZ)) + { + u32NO = 0; + } + else if((u32PllFreq <= FREQ_100MHZ) && (u32PllFreq > FREQ_50MHZ)) + { + u32NO = 1; + u32PllFreq = u32PllFreq << 1; + } + else if((u32PllFreq <= FREQ_50MHZ) && (u32PllFreq >= FREQ_25MHZ)) + { + u32NO = 3; + u32PllFreq = u32PllFreq << 2; + } + else + { + /* Wrong frequency request. Just return default setting. */ + goto lexit; + } + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinNR = 0; + u32MinNF = 0; + for(; u32NR <= 33; u32NR++) + { + u32Tmp = u32PllSrcClk / u32NR; + if((u32Tmp > 1600000) && (u32Tmp < 15000000)) + { + for(u32NF = 2; u32NF <= 513; u32NF++) + { + u32Tmp2 = u32Tmp * u32NF; + if((u32Tmp2 >= 100000000) && (u32Tmp2 <= 200000000)) + { + u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + + /* Break when get good results */ + if(u32Min == 0) + break; + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCON = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2); + + /* Waiting for PLL clock stable */ + CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk); + + /* Return actual PLL output clock frequency */ + return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF; + +lexit: + + /* Apply default PLL setting and return */ + if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT) + CLK->PLLCON = 0xC22E; /* 48MHz */ + else + CLK->PLLCON = 0x8D66F; /* 48.06498462MHz */ + + CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk); + return CLK_GetPLLClockFreq(); + + +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function disable PLL. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCON |= CLK_PLLCON_PD_Msk; +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_CLKSTATUS_XTL12M_STB_Msk + * - \ref CLK_CLKSTATUS_XTL32K_STB_Msk + * - \ref CLK_CLKSTATUS_OSC22M_STB_Msk + * - \ref CLK_CLKSTATUS_OSC10K_STB_Msk + * - \ref CLK_CLKSTATUS_PLL_STB_Msk + * + * @retval 0 clock is not stable + * @retval 1 clock is stable + * + * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 1200000; + + while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + return 0; + } + + return 1; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLK_S_HXT + * - \ref CLK_CLKSEL0_STCLK_S_LXT + * - \ref CLK_CLKSEL0_STCLK_S_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLK_S_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLK_S_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLK_S_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0; + + /* Set System Tick clock source */ + if( u32ClkSrc == CLK_CLKSEL0_STCLK_S_HCLK ) + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + else + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | u32ClkSrc; + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/crc.c b/BSP/StdDriver/src/crc.c new file mode 100644 index 0000000..568ca88 --- /dev/null +++ b/BSP/StdDriver/src/crc.c @@ -0,0 +1,102 @@ +/**************************************************************************//** + * @file crc.c + * @version V3.00 + * $Revision: 8 $ + * $Date: 15/05/04 3:59p $ + * @brief CRC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC Polynomial Mode. CRC_CCITT, CRC_8, CRC_16, CRC_32 + * @param[in] u32Attribute Parameter attribute. CRC_CHECKSUM_COM, CRC_CHECKSUM_RVS, CRC_WDATA_COM, CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. CRC_CPU_WDATA_8, CRC_CPU_WDATA_16, CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function enable the CRC channel by specify CRC mode, attribute, initial seed and write data length. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + /* Enable CRC channel clock */ + PDMA_GCR->GCRCSR |= PDMA_GCRCSR_CRC_CLK_EN_Msk; + + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCCEN_Msk; + + /* Setting RST bit will reload the initial seed value (CRC_SEED register) */ + CRC->CTL |= CRC_CTL_CRC_RST_Msk; +} + +/** + * @brief CRC Start DMA transfer + * + * @param[in] u32SrcAddr Source address + * @param[in] u32ByteCount Calculate byte count + * + * @return None + * + * @details This function start CRC DMA transfer from specify source address and byte counts. + */ +void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount) +{ + CRC->DMASAR = u32SrcAddr; + CRC->DMABCR = u32ByteCount; + CRC->CTL |= CRC_CTL_TRIG_EN_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum + * + * @details This macro get the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + switch(CRC->CTL & CRC_CTL_CRC_MODE_Msk) + { + case CRC_CCITT: + case CRC_16: + return (CRC->CHECKSUM & 0xFFFF); + + case CRC_32: + return (CRC->CHECKSUM); + + case CRC_8: + return (CRC->CHECKSUM & 0xFF); + + default: + return 0; + } +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/fmc.c b/BSP/StdDriver/src/fmc.c new file mode 100644 index 0000000..a27ba95 --- /dev/null +++ b/BSP/StdDriver/src/fmc.c @@ -0,0 +1,282 @@ +/**************************************************************************//** + * @file fmc.c + * @version V3.00 + * $Revision: 8 $ + * $Date: 15/05/04 3:59p $ + * @brief FMC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +//* Includes ------------------------------------------------------------------*/ +#include +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * + * @param[in] i32BootSrc + * 1: Boot from LDROM, + * 0: Boot from APROM + * + * @return None + * + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + * + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + FMC->ISPCON |= FMC_ISPCON_BS_Msk; /* Boot from LDROM */ + else + FMC->ISPCON &= ~FMC_ISPCON_BS_Msk;/* Boot from APROM */ +} + + +/** + * @brief Disable ISP Functions + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCON to disable ISP function + * + */ +void FMC_Close(void) +{ + FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk; +} + + +/** + * @brief Disable APROM update function + * + * @param None + * + * @return None + * + * @details Disable APROM update function will forbid APROM programming when boot form APROM. + * APROM update is default to be disable. + * + */ +void FMC_DisableAPUpdate(void) +{ + FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk; +} + + +/** + * @brief Disable User Configuration update function + * + * @param None + * + * @return None + * + * @details Disable User Configuration update function will forbid User Configuration programming. + * User Configuration update is default to be disable. + */ +void FMC_DisableConfigUpdate(void) +{ + FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk; +} + + +/** + * @brief Disable LDROM update function + * + * @param None + * + * @return None + + * @details Disable LDROM update function will forbid LDROM programming. + * LDROM update is default to be disable. + */ +void FMC_DisableLDUpdate(void) +{ + FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk; +} + + +/** + * @brief Enable APROM update function + * + * @param None + * + * @return None + * + * @details Enable APROM to be able to program when boot from APROM. + * + */ +void FMC_EnableAPUpdate(void) +{ + FMC->ISPCON |= FMC_ISPCON_APUEN_Msk; +} + + +/** + * @brief Enable User Configuration update function + * + * @param None + * + * @return None + * + * @details Enable User Configuration to be able to program. + * + */ +void FMC_EnableConfigUpdate(void) +{ + FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk; +} + + +/** + * @brief Enable LDROM update function + * + * @param None + * + * @return None + * + * @details Enable LDROM to be able to program. + * + */ +void FMC_EnableLDUpdate(void) +{ + FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk; +} + + +/** + * @brief Get the current boot source + * + * @param None + * + * @retval 0 This chip is currently booting from APROM + * @retval 1 This chip is currently booting from LDROM + * + * @note This function only show the boot source. + * User need to read ISPSTA register to know if IAP mode supported or not in relative boot. + */ +int32_t FMC_GetBootSource(void) +{ + if(FMC->ISPCON & FMC_ISPCON_BS_Msk) + return 1; + else + return 0; +} + + +/** + * @brief Enable FMC ISP function + * + * @param None + * + * @return None + * + * @details ISPEN bit of ISPCON must be set before we can use ISP commands. + * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions. + * + * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions. + * + */ +void FMC_Open(void) +{ + FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk; +} + +/** + * @brief Get the base address of Data Flash if enabled. + * + * @param None + * + * @return The base address of Data Flash + * + * @details This function is used to return the base address of Data Flash. + * + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBADR; +} + + +/** + * @brief Read the User Configuration words. + * + * @param[out] u32Config The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to be read. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details This function is used to read the settings of user configuration. + * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config. + * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned. + */ +int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count) +{ + int32_t i; + + for(i = 0; i < u32Count; i++) + u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4); + + return 0; +} + + +/** + * @brief Write User Configuration + * + * @param[in] u32Config The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to program to User Configuration. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details User must enable User Configuration update before writing it. + * User must erase User Configuration before writing it. + * User Configuration is also be page erase. User needs to backup necessary data + * before erase User Configuration. + */ +int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count) +{ + int32_t i; + + for(i = 0; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]); + if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i]) + return -1; + } + + return 0; +} + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + + diff --git a/BSP/StdDriver/src/gpio.c b/BSP/StdDriver/src/gpio.c new file mode 100644 index 0000000..268460b --- /dev/null +++ b/BSP/StdDriver/src/gpio.c @@ -0,0 +1,100 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * $Revision: 9 $ + * $Date: 15/05/04 3:59p $ + * @brief GPIO driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PE GPIO port. + * It could be BIT0 ~ BIT3 for PF GPIO port. + * @param[in] u32Mode Operation mode. . It could be \n + * GPIO_PMD_INPUT, GPIO_PMD_OUTPUT, GPIO_PMD_OPEN_DRAIN, GPIO_PMD_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1 << i)) + { + port->PMD = (port->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + port->IEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD and PE GPIO port. + * It could be 0 ~ 3 for PF GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + port->IMD &= ~(1UL << u32Pin); + port->IEN &= ~((0x00010001UL) << u32Pin); +} + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/i2c.c b/BSP/StdDriver/src/i2c.c new file mode 100644 index 0000000..fb38680 --- /dev/null +++ b/BSP/StdDriver/src/i2c.c @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * $Revision: 14 $ + * $Date: 15/05/20 11:55a $ + * @brief I2C driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + + u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */ + i2c->I2CLK = u32Div; + + /* Enable I2C */ + i2c->I2CON |= I2C_I2CON_ENS1_Msk; + + return (SystemCoreClock / ((u32Div + 1) << 2)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRSTC2 |= SYS_IPRSTC2_I2C0_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_I2C0_RST_Msk; + } + else if((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRSTC2 |= SYS_IPRSTC2_I2C1_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_I2C1_RST_Msk; + } + + /* Disable I2C */ + i2c->I2CON &= ~I2C_I2CON_ENS1_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out Counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->I2CTOC |= I2C_I2CTOC_TIF_Msk; +} + +/** + * @brief Set control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0; + + if(u8Start) + u32Reg |= I2C_I2CON_STA; + if(u8Stop) + u32Reg |= I2C_I2CON_STO; + if(u8Si) + u32Reg |= I2C_I2CON_SI; + if(u8Ack) + u32Reg |= I2C_I2CON_AA; + + i2c->I2CON = (i2c->I2CON & ~0x3C) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->I2CON &= ~I2C_I2CON_EI_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->I2CON |= I2C_I2CON_EI_Msk; +} + +/** + * @brief Get I2C Bus clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->I2CLK; + + return (SystemCoreClock / ((u32Divider + 1) << 2)); +} + +/** + * @brief Set I2C Bus clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus clock in Hz + * + * @return The actual I2C Bus clock in Hz + * + * @details To set the actual I2C Bus clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + + u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */ + i2c->I2CLK = u32Div; + + return (SystemCoreClock / ((u32Div + 1) << 2)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + return ((i2c->I2CON & I2C_I2CON_SI_Msk) == I2C_I2CON_SI_Msk ? 1 : 0); +} + +/** + * @brief Get I2C bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->I2CSTATUS); +} + +/** + * @brief Read a byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a byte data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (i2c->I2CDAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c I2C port + * @param[in] u8Data The data to send to I2C Bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->I2CDAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC Mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->I2CADDR1 = (u8SlaveAddr << 1) | u8GCMode; + break; + case 2: + i2c->I2CADDR2 = (u8SlaveAddr << 1) | u8GCMode; + break; + case 3: + i2c->I2CADDR3 = (u8SlaveAddr << 1) | u8GCMode; + break; + case 0: + default: + i2c->I2CADDR0 = (u8SlaveAddr << 1) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->I2CADM1 = u8SlaveAddrMask << 1; + break; + case 2: + i2c->I2CADM2 = u8SlaveAddrMask << 1; + break; + case 3: + i2c->I2CADM3 = u8SlaveAddrMask << 1; + break; + case 0: + default: + i2c->I2CADM0 = u8SlaveAddrMask << 1; + break; + } +} + +/** + * @brief Enable Time-out Counter function and support Long Time-out + * + * @param[in] i2c I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + i2c->I2CTOC |= I2C_I2CTOC_DIV4_Msk; + else + i2c->I2CTOC &= ~I2C_I2CTOC_DIV4_Msk; + + i2c->I2CTOC |= I2C_I2CTOC_ENTI_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c I2C port + * + * @return None + * + * @details To disable Time-out counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->I2CTOC &= ~I2C_I2CTOC_ENTI_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->I2CWKUPCON |= I2C_I2CWKUPCON_WKUPEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->I2CWKUPCON &= ~I2C_I2CWKUPCON_WKUPEN_Msk; +} + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/i2s.c b/BSP/StdDriver/src/i2s.c new file mode 100644 index 0000000..99c447e --- /dev/null +++ b/BSP/StdDriver/src/i2s.c @@ -0,0 +1,204 @@ +/**************************************************************************//** + * @file i2s.c + * @version V3.0 + * $Revision: 15 $ + * $Date: 15/05/04 3:59p $ + * @brief I2S driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of I2S_S (CLKSEL2[1:0]). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_I2S_S_Msk; + + switch(u32ClkSrcSel) + { + case CLK_CLKSEL2_I2S_S_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL2_I2S_S_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL2_I2S_S_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL2_I2S_S_HCLK: + u32Freq = SystemCoreClock; + break; + + default: + u32Freq = __HIRC; + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are: + * - \ref I2S_MONO + * - \ref I2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_MSB + * @return Real sample rate. + * @details This function will configure I2S controller according to the input parameters. Set TX and RX FIFO threshold to middle value. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note Both the TX and RX functions will be enabled. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint8_t u8Divider; + uint32_t u32BitRate, u32SrcClk; + + /* Reset I2S */ + SYS->IPRSTC2 |= SYS_IPRSTC2_I2S_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_I2S_RST_Msk; + + /* Configure I2S controller according to input parameters. */ + i2s->CON = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4; + + /* Get I2S source clock frequency */ + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + /* Calculate bit clock rate */ + u32BitRate = u32SampleRate * (((u32WordWidth >> 4) & 0x3) + 1) * 16; + u8Divider = ((u32SrcClk / u32BitRate) >> 1) - 1; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLK_DIV_Msk) | (u8Divider << 8); + + /* Calculate real sample rate */ + u32BitRate = u32SrcClk / ((u8Divider + 1) * 2); + u32SampleRate = u32BitRate / ((((u32WordWidth >> 4) & 0x3) + 1) * 16); + + /* Enable TX, RX and I2S controller */ + i2s->CON |= (I2S_CON_RXEN_Msk | I2S_CON_TXEN_Msk | I2S_CON_I2SEN_Msk); + + return u32SampleRate; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CON &= ~I2S_CON_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function enables the interrupt according to the mask parameter. + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IE |= u32Mask; +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function disables the interrupt according to the mask parameter. + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IE &= ~u32Mask; +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock. + * @return Actual MCLK clock + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + u8Divider = 0; + else + u8Divider = (u32SrcClk / u32BusClock) >> 1; + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLK_DIV_Msk) | u8Divider; + + i2s->CON |= I2S_CON_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLK_DIV_Msk; + + if(u32Reg == 0) + return u32SrcClk; + else + return ((u32SrcClk >> 1) / u32Reg); +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable master clock output. + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CON &= ~I2S_CON_MCLKEN_Msk; +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/pdma.c b/BSP/StdDriver/src/pdma.c new file mode 100644 index 0000000..044b81a --- /dev/null +++ b/BSP/StdDriver/src/pdma.c @@ -0,0 +1,284 @@ +/**************************************************************************//** + * @file pdma.c + * @version V3.00 + * $Revision: 9 $ + * $Date: 15/05/04 3:59p $ + * @brief PDMA driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(uint32_t u32Mask) +{ + PDMA_GCR->GCRCSR |= (u32Mask << 8); +} + +/** + * @brief PDMA Close + * + * @param None + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(void) +{ + PDMA_GCR->GCRCSR = 0; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width; + switch(u32Width) + { + case PDMA_WIDTH_32: + pdma->BCR = (u32TransCount << 2); + break; + + case PDMA_WIDTH_8: + pdma->BCR = u32TransCount; + break; + + case PDMA_WIDTH_16: + pdma->BCR = (u32TransCount << 1); + break; + + default: + ; + } +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + + pdma->SAR = u32SrcAddr; + pdma->DAR = u32DstAddr; + pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk | PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART1_TX + * - \ref PDMA_I2S_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_RX + * - \ref PDMA_I2S_RX + * - \ref PDMA_ADC + * - \ref PDMA_MEM + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + uint32_t u32Index = 0; + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + + if(u32Peripheral > PDMA_ADC) /* Memory-to-Memory */ + pdma->CSR = (pdma->CSR & ~(PDMA_CSR_MODE_SEL_Msk)); + else if(u32Peripheral > PDMA_I2S_TX) /* Peripheral-to-Memory */ + pdma->CSR = (pdma->CSR & ~(PDMA_CSR_MODE_SEL_Msk) | (0x1 << PDMA_CSR_MODE_SEL_Pos)); + else /* Memory-to-Peripheral */ + pdma->CSR = (pdma->CSR & ~(PDMA_CSR_MODE_SEL_Msk) | (0x2 << PDMA_CSR_MODE_SEL_Pos)); + + switch(u32Peripheral) + { + case 0: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI0_TXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI0_TXSEL_Pos); + break; + case 1: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI1_TXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI1_TXSEL_Pos); + break; + case 2: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI2_TXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI2_TXSEL_Pos); + break; + case 3: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI3_TXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI3_TXSEL_Pos); + break; + case 4: + PDMA_GCR->PDSSR1 = (PDMA_GCR->PDSSR1 & ~PDMA_PDSSR1_UART0_TXSEL_Msk) | (u32Ch << PDMA_PDSSR1_UART0_TXSEL_Pos); + break; + case 5: + PDMA_GCR->PDSSR1 = (PDMA_GCR->PDSSR1 & ~PDMA_PDSSR1_UART1_TXSEL_Msk) | (u32Ch << PDMA_PDSSR1_UART1_TXSEL_Pos); + break; + case 6: + PDMA_GCR->PDSSR2 = (PDMA_GCR->PDSSR2 & ~PDMA_PDSSR2_I2S_TXSEL_Msk) | (u32Ch << PDMA_PDSSR2_I2S_TXSEL_Pos); + break; + case 7: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI0_RXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI0_RXSEL_Pos); + break; + case 8: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI1_RXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI1_RXSEL_Pos); + break; + case 9: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI2_RXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI2_RXSEL_Pos); + break; + case 10: + PDMA_GCR->PDSSR0 = (PDMA_GCR->PDSSR0 & ~PDMA_PDSSR0_SPI3_RXSEL_Msk) | (u32Ch << PDMA_PDSSR0_SPI3_RXSEL_Pos); + break; + case 11: + PDMA_GCR->PDSSR1 = (PDMA_GCR->PDSSR1 & ~PDMA_PDSSR1_UART0_RXSEL_Msk) | (u32Ch << PDMA_PDSSR1_UART0_RXSEL_Pos); + break; + case 12: + PDMA_GCR->PDSSR1 = (PDMA_GCR->PDSSR1 & ~PDMA_PDSSR1_UART1_RXSEL_Msk) | (u32Ch << PDMA_PDSSR1_UART1_RXSEL_Pos); + break; + case 13: + PDMA_GCR->PDSSR2 = (PDMA_GCR->PDSSR2 & ~PDMA_PDSSR2_I2S_RXSEL_Msk) | (u32Ch << PDMA_PDSSR2_I2S_RXSEL_Pos); + break; + case 14: + PDMA_GCR->PDSSR1 = (PDMA_GCR->PDSSR1 & ~PDMA_PDSSR1_ADC_RXSEL_Msk) | (u32Ch << PDMA_PDSSR1_ADC_RXSEL_Pos); + break; + + default:/* select PDMA channel as memory to memory */ + for(u32Index = 0; u32Index < 8; u32Index++) + { + if((PDMA_GCR->PDSSR0 & (0xF << (u32Index * 4))) == (u32Ch << (u32Index * 4))) + PDMA_GCR->PDSSR0 |= 0xF << (u32Index * 4); + if((PDMA_GCR->PDSSR1 & (0xF << (u32Index * 4))) == (u32Ch << (u32Index * 4))) + PDMA_GCR->PDSSR1 |= 0xF << (u32Index * 4); + if((PDMA_GCR->PDSSR2 & (0xF << (u32Index * 4))) == (u32Ch << (u32Index * 4))) + PDMA_GCR->PDSSR2 |= 0xF << (u32Index * 4); + } + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(uint32_t u32Ch) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + + pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk); +} + +/** + * @brief Enable Interrupt + * + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + + pdma->IER |= u32Mask; +} + +/** + * @brief Disable Interrupt + * + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch)); + + pdma->IER &= ~u32Mask; +} + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/ps2.c b/BSP/StdDriver/src/ps2.c new file mode 100644 index 0000000..d9866eb --- /dev/null +++ b/BSP/StdDriver/src/ps2.c @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file ps2.c + * @version V3.00 + * $Revision: 14 $ + * $Date: 15/05/04 3:59p $ + * @brief PS/2 driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NUC200Series.h" + +/*---------------------------------------------------------------------------------------------------------*/ +/* Includes of local headers */ +/*---------------------------------------------------------------------------------------------------------*/ +#include "ps2.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PS2_Driver PS2 Driver + @{ +*/ + + +/** @addtogroup PS2_EXPORTED_FUNCTIONS PS2 Exported Functions + @{ +*/ + + +/** + * @brief Enable PS/2 Interrupt + * + * @param[in] u32Mask The specified interrupt of PS/2 module: + * - PS2D_PS2CON_TXINTEN_Msk: PS/2 Tx interrupt + * - PS2D_PS2CON_RXINTEN_Msk: PS/2 Rx interrupt + * + * @return None + * + * @details The function is used to enable PS/2 specified Tx or Rx interrupt. + */ +void PS2_EnableInt(uint32_t u32Mask) +{ + PS2->PS2CON |= u32Mask; +} + +/** + * @brief Disable PS/2 Interrupt. + * + * @param[in] u32Mask The specified interrupt of PS2 module: + * - PS2D_PS2CON_TXINTEN_Msk: PS2 Tx interrupt + * - PS2D_PS2CON_RXINTEN_Msk: PS2 Rx interrupt + * + * @return None + * + * @details The function is used to disable PS/2 specified Tx or Rx interrupt. + */ +void PS2_DisableInt(uint32_t u32Mask) +{ + PS2->PS2CON &= ~u32Mask; +} + +/** + * @brief Enable PS/2 function and Set Parameter + * + * @param None + * + * @return None + * + * @details This function is used to enable PS/2 function and set one byte per transfer. + */ +void PS2_Open(void) +{ + /* Reset PS2 device */ + SYS->IPRSTC2 |= SYS_IPRSTC2_PS2_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_PS2_RST_Msk; + + /* Enable PS2 module */ + PS2->PS2CON |= PS2_PS2CON_PS2EN_Msk; + + /* Set One byte per transfer */ + PS2->PS2CON &= ~PS2_PS2CON_TXFIFO_DEPTH_Msk; + + /* Clear Tx FIFO */ + PS2->PS2CON |= PS2_PS2CON_CLRFIFO_Msk; + PS2->PS2CON &= (~PS2_PS2CON_CLRFIFO_Msk); +} + +/** + * @brief Disable PS/2 function + * + * @param None + * + * @return None + * + * @details This function use to disable PS/2 function. + */ +void PS2_Close(void) +{ + /* Enable PS2 module */ + PS2->PS2CON &= ~PS2_PS2CON_PS2EN_Msk; +} + +/** + * @brief This function use to read PS/2 Rx data. + * + * @param None + * + * @return Rx data + * + * @details To get PS/2 receive 8 bits data from PS2RXDATA register. + */ +uint8_t PS2_Read(void) +{ + return (uint8_t)(PS2->PS2RXDATA & PS2_PS2RXDATA_RXDATA_Msk); +} + +/** + * @brief This function use to transmit PS/2 data. + * + * @param[in] pu32Buf The buffer to send the data to PS/2 transmission FIFO. + * @param[in] u32ByteCount The byte number of data. + * + * @retval 0 transmit data time-out + * @retval 1 transmit data successful + * + * @details Write data to PS/2 transmit FIFO and set the depth of Tx transmit bytes, then check every data transmission success or time-out. + */ +int32_t PS2_Write(uint32_t *pu32Buf, uint32_t u32ByteCount) +{ + uint32_t u32TxFIFO_Depth = 16; + uint32_t u32delayno, txcnt, remainder; + uint8_t i = 0; + + txcnt = u32ByteCount / u32TxFIFO_Depth; + + remainder = u32ByteCount % u32TxFIFO_Depth; + if(remainder) txcnt++; + + u32delayno = 0; + while(!(PS2->PS2STATUS & PS2_PS2STATUS_TXEMPTY_Msk)) + { + u32delayno++; + if(u32delayno >= 0xF00000) + return FALSE; // Time Out + } + + if(u32ByteCount >= u32TxFIFO_Depth)//Tx FIFO is 16 bytes + PS2_SET_TX_BYTE_CNT(u32TxFIFO_Depth); + + do + { + u32delayno = 0; + while(!(PS2->PS2STATUS & PS2_PS2STATUS_TXEMPTY_Msk)) + { + u32delayno++; + if(u32delayno >= 0xF00000) + return FALSE; // Time Out + } + + if((txcnt == 1) && (remainder != 0)) + PS2_SET_TX_BYTE_CNT(u32ByteCount); + + PS2->PS2TXDATA0 = pu32Buf[i]; + PS2->PS2TXDATA1 = pu32Buf[i + 1]; + PS2->PS2TXDATA2 = pu32Buf[i + 2]; + PS2->PS2TXDATA3 = pu32Buf[i + 3]; + + i = i + 4; + + } + while(--txcnt); + + u32delayno = 0; + while(!(PS2->PS2STATUS & PS2_PS2STATUS_TXEMPTY_Msk)) + { + u32delayno++; + if(u32delayno >= 0xF00000) + return FALSE; // Time Out + } + + return TRUE; + +} + + +/*@}*/ /* end of group PS2_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PS2_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + + + diff --git a/BSP/StdDriver/src/pwm.c b/BSP/StdDriver/src/pwm.c new file mode 100644 index 0000000..96d77f1 --- /dev/null +++ b/BSP/StdDriver/src/pwm.c @@ -0,0 +1,672 @@ +/**************************************************************************//** + * @file pwm.c + * @version V3.00 + * $Revision: 12 $ + * $Date: 15/05/05 3:35p $ + * @brief PWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PWM_Driver PWM Driver + @{ +*/ + + +/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief Configure PWM capture and get the nearest unit time. + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to configure PWM capture and get the nearest unit time. + */ +uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32UnitTimeNsec, + uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32PWMClkTbl[8] = {__HXT, __LXT, NULL, __HIRC, NULL, NULL, NULL, __LIRC}; + uint32_t u32NearestUnitTimeNsec; + uint8_t u8Divider = 1; + /* this table is mapping divider value to register configuration */ + uint32_t u32PWMDividerToRegTbl[17] = {NULL, 4, 0, NULL, 1, NULL, NULL, NULL, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 3}; + uint16_t u16Prescale = 2; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWMA) + { + if(u32ChannelNum < 2)/* channel 0 and channel 1 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM01_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM01_S_EXT_Pos - 2)) | (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM01_S_Msk)) >> (CLK_CLKSEL1_PWM01_S_Pos); + else /* channel 2 and channel 3 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM23_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM23_S_EXT_Pos - 2)) | (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM23_S_Msk)) >> (CLK_CLKSEL1_PWM23_S_Pos); + } + else /*pwm == PWMB*/ + { + if(u32ChannelNum < 2)/* channel 0 and channel 1 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM45_S_EXT_Pos - 2)) | (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_Msk)) >> (CLK_CLKSEL2_PWM45_S_Pos); + else /* channel 2 and channel 3 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM67_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM67_S_EXT_Pos - 2)) | (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM67_S_Msk)) >> (CLK_CLKSEL2_PWM67_S_Pos); + } + + if(u32Src == 2) + { + SystemCoreClockUpdate(); + u32PWMClockSrc = SystemCoreClock; + } + else + { + u32PWMClockSrc = u32PWMClkTbl[u32Src]; + } + + u32PWMClockSrc /= 1000; + for(; u16Prescale <= 0x100; u16Prescale++) + { + u32NearestUnitTimeNsec = (1000000 * u16Prescale * u8Divider) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if((u16Prescale == 0x100) && (u8Divider == 16)) //limit to the maximum unit time(nano second) + break; + if(u16Prescale == 0x100) + { + u16Prescale = 2; + u8Divider <<= 1; // clk divider could only be 1, 2, 4, 8, 16 + continue; + } + if(!((1000000 * ((u16Prescale * u8Divider) + 1)) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) + break; + continue; + } + break; + } + + // Store return value here 'cos we're gonna change u8Divider & u16Prescale & u16CNR to the real value to fill into register + u16Prescale -= 1; + + // convert to real register value + u8Divider = u32PWMDividerToRegTbl[u8Divider]; + + // every two channels share a prescaler + (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u16Prescale << ((u32ChannelNum >> 1) * 8)); + (pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + // set PWM to edge aligned type + (pwm)->PCR &= ~(PWM_PCR_PWM01TYPE_Msk << (u32ChannelNum >> 1)); + (pwm)->PCR |= PWM_PCR_CH0MOD_Msk << (8 * u32ChannelNum); + *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u16CNR; + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @details This function is used to configure PWM generator and get the nearest frequency in edge aligned auto-reload mode. + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32PWMClkTbl[8] = {__HXT, __LXT, NULL, __HIRC, NULL, NULL, NULL, __LIRC}; + uint32_t i; + uint8_t u8Divider = 1, u8Prescale = 0xFF; + /* this table is mapping divider value to register configuration */ + uint32_t u32PWMDividerToRegTbl[17] = {NULL, 4, 0, NULL, 1, NULL, NULL, NULL, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 3}; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWMA) + { + if(u32ChannelNum < 2)/* channel 0 and channel 1 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM01_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM01_S_EXT_Pos - 2)) | (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM01_S_Msk)) >> (CLK_CLKSEL1_PWM01_S_Pos); + else /* channel 2 and channel 3 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM23_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM23_S_EXT_Pos - 2)) | (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM23_S_Msk)) >> (CLK_CLKSEL1_PWM23_S_Pos); + } + else /*pwm == PWMB*/ + { + if(u32ChannelNum < 2)/* channel 0 and channel 1 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM45_S_EXT_Pos - 2)) | (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_Msk)) >> (CLK_CLKSEL2_PWM45_S_Pos); + else /* channel 2 and channel 3 */ + u32Src = ((CLK->CLKSEL2 & (CLK_CLKSEL2_PWM67_S_EXT_Msk)) >> (CLK_CLKSEL2_PWM67_S_EXT_Pos - 2)) | (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM67_S_Msk)) >> (CLK_CLKSEL2_PWM67_S_Pos); + } + + if(u32Src == 2) + { + SystemCoreClockUpdate(); + u32PWMClockSrc = SystemCoreClock; + } + else + { + u32PWMClockSrc = u32PWMClkTbl[u32Src]; + } + + for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16 + { + i = (u32PWMClockSrc / u32Frequency) / u8Divider; + // If target value is larger than CNR * prescale, need to use a larger divider + if(i > (0x10000 * 0x100)) + continue; + + // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF + u8Prescale = (i + 0xFFFF) / 0x10000; + + // u8Prescale must at least be 2, otherwise the output stop + if(u8Prescale < 3) + u8Prescale = 2; + + i /= u8Prescale; + + if(i <= 0x10000) + { + if(i == 1) + u16CNR = 1; // Too fast, and PWM cannot generate expected frequency... + else + u16CNR = i; + break; + } + } + // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register + i = u32PWMClockSrc / (u8Prescale * u8Divider * u16CNR); + + u8Prescale -= 1; + u16CNR -= 1; + // convert to real register value + u8Divider = u32PWMDividerToRegTbl[u8Divider]; + + // every two channels share a prescaler + (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)); + (pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + // set PWM to edge aligned type + (pwm)->PCR &= ~(PWM_PCR_PWM01TYPE_Msk << (u32ChannelNum >> 1)); + (pwm)->PCR |= PWM_PCR_CH0MOD_Msk << (8 * u32ChannelNum); + + if(u32DutyCycle) + { + *((__IO uint32_t *)((((uint32_t) & ((pwm)->CMR0)) + u32ChannelNum * 12))) = u32DutyCycle * (u16CNR + 1) / 100 - 1; + } + else + { + *((__IO uint32_t *)((((uint32_t) & ((pwm)->CMR0)) + u32ChannelNum * 12))) = 0; + } + *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u16CNR; + + return(i); +} + + +/** + * @brief Start PWM module + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start PWM module. + */ +void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t u32Mask = 0, i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + u32Mask |= (PWM_PCR_CH0EN_Msk << (i * 8)); + } + } + + (pwm)->PCR |= u32Mask; +} + +/** + * @brief Stop PWM module + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop PWM module. + */ +void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + i * 12))) = 0; + } + } +} + +/** + * @brief Stop PWM generation immediately by clear channel enable bit + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop PWM generation immediately by clear channel enable bit. + */ +void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t u32Mask = 0, i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + u32Mask |= (PWM_PCR_CH0EN_Msk << (i * 8)); + } + } + + (pwm)->PCR &= ~u32Mask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to enable selected channel to trigger ADC. + * @note This function is only supported when PWM operating at Center-aligned type. + */ +void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (pwm)->TCON |= (PWM_TCON_PWM0TEN_Msk << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->TCON = ((pwm)->TCON & ~(PWM_TCON_PWM0TEN_Msk << u32ChannelNum)); +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (pwm)->TSTATUS = (PWM_TSTATUS_PWM0TF_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get PWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->TSTATUS & (PWM_TSTATUS_PWM0TF_Msk << (u32ChannelNum))) ? 1 : 0); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + if(i < 2) + { + (pwm)->CCR0 |= PWM_CCR0_CAPCH0EN_Msk << (i * 16); + } + else + { + (pwm)->CCR2 |= PWM_CCR2_CAPCH2EN_Msk << ((i - 2) * 16); + } + } + } + (pwm)->CAPENR |= u32ChannelMask; + (pwm)->PBCR = 1; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + if(i < 2) + { + (pwm)->CCR0 &= ~(PWM_CCR0_CAPCH0EN_Msk << (i * 16)); + } + else + { + (pwm)->CCR2 &= ~(PWM_CCR2_CAPCH2EN_Msk << ((i - 2) * 16)); + } + } + } + (pwm)->CAPENR &= ~u32ChannelMask; +} + +/** + * @brief Enables PWM output generation of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables PWM output generation of selected channel(s). + */ +void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->POE |= u32ChannelMask; +} + +/** + * @brief Disables PWM output generation of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables PWM output generation of selected channel(s). + */ +void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->POE &= ~u32ChannelMask; +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no + * dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + */ +void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // set duration + (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_DZI01_Msk << (8 * u32ChannelNum))) | (u32Duration << (PWM_PPR_DZI01_Pos + 8 * u32ChannelNum)); + // enable dead zone + (pwm)->PCR |= (PWM_PCR_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable Dead zone of selected channel. + */ +void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // enable dead zone + (pwm)->PCR &= ~(PWM_PCR_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + if(u32ChannelNum < 2) + (pwm)->CCR0 |= u32Edge << (u32ChannelNum * 16); + else + (pwm)->CCR2 |= u32Edge << ((u32ChannelNum - 2) * 16); + +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + if(u32ChannelNum < 2) + (pwm)->CCR0 &= ~(u32Edge << (u32ChannelNum * 16)); + else + (pwm)->CCR2 &= ~(u32Edge << ((u32ChannelNum - 2) * 16)); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + //clear capture interrupt flag, and clear CRLR or CFLR latched indicator + if(u32ChannelNum < 2) + (pwm)->CCR0 = ((pwm)->CCR0 & PWM_CCR_MASK) | (PWM_CCR0_CAPIF0_Msk << (u32ChannelNum * 16)) | (u32Edge << (u32ChannelNum * 16 + 5)); + else + (pwm)->CCR2 = ((pwm)->CCR2 & PWM_CCR_MASK) | (PWM_CCR2_CAPIF2_Msk << ((u32ChannelNum - 2) * 16)) | (u32Edge << ((u32ChannelNum - 2) * 16 + 5)); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 2) + { + return (((pwm)->CCR0 & ((PWM_CCR0_CRLRI0_Msk | PWM_CCR0_CFLRI0_Msk) << (u32ChannelNum * 16))) >> (PWM_CCR0_CRLRI0_Pos + u32ChannelNum * 16)); + } + else + { + return (((pwm)->CCR2 & ((PWM_CCR2_CRLRI2_Msk | PWM_CCR2_CFLRI2_Msk) << ((u32ChannelNum - 2) * 16))) >> (PWM_CCR2_CRLRI2_Pos + (u32ChannelNum - 2) * 16)); + } + +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32IntDutyType This parameter is not used + * @return None + * @details This function is used to enable duty interrupt of selected channel. + * Every two channels, (0 & 1), (2 & 3), shares the duty interrupt type setting. + */ +void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (pwm)->PIER |= (PWM_PIER_PWMDIE0_Msk << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWMA : PWM Group A + * - PWMB : PWM Group B + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->PIER &= ~(PWM_PIER_PWMDIE0_Msk << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->PIIR = PWM_PIIR_PWMDIF0_Msk << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->PIIR & (PWM_PIIR_PWMDIF0_Msk << u32ChannelNum)) ? 1 : 0); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @param[in] u32IntPeriodType Period interrupt type, could be either + * - \ref PWM_PERIOD_INT_UNDERFLOW + * - \ref PWM_PERIOD_INT_MATCH_CNR + * @return None + * @details This function is used to enable period interrupt of selected channel. + * Every two channels, (0 & 1), (2 & 3), shares the period interrupt type setting. + */ +void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (pwm)->PIER = ((pwm)->PIER & ~(PWM_PIER_INT01TYPE_Msk << (u32ChannelNum >> 1))) | \ + (PWM_PIER_PWMIE0_Msk << u32ChannelNum) | (u32IntPeriodType << (u32ChannelNum >> 1)); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->PIER &= ~(PWM_PIER_PWMIE0_Msk << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->PIIR = (PWM_PIIR_PWMIF0_Msk << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3 + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->PIIR & (PWM_PIIR_PWMIF0_Msk << (u32ChannelNum))) ? 1 : 0); +} + + + +/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PWM_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/retarget.c b/BSP/StdDriver/src/retarget.c new file mode 100644 index 0000000..8e012dd --- /dev/null +++ b/BSP/StdDriver/src/retarget.c @@ -0,0 +1,760 @@ +/**************************************************************************//** + * @file retarget.c + * @version V3.00 + * $Revision: 10 $ + * $Date: 15/11/03 9:02a $ + * @brief Debug Port and Semihost Setting Source File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + + +#include +#include "NUC200Series.h" + +#if defined ( __CC_ARM ) +#if (__ARMCC_VERSION < 400000) +#else +/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */ +#pragma import _printf_widthprec +#endif +#endif + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ +#if !(defined(__ICCARM__) && (__VER__ >= 6010000)) +struct __FILE +{ + int handle; /* Add whatever you need here */ +}; +#endif +FILE __stdout; +FILE __stdin; + +enum { r0, r1, r2, r3, r12, lr, pc, psr}; + +/** + * @brief Helper function to dump register while hard fault occurred + * @param[in] stack pointer points to the dumped registers in SRAM + * @return None + * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr + */ +static void stackDump(uint32_t stack[]) +{ + printf("r0 = 0x%x\n", stack[r0]); + printf("r1 = 0x%x\n", stack[r1]); + printf("r2 = 0x%x\n", stack[r2]); + printf("r3 = 0x%x\n", stack[r3]); + printf("r12 = 0x%x\n", stack[r12]); + printf("lr = 0x%x\n", stack[lr]); + printf("pc = 0x%x\n", stack[pc]); + printf("psr = 0x%x\n", stack[psr]); +} + +/** + * @brief Hard fault handler + * @param[in] stack pointer points to the dumped registers in SRAM + * @return None + * @details Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product + */ +void Hard_Fault_Handler(uint32_t stack[]) +{ + printf("In Hard Fault Handler\n"); + + stackDump(stack); + + // Replace while(1) with chip reset if WDT is not enabled for end product + while(1); + //SYS->IPRSTC1 = SYS_IPRSTC1_CHIP_RST_Msk; +} + +/*---------------------------------------------------------------------------------------------------------*/ +/* Routine to write a char */ +/*---------------------------------------------------------------------------------------------------------*/ + +#if defined(DEBUG_ENABLE_SEMIHOST) +/* The static buffer is used to speed up the semihost */ +static char g_buf[16]; +static char g_buf_len = 0; + +/* Make sure won't goes here only because --gnu is defined , so + add !__CC_ARM and !__ICCARM__ checking */ +# if defined ( __GNUC__ ) && !(__CC_ARM) && !(__ICCARM__) + +# elif defined(__ICCARM__) + + +void SH_End(void) +{ + asm("MOVS R0,#1 \n" //; Set return value to 1 + "BX lr \n" //; Return + ); +} + +void SH_ICE(void) +{ + asm("CMP R2,#0 \n" + "BEQ SH_End \n" + "STR R0,[R2] \n" //; Save the return value to *pn32Out_R0 + ); +} + +/** + * + * @brief The function to process semihosted command + * @param[in] n32In_R0 : semihost register 0 + * @param[in] n32In_R1 : semihost register 1 + * @param[out] pn32Out_R0: semihost register 0 + * @retval 0: No ICE debug + * @retval 1: ICE debug + * + */ +int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault + "B SH_ICE \n" + "SH_HardFault: \n" //; Captured by HardFault + "MOVS R0,#0 \n" //; Set return value to 0 + "BX lr \n" //; Return + ); + + return 1; //; Return 1 when it is trap by ICE +} + +/** + * @brief Get LR value and branch to Hard_Fault_Handler function + * @param None + * @return None + * @details This function is use to get LR value and branch to Hard_Fault_Handler function. + */ +void Get_LR_and_Branch(void) +{ + asm("MOV R1, LR \n" //; LR current value + "B Hard_Fault_Handler \n" + ); +} + +/** + * @brief Get MSP value and branch to Get_LR_and_Branch function + * @param None + * @return None + * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function. + */ +void Stack_Use_MSP(void) +{ + asm("MRS R0, MSP \n" //; read MSP + "B Get_LR_and_Branch \n" + ); +} + +/** + * @brief Get stack pointer value and branch to Get_LR_and_Branch function + * @param None + * @return None + * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function. + */ +void HardFault_Handler_Ret(void) +{ + asm("MOVS r0, #4 \n" + "MOV r1, LR \n" + "TST r0, r1 \n" //; check LR bit 2 + "BEQ Stack_Use_MSP \n" //; stack use MSP + "MRS R0, PSP \n" //; stack use PSP, read PSP + "B Get_LR_and_Branch \n" + ); +} + +/** + * @brief This function is implemented to support semihost + * @param None + * @returns None + * @details This function is implement to support semihost message print. + * + */ +void SP_Read_Ready(void) +{ + asm("LDR R1, [R0, #24] \n" //; Get previous PC + "LDRH R3, [R1] \n" //; Get instruction + "LDR R2, [pc, #8] \n" //; The special BKPT instruction + "CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT + "BNE HardFault_Handler_Ret \n" //; Not BKPT + "ADDS R1, #4 \n" //; Skip BKPT and next line + "STR R1, [R0, #24] \n" //; Save previous PC + "BX lr \n" //; Return + "DCD 0xBEAB \n" //; BKPT instruction code + "B HardFault_Handler_Ret \n" + ); +} + +/** + * @brief Get stack pointer value and branch to Get_LR_and_Branch function + * @param None + * @return None + * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function. + */ +void SP_is_PSP(void) +{ + asm( + "MRS R0, PSP \n" //; stack use PSP, read PSP + "B Get_LR_and_Branch \n" + + ); +} + +/** + * @brief This HardFault handler is implemented to support semihost + * + * @param None + * + * @returns None + * + * @details This function is implement to support semihost message print. + * + */ +void HardFault_Handler (void) +{ + asm("MOV R0, lr \n" + "LSLS R0, #29 \n" //; Check bit 2 + "BMI SP_is_PSP \n" //; previous stack is PSP + "MRS R0, MSP \n" //; previous stack is MSP, read MSP + "B SP_Read_Ready \n" + ); + + while(1); +} + + +# else + +/** + * @brief This HardFault handler is implemented to support semihost + * @param None + * @returns None + * @details This function is implement to support semihost message print. + * + */ +__asm int32_t HardFault_Handler(void) +{ + MOV R0, LR + LSLS R0, #29 //; Check bit 2 + BMI SP_is_PSP //; previous stack is PSP + MRS R0, MSP //; previous stack is MSP, read MSP + B SP_Read_Ready +SP_is_PSP + MRS R0, PSP //; Read PSP + +SP_Read_Ready + LDR R1, [R0, #24] //; Get previous PC + LDRH R3, [R1] //; Get instruction + LDR R2, =0xBEAB //; The special BKPT instruction + CMP R3, R2 //; Test if the instruction at previous PC is BKPT + BNE HardFault_Handler_Ret //; Not BKPT + + ADDS R1, #4 //; Skip BKPT and next line + STR R1, [R0, #24] //; Save previous PC + + BX LR //; Return +HardFault_Handler_Ret + + /* TODO: Implement your own hard fault handler here. */ + MOVS r0, #4 + MOV r1, LR + TST r0, r1 //; check LR bit 2 + BEQ Stack_Use_MSP //; stack use MSP + MRS R0, PSP ;stack use PSP //; stack use PSP, read PSP + B Get_LR_and_Branch +Stack_Use_MSP + MRS R0, MSP ; stack use MSP //; read MSP +Get_LR_and_Branch + MOV R1, LR ; LR current value //; LR current value + LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler + BX R2 + + B . + + ALIGN +} + +/** + * + * @brief The function to process semihosted command + * @param[in] n32In_R0 : semihost register 0 + * @param[in] n32In_R1 : semihost register 1 + * @param[out] pn32Out_R0: semihost register 0 + * @retval 0: No ICE debug + * @retval 1: ICE debug + * + */ +__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + BKPT 0xAB //; Wait ICE or HardFault + //; ICE will step over BKPT directly + //; HardFault will step BKPT and the next line + B SH_ICE + +SH_HardFault //; Captured by HardFault + MOVS R0, #0 //; Set return value to 0 + BX lr //; Return + +SH_ICE //; Captured by ICE + //; Save return value + CMP R2, #0 + BEQ SH_End + STR R0, [R2] //; Save the return value to *pn32Out_R0 + +SH_End + MOVS R0, #1 //; Set return value to 1 + BX lr //; Return +} +#endif + + +#else // Non-semihost + +/* Make sure won't goes here only because --gnu is defined , so + add !__CC_ARM and !__ICCARM__ checking */ +# if defined ( __GNUC__ ) && !(__CC_ARM) && !(__ICCARM__) + +/** + * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr + * + * @param None + * + * @returns None + * + * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr. + * + */ +void HardFault_Handler(void) +{ + asm("MOVS r0, #4 \n" + "MOV r1, LR \n" + "TST r0, r1 \n" /*; check LR bit 2 */ + "BEQ 1f \n" /*; stack use MSP */ + "MRS R0, PSP \n" /*; stack use PSP, read PSP */ + "MOV R1, LR \n" /*; LR current value */ + "B Hard_Fault_Handler \n" + "1: \n" + "MRS R0, MSP \n" /*; LR current value */ + "B Hard_Fault_Handler \n" + ::[Hard_Fault_Handler] "r" (Hard_Fault_Handler) // input + ); + while(1); +} + +# elif defined(__ICCARM__) + +void Get_LR_and_Branch(void) +{ + asm("MOV R1, LR \n" //; LR current value + "B Hard_Fault_Handler \n" + ); +} + +void Stack_Use_MSP(void) +{ + asm("MRS R0, MSP \n" //; read MSP + "B Get_LR_and_Branch \n" + ); +} + +/** + * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr + * + * @param None + * + * @returns None + * + * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr. + * + */ +void HardFault_Handler(void) +{ + asm("MOVS r0, #4 \n" + "MOV r1, LR \n" + "TST r0, r1 \n" //; check LR bit 2 + "BEQ Stack_Use_MSP \n" //; stack use MSP + "MRS R0, PSP \n" //; stack use PSP, read PSP + "B Get_LR_and_Branch \n" + ); + + while(1); +} + +# else + +/** + * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr + * + * @param None + * + * @return None + * + * @details The function extracts the location of stack frame and passes it to Hard_Fault_Handler function as a pointer + * + */ +__asm int32_t HardFault_Handler(void) +{ + MOVS r0, #4 + MOV r1, LR + TST r0, r1 //; check LR bit 2 + BEQ Stack_Use_MSP //; stack use MSP + MRS R0, PSP //; stack use PSP, read PSP + B Get_LR_and_Branch +Stack_Use_MSP + MRS R0, MSP //; read MSP +Get_LR_and_Branch + MOV R1, LR //; LR current value + LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler + BX R2 +} + +#endif + +#endif + + + +/** + * @brief Routine to send a char + * + * @param[in] ch Character to send to debug port. + * + * @returns Send value from UART debug port + * + * @details Send a target char to UART debug port . + */ + +#ifndef NONBLOCK_PRINTF + +void SendChar_ToUART(int ch) +{ + + while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk); + if(ch == '\n') + { + DEBUG_PORT->DATA = '\r'; + while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk); + } + + DEBUG_PORT->DATA = ch; +} + +#else +/* Non-block implement of send char */ +#define BUF_SIZE 2048 +void SendChar_ToUART(int ch) +{ + static uint8_t u8Buf[BUF_SIZE] = {0}; + static int32_t i32Head = 0; + static int32_t i32Tail = 0; + int32_t i32Tmp; + + /* Only flush the data in buffer to UART when ch == 0 */ + if(ch) + { + // Push char + if(ch == '\n') + { + i32Tmp = i32Head + 1; + if(i32Tmp >= BUF_SIZE) i32Tmp = 0; + if(i32Tmp != i32Tail) + { + u8Buf[i32Head] = '\r'; + i32Head = i32Tmp; + } + } + + i32Tmp = i32Head + 1; + if(i32Tmp >= BUF_SIZE) i32Tmp = 0; + if(i32Tmp != i32Tail) + { + u8Buf[i32Head] = ch; + i32Head = i32Tmp; + } + } + else + { + if(i32Tail == i32Head) + return; + } + + // pop char + do + { + i32Tmp = i32Tail + 1; + if(i32Tmp >= BUF_SIZE) i32Tmp = 0; + + if((DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk) == 0) + { + DEBUG_PORT->THR = u8Buf[i32Tail]; + i32Tail = i32Tmp; + } + else + break; // FIFO full + } + while(i32Tail != i32Head); +} +#endif + + + +/** + * @brief Routine to send a char + * + * @param[in] ch Character to send to debug port. + * + * @returns Send value from UART debug port or semihost + * + * @details Send a target char to UART debug port or semihost. + */ +void SendChar(int ch) +{ +#if defined(DEBUG_ENABLE_SEMIHOST) + g_buf[g_buf_len++] = ch; + g_buf[g_buf_len] = '\0'; + if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0') + { + /* Send the char */ + if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0) + { + g_buf_len = 0; + return; + } + else + { + g_buf_len = 0; + } + } +#else + SendChar_ToUART(ch); +#endif +} + +/** + * @brief Routine to get a char + * + * @param None + * + * @returns Get value from UART debug port or semihost + * + * @details Wait UART debug port or semihost to input a char. + */ +char GetChar(void) +{ +#ifdef DEBUG_ENABLE_SEMIHOST +# if defined ( __CC_ARM ) + int nRet; + while(SH_DoCommand(0x101, 0, &nRet) != 0) + { + if(nRet != 0) + { + SH_DoCommand(0x07, 0, &nRet); + return (char)nRet; + } + } +# else + int nRet; + while(SH_DoCommand(0x7, 0, &nRet) != 0) + { + if(nRet != 0) + return (char)nRet; + } +# endif + return (0); +#else + + while(1) + { + if((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_Msk) == 0) + { + return (DEBUG_PORT->DATA); + } + } + +#endif +} + +/** + * @brief Check any char input from UART + * + * @param None + * + * @retval 1: No any char input + * @retval 0: Have some char input + * + * @details Check UART RSR RX EMPTY or not to determine if any char input from UART + */ + +int kbhit(void) +{ + return !((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_Msk) == 0); +} +/** + * @brief Check if debug message finished + * + * @param None + * + * @retval 1: Message is finished + * @retval 0: Message is transmitting. + * + * @details Check if message finished (FIFO empty of debug port) + */ + +int IsDebugFifoEmpty(void) +{ + return ((DEBUG_PORT->FSR & UART_FSR_TE_FLAG_Msk) != 0); +} + +/** + * @brief C library retargetting + * + * @param[in] ch Character to send to debug port. + * + * @returns None + * + * @details Check if message finished (FIFO empty of debug port) + */ + +void _ttywrch(int ch) +{ + SendChar(ch); + return; +} + + +/** + * @brief Write character to stream + * + * @param[in] ch Character to be written. The character is passed as its int promotion. + * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written. + * + * @returns If there are no errors, the same character that has been written is returned. + * If an error occurs, EOF is returned and the error indicator is set (see ferror). + * + * @details Writes a character to the stream and advances the position indicator.\n + * The character is written at the current position of the stream as indicated \n + * by the internal position indicator, which is then advanced one character. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/. + * + * + */ + +int fputc(int ch, FILE *stream) +{ + SendChar(ch); + return ch; +} + +#if defined ( __GNUC__ ) + +#if !defined(OS_USE_SEMIHOSTING) + +int _write (int fd, char *ptr, int len) +{ + int i = len; + + while(i--) + { + while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk); + + if(*ptr == '\n') + { + DEBUG_PORT->DATA = '\r'; + while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk); + } + + DEBUG_PORT->DATA = *ptr++; +} + return len; +} + +int _read (int fd, char *ptr, int len) +{ + + while((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_Msk) != 0); + *ptr = DEBUG_PORT->DATA; + return 1; + + +} + +#endif + +#else +/** + * @brief Get character from UART debug port or semihosting input + * + * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed. + * + * @returns The character read from UART debug port or semihosting + * + * @details For get message from debug port or semihosting. + * + */ + +int fgetc(FILE *stream) +{ + return (GetChar()); +} + +/** + * @brief Check error indicator + * + * @param[in] stream Pointer to a FILE object that identifies the stream. + * + * @returns If the error indicator associated with the stream was set, the function returns a nonzero value. + * Otherwise, it returns a zero value. + * + * @details Checks if the error indicator associated with stream is set, returning a value different + * from zero if it is. This indicator is generally set by a previous operation on the stream that failed. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/. + * + */ + +int ferror(FILE *stream) +{ + return EOF; +} +#endif + +#ifdef DEBUG_ENABLE_SEMIHOST +# ifdef __ICCARM__ +void __exit(int return_code) +{ + + /* Check if link with ICE */ + if(SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while(IsDebugFifoEmpty() == 0); + } +label: + goto label; /* endless loop */ +} +# else +void _sys_exit(int return_code) +{ + + /* Check if link with ICE */ + if(SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while(IsDebugFifoEmpty() == 0); + } +label: + goto label; /* endless loop */ +} +# endif +#endif + + + + + diff --git a/BSP/StdDriver/src/rtc.c b/BSP/StdDriver/src/rtc.c new file mode 100644 index 0000000..6ef509a --- /dev/null +++ b/BSP/StdDriver/src/rtc.c @@ -0,0 +1,786 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * $Revision: 13 $ + * $Date: 15/05/06 6:51p $ + * @brief RTC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/// @cond HIDDEN_SYMBOLS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/// @endcond HIDDEN_SYMBOLS + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC setting and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIR = RTC_INIT_KEY; + + if(RTC->INIR != 0x1) + { + RTC->INIR = RTC_INIT_KEY; + while(RTC->INIR != 0x1); + } + + if(sPt == NULL) + return ; + + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + + /* Waiting for RTC settings stable */ + while((RTC->AER & RTC_AER_ENF_Msk) == RTC_AER_ENF_Msk); +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK &= ~CLK_APBCLK_RTC_EN_Msk; +} + +/** + * @brief Set 32k Frequency Compensation Data + * + * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65. + * + * @return None + * + * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application. + */ +void RTC_32KCalibration(int32_t i32FrequencyX100) +{ + int32_t i32RegInt, i32RegFra; + + /* Compute integer and fraction for RTC FCR register */ + i32RegInt = (i32FrequencyX100 / 100) - RTC_FCR_REFERENCE; + i32RegFra = (((i32FrequencyX100 % 100)) * 60) / 100; + + /* Judge Integer part is reasonable */ + if((i32RegInt < 0) | (i32RegInt > 15)) + { + return ; + } + + RTC_WaitAccessEnable(); + RTC->FCR = (uint32_t)((i32RegInt << 8) | i32RegFra); +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CLR & RTC_CLR_10YEAR_Msk) >> RTC_CLR_10YEAR_Pos; + g_u32loYear = (RTC->CLR & RTC_CLR_1YEAR_Msk) >> RTC_CLR_1YEAR_Pos; + g_u32hiMonth = (RTC->CLR & RTC_CLR_10MON_Msk) >> RTC_CLR_10MON_Pos; + g_u32loMonth = (RTC->CLR & RTC_CLR_1MON_Msk) >> RTC_CLR_1MON_Pos; + g_u32hiDay = (RTC->CLR & RTC_CLR_10DAY_Msk) >> RTC_CLR_10DAY_Pos; + g_u32loDay = (RTC->CLR & RTC_CLR_1DAY_Msk); + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TLR & RTC_TLR_10HR_Msk) >> RTC_TLR_10HR_Pos; + g_u32loHour = (RTC->TLR & RTC_TLR_1HR_Msk) >> RTC_TLR_1HR_Pos; + g_u32hiMin = (RTC->TLR & RTC_TLR_10MIN_Msk) >> RTC_TLR_10MIN_Pos; + g_u32loMin = (RTC->TLR & RTC_TLR_1MIN_Msk) >> RTC_TLR_1MIN_Pos; + g_u32hiSec = (RTC->TLR & RTC_TLR_10SEC_Msk) >> RTC_TLR_10SEC_Pos; + g_u32loSec = (RTC->TLR & RTC_TLR_1SEC_Msk); + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + RTC_WaitAccessEnable(); + g_u32hiYear = (RTC->CAR & RTC_CAR_10YEAR_Msk) >> RTC_CAR_10YEAR_Pos; + g_u32loYear = (RTC->CAR & RTC_CAR_1YEAR_Msk) >> RTC_CAR_1YEAR_Pos; + g_u32hiMonth = (RTC->CAR & RTC_CAR_10MON_Msk) >> RTC_CAR_10MON_Pos; + g_u32loMonth = (RTC->CAR & RTC_CAR_1MON_Msk) >> RTC_CAR_1MON_Pos; + g_u32hiDay = (RTC->CAR & RTC_CAR_10DAY_Msk) >> RTC_CAR_10DAY_Pos; + g_u32loDay = (RTC->CAR & RTC_CAR_1DAY_Msk); + + /* Get alarm [Time digit] data */ + RTC_WaitAccessEnable(); + g_u32hiHour = (RTC->TAR & RTC_TAR_10HR_Msk) >> RTC_TAR_10HR_Pos; + g_u32loHour = (RTC->TAR & RTC_TAR_1HR_Msk) >> RTC_TAR_1HR_Pos; + g_u32hiMin = (RTC->TAR & RTC_TAR_10MIN_Msk) >> RTC_TAR_10MIN_Pos; + g_u32loMin = (RTC->TAR & RTC_TAR_1MIN_Msk) >> RTC_TAR_1MIN_Pos; + g_u32hiSec = (RTC->TAR & RTC_TAR_10SEC_Msk) >> RTC_TAR_10SEC_Pos; + g_u32loSec = (RTC->TAR & RTC_TAR_1SEC_Msk); + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCLR, u32RegTLR; + + if(sPt == NULL) + return ; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + sPt->u32Hour += 20; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + /* Set Day of the Week */ + RTC->DWR = sPt->u32DayOfWeek; + + u32RegCLR = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20; + u32RegCLR |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16); + u32RegCLR |= ((sPt->u32Month / 10) << 12); + u32RegCLR |= ((sPt->u32Month % 10) << 8); + u32RegCLR |= ((sPt->u32Day / 10) << 4); + u32RegCLR |= (sPt->u32Day % 10); + + u32RegTLR = ((sPt->u32Hour / 10) << 20); + u32RegTLR |= ((sPt->u32Hour % 10) << 16); + u32RegTLR |= ((sPt->u32Minute / 10) << 12); + u32RegTLR |= ((sPt->u32Minute % 10) << 8); + u32RegTLR |= ((sPt->u32Second / 10) << 4); + u32RegTLR |= (sPt->u32Second % 10); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + RTC->CLR = (uint32_t)u32RegCLR; + RTC->TLR = (uint32_t)u32RegTLR; +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAR, u32RegTAR; + + if(sPt == NULL) + return ; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + sPt->u32Hour += 20; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + /* Set Day of the Week */ + RTC->DWR = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAR = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20; + u32RegCAR |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16); + u32RegCAR |= ((sPt->u32Month / 10) << 12); + u32RegCAR |= ((sPt->u32Month % 10) << 8); + u32RegCAR |= ((sPt->u32Day / 10) << 4); + u32RegCAR |= (sPt->u32Day % 10); + + u32RegTAR = ((sPt->u32Hour / 10) << 20); + u32RegTAR |= ((sPt->u32Hour % 10) << 16); + u32RegTAR |= ((sPt->u32Minute / 10) << 12); + u32RegTAR |= ((sPt->u32Minute % 10) << 8); + u32RegTAR |= ((sPt->u32Second / 10) << 4); + u32RegTAR |= (sPt->u32Second % 10); + + RTC_WaitAccessEnable(); + RTC->CAR = (uint32_t)u32RegCAR; + RTC->TAR = (uint32_t)u32RegTAR; +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCLR; + + u32RegCLR = ((u32Year - RTC_YEAR2000) / 10) << 20; + u32RegCLR |= (((u32Year - RTC_YEAR2000) % 10) << 16); + u32RegCLR |= ((u32Month / 10) << 12); + u32RegCLR |= ((u32Month % 10) << 8); + u32RegCLR |= ((u32Day / 10) << 4); + u32RegCLR |= (u32Day % 10); + + RTC_WaitAccessEnable(); + + /* Set Day of the Week */ + RTC->DWR = u32DayOfWeek & RTC_DWR_DWR_Msk; + + /* Set RTC Calender Loading */ + RTC->CLR = (uint32_t)u32RegCLR; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTLR; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + u32Hour += 20; + + u32RegTLR = ((u32Hour / 10) << 20); + u32RegTLR |= ((u32Hour % 10) << 16); + u32RegTLR |= ((u32Minute / 10) << 12); + u32RegTLR |= ((u32Minute % 10) << 8); + u32RegTLR |= ((u32Second / 10) << 4); + u32RegTLR |= (u32Second % 10); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + RTC->TLR = (uint32_t)u32RegTLR; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCAR; + + u32RegCAR = ((u32Year - RTC_YEAR2000) / 10) << 20; + u32RegCAR |= (((u32Year - RTC_YEAR2000) % 10) << 16); + u32RegCAR |= ((u32Month / 10) << 12); + u32RegCAR |= ((u32Month % 10) << 8); + u32RegCAR |= ((u32Day / 10) << 4); + u32RegCAR |= (u32Day % 10); + + RTC_WaitAccessEnable(); + + /* Set RTC Alarm Date */ + RTC->CAR = (uint32_t)u32RegCAR; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTAR; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + u32Hour += 20; + + u32RegTAR = ((u32Hour / 10) << 20); + u32RegTAR |= ((u32Hour % 10) << 16); + u32RegTAR |= ((u32Minute / 10) << 12); + u32RegTAR |= ((u32Minute % 10) << 8); + u32RegTAR |= ((u32Second / 10) << 4); + u32RegTAR |= (u32Second % 10); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + /* Set RTC Alarm Time */ + RTC->TAR = (uint32_t)u32RegTAR; +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC setting. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->DWR & RTC_DWR_DWR_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC time tick period for Periodic Time Tick request. \n + * It consists of: \n + * RTC_TICK_1_SEC: Time tick is 1 second \n + * RTC_TICK_1_2_SEC: Time tick is 1/2 second \n + * RTC_TICK_1_4_SEC: Time tick is 1/4 second \n + * RTC_TICK_1_8_SEC: Time tick is 1/8 second \n + * RTC_TICK_1_16_SEC: Time tick is 1/16 second \n + * RTC_TICK_1_32_SEC: Time tick is 1/32 second \n + * RTC_TICK_1_64_SEC: Time tick is 1/64 second \n + * RTC_TICK_1_128_SEC: Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set time tick period for periodic time tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC_WaitAccessEnable(); + + RTC->TTR = (RTC->TTR & ~RTC_TTR_TTR_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n + * RTC_RIER_AIER_Msk: Alarm interrupt \n + * RTC_RIER_TIER_Msk: Tick interrupt \n + * RTC_RIER_SNOOPIER_Msk: Snooper Pin Event Detection Interrupt \n + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC->RIER |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n + * RTC_RIER_AIER_Msk: Alarm interrupt \n + * RTC_RIER_TIER_Msk: Tick interrupt \n + * RTC_RIER_SNOOPIER_Msk: Snooper Pin Event Detection interrupt \n + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + if(u32IntFlagMask & RTC_RIER_TIER_Msk) + { + RTC->RIER &= ~RTC_RIER_TIER_Msk; + RTC->RIIR |= RTC_RIIR_TIF_Msk; + } + + if(u32IntFlagMask & RTC_RIER_AIER_Msk) + { + RTC->RIER &= ~RTC_RIER_AIER_Msk; + RTC->RIIR |= RTC_RIIR_AIF_Msk; + } + + if(u32IntFlagMask & RTC_RIER_SNOOPIER_Msk) + { + RTC->RIER &= ~RTC_RIER_SNOOPIER_Msk; + RTC->RIIR |= RTC_RIIR_SNOOPIF_Msk; + } +} + +/** + * @brief Enable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare register 0~19 can be accessed. + */ +void RTC_EnableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL |= RTC_SPRCTL_SPREN_Msk; + + while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRDY_Msk)); +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SPREN_Msk; +} + +/** + * @brief Enable Snooper Pin Detect + * + * @param[in] u32PinCondition Snooper pin trigger condition. Possible options are + * - \ref RTC_SNOOPER_LOW_LEVEL + * - \ref RTC_SNOOPER_HIGH_LEVEL + * - \ref RTC_SNOOPER_FALLING_EDGE + * - \ref RTC_SNOOPER_RISING_EDGE + * + * @return None + * + * @details This API is used to enable the snooper pin detect function with specify trigger condition. + */ +void RTC_EnableSnooperDetection(uint32_t u32PinCondition) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL = ((RTC->SPRCTL & ~RTC_SNOOPER_DETECT_Msk) | u32PinCondition) | RTC_SPRCTL_SNOOPEN_Msk; +} + +/** + * @brief Disable Snooper Pin Detect + * + * @param None + * + * @return None + * + * @details This API is used to disable the snooper pin detect function. + */ +void RTC_DisableSnooperDetection(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEN_Msk; +} + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/sc.c b/BSP/StdDriver/src/sc.c new file mode 100644 index 0000000..2f1c349 --- /dev/null +++ b/BSP/StdDriver/src/sc.c @@ -0,0 +1,280 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * $Revision: 10 $ + * $Date: 15/05/12 2:26p $ + * @brief Smartcard(SC) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + +// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined +/// @cond HIDDEN_SYMBOLS +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0, 0, 0}; + +/// @endcond HIDDEN_SYMBOLS + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status. + * @param[in] sc The pointer of smartcard module. + * @retval TRUE Card insert. + * @retval FALSE Card remove. + * @details This function is used to check if specified smart card slot is presented. + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + // put conditions into two variable to remove IAR compilation warning + uint32_t cond1 = ((sc->PINCSR & SC_PINCSR_CD_PIN_ST_Msk) >> SC_PINCSR_CD_PIN_ST_Pos); + uint32_t cond2 = ((sc->PINCSR & SC_PINCSR_CD_LEV_Msk) >> SC_PINCSR_CD_LEV_Pos); + + if(sc == SC0 && u32CardStateIgnore[0] == 1) + return TRUE; + else if(sc == SC1 && u32CardStateIgnore[1] == 1) + return TRUE; + else if(sc == SC2 && u32CardStateIgnore[2] == 1) + return TRUE; + else if(cond1 != cond2) + return FALSE; + else + return TRUE; +} + +/** + * @brief Reset the Tx/Rx FIFO. + * @param[in] sc The pointer of smartcard module. + * @return None + * @details This function reset both transmit and receive FIFO of specified smartcard module. + */ +void SC_ClearFIFO(SC_T *sc) +{ + sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk); +} + +/** + * @brief This function disable specified smartcard module. + * @param[in] sc The pointer of smartcard module. + * @return None + * @details SC will force all transition to IDLE state. + */ +void SC_Close(SC_T *sc) +{ + sc->IER = 0; + sc->PINCSR = 0; + sc->ALTCTL = 0; + sc->CTL = 0; +} + +/** + * @brief This function initialized smartcard module. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be: + * -\ref SC_PIN_STATE_HIGH. + * -\ref SC_PIN_STATE_LOW. + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present. + * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be: + * -\ref SC_PIN_STATE_HIGH. + * -\ref SC_PIN_STATE_LOW. + * @return None + * @details Initialization process configures smartcard and enables engine clock. + */ +void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR) +{ + uint32_t u32Reg = 0, u32Intf; + + if(sc == SC0) + u32Intf = 0; + else if(sc == SC1) + u32Intf = 1; + else + u32Intf = 2; + + if(u32CD != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CD ? 0 : SC_PINCSR_CD_LEV_Msk; + u32CardStateIgnore[u32Intf] = 0; + } + else + { + u32CardStateIgnore[u32Intf] = 1; + } + u32Reg |= u32PWR ? 0 : SC_PINCSR_POW_INV_Msk; + sc->PINCSR = u32Reg; + sc->CTL = SC_CTL_SC_CEN_Msk; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard. + * @param[in] sc The pointer of smartcard module. + * @return None + * @details Reset the Tx/Rx FIFO & clock & initial default parameter. + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if(sc == SC0) + u32Intf = 0; + else if(sc == SC1) + u32Intf = 1; + else + u32Intf = 2; + + // Reset FIFO + sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk); + // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) + sc->CTL &= ~(SC_CTL_RX_FTRI_LEV_Msk | SC_CTL_CD_DEB_SEL_Msk | SC_CTL_TX_ERETRY_Msk | SC_CTL_RX_ERETRY_Msk); + // Enable auto convention, and all three smartcard internal timers + sc->CTL |= SC_CTL_AUTO_CON_EN_Msk | SC_CTL_TMR_SEL_Msk; + // Disable Rx timeout + sc->RFTMR = 0; + // 372 clocks per ETU by default + sc->ETUCR = 371; + // Enable auto de-activation while card removal + sc->PINCSR |= SC_PINCSR_ADAC_CD_EN_Msk; + + /* Enable necessary interrupt for smartcard operation */ + if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore + sc->IER = (SC_IER_RDA_IE_Msk | + SC_IER_TERR_IE_Msk | + SC_IER_TMR0_IE_Msk | + SC_IER_TMR1_IE_Msk | + SC_IER_TMR2_IE_Msk | + SC_IER_BGT_IE_Msk | + SC_IER_ACON_ERR_IE_Msk); + else + sc->IER = (SC_IER_RDA_IE_Msk | + SC_IER_TERR_IE_Msk | + SC_IER_TMR0_IE_Msk | + SC_IER_TMR1_IE_Msk | + SC_IER_TMR2_IE_Msk | + SC_IER_BGT_IE_Msk | + SC_IER_CD_IE_Msk | + SC_IER_ACON_ERR_IE_Msk); + + return; +} + +/** + * @brief Set Block Guard Time. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32. + * @return None + * @details This function block guard time (BGT) of specified smartcard module. + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos); +} + +/** + * @brief Set character guard time. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267. + * @return None + * @details This function character guard time (CGT) of specified smartcard module. + * @note Before using this API, user should set the correct stop bit length first. + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_SLEN_Msk ? 11 : 12; + sc->EGTR = u32CGT; +} + +/** + * @brief Stop all Timer counting. + * @param[in] sc The pointer of smartcard module. + * @return None + * @details This function stop all smartcard timer of specified smartcard module. + * @note This function stop the timers within smartcard module, \b not timer module. + */ +void SC_StopAllTimer(SC_T *sc) +{ + sc->ALTCTL &= ~(SC_ALTCTL_TMR0_SEN_Msk | SC_ALTCTL_TMR1_SEN_Msk | SC_ALTCTL_TMR2_SEN_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs. + * @return None + * @details Enable Timer starting, counter will count when condition match. + * @note This function start the timer within smartcard module, \b not timer module. + * @note Depend on the timer operating mode, timer may not start counting immediately. + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMR0_CNT_Msk & (u32ETUCount - 1)); + + if(u32TimerNum == 0) + { + sc->TMR0 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR0_SEN_Msk; + } + else if(u32TimerNum == 1) + { + sc->TMR1 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR1_SEN_Msk; + } + else // timer 2 + { + sc->TMR2 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR2_SEN_Msk; + } +} + +/** + * @brief Stop Timer counting. + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2. + * @return None + * @details This function stop a smartcard timer of specified smartcard module. + * @note This function stop the timer within smartcard module, \b not timer module. + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + if(u32TimerNum == 0) + sc->ALTCTL &= ~SC_ALTCTL_TMR0_SEN_Msk; + else if(u32TimerNum == 1) + sc->ALTCTL &= ~SC_ALTCTL_TMR1_SEN_Msk; + else // timer 2 + sc->ALTCTL &= ~SC_ALTCTL_TMR2_SEN_Msk; +} + + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/spi.c b/BSP/StdDriver/src/spi.c new file mode 100644 index 0000000..0e0455e --- /dev/null +++ b/BSP/StdDriver/src/spi.c @@ -0,0 +1,638 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * $Revision: 12 $ + * $Date: 15/05/04 3:59p $ + * @brief SPI driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first and the automatic slave selection function is disabled. + * In Slave mode, the u32BusClock must be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to HCLK and DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be set to equal to system clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq; + + if(u32DataWidth == 32) + u32DataWidth = 0; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode); + + /* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk; + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave select signal is active low; disable automatic slave select function. */ + spi->SSR = SPI_SS_ACTIVE_LOW; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI1) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI2) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2_S_Msk) == CLK_CLKSEL1_SPI2_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3_S_Msk) == CLK_CLKSEL1_SPI3_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Select HCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI0_S_Msk)) | CLK_CLKSEL1_SPI0_S_HCLK; + else if(spi == SPI1) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI1_S_Msk)) | CLK_CLKSEL1_SPI1_S_HCLK; + else if(spi == SPI2) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI2_S_Msk)) | CLK_CLKSEL1_SPI2_S_HCLK; + else + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI3_S_Msk)) | CLK_CLKSEL1_SPI3_S_HCLK; + + /* Set DIVIDER = 0 */ + spi->DIVIDER = 0; + /* Return slave peripheral clock rate */ + return u32HCLKFreq; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->DIVIDER = 0; + /* Return master peripheral clock rate */ + return u32ClkSrc; + } + else if(u32BusClock == 0) + { + /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */ + spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk); + /* Set DIVIDER to the maximum value 0xFF */ + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / ((0xFF + 1) * 2)); + } + else + { + u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */ + if(u32Div > 0xFF) + { + /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */ + spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk); + u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */ + if(u32Div > 0xFF) + u32Div = 0xFF; + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / ((u32Div + 1) * 2)); + } + else + { + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / (u32Div + 1)); + } + } + + } + else /* For slave mode, force the SPI peripheral clock rate to system clock rate. */ + { + /* Default setting: slave select signal is low level active. */ + spi->SSR = SPI_SSR_SS_LTRIG_Msk; + + /* Select HCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI0_S_Msk)) | CLK_CLKSEL1_SPI0_S_HCLK; + else if(spi == SPI1) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI1_S_Msk)) | CLK_CLKSEL1_SPI1_S_HCLK; + else if(spi == SPI2) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI2_S_Msk)) | CLK_CLKSEL1_SPI2_S_HCLK; + else + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI3_S_Msk)) | CLK_CLKSEL1_SPI3_S_HCLK; + + /* Set DIVIDER = 0 */ + spi->DIVIDER = 0; + /* Return slave peripheral clock rate */ + return u32HCLKFreq; + } + +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if(spi == SPI0) + { + /* Reset SPI */ + SYS->IPRSTC2 |= SYS_IPRSTC2_SPI0_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI0_RST_Msk; + } + else if(spi == SPI1) + { + /* Reset SPI */ + SYS->IPRSTC2 |= SYS_IPRSTC2_SPI1_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI1_RST_Msk; + } + else if(spi == SPI2) + { + /* Reset SPI */ + SYS->IPRSTC2 |= SYS_IPRSTC2_SPI2_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI2_RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRSTC2 |= SYS_IPRSTC2_SPI3_RST_Msk; + SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI3_RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFO_CTL |= SPI_FIFO_CTL_RX_CLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFO_CTL |= SPI_FIFO_CTL_TX_CLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSR &= ~(SPI_SSR_AUTOSS_Msk | SPI_SSR_SSR_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS0, SPI_SS1) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSR = (spi->SSR & (~(SPI_SSR_AUTOSS_Msk | SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSR_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the actual SPI bus clock + * rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to HCLK and DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div; + + /* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk; + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI1) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI2) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2_S_Msk) == CLK_CLKSEL1_SPI2_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3_S_Msk) == CLK_CLKSEL1_SPI3_S_HCLK) + u32ClkSrc = u32HCLKFreq; + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Select HCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI0_S_Msk)) | CLK_CLKSEL1_SPI0_S_HCLK; + else if(spi == SPI1) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI1_S_Msk)) | CLK_CLKSEL1_SPI1_S_HCLK; + else if(spi == SPI2) + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI2_S_Msk)) | CLK_CLKSEL1_SPI2_S_HCLK; + else + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI3_S_Msk)) | CLK_CLKSEL1_SPI3_S_HCLK; + + /* Set DIVIDER = 0 */ + spi->DIVIDER = 0; + /* Return slave peripheral clock rate */ + return u32HCLKFreq; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->DIVIDER = 0; + /* Return master peripheral clock rate */ + return u32ClkSrc; + } + else if(u32BusClock == 0) + { + /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */ + spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk); + /* Set DIVIDER to the maximum value 0xFF */ + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / ((0xFF + 1) * 2)); + } + else + { + u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */ + if(u32Div > 0xFF) + { + /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */ + spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk); + u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */ + if(u32Div > 0xFF) + u32Div = 0xFF; + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / ((u32Div + 1) * 2)); + } + else + { + spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos); + /* Return master peripheral clock rate */ + return (u32ClkSrc / (u32Div + 1)); + } + } +} + +/** + * @brief Enable FIFO mode. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. + * @return None + * @details Enable FIFO mode with user-specified TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFO_CTL = (spi->FIFO_CTL & ~(SPI_FIFO_CTL_TX_THRESHOLD_Msk | SPI_FIFO_CTL_RX_THRESHOLD_Msk)) | + ((u32TxThreshold << SPI_FIFO_CTL_TX_THRESHOLD_Pos) | + (u32RxThreshold << SPI_FIFO_CTL_RX_THRESHOLD_Pos)); + + spi->CNTRL |= SPI_CNTRL_FIFO_Msk; +} + +/** + * @brief Disable FIFO mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details Clear FIFO bit of SPI_CNTRL register to disable FIFO mode. + */ +void SPI_DisableFIFO(SPI_T *spi) +{ + spi->CNTRL &= ~SPI_CNTRL_FIFO_Msk; +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency. + * @details This function will calculate the actual SPI bus clock rate according to the settings of SPIn_S, BCn and DIVIDER. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->DIVIDER & SPI_DIVIDER_DIVIDER_Msk) >> SPI_DIVIDER_DIVIDER_Pos; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI1) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI2) + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2_S_Msk) == CLK_CLKSEL1_SPI2_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else + { + if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3_S_Msk) == CLK_CLKSEL1_SPI3_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + + if(spi->CNTRL2 & SPI_CNTRL2_BCn_Msk) /* BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */ + { + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1)); + } + else /* BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */ + { + /* Return SPI bus clock rate */ + return (u32ClkSrc / ((u32Div + 1) * 2)); + } +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. + * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK, + * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK) + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + spi->CNTRL |= SPI_CNTRL_IE_Msk; + + /* Enable slave 3-wire mode start interrupt flag */ + if((u32Mask & SPI_SSTA_INT_MASK) == SPI_SSTA_INT_MASK) + spi->CNTRL2 |= SPI_CNTRL2_SSTA_INTEN_Msk; + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TX_INT_MASK) == SPI_FIFO_TX_INT_MASK) + spi->FIFO_CTL |= SPI_FIFO_CTL_TX_INTEN_Msk; + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RX_INT_MASK) == SPI_FIFO_RX_INT_MASK) + spi->FIFO_CTL |= SPI_FIFO_CTL_RX_INTEN_Msk; + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + spi->FIFO_CTL |= SPI_FIFO_CTL_RXOV_INTEN_Msk; + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) == SPI_FIFO_TIMEOUT_INT_MASK) + spi->FIFO_CTL |= SPI_FIFO_CTL_TIMEOUT_INTEN_Msk; +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. + * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK, + * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK) + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + spi->CNTRL &= ~SPI_CNTRL_IE_Msk; + + /* Disable slave 3-wire mode start interrupt flag */ + if((u32Mask & SPI_SSTA_INT_MASK) == SPI_SSTA_INT_MASK) + spi->CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk; + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TX_INT_MASK) == SPI_FIFO_TX_INT_MASK) + spi->FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk; + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RX_INT_MASK) == SPI_FIFO_RX_INT_MASK) + spi->FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk; + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + spi->FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk; + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) == SPI_FIFO_TIMEOUT_INT_MASK) + spi->FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk; +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. + * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK, + * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK) + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0; + + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (spi->CNTRL & SPI_CNTRL_IF_Msk)) + u32IntFlag |= SPI_UNIT_INT_MASK; + + /* Check slave 3-wire mode start interrupt flag */ + if((u32Mask & SPI_SSTA_INT_MASK) && (spi->CNTRL2 & SPI_CNTRL2_SLV_START_INTSTS_Msk)) + u32IntFlag |= SPI_SSTA_INT_MASK; + + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TX_INT_MASK) && (spi->STATUS & SPI_STATUS_TX_INTSTS_Msk)) + u32IntFlag |= SPI_FIFO_TX_INT_MASK; + + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RX_INT_MASK) && (spi->STATUS & SPI_STATUS_RX_INTSTS_Msk)) + u32IntFlag |= SPI_FIFO_RX_INT_MASK; + + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RX_OVERRUN_Msk)) + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) && (spi->STATUS & SPI_STATUS_TIMEOUT_Msk)) + u32IntFlag |= SPI_FIFO_TIMEOUT_INT_MASK; + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, + * SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK) + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + spi->CNTRL |= SPI_CNTRL_IF_Msk; /* Clear unit transfer interrupt flag */ + + if(u32Mask & SPI_SSTA_INT_MASK) + spi->CNTRL2 |= SPI_CNTRL2_SLV_START_INTSTS_Msk; /* Clear slave 3-wire mode start interrupt flag */ + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + spi->STATUS = SPI_STATUS_RX_OVERRUN_Msk; /* Clear RX overrun interrupt flag */ + + if(u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) + spi->STATUS = SPI_STATUS_TIMEOUT_Msk; /* Clear RX time-out interrupt flag */ +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. + * (SPI_BUSY_MASK, SPI_RX_EMPTY_MASK, SPI_RX_FULL_MASK, + * SPI_TX_EMPTY_MASK, SPI_TX_FULL_MASK) + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0; + + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (spi->CNTRL & SPI_CNTRL_GO_BUSY_Msk)) + u32Flag |= SPI_BUSY_MASK; + + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->CNTRL & SPI_CNTRL_RX_EMPTY_Msk)) + u32Flag |= SPI_RX_EMPTY_MASK; + + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (spi->CNTRL & SPI_CNTRL_RX_FULL_Msk)) + u32Flag |= SPI_RX_FULL_MASK; + + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->CNTRL & SPI_CNTRL_TX_EMPTY_Msk)) + u32Flag |= SPI_TX_EMPTY_MASK; + + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (spi->CNTRL & SPI_CNTRL_TX_FULL_Msk)) + u32Flag |= SPI_TX_FULL_MASK; + + return u32Flag; +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/sys.c b/BSP/StdDriver/src/sys.c new file mode 100644 index 0000000..760254b --- /dev/null +++ b/BSP/StdDriver/src/sys.c @@ -0,0 +1,206 @@ +/**************************************************************************//** + * @file sys.c + * @version V3.00 + * $Revision: 16 $ + * $Date: 15/05/04 3:59p $ + * @brief SYS driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NUC200Series.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSRC_RSTS_CPU_Msk + * - \ref SYS_RSTSRC_RSTS_SYS_Msk + * - \ref SYS_RSTSRC_RSTS_BOD_Msk + * - \ref SYS_RSTSRC_RSTS_LVR_Msk + * - \ref SYS_RSTSRC_RSTS_WDT_Msk + * - \ref SYS_RSTSRC_RSTS_RESET_Msk + * - \ref SYS_RSTSRC_RSTS_POR_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSRC |= u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0. + * @retval 1 System voltage is lower than BOD_VL setting. + * @details This function get Brown-out detector output status. + * If the BOD_EN is 0, this function always return 0. + */ +uint32_t SYS_GetBODStatus(void) +{ + return (SYS->BODCR & SYS_BODCR_BOD_OUT_Msk) ? 1 : 0; +} + +/** + * @brief Get reset source + * @param None + * @return Reset source + * @details This function get the system reset source register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSRC); +} + +/** + * @brief Check if register lock is set + * @param None + * @retval 0 Write-protection function is disabled. + * @retval 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return !(SYS->REGWRPROT & SYS_REGWRPROT_REGPROTDIS_Msk); +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + */ +void SYS_ResetChip(void) +{ + SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk; +} + +/** + * @brief Reset Module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref SPI3_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref PWM03_RST + * - \ref PWM47_RST + * - \ref ACMP_RST + * - \ref PS2_RST + * - \ref USBD_RST + * - \ref ADC_RST + * - \ref I2S_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + /* Generate reset signal to the corresponding module */ + *(volatile uint32_t *)((uint32_t)&SYS->IPRSTC1 + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff); + + /* Release corresponding module from reset state */ + *(volatile uint32_t *)((uint32_t)&SYS->IPRSTC1 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff)); + +} + +/** + * @brief Enable and set Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCR_BOD_RST_EN + * - \ref SYS_BODCR_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCR_BOD_VL_4_4V + * - \ref SYS_BODCR_BOD_VL_3_7V + * - \ref SYS_BODCR_BOD_VL_2_7V + * - \ref SYS_BODCR_BOD_VL_2_2V + * @return None + * @details This function configure Brown-out detector function. + * It configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + SYS->BODCR |= SYS_BODCR_BOD_EN_Msk; + SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_RSTEN_Msk) | i32Mode; + SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk; +} + + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/timer.c b/BSP/StdDriver/src/timer.c new file mode 100644 index 0000000..8e251df --- /dev/null +++ b/BSP/StdDriver/src/timer.c @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * $Revision: 11 $ + * $Date: 15/05/04 3:59p $ + * @brief Timer driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer in specified mode and frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real Timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->TCSR = u32Mode | u32Prescale; + timer->TCMPR = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops Timer counting and disable all Timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->TCSR = 0; + timer->TEXCON = 0; +} + +/** + * @brief Create a specify delay time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->TCSR = 0UL; + timer->TEXCON = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->TCMPR = u32Cmpr; + timer->TCSR = TIMER_TCSR_CEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* + When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. + */ + for(; u32Delay > 0UL; u32Delay--) + { + __NOP(); + } + + while(timer->TCSR & TIMER_TCSR_CACT_Msk); +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture edge. Possible values are + * - \ref TIMER_CAPTURE_FALLING_EDGE + * - \ref TIMER_CAPTURE_RISING_EDGE + * - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE + * + * @return None + * + * @details This API is used to enable timer capture function with specified mode and capture edge. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + + timer->TEXCON = (timer->TEXCON & ~(TIMER_TEXCON_RSTCAPSEL_Msk | + TIMER_TEXCON_TEX_EDGE_Msk)) | + u32CapMode | u32Edge | TIMER_TEXCON_TEXEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the Timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->TEXCON &= ~TIMER_TEXCON_TEXEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_FALLING_EDGE, or + * - \ref TIMER_COUNTER_RISING_EDGE + * + * @return None + * + * @details This function is used to enable the Timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->TEXCON = (timer->TEXCON & ~TIMER_TEXCON_TX_PHASE_Msk) | u32Edge; + timer->TCSR |= TIMER_TCSR_CTB_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the Timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->TCSR &= ~TIMER_TCSR_CTB_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the clock frequency of Timer. + * @note This API cannot return correct clock rate if timer source is external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src; + const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC}; + + if(timer == TIMER0) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos; + else if(timer == TIMER1) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos; + else if(timer == TIMER2) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2_S_Msk) >> CLK_CLKSEL1_TMR2_S_Pos; + else // Timer 3 + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3_S_Msk) >> CLK_CLKSEL1_TMR3_S_Pos; + + if(u32Src == 2) + { + return(SystemCoreClock); + } + + return(au32Clk[u32Src]); +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/uart.c b/BSP/StdDriver/src/uart.c new file mode 100644 index 0000000..12b0b78 --- /dev/null +++ b/BSP/StdDriver/src/uart.c @@ -0,0 +1,495 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * $Revision: 18 $ + * $Date: 16/03/04 9:25a $ + * @brief UART driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NUC200Series.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - UART_ISR_LIN_INT_Msk : LIN bus interrupt + * - UART_ISR_BUF_ERR_INT_Msk : Buffer Error interrupt + * - UART_ISR_MODEM_INT_Msk : Modem interrupt + * - UART_ISR_RLS_INT_Msk : Rx Line status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ +void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_ISR_RLS_INT_Msk) /* clear Receive Line Status Interrupt */ + { + uart->FSR = UART_FSR_BIF_Msk | UART_FSR_FEF_Msk | UART_FSR_PEF_Msk; + uart->FSR = UART_FSR_RS485_ADD_DETF_Msk; + } + + if(u32InterruptFlag & UART_ISR_MODEM_INT_Msk) /* clear Modem Interrupt */ + uart->MSR |= UART_MSR_DCTSF_Msk; + + if(u32InterruptFlag & UART_ISR_BUF_ERR_INT_Msk) /* clear Buffer Error Interrupt */ + { + uart->FSR = UART_FSR_RX_OVER_IF_Msk | UART_FSR_TX_OVER_IF_Msk; + } + + if(u32InterruptFlag & UART_ISR_LIN_INT_Msk) /* clear LIN break Interrupt */ + { + uart->ISR = UART_ISR_LIN_IF_Msk; + uart->LIN_SR = UART_LIN_SR_BIT_ERR_F_Msk | UART_LIN_SR_LINS_BKDET_F_Msk | + UART_LIN_SR_LINS_SYNC_F_Msk | UART_LIN_SR_LINS_IDPERR_F_Msk | + UART_LIN_SR_LINS_HERR_F_Msk | UART_LIN_SR_LINS_HDET_F_Msk ; + } + +} + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->IER = 0; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->IER &= ~(UART_IER_AUTO_RTS_EN_Msk | UART_IER_AUTO_CTS_EN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - UART_IER_LIN_IEN_Msk : LIN bus interrupt + * - UART_IER_WAKE_EN_Msk : Wakeup interrupt + * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt + * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt + * - UART_IER_MODEM_IEN_Msk : Modem interrupt + * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt + * - UART_IER_THRE_IEN_Msk : Tx empty interrupt + * - UART_IER_RDA_IEN_Msk : Rx ready interrupt + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); + + /* Disable NVIC UART IRQ */ + if(uart == UART0) + NVIC_DisableIRQ(UART02_IRQn); + else if(uart == UART1) + NVIC_DisableIRQ(UART1_IRQn); + else + NVIC_DisableIRQ(UART02_IRQn); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MCR |= UART_MCR_LEV_RTS_Msk; + + /* Set CTS pin input is low level active */ + uart->MSR |= UART_MSR_LEV_CTS_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->IER |= UART_IER_AUTO_RTS_EN_Msk | UART_IER_AUTO_CTS_EN_Msk; +} + + +/** + * @brief Enable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - UART_IER_LIN_IEN_Msk : LIN bus interrupt + * - UART_IER_WAKE_EN_Msk : Wakeup interrupt + * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt + * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt + * - UART_IER_MODEM_IEN_Msk : Modem interrupt + * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt + * - UART_IER_THRE_IEN_Msk : Tx empty interrupt + * - UART_IER_RDA_IEN_Msk : Rx ready interrupt + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); + + /* Enable NVIC UART IRQ */ + if(uart == UART0) + NVIC_EnableIRQ(UART02_IRQn); + else if(uart == UART1) + NVIC_EnableIRQ(UART1_IRQn); + else + NVIC_EnableIRQ(UART02_IRQn); + +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint8_t u8UartClkSrcSel, u8UartClkDivNum; + uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC}; + uint32_t u32Baud_Div = 0; + + /* Get UART clock source selection */ + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + /* Get UART clock divider number */ + u8UartClkDivNum = (CLK->CLKDIV & CLK_CLKDIV_UART_N_Msk) >> CLK_CLKDIV_UART_N_Pos; + + /* Select UART function */ + uart->FUN_SEL = UART_FUNC_SEL_UART; + + /* Set UART line configuration */ + uart->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FCR &= ~(UART_FCR_RFITL_Msk | UART_FCR_RTS_TRI_LEV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u8UartClkSrcSel == 1) + u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq(); + + /* Set UART baud rate */ + if(u32baudrate != 0) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate); + + if(u32Baud_Div > 0xFFFF) + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate)); + else + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0; + + while(uart->FSR & UART_FSR_RX_EMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000) + return FALSE; + } + pu8RxBuf[u32Count] = uart->RBR; /* Get Data from UART RX */ + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - UART_WORD_LEN_5 + * - UART_WORD_LEN_6 + * - UART_WORD_LEN_7 + * - UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - UART_PARITY_NONE + * - UART_PARITY_ODD + * - UART_PARITY_EVEN + * - UART_PARITY_MARK + * - UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - UART_STOP_BIT_1 + * - UART_STOP_BIT_1_5 + * - UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + + */ +void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint8_t u8UartClkSrcSel, u8UartClkDivNum; + uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC}; + uint32_t u32Baud_Div = 0; + + /* Get UART clock source selection */ + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + /* Get UART clock divider number */ + u8UartClkDivNum = (CLK->CLKDIV & CLK_CLKDIV_UART_N_Msk) >> CLK_CLKDIV_UART_N_Pos; + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u8UartClkSrcSel == 1) + u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq(); + + /* Set UART baud rate */ + if(u32baudrate != 0) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate); + + if(u32Baud_Div > 0xFFFF) + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate)); + else + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + + /* Set UART line configuration */ + uart->LCR = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOR = (uart->TOR & ~UART_TOR_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->IER |= UART_IER_TIME_OUT_EN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode: + * - UART_IRCR_TX_SELECT + * - UART_IRCR_RX_SELECT + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint8_t u8UartClkSrcSel, u8UartClkDivNum; + uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC}; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUN_SEL = UART_FUNC_SEL_IrDA; + + /* Get UART clock source selection */ + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + /* Get UART clock divider number */ + u8UartClkDivNum = (CLK->CLKDIV & CLK_CLKDIV_UART_N_Msk) >> CLK_CLKDIV_UART_N_Pos; + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u8UartClkSrcSel == 1) + u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq(); + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32Buadrate); + + if(u32Baud_Div < 0xFFFF) + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRCR_RX_SELECT) + { + uart->IRCR |= UART_IRCR_INV_RX_Msk; //Rx signal is inverse + uart->IRCR &= ~UART_IRCR_TX_SELECT_Msk; + } + else + { + uart->IRCR &= ~UART_IRCR_INV_TX_Msk; //Tx signal is not inverse + uart->IRCR |= UART_IRCR_TX_SELECT_Msk; + } +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - UART_ALT_CSR_RS485_NMM_Msk + * - UART_ALT_CSR_RS485_AUD_Msk + * - UART_ALT_CSR_RS485_AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUN_SEL = UART_FUNC_SEL_RS485; + + /* Set RS585 configuration */ + uart->ALT_CSR &= ~(UART_ALT_CSR_RS485_NMM_Msk | UART_ALT_CSR_RS485_AUD_Msk | UART_ALT_CSR_RS485_AAD_Msk | UART_ALT_CSR_ADDR_MATCH_Msk); + uart->ALT_CSR |= (u32Mode | (u32Addr << UART_ALT_CSR_ADDR_MATCH_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - UART_ALT_CSR_LIN_TX_EN_Msk + * - UART_ALT_CSR_LIN_RX_EN_Msk + * - (UART_ALT_CSR_LIN_TX_EN_Msk|UART_ALT_CSR_LIN_RX_EN_Msk) + * @param[in] u32BreakLength The breakfield length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUN_SEL = UART_FUNC_SEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALT_CSR &= ~(UART_ALT_CSR_LIN_TX_EN_Msk | UART_ALT_CSR_LIN_RX_EN_Msk | UART_ALT_CSR_UA_LIN_BKFL_Msk); + uart->ALT_CSR |= (u32Mode | (u32BreakLength << UART_ALT_CSR_UA_LIN_BKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0; + while((uart->FSR & UART_FSR_TE_FLAG_Msk) == 0) /* Wait Tx empty and Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000) + return FALSE; + } + uart->THR = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + + return u32Count; + +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2012 Nuvoton Technology Corp. ***/ + + + diff --git a/BSP/StdDriver/src/usbd.c b/BSP/StdDriver/src/usbd.c new file mode 100644 index 0000000..9121f02 --- /dev/null +++ b/BSP/StdDriver/src/usbd.c @@ -0,0 +1,689 @@ +/**************************************************************************//** + * @file usbd.c + * @version V3.00 + * $Revision: 19 $ + * $Date: 15/07/17 1:36p $ + * @brief USBD driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include "NUC200Series.h" + +#if 0 +#define DBG_PRINTF printf +#else +#define DBG_PRINTF(...) +#endif +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0}; /*!< Setup packet buffer */ +volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */ + +static volatile uint8_t *g_usbd_CtrlInPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0; +static volatile uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlOutSize = 0; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0; +static volatile uint32_t g_usbd_UsbAddr = 0; +static volatile uint32_t g_usbd_UsbConfig = 0; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8; +static volatile uint32_t g_usbd_UsbAltInterface = 0; +static volatile uint32_t g_usbd_CtrlOutToggle = 0; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0; + +const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + USBD->ATTR = 0x7D0; + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + CLK_SysTickDelay(100000); + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + g_usbd_CtrlOutToggle = 0; + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8); + + /* Check the request type */ + switch(g_usbd_SetupPacket[0] & 0x60) + { + case REQ_STANDARD: // Standard + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: // Class + { + if(g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: // Vendor + { + if(g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: // reserved + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0; + u32Len = 0; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8; + u32Len += g_usbd_SetupPacket[6]; + + switch(g_usbd_SetupPacket[3]) + { + // Get Device Descriptor + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + DBG_PRINTF("Get device desc, %d\n", u32Len); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + USBD_PrepareCtrlOut(0, 0); + break; + } + // Get Configuration Descriptor + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + USBD_PrepareCtrlOut(0, 0); + break; + } + // Get HID Descriptor + case DESC_HID: + { + u32Len = Minimum(u32Len, LEN_HID); + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[LEN_CONFIG + LEN_INTERFACE], u32Len); + USBD_PrepareCtrlOut(0, 0); + break; + } + // Get Report Descriptor + case DESC_HID_RPT: + { + uint32_t u32TotalLen; + uint32_t u32RptDescLen; + + /* Get configuration descriptor size */ + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + /* Calculate the offset of HID report descriptor size to get report descriptor size. + User may need to modify this if configuration descriptor changed. */ + u32RptDescLen = g_usbd_sInfo->gu8ConfigDesc[u32TotalLen - LEN_ENDPOINT - 1]; + u32RptDescLen = g_usbd_sInfo->gu8ConfigDesc[u32TotalLen - LEN_ENDPOINT - 2] + (u32RptDescLen << 8); + + if(u32Len > u32RptDescLen) + { + u32Len = u32RptDescLen; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc, u32Len); + USBD_PrepareCtrlOut(0, 0); + break; + } + // Get String Descriptor + case DESC_STRING: + { + // Get String Descriptor + if(g_usbd_SetupPacket[2] < 4) + { + if(u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + USBD_PrepareCtrlOut(0, 0); + break; + } + else + { + // Not support. Reply STALL. + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_usbd_SetupPacket[2]); + break; + } + } + default: + // Not support. Reply STALL. + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n"); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + + if(g_usbd_SetupPacket[0] & 0x80) /* request data transfer direction */ + { + // Device to host + switch(g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + // Return current configuration setting + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig; + USBD_SET_DATA1(EP1); + USBD_SET_PAYLOAD_LEN(EP1, 0); + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0); + DBG_PRINTF("Get configuration\n"); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0); + DBG_PRINTF("Get descriptor\n"); + break; + } + case GET_INTERFACE: + { + // Return current interface setting + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0); + DBG_PRINTF("Get interface\n"); + break; + } + case GET_STATUS: + { + // Device + if(g_usbd_SetupPacket[0] == 0x80) + { + uint8_t u8Tmp; + + u8Tmp = 0; + if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered. + if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp; + } + // Interface + else if(g_usbd_SetupPacket[0] == 0x81) + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0; + // Endpoint + else if(g_usbd_SetupPacket[0] == 0x82) + { + uint8_t ep = g_usbd_SetupPacket[4] & 0xF; + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep) ? 1 : 0; + } + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0); + DBG_PRINTF("Get status\n"); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + DBG_PRINTF("Unknown request. stall ctrl pipe.\n"); + break; + } + } + } + else + { + // Host to device + switch(g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + int32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = g_usbd_SetupPacket[4] & 0xF; + for(i = 0; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk; + DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP); + } + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + g_usbd_RemoteWakeupEn = 0; + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + DBG_PRINTF("Clear feature op %d\n", g_usbd_SetupPacket[2]); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + DBG_PRINTF("Set addr to %d\n", g_usbd_UsbAddr); + + // DATA IN for end of setup + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if(g_usbd_pfnSetConfigCallback) + g_usbd_pfnSetConfigCallback(); + // DATA IN for end of setup + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + DBG_PRINTF("Set config to %d\n", g_usbd_UsbConfig); + break; + } + case SET_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall(g_usbd_SetupPacket[4] & 0xF); + DBG_PRINTF("Set feature. stall ep %d\n", g_usbd_SetupPacket[4] & 0xF); + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = 1; + DBG_PRINTF("Set feature. enable remote wakeup\n"); + } + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + if(g_usbd_pfnSetInterface != NULL) + g_usbd_pfnSetInterface(); + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + DBG_PRINTF("Set interface to %d\n", g_usbd_UsbAltInterface); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + DBG_PRINTF("Unsupported request. stall ctrl pipe.\n"); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size) +{ + DBG_PRINTF("Prepare Ctrl In %d\n", u32Size); + if(u32Size > g_usbd_CtrlMaxPktSize) + { + // Data size > MXPLD + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + // Data size <= MXPLD + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + DBG_PRINTF("Ctrl In Ack. residue %d\n", g_usbd_CtrlInSize); + if(g_usbd_CtrlInSize) + { + // Process remained data + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + // Data size > MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + // Data size <= MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + } + } + else // No more data for IN token + { + // In ACK for Set address + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0); + g_usbd_CtrlInZeroFlag = 0; + } + DBG_PRINTF("Ctrl In done.\n"); + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + + DBG_PRINTF("Ctrl Out Ack %d\n", g_usbd_CtrlOutSize); + if(g_usbd_CtrlOutToggle != (USBD->EPSTS & USBD_EPSTS_EPSTS1_Msk)) + { + g_usbd_CtrlOutToggle = USBD->EPSTS & USBD_EPSTS_EPSTS1_Msk; + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } + } + else + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + int i; + + // Reset all variables for protocol + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0; + g_usbd_CtrlOutSizeLimit = 0; + g_u32EpStallLock = 0; + memset(g_usbd_SetupPacket, 0, 8); + + /* Reset PID DATA0 */ + for(i=0; iEP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk; + + // Reset USB device address + USBD_SET_ADDR(0); +} + +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} + +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/wdt.c b/BSP/StdDriver/src/wdt.c new file mode 100644 index 0000000..894f59d --- /dev/null +++ b/BSP/StdDriver/src/wdt.c @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * $Revision: 10 $ + * $Date: 15/05/04 3:59p $ + * @brief WDT driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT counter and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure reset delay period while WDT time-out happened. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function make WDT module start counting with different time-out interval and reset delay period. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->WTCRALT = u32ResetDelay; + + WDT->WTCR = u32TimeoutInterval | WDT_WTCR_WTE_Msk | + (u32EnableReset << WDT_WTCR_WTRE_Pos) | + (u32EnableWakeup << WDT_WTCR_WTWKE_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/BSP/StdDriver/src/wwdt.c b/BSP/StdDriver/src/wwdt.c new file mode 100644 index 0000000..97c0c94 --- /dev/null +++ b/BSP/StdDriver/src/wwdt.c @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * $Revision: 8 $ + * $Date: 15/05/04 3:59p $ + * @brief WWDT driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NUC200Series.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT function to start counting + * + * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function make WWDT module start counting with different counter period and compared window value. + * @note Application can call this function valid only once after boot up. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->WWDTCR = u32PreScale | + (u32CmpValue << WWDT_WWDTCR_WINCMP_Pos) | + ((u32EnableInt == TRUE) ? WWDT_WWDTCR_WWDTIE_Msk : 0) | + WWDT_WWDTCR_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..360e664 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,117 @@ +cmake_minimum_required(VERSION 3.10) + +project(NUC200_Template) + +enable_language(CXX) +enable_language(ASM) + +# Extra CFlags +set(TARGET_CFLAGS_EXTRA "") +set(TARGET_CXXFLAGS_EXTRA "") +set(TARGET_LDFLAGS_EXTRA "-Wl,--print-memory-usage") + +# Different linker scripts +set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/BSP/Device/Nuvoton/NUC200Series/Source/GCC/gcc_arm.ld") + +# Copy them from Makefile +set(TARGET_C_SOURCES + # "BSP/Device/Nuvoton/NUC200Series/Source/GCC/_syscalls.c" # Not used + "BSP/Device/Nuvoton/NUC200Series/Source/system_NUC200Series.c" + "BSP/StdDriver/src/acmp.c" + "BSP/StdDriver/src/adc.c" + "BSP/StdDriver/src/clk.c" + "BSP/StdDriver/src/crc.c" + "BSP/StdDriver/src/fmc.c" + "BSP/StdDriver/src/gpio.c" + "BSP/StdDriver/src/i2c.c" + "BSP/StdDriver/src/i2s.c" + "BSP/StdDriver/src/pdma.c" + "BSP/StdDriver/src/ps2.c" + "BSP/StdDriver/src/pwm.c" + # "BSP/StdDriver/src/retarget.c" # Low quality code. + "BSP/StdDriver/src/rtc.c" + "BSP/StdDriver/src/sc.c" + "BSP/StdDriver/src/spi.c" + "BSP/StdDriver/src/sys.c" + "BSP/StdDriver/src/timer.c" + "BSP/StdDriver/src/uart.c" + "BSP/StdDriver/src/usbd.c" + "BSP/StdDriver/src/wdt.c" + "BSP/StdDriver/src/wwdt.c" + "src/main.c" +) + +# Copy them from Makefile +set(TARGET_ASM_SOURCES + "BSP/Device/Nuvoton/NUC200Series/Source/GCC/startup_NUC200Series.S" +) + +# Copy them from Makefile +set(TARGET_C_DEFINES +) + +# Copy them from Makefile +set(TARGET_C_INCLUDES + "BSP/CMSIS/Include" + "BSP/Device/Nuvoton/NUC200Series/Include" + "BSP/SmartcardLib/Include" + "BSP/StdDriver/inc" +) + +# Shared libraries linked with application +set(TARGET_LIBS + "smartcard" +) + +# Shared library and linker script search paths +set(TARGET_LIB_DIRECTORIES + "BSP/SmartcardLib" +) + +# Device specific settings, goes to CFLAGS and LDFLAGS +set(TARGET_CFLAGS_HARDWARE "-mcpu=cortex-m0 -mthumb") + +# Conditional flags +# DEBUG +set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -Og -g") +set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -Og -g") +set(CMAKE_ASM_FLAGS_DEBUG "-DDEBUG -Og -g") + +# RELEASE +set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto") +set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto") +set(CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG -O2 -flto") +set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto") + +# Final compiler flags +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_CFLAGS_HARDWARE} ${TARGET_CFLAGS_EXTRA} -Wall -fdata-sections -ffunction-sections") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${TARGET_CFLAGS_HARDWARE} ${TARGET_CXXFLAGS_EXTRA} -Wall -fdata-sections -ffunction-sections") +set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} ${CMAKE_C_FLAGS} -x assembler-with-cpp") +set(CMAKE_EXE_LINKER_FLAGS "-specs=nano.specs -Wl,--gc-sections -lc -lm -lnosys ${TARGET_LDFLAGS_EXTRA}") + +# Include sub directories here + +# Shared sources, includes and definitions +add_compile_definitions(${TARGET_C_DEFINES}) +include_directories(${TARGET_C_INCLUDES}) +link_directories(${TARGET_LIB_DIRECTORIES}) +link_libraries(${TARGET_LIBS}) + +# Main targets are added here + +# **** Internal Flash **** + +# Create ELF +add_executable("${CMAKE_PROJECT_NAME}_FLASH.elf" ${TARGET_C_SOURCES} ${TARGET_ASM_SOURCES}) +target_link_options("${CMAKE_PROJECT_NAME}_FLASH.elf" + PRIVATE "-T${TARGET_LDSCRIPT_FLASH}" + PRIVATE "-Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}_FLASH.map,--cref" +) + +add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLASH.hex" + COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLASH.elf" "${CMAKE_PROJECT_NAME}_FLASH.hex" + DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.elf" +) +add_custom_target("${CMAKE_PROJECT_NAME}_FLASH_HEX" DEPENDS "${CMAKE_PROJECT_NAME}_FLASH.hex") + +# **** Cortex-M0 does not support SCB->VTOR configuration, so RAM debug is not possible. **** \ No newline at end of file diff --git a/arm-none-eabi.cmake b/arm-none-eabi.cmake new file mode 100644 index 0000000..83616fe --- /dev/null +++ b/arm-none-eabi.cmake @@ -0,0 +1,4 @@ +set(CMAKE_C_COMPILER arm-none-eabi-gcc) +set(CMAKE_CXX_COMPILER arm-none-eabi-g++) +# Make CMake happy about those compilers +set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") \ No newline at end of file diff --git a/run_debugserver.sh b/run_debugserver.sh new file mode 100755 index 0000000..d87b0bf --- /dev/null +++ b/run_debugserver.sh @@ -0,0 +1,38 @@ +#!/bin/bash + +run_jlinkserver() { + JLinkGDBServerCLExe -if SWD -device STM32H750VBTx \ + -ir -localhostonly -nogui \ + -rtos GDBServer/RTOSPlugin_FreeRTOS.so +} + +run_openocd_stlink() { + openocd -f "interface/stlink.cfg" -f "target/stm32h7x.cfg" +} + +run_openocd_jlink() { + openocd -f "interface/jlink.cfg" -c "transport select swd" -f "target/stm32h7x.cfg" +} + +run_pyocd() { + pyocd gdbserver -t stm32h750vbtx -f 24m --persist +} + +case $1 in + jlink) + run_jlinkserver + ;; + + pyocd) + run_pyocd + ;; + + openocd-stlink) + run_openocd_stlink + ;; + + openocd-jlink) + run_openocd_jlink + ;; + +esac \ No newline at end of file diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..d4ed1fd --- /dev/null +++ b/src/main.c @@ -0,0 +1,8 @@ +#include "NUC200Series.h" + +int main(int argc, const char *argv[]) { + SystemCoreClockUpdate(); + + for(;;) { + } +} \ No newline at end of file