88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
#include "NUC200Series.h"
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/**
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* This function enables external crystal oscillator,
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* configures internal PLL and switch CPU and Bus clock
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* to PLL frequency.
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*/
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static void system_clock_config(void) {
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/**
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* Configure External crystal input
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* Note: This register is guarded.
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*/
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SYS_UnlockReg();
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CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; /* Enable XTL12M */
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SYS_LockReg();
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while (!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk)) {
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/* Wait until external crystal stabilized */
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}
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/**
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* Configure PLL
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* NUC200 series has 1 PLL, up to 50MHz.
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* We set up PLL running at 48MHz, which is default.
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* PLLCON register:
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* OUT_DV = 3, NO = 4
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* IN_DV = 1, NR = 3
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* FB_DV = 46, NF = 48
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* PLL FOUT = FIN * (NF / NR) * (1 / NO) = 12MHz * (48 / 3) * (1 / 4) = 48MHz
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*/
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CLK->PLLCON = (CLK_PLLCON_IN_DV_Msk & (1U << CLK_PLLCON_IN_DV_Pos)) |
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(CLK_PLLCON_FB_DV_Msk & (46U << CLK_PLLCON_FB_DV_Pos)) |
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(CLK_PLLCON_OUT_DV_Msk & (3U << CLK_PLLCON_OUT_DV_Pos));
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CLK->PLLCON &= ~CLK_PLLCON_OE_Msk; /* Enable PLL FOUT output. NOTE: This bit is active-low! */
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while (!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk)) {
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/* Wait until PLL clock stabilized */
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}
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/**
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* Configure Clock dividers.
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* NUC200 series has 2 divider registers, one for SC peripherals,
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* another for everything else.
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* ADC: 12MHz
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* UART: 12MHz
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* USB: 48MHz
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* HCLK: 48MHz
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* SC0-2: 12MHz
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*/
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CLK->CLKDIV = CLK_CLKDIV_ADC(4) | CLK_CLKDIV_UART(4) | CLK_CLKDIV_USB(1) | CLK_CLKDIV_HCLK(1);
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CLK->CLKDIV1 = CLK_CLKDIV1_SC2(4) | CLK_CLKDIV1_SC1(4) | CLK_CLKDIV1_SC0(4);
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/**
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* Configure Clock selectors.
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* Some of these register bits (in CLKSEL0) are guarded by a latch register,
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* however it will not cleared automatically by write operations.
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* Clear the latch manually after clock changes.
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*/
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SYS_UnlockReg();
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CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL; /* HCLK */
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SYS_LockReg();
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SysTick->CTRL &= ~(SysTick_CTRL_CLKSOURCE_Msk); /* SysTick */
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SysTick->CTRL |= CLK_CLKSEL0_STCLK_S_HCLK;
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CLK->CLKSEL1 = 0xFFFFFFFF; /* Reset value */
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CLK->CLKSEL1 &= ~CLK_CLKSEL1_SPI0_S_Msk;
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CLK->CLKSEL1 |= CLK_CLKSEL1_SPI0_S_HCLK;
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CLK->CLKSEL2 = 0x200FFU; /* Reset value */
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CLK->CLKSEL3 = 0x3FU; /* Reset value */
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SystemCoreClockUpdate();
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}
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static void pinmux_config(void) {
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// Nothing for now.
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}
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int main(int argc, const char *argv[]) {
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system_clock_config();
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pinmux_config();
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for (;;) {
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}
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} |