238 lines
11 KiB
C
238 lines
11 KiB
C
/**************************************************************************//**
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* @file pwm.h
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* @version V3.00
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* $Revision: 12 $
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* $Date: 15/05/06 2:33p $
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* @brief PWM driver header file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PWM_H__
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#define __PWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
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@{
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*/
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#define PWM_CHANNEL_NUM (4) /*!< PWM channel number */
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#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
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#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
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#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
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#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
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#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
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#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
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#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type */
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#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt triggered if counter underflow */
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#define PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT01TYPE_Msk) /*!< PWM period interrupt triggered if counter match CNR */
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#define PWM_CAPTURE_INT_RISING_LATCH (PWM_CCR0_CRL_IE0_Msk) /*!< PWM capture interrupt if channel has rising transition */
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#define PWM_CAPTURE_INT_FALLING_LATCH (PWM_CCR0_CFL_IE0_Msk) /*!< PWM capture interrupt if channel has falling transition */
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/*---------------------------------------------------------------------------------------------------------*/
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/* PWM Group channel number constants definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define PWM_CH0 0x0 /*!< PWM Group A/B channel 0 */
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#define PWM_CH1 0x1 /*!< PWM Group A/B channel 1 */
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#define PWM_CH2 0x2 /*!< PWM Group A/B channel 2 */
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#define PWM_CH3 0x3 /*!< PWM Group A/B channel 3 */
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#define PWM_CCR_MASK 0x000F000F /*!< PWM CCR0/CCR2 bit0~3 and bit16~19 mask */
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/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
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/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief Enable output inverter of specified channel(s)
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* @details This macro is used to enable capture input inverter for specified channel(s).
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* \hideinitializer
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*/
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#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
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do{ \
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int i;\
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(pwm)->PCR &= ~(PWM_PCR_CH0INV_Msk|PWM_PCR_CH1INV_Msk|PWM_PCR_CH2INV_Msk|PWM_PCR_CH3INV_Msk);\
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for(i = 0; i < 4; i++) { \
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if((u32ChannelMask) & (1 << i)) \
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(pwm)->PCR |= (PWM_PCR_CH0INV_Msk << (PWM_PCR_CH0INV_Pos * (i * 4))); \
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} \
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}while(0)
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/**
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* @brief Get captured rising data of specified channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @return The timer counter, 0~0xFFFF
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* @details This macro is used to get captured rising data for specified channel.
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*/
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#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CRLR0)) + (u32ChannelNum) * 8))))
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/**
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* @brief Get captured falling data of specified channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @return The timer counter, 0~0xFFFF
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* @details This macro is used to get captured falling data for specified channel.
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*/
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#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CFLR0)) + (u32ChannelNum) * 8))))
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/**
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* @brief Set the prescaler of the selected channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
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* @return None
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* @details This macro is used to set timer pre-scale for specified channel.
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* @note If u32Prescaler = 0, corresponding PWM-timer will be stopped.
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* @note If u32Prescaler = x (x not equal to 0), it means Clock input is divided by (x + 1) before it is fed to the corresponding PWM counter.
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*/
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#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
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((pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
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/**
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* @brief Set the divider of the selected channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @param[in] u32Divider Clock divider of specified channel. Valid values are
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* - \ref PWM_CLK_DIV_1
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* - \ref PWM_CLK_DIV_2
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* - \ref PWM_CLK_DIV_4
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* - \ref PWM_CLK_DIV_8
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* - \ref PWM_CLK_DIV_16
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* @return None
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* @details This macro is used to set Timer clock source divider selection for specified channel.
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*/
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#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
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((pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
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/**
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* @brief Set the duty of the selected channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @details This macro is used to set PWM Comparator value for specified channel.
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* @note This new setting will take effect on next PWM period.
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*/
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#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CMR0)) + (u32ChannelNum) * 12))) = (u32CMR))
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/**
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* @brief Set the period of the selected channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @details This macro is used to set timer loaded value(CNR) for specified channel.\n
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* Loaded value determines the PWM period.
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* @note This new setting will take effect on next PWM period.
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* @note PWM counter will stop if period length set to 0.
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*/
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#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CNR0)) + (u32ChannelNum) * 12))) = (u32CNR))
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/**
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* @brief Set the PWM aligned type
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* @param[in] pwm The pointer of the specified PWM module
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* - PWMA : PWM Group A
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* - PWMB : PWM Group B
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32AlignedType PWM aligned type, valid values are:
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* - \ref PWM_EDGE_ALIGNED
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* - \ref PWM_CENTER_ALIGNED
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* @return None
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* @details This macro is used to set the PWM aligned type.
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* @note PWM trigger ADC function is only supported when PWM operating at Center-aligned type.
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* \hideinitializer
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*/
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#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
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do{ \
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int i; \
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for(i = 0; i < 4; i++) { \
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if((u32ChannelMask) & (1 << i)) \
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(pwm)->PCR = ((pwm)->PCR & ~(PWM_PCR_PWM01TYPE_Msk << (i >> 1))) | ((u32AlignedType) << (PWM_PCR_PWM01TYPE_Pos + (i >> 1))); \
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} \
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}while(0)
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uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32UnitTimeNsec,
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uint32_t u32CaptureEdge);
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequncy,
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uint32_t u32DutyCycle);
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
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void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
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void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
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void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group PWM_Driver */
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/*@}*/ /* end of group Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PWM_H__
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/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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