393 lines
17 KiB
C
393 lines
17 KiB
C
/**************************************************************************//**
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* @file spi.h
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* @version V3.0
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* $Revision: 15 $
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* $Date: 15/05/28 9:45p $
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* @brief SPI Driver Header File
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*
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******************************************************************************/
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#ifndef __SPI_H__
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#define __SPI_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup SPI_Driver SPI Driver
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@{
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*/
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/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
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@{
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*/
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#define SPI_MODE_0 (SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
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#define SPI_MODE_1 (SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
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#define SPI_MODE_2 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
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#define SPI_MODE_3 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
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#define SPI_SLAVE (SPI_CNTRL_SLAVE_Msk) /*!< Set as slave */
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#define SPI_MASTER (0x0) /*!< Set as master */
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#define SPI_SS0 (1<<SPI_SSR_SSR_Pos) /*!< Select SPIn_SS0 */
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#define SPI_SS1 (2<<SPI_SSR_SSR_Pos) /*!< Select SPIn_SS1 */
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#define SPI_SS_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS active high */
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#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
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#define SPI_UNIT_INT_MASK (0x01) /*!< Unit transfer interrupt mask */
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#define SPI_SSTA_INT_MASK (0x02) /*!< Slave 3-Wire mode start interrupt mask */
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#define SPI_FIFO_TX_INT_MASK (0x04) /*!< FIFO TX interrupt mask */
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#define SPI_FIFO_RX_INT_MASK (0x08) /*!< FIFO RX interrupt mask */
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#define SPI_FIFO_RXOV_INT_MASK (0x10) /*!< FIFO RX overrun interrupt mask */
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#define SPI_FIFO_TIMEOUT_INT_MASK (0x20) /*!< FIFO RX timeout interrupt mask */
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#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
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#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
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#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
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#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
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#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
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#define SPI_FIFO_SIZE (8) /*!< NUC200 Series provides separate 8-layer transmit and receive FIFO buffers */
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/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
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/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
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@{
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*/
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/**
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* @brief Abort the current transfer in Slave 3-wire mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set the SLV_ABORT bit of SPI_CNTRL2 register to abort the current transfer in Slave 3-wire mode.
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*/
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#define SPI_ABORT_3WIRE_TRANSFER(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk)
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/**
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* @brief Clear the Slave 3-wire mode start interrupt flag.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Write 1 to SLV_START_INTSTS bit of SPI_STATUS register to clear the Slave 3-wire mode start interrupt flag.
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*/
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#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk)
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/**
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* @brief Clear the unit transfer interrupt flag.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Write 1 to IF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
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*/
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#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_IF_Msk)
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/**
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* @brief Disable 2-bit Transfer mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear TWOB bit of SPI_CNTRL register to disable 2-bit Transfer mode.
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*/
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#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CNTRL &= ~SPI_CNTRL_TWOB_Msk)
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/**
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* @brief Disable Slave 3-wire mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear NOSLVSEL bit of SPI_CNTRL2 register to disable Slave 3-wire mode.
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*/
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#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk)
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/**
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* @brief Disable Dual I/O mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear DUAL_IO_EN bit of SPI_CNTRL2 register to disable Dual I/O mode.
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*/
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#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_DUAL_IO_EN_Msk)
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/**
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* @brief Enable 2-bit Transfer mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set TWOB bit of SPI_CNTRL register to enable 2-bit Transfer mode.
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*/
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#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CNTRL |= SPI_CNTRL_TWOB_Msk)
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/**
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* @brief Enable Slave 3-wire mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set NOSLVSEL bit of SPI_CNTRL2 register to enable Slave 3-wire mode.
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* Only available in Slave mode.
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*/
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#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk)
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/**
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* @brief Enable Dual input mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear DUAL_IO_DIR bit and set DUAL_IO_EN bit of SPI_CNTRL2 register to enable Dual input mode.
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*/
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#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CNTRL2 = ((spi)->CNTRL2 & (~SPI_CNTRL2_DUAL_IO_DIR_Msk)) | SPI_CNTRL2_DUAL_IO_EN_Msk)
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/**
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* @brief Enable Dual output mode.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set DUAL_IO_DIR bit and DUAL_IO_EN bit of SPI_CNTRL2 register to enable Dual output mode.
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*/
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#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CNTRL2 |= (SPI_CNTRL2_DUAL_IO_EN_Msk | SPI_CNTRL2_DUAL_IO_DIR_Msk))
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/**
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* @brief Trigger RX PDMA function.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set RX_DMA_GO bit of SPI_DMA register to enable RX PDMA transfer function.
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*/
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#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->DMA |= SPI_DMA_RX_DMA_GO_Msk)
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/**
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* @brief Trigger TX PDMA function.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set TX_DMA_GO bit of SPI_DMA register to enable TX PDMA transfer function.
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*/
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#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->DMA |= SPI_DMA_TX_DMA_GO_Msk)
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/**
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* @brief Trigger TX and RX PDMA function.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set TX_DMA_GO bit and RX_DMA_GO bit of SPI_DMA register to enable TX and RX PDMA transfer function.
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*/
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#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->DMA |= (SPI_DMA_TX_DMA_GO_Msk | SPI_DMA_RX_DMA_GO_Msk))
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/**
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* @brief Get the count of available data in RX FIFO.
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* @param[in] spi The pointer of the specified SPI module.
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* @return The count of available data in RX FIFO.
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* @details Read RX_FIFO_COUNT (SPI_STATUS[15:12]) to get the count of available data in RX FIFO.
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*/
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#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos)
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/**
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* @brief Get the RX FIFO empty flag.
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* @param[in] spi The pointer of the specified SPI module.
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* @retval 0 RX FIFO is not empty.
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* @retval 1 RX FIFO is empty.
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* @details Read RX_EMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
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*/
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#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk)>>SPI_STATUS_RX_EMPTY_Pos)
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/**
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* @brief Get the TX FIFO empty flag.
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* @param[in] spi The pointer of the specified SPI module.
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* @retval 0 TX FIFO is not empty.
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* @retval 1 TX FIFO is empty.
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* @details Read TX_EMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
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*/
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#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk)>>SPI_STATUS_TX_EMPTY_Pos)
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/**
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* @brief Get the TX FIFO full flag.
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* @param[in] spi The pointer of the specified SPI module.
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* @retval 0 TX FIFO is not full.
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* @retval 1 TX FIFO is full.
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* @details Read TX_FULL bit of SPI_STATUS register to get the TX FIFO full flag.
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*/
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#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_FULL_Msk)>>SPI_STATUS_TX_FULL_Pos)
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/**
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* @brief Get the datum read from RX0 register.
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* @param[in] spi The pointer of the specified SPI module.
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* @return Data in RX0 register.
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* @details Read SPI_RX0 register to get the received datum.
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*/
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#define SPI_READ_RX0(spi) ((spi)->RX[0])
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/**
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* @brief Get the datum read from RX1 register.
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* @param[in] spi The pointer of the specified SPI module.
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* @return Data in RX1 register.
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* @details Read SPI_RX1 register to get the received datum.
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*/
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#define SPI_READ_RX1(spi) ((spi)->RX[1])
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/**
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* @brief Write datum to TX0 register.
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* @param[in] spi The pointer of the specified SPI module.
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* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
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* @return None.
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* @details Write u32TxData to TX0 register.
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*/
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#define SPI_WRITE_TX0(spi, u32TxData) ((spi)->TX[0] = (u32TxData))
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/**
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* @brief Write datum to TX1 register.
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* @param[in] spi The pointer of the specified SPI module.
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* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
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* @return None.
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* @details Write u32TxData to TX1 register.
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*/
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#define SPI_WRITE_TX1(spi, u32TxData) ((spi)->TX[1] = (u32TxData))
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/**
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* @brief Set SPIn_SS0, SPIn_SS1 pin to high or low state.
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* @param[in] spi The pointer of the specified SPI module.
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* @param[in] ss0 0 = Set SPIn_SS0 to low. 1 = Set SPIn_SS0 to high.
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* @param[in] ss1 0 = Set SPIn_SS1 to low. 1 = Set SPIn_SS1 to high.
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* @return None.
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* @details Disable automatic slave selection function and set SPIn_SS0/SPIn_SS1 pin to specified high/low state.
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* Only available in Master mode.
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*/
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#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1))
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/**
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* @brief Set SPIn_SS0 pin to high state.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode.
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*/
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#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)))
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/**
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* @brief Set SPIn_SS1 pin to high state.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode.
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*/
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#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)))
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/**
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* @brief Set SPIn_SS0 pin to low state.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode.
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*/
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#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0)
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/**
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* @brief Set SPIn_SS1 pin to low state.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode.
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*/
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#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1)
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/**
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* @brief Enable Byte Reorder function.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set REORDER bit of SPI_CNTRL register to enable Byte Reorder function.
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*/
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#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CNTRL |= SPI_CNTRL_REORDER_Msk)
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/**
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* @brief Disable Byte Reorder function.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear REORDER bit of SPI_CNTRL register to disable Byte Reorder function.
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*/
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#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk)
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/**
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* @brief Set the length of suspend interval.
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* @param[in] spi The pointer of the specified SPI module.
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* @param[in] u32SuspCycle Decides the length of suspend interval.
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* @return None.
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* @details Set the length of suspend interval according to u32SuspCycle.
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* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
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* Only available in Master mode.
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*/
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#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | ((u32SuspCycle) << SPI_CNTRL_SP_CYCLE_Pos))
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/**
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* @brief Set the SPI transfer sequence with LSB first.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Set LSB bit of SPI_CNTRL register to set the SPI transfer sequence with LSB first.
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*/
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#define SPI_SET_LSB_FIRST(spi) ((spi)->CNTRL |= SPI_CNTRL_LSB_Msk)
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/**
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* @brief Set the SPI transfer sequence with MSB first.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details Clear LSB bit of SPI_CNTRL register to set the SPI transfer sequence with MSB first.
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*/
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#define SPI_SET_MSB_FIRST(spi) ((spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk)
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/**
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* @brief Set the data width of a SPI transaction.
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* @param[in] spi The pointer of the specified SPI module.
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* @param[in] u32Width The bit width of transfer data.
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* @return None.
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* @details The data width can be 8 ~ 32 bits.
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*/
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#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_TX_BIT_LEN_Msk) | (((u32Width)&0x1F) << SPI_CNTRL_TX_BIT_LEN_Pos))
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/**
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* @brief Get the SPI busy state.
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* @param[in] spi The pointer of the specified SPI module.
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* @retval 0 SPI controller is not busy.
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* @retval 1 SPI controller is busy.
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* @details This macro will return the busy state of SPI controller.
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*/
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#define SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk)>>SPI_CNTRL_GO_BUSY_Pos )
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/**
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* @brief Set the GO_BUSY bit to trigger SPI transfer.
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* @param[in] spi The pointer of the specified SPI module.
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* @return None.
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* @details If FIFO mode is disabled, user can use this macro to trigger the data transfer after all configuration is ready.
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* If FIFO mode is enabled, user should not use this macro to trigger the data transfer. SPI controller will trigger the data transfer
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* automatically after user write to SPI_TX0/1 register.
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*/
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#define SPI_TRIGGER(spi) ((spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk)
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/* Function prototype declaration */
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uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
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void SPI_Close(SPI_T *spi);
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void SPI_ClearRxFIFO(SPI_T *spi);
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void SPI_ClearTxFIFO(SPI_T *spi);
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void SPI_DisableAutoSS(SPI_T *spi);
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void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
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uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
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void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
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void SPI_DisableFIFO(SPI_T *spi);
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uint32_t SPI_GetBusClock(SPI_T *spi);
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void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
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void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
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uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
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void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
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uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
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/**
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* @} End of SPI Device Function Interface
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*/
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/**
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* @} End of Function Interface
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*/
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/**
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* @} End of Device_Driver
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*/
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#endif
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