NXP NFC Reader Library
v4.040.05.011646
|
Register definitions. More...
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Macros | |
#define | PHHAL_HW_RC663_REG_COMMAND 0x00 |
Command Register. More... | |
#define | PHHAL_HW_RC663_REG_HOSTCTRL 0x01 |
Host-Control Register. More... | |
#define | PHHAL_HW_RC663_REG_ERROR 0x0A |
Error Register. More... | |
#define | PHHAL_HW_RC663_REG_STATUS 0x0B |
Status Register. More... | |
#define | PHHAL_HW_RC663_REG_RXBITCTRL 0x0C |
Rx-Bit-Control Register. More... | |
#define | PHHAL_HW_RC663_REG_RXCOLL 0x0D |
Rx-Coll Register. More... | |
#define | PHHAL_HW_RC663_REG_DRVMODE 0x28 |
Driver Mode Register. More... | |
#define | PHHAL_HW_RC663_REG_TXAMP 0x29 |
Tx Amplifier Register. More... | |
#define | PHHAL_HW_RC663_REG_DRVCON 0x2A |
Driver Control Register. More... | |
#define | PHHAL_HW_RC663_REG_TXI 0x2B |
TxI Register. More... | |
#define | PHHAL_HW_RC663_REG_TXCRCCON 0x2C |
Tx-CRC Control Register. More... | |
#define | PHHAL_HW_RC663_REG_RXCRCCON 0x2D |
Rx-CRC Control Register. More... | |
#define | PHHAL_HW_RC663_REG_TXDATANUM 0x2E |
Tx-DataNum Register. More... | |
#define | PHHAL_HW_RC663_REG_TXMODWIDTH 0x2F |
Tx-Modwidth Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM10BURSTLEN 0x30 |
Symbol 0 and 1 Register. More... | |
#define | PHHAL_HW_RC663_REG_TXWAITCTRL 0x31 |
Tx-Wait Control Register. More... | |
#define | PHHAL_HW_RC663_REG_TXWAITLO 0x32 |
TxWaitLo Register. More... | |
#define | PHHAL_HW_RC663_REG_FRAMECON 0x33 |
Frame control register. More... | |
#define | PHHAL_HW_RC663_REG_RXSOFD 0x34 |
RxSOFD Register. More... | |
#define | PHHAL_HW_RC663_REG_RXCTRL 0x35 |
Rx Control Register. More... | |
#define | PHHAL_HW_RC663_REG_RXWAIT 0x36 |
Rx-Wait Register. More... | |
#define | PHHAL_HW_RC663_REG_RXTHRESHOLD 0x37 |
Rx-Threshold Register. More... | |
#define | PHHAL_HW_RC663_REG_RCV 0x38 |
Receiver Register. More... | |
#define | PHHAL_HW_RC663_REG_RXANA 0x39 |
Rx-Analog Register. More... | |
#define | PHHAL_HW_RC663_REG_SERIALSPEED 0x3B |
Serial Speed Register. More... | |
#define | PHHAL_HW_RC663_REG_LPO_TRIMM 0x3C |
LPO_TRIMM Register. More... | |
#define | PHHAL_HW_RC663_REG_PLL_CTRL 0x3D |
PLL Control Register. More... | |
#define | PHHAL_HW_RC663_REG_PLL_DIV 0x3E |
PLL DivO Register. More... | |
#define | PHHAL_HW_RC663_REG_LPCD_QMIN 0x3F |
LPCD QMin Register. More... | |
#define | PHHAL_HW_RC663_REG_LPCD_QMAX 0x40 |
LPCD QMax Register. More... | |
#define | PHHAL_HW_RC663_REG_LPCD_IMIN 0x41 |
LPCD IMin Register. More... | |
#define | PHHAL_HW_RC663_REG_LPCD_RESULT_I 0x42 |
LPCD Result(I) Register. More... | |
#define | PHHAL_HW_RC663_REG_LPCD_RESULT_Q 0x43 |
LPCD Result(Q) Register. More... | |
#define | PHHAL_HW_RC663_TXBITMOD 0x48 |
Transmitter bit modulus Register. More... | |
#define | PHHAL_HW_RC663_REG_TXDATACON 0x4A |
Transmitter data configuration register. More... | |
#define | PHHAL_HW_RC663_REG_TXDATAMOD 0x4B |
Transmitter data modulation Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYMFREQ 0x4C |
Transmitter Symbol Frequency. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM0H 0x4D |
Transmitter Symbol 0 High Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM0L 0x4E |
Transmitter Symbol 0 Low Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM1H 0x4F |
Transmitter Symbol 1 High Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM1L 0x50 |
Transmitter Symbol 1 Low Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM2 0x51 |
Tx Symbol 2 Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM3 0x52 |
Tx Symbol 3 Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM10LEN 0x53 |
Transmitter Symbol 0 + Symbol 1 Length Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM32LEN 0x54 |
Transmitter symbol 3 + symbol 2 length register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM10BURSTCTRL 0x55 |
Symbol 0 and 1 Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM10MOD 0x56 |
Symbol 0 and 1 Register. More... | |
#define | PHHAL_HW_RC663_REG_TXSYM32MOD 0x57 |
Transmitter symbol 3 + symbol 2 modulation register. More... | |
#define | PHHAL_HW_RC663_REG_RXBITMOD 0x58 |
Receiver bit modulation register. More... | |
#define | PHHAL_HW_RC663_REG_RXEOFSYM 0x59 |
Receiver end of frame symbol register. More... | |
#define | PHHAL_HW_RC663_REG_RXSYNCVAlH 0x5A |
Receiver synchronisation value high register. More... | |
#define | PHHAL_HW_RC663_REG_RXSYNCVAlL 0x5B |
Receiver synchronisation value low register. More... | |
#define | PHHAL_HW_RC663_REG_RXSYNCMOD 0x5C |
Receiver synchronisation mode register. More... | |
#define | PHHAL_HW_RC663_REG_RXMOD 0x5D |
Receiver modulation register. More... | |
#define | PHHAL_HW_RC663_REG_RXCORR 0x5E |
Receiver Correlation Register. More... | |
#define | PHHAL_HW_RC663_REG_RXSVETTE 0x5F |
Calibration register of the receiver. More... | |
#define | PHHAL_HW_RC663_REG_DACVAL 0x64 |
DAC value Register. More... | |
#define | PHHAL_HW_RC663_REG_TESTMOD 0x66 |
Test mode Register. More... | |
#define | PHHAL_HW_RC663_REG_ANAXTAL 0x71 |
Analog Xtal register. More... | |
#define | PHHAL_HW_RC663_REG_SIGPROTEST 0x72 |
EPCv2 mode Register. More... | |
#define | PHHAL_HW_RC663_REG_VERSION 0x7F |
Version Register. More... | |
Functions | |
phStatus_t | phhalHw_Rc663_WriteRegister (phhalHw_Rc663_DataParams_t *pDataParams, uint8_t bAddress, uint8_t bValue) |
Write to 8bit address of CL front-end register. More... | |
phStatus_t | phhalHw_Rc663_ReadRegister (phhalHw_Rc663_DataParams_t *pDataParams, uint8_t bAddress, uint8_t *pValue) |
Read 8bit register address from CL front-ends. More... | |
Fifo Registers | |
#define | PHHAL_HW_RC663_REG_FIFOCONTROL 0x02 |
FIFO-Control Register. More... | |
#define | PHHAL_HW_RC663_REG_WATERLEVEL 0x03 |
WaterLevel Register. More... | |
#define | PHHAL_HW_RC663_REG_FIFOLENGTH 0x04 |
FIFO-Length Register. More... | |
#define | PHHAL_HW_RC663_REG_FIFODATA 0x05 |
FIFO-Data Register. More... | |
IRQ Registers | |
#define | PHHAL_HW_RC663_REG_IRQ0 0x06 |
IRQ0 Register. More... | |
#define | PHHAL_HW_RC663_REG_IRQ1 0x07 |
IRQ1 Register. More... | |
#define | PHHAL_HW_RC663_REG_IRQ0EN 0x08 |
IRQ0EN Register. More... | |
#define | PHHAL_HW_RC663_REG_IRQ1EN 0x09 |
IRQ1EN Register. More... | |
Timer Registers | |
#define | PHHAL_HW_RC663_REG_TCONTROL 0x0E |
Timer Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T0CONTROL 0x0F |
Timer0 Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T0RELOADHI 0x10 |
Timer0 Reload(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T0RELOADLO 0x11 |
Timer0 Reload(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T0COUNTERVALHI 0x12 |
Timer0 Counter(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T0COUNTERVALLO 0x13 |
Timer0 Counter(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T1CONTROL 0x14 |
Timer1 Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T1RELOADHI 0x15 |
Timer1 Reload(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T1RELOADLO 0x16 |
Timer1 Reload(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T1COUNTERVALHI 0x17 |
Timer1 Counter(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T1COUNTERVALLO 0x18 |
Timer1 Counter(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T2CONTROL 0x19 |
Timer2 Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T2RELOADHI 0x1A |
Timer2 Reload(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T2RELOADLO 0x1B |
Timer2 Reload(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T2COUNTERVALHI 0x1C |
Timer2 Counter(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T2COUNTERVALLO 0x1D |
Timer2 Counter(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T3CONTROL 0x1E |
Timer3 Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T3RELOADHI 0x1F |
Timer3 Reload(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T3RELOADLO 0x20 |
Timer3 Reload(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T3COUNTERVALHI 0x21 |
Timer3 Counter(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T3COUNTERVALLO 0x22 |
Timer3 Counter(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T4CONTROL 0x23 |
Timer4 Control Register. More... | |
#define | PHHAL_HW_RC663_REG_T4RELOADHI 0x24 |
Timer4 Reload(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T4RELOADLO 0x25 |
Timer4 Reload(Low) Register. More... | |
#define | PHHAL_HW_RC663_REG_T4COUNTERVALHI 0x26 |
Timer4 Counter(High) Register. More... | |
#define | PHHAL_HW_RC663_REG_T4COUNTERVALLO 0x27 |
Timer4 Counter(Low) Register. More... | |
Command Register Contents (0x00) | |
#define | PHHAL_HW_RC663_BIT_STANDBY 0x80U |
Standby bit; If set, the IC transits to standby mode. More... | |
#define | PHHAL_HW_RC663_CMD_IDLE 0x00U |
No action; cancels current command execution. More... | |
#define | PHHAL_HW_RC663_CMD_LPCD 0x01U |
Low Power Card Detection. More... | |
#define | PHHAL_HW_RC663_CMD_LOADKEY 0x02U |
Reads a key from the FIFO buffer and puts it into the key buffer. More... | |
#define | PHHAL_HW_RC663_CMD_MFAUTHENT 0x03U |
Performs the Mifare standard authentication (in Mifare Reader/Writer mode only). More... | |
#define | PHHAL_HW_RC663_CMD_ACKREQ 0x04U |
Performs a Query, a Ack and a Req-Rn for EPC V2. More... | |
#define | PHHAL_HW_RC663_CMD_RECEIVE 0x05U |
Activates the receiver circuitry. More... | |
#define | PHHAL_HW_RC663_CMD_TRANSMIT 0x06U |
Transmits data from the FIFO buffer to Card. More... | |
#define | PHHAL_HW_RC663_CMD_TRANSCEIVE 0x07U |
Like PHHAL_HW_RC663_CMD_TRANSMIT but automatically activates the receiver after transmission is finished. More... | |
#define | PHHAL_HW_RC663_CMD_WRITEE2 0x08U |
Gets one byte from FIFO buffer and writes it to the internal EEPROM. More... | |
#define | PHHAL_HW_RC663_CMD_WRITEE2PAGE 0x09U |
Gets up to 64 Bytes from FIFO buffer and writes it to the EEPROM. More... | |
#define | PHHAL_HW_RC663_CMD_READE2 0x0AU |
Reads data from EEPROM and puts it into the FIFO buffer. More... | |
#define | PHHAL_HW_RC663_CMD_LOADREG 0x0CU |
Reads data from EEPROM and initializes the registers. More... | |
#define | PHHAL_HW_RC663_CMD_LOADPROTOCOL 0x0DU |
Reads data from EEPROM and initializes the registers needed for a protocol change. More... | |
#define | PHHAL_HW_RC663_CMD_LOADKEYE2 0x0EU |
Copies a Mifare key from the EEPROM into the key buffer. More... | |
#define | PHHAL_HW_RC663_CMD_STOREKEYE2 0x0FU |
Stores a Mifare key into the EEPROM. More... | |
#define | PHHAL_HW_RC663_CMD_SOFTRESET 0x1FU |
Resets the IC. More... | |
#define | PHHAL_HW_RC663_MASK_COMMAND 0x1FU |
Mask for Command-bits. More... | |
Status Register Contents (0x0B) | |
#define | PHHAL_HW_RC663_BIT_CRYPTO1ON 0x20U |
#define | PHHAL_HW_RC663_MASK_COMMSTATE 0x07U |
Rx-Coll Register Contents (0x0D) | |
#define | PHHAL_HW_RC663_BIT_COLLPOSVALID 0x80U |
#define | PHHAL_HW_RC663_MASK_COLLPOS 0x7FU |
T[0-3]-Control Register Contents (0x0F/0x14/0x19/0x1E) | |
#define | PHHAL_HW_RC663_BIT_TSTOP_RX 0x80U |
Stop timer on receive interrupt. More... | |
#define | PHHAL_HW_RC663_BIT_TAUTORESTARTED 0x08U |
Auto-restart timer after underflow. More... | |
#define | PHHAL_HW_RC663_BIT_TSTART_TX 0x10U |
Start timer on transmit interrupt. More... | |
#define | PHHAL_HW_RC663_BIT_TSTART_LFO 0x20U |
Use this timer for LFO trimming. More... | |
#define | PHHAL_HW_RC663_BIT_TSTART_LFO_UV 0x30U |
Use this timer for LFO trimming (generate UV at a trimming event). More... | |
#define | PHHAL_HW_RC663_MASK_TSTART 0x30U |
Mask for TSTART bits. More... | |
#define | PHHAL_HW_RC663_VALUE_TCLK_1356_MHZ 0x00U |
Use 13.56MHz as input clock. More... | |
#define | PHHAL_HW_RC663_VALUE_TCLK_212_KHZ 0x01U |
Use 212KHz as input clock. More... | |
#define | PHHAL_HW_RC663_VALUE_TCLK_T0 0x02U |
Use timer0 as input clock. More... | |
#define | PHHAL_HW_RC663_VALUE_TCLK_T1 0x03U |
Use timer1 as input clock. More... | |
Tx Amplifier Register Contents (0x29) | |
#define | PHHAL_HW_RC663_MASK_CW_AMPLITUDE 0xC0U |
#define | PHHAL_HW_RC663_MASK_RESIDUAL_CARRIER 0x1FU |
Rx-Wait Register Contents (0x36) | |
#define | PHHAL_HW_RC663_BIT_RXWAITDBFREQ 0x80U |
#define | PHHAL_HW_RC663_MASK_RXWAIT 0x7FU |
Rx-Threshold Register Contents (0x37) | |
#define | PHHAL_HW_RC663_MASK_MINLEVEL 0xF0U |
#define | PHHAL_HW_RC663_MASK_MINLEVELP 0x0FU |
Serial-Speed Register Contents (0x3B) | |
#define | PHHAL_HW_RC663_MASK_BR_T0 0xE0U |
#define | PHHAL_HW_RC663_MASK_BR_T1 0x1FU |
LPCD Result(Q) Register Contents (0x43) | |
#define | PHHAL_HW_RC663_BIT_LPCDIRQ_CLR 0x40U |
Register definitions.
#define PHHAL_HW_RC663_REG_COMMAND 0x00 |
Command Register.
Used for starting / stopping commands and for sending the IC into standby mode.
#define PHHAL_HW_RC663_REG_HOSTCTRL 0x01 |
Host-Control Register.
Configure Host and SAM interfaces.
#define PHHAL_HW_RC663_REG_FIFOCONTROL 0x02 |
FIFO-Control Register.
Set FIFO size and retrieve FIFO parameters.
Note: Also contains 1 additional Water-Level bit (MSB) and 2 additional FIFO-Length bits (also MSB).
#define PHHAL_HW_RC663_REG_WATERLEVEL 0x03 |
WaterLevel Register.
FIFO WaterLevel configuration.
#define PHHAL_HW_RC663_REG_FIFOLENGTH 0x04 |
FIFO-Length Register.
Retrieve the number of bytes within the FIFO.
#define PHHAL_HW_RC663_REG_FIFODATA 0x05 |
FIFO-Data Register.
Writing to this register moves a byte into the FIFO while incrementing the FIFO length and raising the internal WaterLevel.
#define PHHAL_HW_RC663_REG_IRQ0 0x06 |
IRQ0 Register.
Read or modify the first 7 IRQ bits.
#define PHHAL_HW_RC663_REG_IRQ1 0x07 |
IRQ1 Register.
Read or modify the second 7 IRQ bits.
#define PHHAL_HW_RC663_REG_IRQ0EN 0x08 |
IRQ0EN Register.
Enable or disable the first IRQ bits or invert the IRQ propagation.
#define PHHAL_HW_RC663_REG_IRQ1EN 0x09 |
IRQ1EN Register.
Enable or disable the second IRQ bits or enable/disable PushPull mode.
#define PHHAL_HW_RC663_REG_ERROR 0x0A |
Error Register.
Contains bits for the occured erros.
#define PHHAL_HW_RC663_REG_STATUS 0x0B |
Status Register.
Contains the Crypto1 state and information about the ComState.
#define PHHAL_HW_RC663_REG_RXBITCTRL 0x0C |
Rx-Bit-Control Register.
Set/Get Bit-granularity and collision information.
#define PHHAL_HW_RC663_REG_RXCOLL 0x0D |
Rx-Coll Register.
Contains information about the collision position after a collision.
#define PHHAL_HW_RC663_REG_TCONTROL 0x0E |
Timer Control Register.
Provides timer control and status information for all timers.
#define PHHAL_HW_RC663_REG_T0CONTROL 0x0F |
Timer0 Control Register.
Configure the timer.
#define PHHAL_HW_RC663_REG_T0RELOADHI 0x10 |
Timer0 Reload(High) Register.
Set the most significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T0RELOADLO 0x11 |
Timer0 Reload(Low) Register.
Set the least significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T0COUNTERVALHI 0x12 |
Timer0 Counter(High) Register.
Get the most significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T0COUNTERVALLO 0x13 |
Timer0 Counter(Low) Register.
Get the least significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T1CONTROL 0x14 |
Timer1 Control Register.
Configure the timer.
#define PHHAL_HW_RC663_REG_T1RELOADHI 0x15 |
Timer1 Reload(High) Register.
Set the most significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T1RELOADLO 0x16 |
Timer1 Reload(Low) Register.
Set the least significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T1COUNTERVALHI 0x17 |
Timer1 Counter(High) Register.
Get the most significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T1COUNTERVALLO 0x18 |
Timer1 Counter(Low) Register.
Get the least significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T2CONTROL 0x19 |
Timer2 Control Register.
Configure the timer.
#define PHHAL_HW_RC663_REG_T2RELOADHI 0x1A |
Timer2 Reload(High) Register.
Set the most significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T2RELOADLO 0x1B |
Timer2 Reload(Low) Register.
Set the least significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T2COUNTERVALHI 0x1C |
Timer2 Counter(High) Register.
Get the most significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T2COUNTERVALLO 0x1D |
Timer2 Counter(Low) Register.
Get the least significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T3CONTROL 0x1E |
Timer3 Control Register.
Configure the timer.
#define PHHAL_HW_RC663_REG_T3RELOADHI 0x1F |
Timer3 Reload(High) Register.
Set the most significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T3RELOADLO 0x20 |
Timer3 Reload(Low) Register.
Set the least significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T3COUNTERVALHI 0x21 |
Timer3 Counter(High) Register.
Get the most significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T3COUNTERVALLO 0x22 |
Timer3 Counter(Low) Register.
Get the least significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T4CONTROL 0x23 |
Timer4 Control Register.
Configure the timer.
#define PHHAL_HW_RC663_REG_T4RELOADHI 0x24 |
Timer4 Reload(High) Register.
Set the most significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T4RELOADLO 0x25 |
Timer4 Reload(Low) Register.
Set the least significant byte of the Reload-Value.
#define PHHAL_HW_RC663_REG_T4COUNTERVALHI 0x26 |
Timer4 Counter(High) Register.
Get the most significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_T4COUNTERVALLO 0x27 |
Timer4 Counter(Low) Register.
Get the least significant byte of the Counter-Value.
#define PHHAL_HW_RC663_REG_DRVMODE 0x28 |
Driver Mode Register.
Enable / Invert the Tx-Driver and set the Clock Mode.
#define PHHAL_HW_RC663_REG_TXAMP 0x29 |
Tx Amplifier Register.
Modify Amplitude and Carrier settings.
#define PHHAL_HW_RC663_REG_DRVCON 0x2A |
Driver Control Register.
Select / Invert drivers.
#define PHHAL_HW_RC663_REG_TXI 0x2B |
TxI Register.
Contains Overshoot prevention and current control settings.
#define PHHAL_HW_RC663_REG_TXCRCCON 0x2C |
Tx-CRC Control Register.
Configure CRC parameters transmission.
#define PHHAL_HW_RC663_REG_RXCRCCON 0x2D |
Rx-CRC Control Register.
Configure CRC parameters for reception.
#define PHHAL_HW_RC663_REG_TXDATANUM 0x2E |
Tx-DataNum Register.
Set TxLastBits and configure KeepBitGrid functionality.
#define PHHAL_HW_RC663_REG_TXMODWIDTH 0x2F |
Tx-Modwidth Register.
Set the modulation width.
#define PHHAL_HW_RC663_REG_TXSYM10BURSTLEN 0x30 |
Symbol 0 and 1 Register.
Configure Burst-lengths of both symbols.
#define PHHAL_HW_RC663_REG_TXWAITCTRL 0x31 |
Tx-Wait Control Register.
Enable / Configure Tx Waiting-Time.
#define PHHAL_HW_RC663_REG_TXWAITLO 0x32 |
TxWaitLo Register.
Contains the Least-Significant-Bits for the Tx Waiting-Time.
#define PHHAL_HW_RC663_REG_FRAMECON 0x33 |
Frame control register.
Contains active Start/Stop symbol and Parity settings.
#define PHHAL_HW_RC663_REG_RXSOFD 0x34 |
RxSOFD Register.
Contains Start-of-Frame and subcarrier detection bits.
#define PHHAL_HW_RC663_REG_RXCTRL 0x35 |
Rx Control Register.
Configure Receiver settings such as baudrate and EMD-suppression feature.
#define PHHAL_HW_RC663_REG_RXWAIT 0x36 |
Rx-Wait Register.
Configure Receiver Deaf-Time.
#define PHHAL_HW_RC663_REG_RXTHRESHOLD 0x37 |
Rx-Threshold Register.
Configure Receiver Threshold.
#define PHHAL_HW_RC663_REG_RCV 0x38 |
Receiver Register.
Configure Collision-Level and other features.
#define PHHAL_HW_RC663_REG_RXANA 0x39 |
Rx-Analog Register.
Configure analog settings and parameters for Receiver circuitry.
#define PHHAL_HW_RC663_REG_SERIALSPEED 0x3B |
Serial Speed Register.
Configure serial baudrates.
#define PHHAL_HW_RC663_REG_LPO_TRIMM 0x3C |
LPO_TRIMM Register.
Trimm Control Input for Low Power Oscillator.
#define PHHAL_HW_RC663_REG_PLL_CTRL 0x3D |
PLL Control Register.
Configure PLL settings.
#define PHHAL_HW_RC663_REG_PLL_DIV 0x3E |
PLL DivO Register.
Contains PLL output.
#define PHHAL_HW_RC663_REG_LPCD_QMIN 0x3F |
LPCD QMin Register.
Configure IMax(2) and QMin values for LPCD.
#define PHHAL_HW_RC663_REG_LPCD_QMAX 0x40 |
LPCD QMax Register.
Configure IMax(1) and QMax values for LPCD.
#define PHHAL_HW_RC663_REG_LPCD_IMIN 0x41 |
LPCD IMin Register.
Configure IMax(0) and IMin values for LPCD.
#define PHHAL_HW_RC663_REG_LPCD_RESULT_I 0x42 |
LPCD Result(I) Register.
Contains I-Channel results of LPCD.
#define PHHAL_HW_RC663_REG_LPCD_RESULT_Q 0x43 |
LPCD Result(Q) Register.
Contains Q-Channel results of LPCD.
#define PHHAL_HW_RC663_TXBITMOD 0x48 |
Transmitter bit modulus Register.
Define Tx data interpretation.
#define PHHAL_HW_RC663_REG_TXDATACON 0x4A |
Transmitter data configuration register.
Contains Type of data encoding, subcarrier frequency of envelope and frequency of bitstream.
#define PHHAL_HW_RC663_REG_TXDATAMOD 0x4B |
Transmitter data modulation Register.
Configure Frame step, miller coding, Pulse type, Inversion of envelop of data and Envelop type
#define PHHAL_HW_RC663_REG_TXSYMFREQ 0x4C |
Transmitter Symbol Frequency.
Configure Frequency for Transmitter symbol
#define PHHAL_HW_RC663_REG_TXSYM0H 0x4D |
Transmitter Symbol 0 High Register.
Contains value for Transmitter Symbol 0.
#define PHHAL_HW_RC663_REG_TXSYM0L 0x4E |
Transmitter Symbol 0 Low Register.
Contains value for Transmitter Symbol 0.
#define PHHAL_HW_RC663_REG_TXSYM1H 0x4F |
Transmitter Symbol 1 High Register.
Contains value for Transmitter Symbol 1.
#define PHHAL_HW_RC663_REG_TXSYM1L 0x50 |
Transmitter Symbol 1 Low Register.
Contains value for Transmitter Symbol 1.
#define PHHAL_HW_RC663_REG_TXSYM2 0x51 |
Tx Symbol 2 Register.
Contains Symbol definition for Symbol 2.
#define PHHAL_HW_RC663_REG_TXSYM3 0x52 |
Tx Symbol 3 Register.
Contains Symbol definition for Symbol 3.
#define PHHAL_HW_RC663_REG_TXSYM10LEN 0x53 |
Transmitter Symbol 0 + Symbol 1 Length Register.
Contains Length of Transmitter Symbol 0 + Symbol 1.
#define PHHAL_HW_RC663_REG_TXSYM32LEN 0x54 |
Transmitter symbol 3 + symbol 2 length register.
Contains No. of Valid bits in Tx Symbol 2 and Tx Symbol 3 registers.
#define PHHAL_HW_RC663_REG_TXSYM10BURSTCTRL 0x55 |
Symbol 0 and 1 Register.
Configure Burst-control of both symbols.
#define PHHAL_HW_RC663_REG_TXSYM10MOD 0x56 |
Symbol 0 and 1 Register.
Configure Modulation Register of both symbols.
#define PHHAL_HW_RC663_REG_TXSYM32MOD 0x57 |
Transmitter symbol 3 + symbol 2 modulation register.
Configures Miller encoding, Pulse type and Envelope type.
#define PHHAL_HW_RC663_REG_RXBITMOD 0x58 |
Receiver bit modulation register.
Contains Receiver data configurations.
#define PHHAL_HW_RC663_REG_RXEOFSYM 0x59 |
Receiver end of frame symbol register.
This Register defines the pattern of the EOF symbol.
#define PHHAL_HW_RC663_REG_RXSYNCVAlH 0x5A |
Receiver synchronisation value high register.
Defines the high byte of the Start Of Frame (SOF) pattern, which must be in front of the receiving data.
#define PHHAL_HW_RC663_REG_RXSYNCVAlL 0x5B |
Receiver synchronisation value low register.
Defines the low byte of the Start Of Frame (SOF) Pattern, which must be in front of the receiving data.
#define PHHAL_HW_RC663_REG_RXSYNCMOD 0x5C |
Receiver synchronisation mode register.
Contains Rx sync values.
#define PHHAL_HW_RC663_REG_RXMOD 0x5D |
Receiver modulation register.
Contains Reciever configuration registers.
#define PHHAL_HW_RC663_REG_RXCORR 0x5E |
Receiver Correlation Register.
Contains Correlation Frequency, Correlation Speed and Correlation Length.
#define PHHAL_HW_RC663_REG_RXSVETTE 0x5F |
Calibration register of the receiver.
Contains Fabrication calibration of the receiver.
#define PHHAL_HW_RC663_REG_DACVAL 0x64 |
DAC value Register.
Contains DAC Value.
#define PHHAL_HW_RC663_REG_TESTMOD 0x66 |
Test mode Register.
Contains Test Level enable and Test mode configuration.
#define PHHAL_HW_RC663_REG_ANAXTAL 0x71 |
Analog Xtal register.
Contains Xtal mode and Xtal bypassreg.
#define PHHAL_HW_RC663_REG_SIGPROTEST 0x72 |
EPCv2 mode Register.
Enables or Disables Testmode Rx and EPCv2 mode.
#define PHHAL_HW_RC663_REG_VERSION 0x7F |
Version Register.
Contains IC Version and Subversion.
#define PHHAL_HW_RC663_BIT_STANDBY 0x80U |
Standby bit; If set, the IC transits to standby mode.
#define PHHAL_HW_RC663_CMD_IDLE 0x00U |
No action; cancels current command execution.
#define PHHAL_HW_RC663_CMD_LPCD 0x01U |
Low Power Card Detection.
#define PHHAL_HW_RC663_CMD_LOADKEY 0x02U |
Reads a key from the FIFO buffer and puts it into the key buffer.
#define PHHAL_HW_RC663_CMD_MFAUTHENT 0x03U |
Performs the Mifare standard authentication (in Mifare Reader/Writer mode only).
#define PHHAL_HW_RC663_CMD_ACKREQ 0x04U |
Performs a Query, a Ack and a Req-Rn for EPC V2.
#define PHHAL_HW_RC663_CMD_RECEIVE 0x05U |
Activates the receiver circuitry.
#define PHHAL_HW_RC663_CMD_TRANSMIT 0x06U |
Transmits data from the FIFO buffer to Card.
#define PHHAL_HW_RC663_CMD_TRANSCEIVE 0x07U |
Like PHHAL_HW_RC663_CMD_TRANSMIT but automatically activates the receiver after transmission is finished.
#define PHHAL_HW_RC663_CMD_WRITEE2 0x08U |
Gets one byte from FIFO buffer and writes it to the internal EEPROM.
#define PHHAL_HW_RC663_CMD_WRITEE2PAGE 0x09U |
Gets up to 64 Bytes from FIFO buffer and writes it to the EEPROM.
#define PHHAL_HW_RC663_CMD_READE2 0x0AU |
Reads data from EEPROM and puts it into the FIFO buffer.
#define PHHAL_HW_RC663_CMD_LOADREG 0x0CU |
Reads data from EEPROM and initializes the registers.
#define PHHAL_HW_RC663_CMD_LOADPROTOCOL 0x0DU |
Reads data from EEPROM and initializes the registers needed for a protocol change.
#define PHHAL_HW_RC663_CMD_LOADKEYE2 0x0EU |
Copies a Mifare key from the EEPROM into the key buffer.
#define PHHAL_HW_RC663_CMD_STOREKEYE2 0x0FU |
Stores a Mifare key into the EEPROM.
#define PHHAL_HW_RC663_CMD_SOFTRESET 0x1FU |
Resets the IC.
#define PHHAL_HW_RC663_MASK_COMMAND 0x1FU |
Mask for Command-bits.
#define PHHAL_HW_RC663_BIT_TSTOP_RX 0x80U |
Stop timer on receive interrupt.
#define PHHAL_HW_RC663_BIT_TAUTORESTARTED 0x08U |
Auto-restart timer after underflow.
#define PHHAL_HW_RC663_BIT_TSTART_TX 0x10U |
Start timer on transmit interrupt.
#define PHHAL_HW_RC663_BIT_TSTART_LFO 0x20U |
Use this timer for LFO trimming.
#define PHHAL_HW_RC663_BIT_TSTART_LFO_UV 0x30U |
Use this timer for LFO trimming (generate UV at a trimming event).
#define PHHAL_HW_RC663_MASK_TSTART 0x30U |
Mask for TSTART bits.
#define PHHAL_HW_RC663_VALUE_TCLK_1356_MHZ 0x00U |
Use 13.56MHz as input clock.
#define PHHAL_HW_RC663_VALUE_TCLK_212_KHZ 0x01U |
Use 212KHz as input clock.
#define PHHAL_HW_RC663_VALUE_TCLK_T0 0x02U |
Use timer0 as input clock.
#define PHHAL_HW_RC663_VALUE_TCLK_T1 0x03U |
Use timer1 as input clock.
phStatus_t phhalHw_Rc663_WriteRegister | ( | phhalHw_Rc663_DataParams_t * | pDataParams, |
uint8_t | bAddress, | ||
uint8_t | bValue | ||
) |
Write to 8bit address of CL front-end register.
PH_ERR_SUCCESS | Operation successful. |
PH_ERR_INTERFACE_ERROR | Hardware problem |
[in] | pDataParams | Pointer to this layer's parameter structure. |
[in] | bAddress | Register Address. |
[in] | bValue | Register Value. |
phStatus_t phhalHw_Rc663_ReadRegister | ( | phhalHw_Rc663_DataParams_t * | pDataParams, |
uint8_t | bAddress, | ||
uint8_t * | pValue | ||
) |
Read 8bit register address from CL front-ends.
PH_ERR_SUCCESS | Operation successful. |
PH_ERR_INTERFACE_ERROR | Hardware problem |
[in] | pDataParams | Pointer to this layer's parameter structure. |
[in] | bAddress | Register Address. |
[out] | pValue | Register Value. |