639 lines
24 KiB
C
639 lines
24 KiB
C
/*
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* Copyright (c), NXP Semiconductors Gratkorn / Austria
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*
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* (C)NXP Semiconductors
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* All rights are reserved. Reproduction in whole or in part is
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* prohibited without the written consent of the copyright owner.
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* NXP reserves the right to make changes without notice at any time.
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* NXP makes no warranty, expressed, implied or statutory, including but
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* not limited to any implied warranty of merchantability or fitness for any
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*particular purpose, or that the use will not infringe any third party patent,
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* copyright or trademark. NXP must not be liable for any loss or damage
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* arising from its use.
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*/
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/** \file
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* Rc523 register definitions for Reader Library Framework.
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* $Author: Purnank G (ing05193) $
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* $Revision: 5076 $ (v4.040.05.011646)
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* $Date: 2016-06-13 17:29:09 +0530 (Mon, 13 Jun 2016) $
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*
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* History:
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* CHu: Generated 19. May 2009
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*
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*/
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#ifndef PHHALHW_RC523_REG_H
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#define PHHALHW_RC523_REG_H
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#include <ph_Status.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef NXPBUILD__PHHAL_HW_RC523
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/** \defgroup phhalHw_Rc523_Reg Register Definitions
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* \brief Register definitions.
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* @{
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*/
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/** \name Register definitions of Page 0
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* Following all register definitions of Page 0.
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*/
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/*@{*/
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/** \brief Page register.
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*/
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#define PHHAL_HW_RC523_REG_PAGE 0x00U
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/** \brief Command register.
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*
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* Contains Command bits, PowerDown bit and bit to switch receiver off.
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*/
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#define PHHAL_HW_RC523_REG_COMMAND 0x01U
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/** \brief CommIEn register.
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*
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* Contains Communication interrupt enable bits and bit for Interrupt inversion.
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*/
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#define PHHAL_HW_RC523_REG_COMMIEN 0x02U
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/** \brief DivIEn register.
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*
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* Contains RfOn, RfOff, CRC and Mode Interrupt enable and bit to switch Interrupt pin to PushPull mode.
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*/
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#define PHHAL_HW_RC523_REG_DIVIEN 0x03U
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/** \brief CommIrq register.
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*
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* Contains Communication interrupt request bits.
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*/
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#define PHHAL_HW_RC523_REG_COMMIRQ 0x04U
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/** \brief DivIrq register.
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*
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* Contains RfOn, RfOff, CRC and Mode Interrupt request.
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*/
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#define PHHAL_HW_RC523_REG_DIVIRQ 0x05U
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/** \brief Error register.
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*
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* Contains Protocol, Parity, CRC, Collision, Buffer overflow, Temperature and RF error flags.
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*/
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#define PHHAL_HW_RC523_REG_ERROR 0x06U
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/** \brief Status1 register.
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*
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* Contains status information about Lo- and HiAlert, RF-field on, Timer, Interrupt request and CRC status.
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*/
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#define PHHAL_HW_RC523_REG_STATUS1 0x07U
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/** \brief Status2 register.
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*
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* Contains information about internal states and Temperature sensor switch.
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*/
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#define PHHAL_HW_RC523_REG_STATUS2 0x08U
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/** \brief Fifo register.
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*
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* Read/Write Fifo. Writing to register increments the Fifo level, reading decrements it.
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*/
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#define PHHAL_HW_RC523_REG_FIFODATA 0x09U
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/** \brief FifoLevel register.
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*
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* Contains the actual level (number of bytes) of the Fifo.
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*/
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#define PHHAL_HW_RC523_REG_FIFOLEVEL 0x0AU
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/** \brief WaterLevel register.
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*
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* Contains the Waterlevel value for the Fifo.
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*/
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#define PHHAL_HW_RC523_REG_WATERLEVEL 0x0BU
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/** \brief Control register.
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*
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* Contains information about last received bits, and to Start and stop the Timer unit.
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*/
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#define PHHAL_HW_RC523_REG_CONTROL 0x0CU
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/** \brief Bit framing register.
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*
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* Contains information of last bits to send, to align received bits in Fifo and activate sending.
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*/
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#define PHHAL_HW_RC523_REG_BITFRAMING 0x0DU
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/** \brief Collision register.
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*
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* Contains all necessary bits for Collision handling.
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*/
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#define PHHAL_HW_RC523_REG_COLL 0x0EU
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/*@}*/
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/** \name Register definitions of Page 1
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* Following all register definitions of Page 1.
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*/
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/*@{*/
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/** \brief Mode register.
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*
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* Contains bits for auto wait on Rf and MSB first for CRC calculation.
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*/
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#define PHHAL_HW_RC523_REG_MODE 0x11U
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/** \brief TxMode register.
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*
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* Contains Transmit Framing, Speed, CRC enable, bit for inverse mode and TXMix bit.
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*/
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#define PHHAL_HW_RC523_REG_TXMODE 0x12U
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/** \brief RxMode register.
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*
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* Contains Transmit Framing, Speed, CRC enable, bit for multiple receive and to filter errors.
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*/
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#define PHHAL_HW_RC523_REG_RXMODE 0x13U
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/** \brief TxControl register.
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*
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* Contains bits to activate and configure Tx1 and Tx2 and bit to activate 100% modulation.
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*/
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#define PHHAL_HW_RC523_REG_TXCONTROL 0x14U
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/** \brief TxAsk register.
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*
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* Contains Tx ASK settings.
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*/
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#define PHHAL_HW_RC523_REG_TXASK 0x15U
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/** \brief TxSel register.
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*
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* Contains SigoutSel, DriverSel and LoadModSel bits.
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*/
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#define PHHAL_HW_RC523_REG_TXSEL 0x16U
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/** \brief RxSel register.
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*
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* Contains UartSel and RxWait bits.
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*/
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#define PHHAL_HW_RC523_REG_RXSEL 0x17U
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/** \brief RxThreshold register.
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*
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* Contains MinLevel and CollLevel for detection.
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*/
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#define PHHAL_HW_RC523_REG_RXTHRESHOLD 0x18U
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/** \brief Demod register.
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*
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* Contains bits for time constants, hysteresis and IQ demodulator settings.
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*/
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#define PHHAL_HW_RC523_REG_DEMOD 0x19U
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/** \brief FelNFC2Reg register.
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*
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* Contains bits for Disabling Active Communication mode.
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*/
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#define PHHAL_HW_RC523_REG_FELNFC2 0x1BU
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/** \brief MfTx register.
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*
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* Mifare transmission settings.
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*/
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#define PHHAL_HW_RC523_REG_MFTX 0x1CU
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/** \brief MfRx register.
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*
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* Mifare reception settings.
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*/
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#define PHHAL_HW_RC523_REG_MFRX 0x1DU
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/** \brief TypeB register.
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*
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* Used for ISO/IEC 14443 Type B configuration.
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*/
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#define PHHAL_HW_RC523_REG_TYPEB 0x1EU
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/** \brief SerialSpeed register.
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*
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* Contains speed settings for RS232 interface.
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*/
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#define PHHAL_HW_RC523_REG_SERIALSPEED 0x1FU
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/*@}*/
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/** \name Register definitions of Page 2
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* Following all register definitions of Page 2.
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*/
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/*@{*/
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/** \brief CRCResult1 register.
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*
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* Contains MSByte of CRC Result.
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*/
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#define PHHAL_HW_RC523_REG_CRCRESULT1 0x21U
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/** \brief CRCResult2 register.
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*
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* Contains LSByte of CRC Result.
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*/
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#define PHHAL_HW_RC523_REG_CRCRESULT2 0x22U
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/** \brief GSNOff register.
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*
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* Contains the conductance and the modulation settings for the N-MOS transistor for LoadModulation.
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*/
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#define PHHAL_HW_RC523_REG_GSNOFF 0x23U
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/** \brief ModWidth register.
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*
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* Contains modulation width setting.
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*/
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#define PHHAL_HW_RC523_REG_MODWIDTH 0x24U
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#define PHHAL_HW_RC523_REG_TXBITPHASE 0x25U
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/** \brief RfCfg register.
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*
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* Contains sensitivity of Rf Level detector, the receiver gain factor and the RfLevelAmp.
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*/
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#define PHHAL_HW_RC523_REG_RFCFG 0x26U
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/** \brief GSN register.
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*
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* Contains the conductance and the modulation settings for the N-MOS transistor during active modulation.
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*/
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#define PHHAL_HW_RC523_REG_GSN 0x27U
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/** \brief CWGSP register.
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*
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* Contains the conductance for the P-Mos transistor.
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*/
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#define PHHAL_HW_RC523_REG_CWGSP 0x28U
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/** \brief MODGSP register.
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*
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* Contains the modulation index for the PMos transistor.
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*/
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#define PHHAL_HW_RC523_REG_MODGSP 0x29U
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/** \brief TMode register.
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*
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* Contains all settings for the timer and the highest 4 bits of the prescaler.
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*/
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#define PHHAL_HW_RC523_REG_TMODE 0x2AU
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/** \brief TPrescaler register.
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*
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* Contains the lowest byte of the pre-scaler.
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*/
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#define PHHAL_HW_RC523_REG_TPRESCALER 0x2BU
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/** \brief TReloadHi register.
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*
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* Contains the high byte of the reload value.
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*/
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#define PHHAL_HW_RC523_REG_TRELOADHI 0x2CU
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/** \brief TReloadLo register.
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*
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* Contains the low byte of the reload value.
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*/
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#define PHHAL_HW_RC523_REG_TRELOADLO 0x2DU
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/** \brief TCounterValHi register.
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*
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* Contains the high byte of the counter value.
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*/
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#define PHHAL_HW_RC523_REG_TCOUNTERVALHI 0x2EU
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/** \brief TCounterValLo register.
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*
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* Contains the low byte of the counter value.
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*/
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#define PHHAL_HW_RC523_REG_TCOUNTERVALLO 0x2FU
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/*@}*/
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/** \name Register definitions of Page 3
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* Following all register definitions of Page 3.
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*/
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/*@{*/
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#define PHHAL_HW_RC523_REG_TESTSEL1 0x31U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTSEL2 0x32U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTPINEN 0x33U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTPINVALUE 0x34U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTBUS 0x35U /**< Test register. */
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#define PHHAL_HW_RC523_REG_AUTOTEST 0x36U /**< Test register. */
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#define PHHAL_HW_RC523_REG_VERSION 0x37U /**< Contains the product number and the version. */
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#define PHHAL_HW_RC523_REG_ANALOGTEST 0x38U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTDAC1 0x39U /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTDAC2 0x3AU /**< Test register. */
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#define PHHAL_HW_RC523_REG_TESTADC 0x3BU /**< Test register. */
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/*@}*/
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/** \name Command Register Contents (0x01)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_RCVOFF 0x20U /**< Switches the receiver on/off. */
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#define PHHAL_HW_RC523_BIT_POWERDOWN 0x10U /**< Switches Ic to Power Down mode. */
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#define PHHAL_HW_RC523_CMD_IDLE 0x00U /**< No action; cancels current command execution. */
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#define PHHAL_HW_RC523_CMD_MEM 0x01U /**< Copy configuration data from Fifo to internal Buffer or if Fifo empty vice versa. */
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#define PHHAL_HW_RC523_CMD_RANDOMIDS 0x02U /**< Replaces stored IDs with random ones. */
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/** \brief Activate the CRC-Coprocessor.
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*
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* <b>Remark:</b> The result of the CRC calculation can be read from e.g. #PHHAL_HW_RC523_REG_CRCRESULT1.
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*/
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#define PHHAL_HW_RC523_CMD_CALCCRC 0x03U
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#define PHHAL_HW_RC523_CMD_TRANSMIT 0x04U /**< Transmits data from the FIFO buffer to Card. */
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#define PHHAL_HW_RC523_CMD_NOCMDCHANGE 0x07U /**< No change; Use together with e.g. #PHHAL_HW_RC523_BIT_POWERDOWN to keep current command-state. */
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#define PHHAL_HW_RC523_CMD_RECEIVE 0x08U /**< Activates the receiver circuitry. */
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#define PHHAL_HW_RC523_CMD_TRANSCEIVE 0x0CU /**< Like #PHHAL_HW_RC523_CMD_TRANSMIT but automatically activates the receiver after transmission is finished. */
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#define PHHAL_HW_RC523_CMD_AUTOCOLL 0x0DU /**< Handles Felica polling or MIFARE anti-collision in Target mode. */
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#define PHHAL_HW_RC523_CMD_AUTHENT 0x0EU /**< Performs the Mifare Classic authentication (in Mifare Reader/Writer mode only). */
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#define PHHAL_HW_RC523_CMD_SOFTRESET 0x0FU /**< Resets the IC. */
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#define PHHAL_HW_RC523_MASK_COMMAND 0x0FU /**< Mask for Command-bits. */
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/*@}*/
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/** \name CommIEn/CommIrq Register Contents (0x02/0x04)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_SET 0x80U /**< Bit position to set/clear dedicated IRQ bits. */
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#define PHHAL_HW_RC523_BIT_IRQINV 0x80U /**< Inverts the output of IRQ Pin. */
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#define PHHAL_HW_RC523_BIT_TXI 0x40U /**< Bit position for Transmit Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_RXI 0x20U /**< Bit position for Receive Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_IDLEI 0x10U /**< Bit position for Idle Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_HIALERTI 0x08U /**< Bit position for HiAlert Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_LOALERTI 0x04U /**< Bit position for LoAlert Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_ERRI 0x02U /**< Bit position for Error Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_TIMERI 0x01U /**< Bit position for Timer Interrupt Enable/Request. */
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/*@}*/
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/** \name DivIEn/DivIrq Register Contents (0x03/0x05)
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*/
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/*@{*/
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/* #define PHHAL_HW_RC523_BIT_SET 0x80U */
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#define PHHAL_HW_RC523_BIT_IRQPUSHPULL 0x80U /**< Sets the IRQ pin to Push Pull mode. */
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#define PHHAL_HW_RC523_BIT_MFINACT 0x10U /**< Bit position for MfInAct Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_CRCI 0x04U /**< Bit position for CRC Interrupt Enable/Request. */
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#define PHHAL_HW_RC523_BIT_EXT_RF_ON 0x02U /**< Bit position for External RF ON. */
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#define PHHAL_HW_RC523_BIT_EXT_RF_OFF 0x01U /**< Bit position for External RF OFF. */
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/*@}*/
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/** \name Error Register Contents (0x06)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_WRERR 0x80U /**< Bit position for Write Access Error. */
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#define PHHAL_HW_RC523_BIT_TEMPERR 0x40U /**< Bit position for Temperature Error. */
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#define PHHAL_HW_RC523_BIT_RFERR 0x20U /**< Bit position for RF Error. */
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#define PHHAL_HW_RC523_BIT_BUFFEROVFL 0x10U /**< Bit position for Buffer Overflow Error. */
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#define PHHAL_HW_RC523_BIT_COLLERR 0x08U /**< Bit position for Collision Error. */
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#define PHHAL_HW_RC523_BIT_CRCERR 0x04U /**< Bit position for CRC Error. */
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#define PHHAL_HW_RC523_BIT_PARITYERR 0x02U /**< Bit position for Parity Error. */
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#define PHHAL_HW_RC523_BIT_PROTERR 0x01U /**< Bit position for Protocol Error. */
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/*@}*/
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/** \name Status1 Register Contents (0x07)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_CRCOK 0x40U /**< Bit position for status CRC OK. */
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#define PHHAL_HW_RC523_BIT_CRCREADY 0x20U /**< Bit position for status CRC Ready. */
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#define PHHAL_HW_RC523_BIT_IRQ 0x10U /**< Bit position for status IRQ is active. */
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#define PHHAL_HW_RC523_BIT_TRUNNUNG 0x08U /**< Bit position for status Timer is running. */
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#define PHHAL_HW_RC523_BIT_RFON 0x04U /**< Bit position for status External RF. */
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#define PHHAL_HW_RC523_BIT_HIALERT 0x02U /**< Bit position for status HiAlert. */
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#define PHHAL_HW_RC523_BIT_LOALERT 0x01U /**< Bit position for status LoAlert. */
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/*@}*/
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/** \name Status2 Register Contents (0x08)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_TEMPSENSOFF 0x80U /**< Bit position to switch Temperature sensors on/off. */
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#define PHHAL_HW_RC523_BIT_I2CFORCEHS 0x40U /**< Bit position to forece High speed mode for I2C Interface. */
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#define PHHAL_HW_RC523_BIT_TARGET_ACTIVATED 0x10U /**< Bit position for reader status Target Activated. */
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#define PHHAL_HW_RC523_BIT_CRYPTO1ON 0x08U /**< Bit position for reader status Crypto is on. */
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#define PHHAL_HW_RC523_MASK_MODEMBITS 0x07U /**< Bitmask for MODEM Status bits. */
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#define PHHAL_HW_RC523_BIT_IDLE 0x00U /**< Bits represent MODEM Status as IDLE. */
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#define PHHAL_HW_RC523_BIT_WAIT_FOR_STARTSEND 0x01U /**< Bits represent MODEM Status as Wait for StartSend. */
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#define PHHAL_HW_RC523_BIT_WAIT_FOR_DATA 0x05U /**< Bits represent MODEM Status as Wait for data. */
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/*@}*/
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/** \name FifoLevel Register Contents (0x0A)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_FLUSHBUFFER 0x80U /**< Clears Fifo buffer if set to 1. */
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/*@}*/
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/** \name WaterLevel Register Contents (0x0B)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_MASK_WATERLEVEL 0x3FU /**< Bitmask for Waterlevel bits. */
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/*@}*/
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/** \name Control Register Contents (0x0C)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_TSTOPNOW 0x80U /**< Stops timer if set to 1. */
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#define PHHAL_HW_RC523_BIT_TSTARTNOW 0x40U /**< Starts timer if set to 1. */
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#define PHHAL_HW_RC523_BIT_INITIATOR 0x10U /**< If set to 1, the IC acts as initiator, otherwise as target. */
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#define PHHAL_HW_RC523_MASK_RXBITS 0x07U /**< Bitmask for RxLast bits. */
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/*@}*/
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/** \name BitFraming Register Contents (0x0D)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_STARTSEND 0x80U /**< Starts transmission in transceive command if set to 1. */
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#define PHHAL_HW_RC523_MASK_TXBITS 0x07U /**< Bitmask for TxLast bits. */
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#define PHHAL_HW_RC523_MASK_RXALIGN 0x70U /**< Bitmask for RxAlign bits. */
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/*@}*/
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/** \name Collision Register Contents (0x0E)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_VALUESAFTERCOLL 0x80U /**< Activates mode to keep data after collision. */
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#define PHHAL_HW_RC523_BIT_COLLPOSNOTVALID 0x20U /**< Whether collision position is valid or not. */
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#define PHHAL_HW_RC523_MASK_COLLPOS 0x1FU /**< Bitmask for CollPos bits. */
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/*@}*/
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/** \name Mode Register Contents (0x11)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_MSBFIRST 0x80U /**< Sets CRC coprocessor with MSB first. */
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#define PHHAL_HW_RC523_BIT_TXWAITRF 0x20U /**< Waits until RF is enabled until transmission is started, else starts immediately. */
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#define PHHAL_HW_RC523_BIT_POLMFIN 0x08U /**< Inverts polarity of MfinActIrq. If bit is set to 1 IRQ occurs when Sigin line is 0. */
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#define PHHAL_HW_RC523_BIT_MODEDETOFF 0x04U /**< Set to logic 1, the internal mode detector is switched off during #PHHAL_HW_RC523_CMD_AUTOCOLL. */
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#define PHHAL_HW_RC523_MASK_CRCPRESET 0x03U /**< Bitmask for CRCPreset bits. */
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/*@}*/
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/** \name TxMode / RxMode Register Contents (0x12/0x13)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_CRCEN 0x80U /**< Activates transmit or receive CRC. */
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#define PHHAL_HW_RC523_BIT_848KBPS 0x30U /**< Activates speed of 848kbps. */
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#define PHHAL_HW_RC523_BIT_424KBPS 0x20U /**< Activates speed of 424kbps. */
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#define PHHAL_HW_RC523_BIT_212KBPS 0x10U /**< Activates speed of 212kbps. */
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#define PHHAL_HW_RC523_BIT_106KBPS 0x00U /**< Activates speed of 106kbps. */
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#define PHHAL_HW_RC523_BIT_INVMOD 0x08U /**< Activates inverted transmission mode. */
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#define PHHAL_HW_RC523_BIT_RXNOERR 0x08U /**< If set, receiver ignores less than 4 bits. */
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#define PHHAL_HW_RC523_BIT_RXMULTIPLE 0x04U /**< Activates reception mode for multiple responses. */
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#define PHHAL_HW_RC523_BIT_TYPEB 0x03U /**< Activates Type B communication mode. */
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#define PHHAL_HW_RC523_BIT_FELICA 0x02U /**< Activates Felica communication mode. */
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#define PHHAL_HW_RC523_BIT_ACTIVE 0x01U /**< Activates Active communication mode. */
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#define PHHAL_HW_RC523_BIT_MIFARE 0x00U /**< Activates Mifare communication mode. */
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#define PHHAL_HW_RC523_BIT_MIFARE_CE 0x80U /**< Activates Mifare communication mode. */
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#define PHHAL_HW_RC523_MASK_SPEED 0x70U /**< Bitmask for Tx/RxSpeed bits. */
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#define PHHAL_HW_RC523_SHIFT_SPEED 0x04U /**< Number of bits to be shifted. */
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#define PHHAL_HW_RC523_MASK_FRAMING 0x03U /**< Bitmask for Tx/RxFraming bits. */
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#define PHHAL_HW_RC523_BIT_AUTORF_OFF 0x80U /**< Bitmask for Auto RF Off. */
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#define PHHAL_HW_RC523_BIT_CA_ON 0x08U /**< Bitmask for CA. */
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#define PHHAL_HW_RC523_BIT_DETECT_SYNC 0x40U /**< Bitmask for Detect Sync. */
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#define PHHAL_HW_RC523_BIT_INITIAL_RF_ON 0x04U /**< Bitmask for Initial RF on. */
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#define PHHAL_HW_RC523_BIT_TX2RFAutoEN 0x02U /**< Bitmask for Auto RF ON. */
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#define PHHAL_HW_RC523_BIT_TX1RFAutoEN 0x1U /**< Bitmask for Auto RF ON. */
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/*@}*/
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/** \name TxControl Register Contents (0x14)
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*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_INVTX2ON 0x80U /**< Inverts the Tx2 output if drivers are switched on. */
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#define PHHAL_HW_RC523_BIT_INVTX1ON 0x40U /**< Inverts the Tx1 output if drivers are switched on. */
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#define PHHAL_HW_RC523_BIT_INVTX2OFF 0x20U /**< Inverts the Tx2 output if drivers are switched off. */
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#define PHHAL_HW_RC523_BIT_INVTX1OFF 0x10U /**< Inverts the Tx1 output if drivers are switched off. */
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#define PHHAL_HW_RC523_BIT_TX2CW 0x08U /**< Does not modulate the Tx2 output, only constant wave. */
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#define PHHAL_HW_RC523_BIT_CHECKRF 0x04U /**< Set to logic 1, RF field cannot be activated if external RF field is detected. */
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#define PHHAL_HW_RC523_BIT_TX2RFEN 0x02U /**< Switches the driver for Tx2 pin on. */
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#define PHHAL_HW_RC523_BIT_TX1RFEN 0x01U /**< Switches the driver for Tx1 pin on. */
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/*@}*/
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/** \name TxASK Register Contents (0x15)
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|
*/
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/*@{*/
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#define PHHAL_HW_RC523_BIT_FORCE100ASK 0x40U /**< Activates 100%ASK mode independent of driver settings. */
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/*@}*/
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/** \name TxSel Register Contents (0x16)
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*/
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|
/*@{*/
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#define PHHAL_HW_RC523_MASK_DRIVERSEL 0x30U /**< Bitmask for DriverSel bits. */
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#define PHHAL_HW_RC523_MASK_MFOUTSEL 0x0FU /**< Bitmask for MfOutSel bits. */
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/*@}*/
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|
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/** \name RxSel Register Contents (0x17)
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|
*/
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|
/*@{*/
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|
#define PHHAL_HW_RC523_MASK_UARTSEL 0xC0U /**< Bitmask for UartSel bits. */
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#define PHHAL_HW_RC523_MASK_RXWAIT 0x3FU /**< Bitmask for RxWait bits. */
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|
/*@}*/
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|
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|
/** \name RxThreshold Register Contents (0x18)
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|
*/
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|
/*@{*/
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|
#define PHHAL_HW_RC523_MASK_MINLEVEL 0xF0U /**< Bitmask for MinLevel bits. */
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|
#define PHHAL_HW_RC523_MASK_COLLEVEL 0x07U /**< Bitmask for CollLevel bits. */
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|
/*@}*/
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|
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|
/** \name Demod Register Contents (0x19)
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|
*/
|
|
/*@{*/
|
|
/**
|
|
* If set and the lower bit of AddIQ is cleared, the receiving is fixed to I channel.\n
|
|
* If set and the lower bit of AddIQ is set, the receiving is fixed to Q channel.
|
|
*/
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|
#define PHHAL_HW_RC523_BIT_FIXIQ 0x20U
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|
#define PHHAL_HW_RC523_MASK_ADDIQ 0xC0U /**< Bitmask for ADDIQ bits. */
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|
#define PHHAL_HW_RC523_MASK_TAURCV 0x0CU /**< Bitmask for TauRcv bits. */
|
|
#define PHHAL_HW_RC523_MASK_TAUSYNC 0x03U /**< Bitmask for TauSync bits. */
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|
/*@}*/
|
|
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|
/** \name FelNFC2Reg Register Contents (0x1B)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_WAIT_FOR_SELECTED 0x80U /**< Bitmask for WaitForSelected bit. */
|
|
/*@}*/
|
|
|
|
/** \name MfTx Register Contents (0x1C)
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|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_TXWAIT 0x03U /**< Bitmask for TxWait bits. */
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|
#define PHHAL_HW_RC523_BIT_MFHALTED 0x04U /**< Set to logic 1, Responds only for ALL_REQ ("52"). */
|
|
/*@}*/
|
|
|
|
/** \name MfRx Register Contents (0x1D)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_BIT_PARITYDISABLE 0x10U /**< Disables the parity generation and sending independent from the mode. */
|
|
/*@}*/
|
|
|
|
/** \name ISO/IEC 14443 Type B configuration Register Contents (0x1E)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_RXEOFREQ 0x40U /**< Bitmask for RX EOF required for Type B. */
|
|
/*@}*/
|
|
|
|
/** \name RFCfg Register Contents (0x26)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_RXGAIN 0x70U /**< Bitmask for RxGain bits. */
|
|
/*@}*/
|
|
|
|
/** \name GsN Register Contents (0x27)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_CWGSN 0xF0U /**< Bitmask for CWGsN bits. */
|
|
#define PHHAL_HW_RC523_MASK_MODGSN 0x0FU /**< Bitmask for ModGsN bits. */
|
|
/*@}*/
|
|
|
|
/** \name CWGsP Register Contents (0x28)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_CWGSP 0x3FU /**< Bitmask for CWGsP bits. */
|
|
/*@}*/
|
|
|
|
/** \name ModGsP Register Contents (0x29)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_MASK_MODGSP 0x3FU /**< Bitmask for ModGsP bits. */
|
|
/*@}*/
|
|
|
|
/** \name TMode Register Contents (0x2A)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC523_BIT_TAUTO 0x80U /**< Sets the Timer start/stop conditions to Auto mode. */
|
|
#define PHHAL_HW_RC523_BIT_TAUTORESTART 0x10U /**< Restarts the timer automatically after counting down to 0. */
|
|
#define PHHAL_HW_RC523_MASK_TGATED 0x60U /**< Bitmask for TGated bits. */
|
|
#define PHHAL_HW_RC523_MASK_TPRESCALER_HI 0x0FU /**< Bitmask for TPrescalerHi bits. */
|
|
/*@}*/
|
|
|
|
/**
|
|
* \brief Write to 8bit address of CL front-end register.
|
|
*
|
|
* \return Status code
|
|
* \retval #PH_ERR_SUCCESS Operation successful.
|
|
* \retval #PH_ERR_INTERFACE_ERROR Hardware problem
|
|
*/
|
|
phStatus_t phhalHw_Rc523_WriteRegister(
|
|
phhalHw_Rc523_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
|
uint8_t bAddress, /**< [In] Register Address. */
|
|
uint8_t bValue /**< [In] Register Value. */
|
|
);
|
|
|
|
/**
|
|
* \brief Read 8bit register address from CL front-ends.
|
|
*
|
|
* \return Status code
|
|
* \retval #PH_ERR_SUCCESS Operation successful.
|
|
* \retval #PH_ERR_INTERFACE_ERROR Hardware problem
|
|
*/
|
|
phStatus_t phhalHw_Rc523_ReadRegister(
|
|
phhalHw_Rc523_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
|
uint8_t bAddress, /**< [In] Register Address. */
|
|
uint8_t * pValue /**< [Out] Register Value. */
|
|
);
|
|
|
|
/** @}
|
|
* end of phhalHw_Rc523_Reg group
|
|
*/
|
|
#endif /* NXPBUILD__PHHAL_HW_RC523 */
|
|
|
|
#ifdef __cplusplus
|
|
} /* Extern C */
|
|
#endif
|
|
|
|
#endif /* PHHALHW_RC523_REG_H */
|