981 lines
29 KiB
C
981 lines
29 KiB
C
/*
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* Copyright (c), NXP Semiconductors Gratkorn / Austria
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*
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* (C)NXP Semiconductors
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* All rights are reserved. Reproduction in whole or in part is
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* prohibited without the written consent of the copyright owner.
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* NXP reserves the right to make changes without notice at any time.
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* NXP makes no warranty, expressed, implied or statutory, including but
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* not limited to any implied warranty of merchantability or fitness for any
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*particular purpose, or that the use will not infringe any third party patent,
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* copyright or trademark. NXP must not be liable for any loss or damage
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* arising from its use.
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*/
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/** \file
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* Rc663 register definitions for Reader Library Framework.
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* $Author: Purnank G (ing05193) $
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* $Revision: 5076 $ (v4.040.05.011646)
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* $Date: 2016-06-13 17:29:09 +0530 (Mon, 13 Jun 2016) $
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*
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* History:
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* CHu: Generated 19. November 2009
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*
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*/
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#ifndef PHHALHW_RC663_REG_H
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#define PHHALHW_RC663_REG_H
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#include <ph_Status.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef NXPBUILD__PHHAL_HW_RC663
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/** \defgroup phhalHw_Rc663_Reg Register Definitions
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* \brief Register definitions.
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* @{
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*/
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/** \brief Command Register.
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*
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* Used for starting / stopping commands and for sending the IC into standby mode.
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*/
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#define PHHAL_HW_RC663_REG_COMMAND 0x00
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/** \brief Host-Control Register.
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*
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* Configure Host and SAM interfaces.
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*/
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#define PHHAL_HW_RC663_REG_HOSTCTRL 0x01
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/** \name Fifo Registers
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*/
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/*@{*/
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/** \brief FIFO-Control Register.
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*
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* Set FIFO size and retrieve FIFO parameters.\n
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* \b Note: Also contains 1 additional Water-Level bit (MSB) and 2 additional FIFO-Length bits (also MSB).
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*/
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#define PHHAL_HW_RC663_REG_FIFOCONTROL 0x02
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/** \brief WaterLevel Register.
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*
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* FIFO WaterLevel configuration.
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*/
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#define PHHAL_HW_RC663_REG_WATERLEVEL 0x03
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/** \brief FIFO-Length Register.
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*
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* Retrieve the number of bytes within the FIFO.
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*/
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#define PHHAL_HW_RC663_REG_FIFOLENGTH 0x04
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/** \brief FIFO-Data Register.
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*
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* Writing to this register moves a byte into the FIFO
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* while incrementing the FIFO length and raising the internal WaterLevel.
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*/
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#define PHHAL_HW_RC663_REG_FIFODATA 0x05
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/*@}*/
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/** \name IRQ Registers
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*/
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/*@{*/
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/** \brief IRQ0 Register.
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*
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* Read or modify the first 7 IRQ bits.
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*/
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#define PHHAL_HW_RC663_REG_IRQ0 0x06
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/** \brief IRQ1 Register.
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*
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* Read or modify the second 7 IRQ bits.
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*/
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#define PHHAL_HW_RC663_REG_IRQ1 0x07
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/** \brief IRQ0EN Register.
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*
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* Enable or disable the first IRQ bits or invert the IRQ propagation.
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*/
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#define PHHAL_HW_RC663_REG_IRQ0EN 0x08
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/** \brief IRQ1EN Register.
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*
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* Enable or disable the second IRQ bits or enable/disable PushPull mode.
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*/
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#define PHHAL_HW_RC663_REG_IRQ1EN 0x09
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/*@}*/
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/** \brief Error Register.
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*
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* Contains bits for the occured erros.
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*/
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#define PHHAL_HW_RC663_REG_ERROR 0x0A
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/** \brief Status Register.
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*
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* Contains the Crypto1 state and information about the ComState.
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*/
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#define PHHAL_HW_RC663_REG_STATUS 0x0B
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/** \brief Rx-Bit-Control Register.
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*
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* Set/Get Bit-granularity and collision information.
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*/
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#define PHHAL_HW_RC663_REG_RXBITCTRL 0x0C
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/** \brief Rx-Coll Register.
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*
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* Contains information about the collision position after a collision.
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*/
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#define PHHAL_HW_RC663_REG_RXCOLL 0x0D
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/** \name Timer Registers
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*/
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/*@{*/
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/** \brief Timer Control Register.
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*
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* Provides timer control and status information for all timers.
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*/
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#define PHHAL_HW_RC663_REG_TCONTROL 0x0E
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/** \brief Timer0 Control Register.
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*
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* Configure the timer.
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*/
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#define PHHAL_HW_RC663_REG_T0CONTROL 0x0F
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/** \brief Timer0 Reload(High) Register.
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*
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* Set the most significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T0RELOADHI 0x10
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/** \brief Timer0 Reload(Low) Register.
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*
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* Set the least significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T0RELOADLO 0x11
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/** \brief Timer0 Counter(High) Register.
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*
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* Get the most significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T0COUNTERVALHI 0x12
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/** \brief Timer0 Counter(Low) Register.
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*
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* Get the least significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T0COUNTERVALLO 0x13
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/** \brief Timer1 Control Register.
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*
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* Configure the timer.
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*/
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#define PHHAL_HW_RC663_REG_T1CONTROL 0x14
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/** \brief Timer1 Reload(High) Register.
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*
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* Set the most significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T1RELOADHI 0x15
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/** \brief Timer1 Reload(Low) Register.
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*
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* Set the least significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T1RELOADLO 0x16
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/** \brief Timer1 Counter(High) Register.
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*
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* Get the most significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T1COUNTERVALHI 0x17
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/** \brief Timer1 Counter(Low) Register.
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*
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* Get the least significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T1COUNTERVALLO 0x18
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/** \brief Timer2 Control Register.
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*
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* Configure the timer.
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*/
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#define PHHAL_HW_RC663_REG_T2CONTROL 0x19
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/** \brief Timer2 Reload(High) Register.
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*
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* Set the most significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T2RELOADHI 0x1A
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/** \brief Timer2 Reload(Low) Register.
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*
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* Set the least significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T2RELOADLO 0x1B
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/** \brief Timer2 Counter(High) Register.
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*
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* Get the most significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T2COUNTERVALHI 0x1C
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/** \brief Timer2 Counter(Low) Register.
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*
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* Get the least significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T2COUNTERVALLO 0x1D
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/** \brief Timer3 Control Register.
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*
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* Configure the timer.
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*/
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#define PHHAL_HW_RC663_REG_T3CONTROL 0x1E
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/** \brief Timer3 Reload(High) Register.
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*
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* Set the most significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T3RELOADHI 0x1F
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/** \brief Timer3 Reload(Low) Register.
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*
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* Set the least significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T3RELOADLO 0x20
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/** \brief Timer3 Counter(High) Register.
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*
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* Get the most significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T3COUNTERVALHI 0x21
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/** \brief Timer3 Counter(Low) Register.
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*
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* Get the least significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T3COUNTERVALLO 0x22
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/** \brief Timer4 Control Register.
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*
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* Configure the timer.
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*/
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#define PHHAL_HW_RC663_REG_T4CONTROL 0x23
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/** \brief Timer4 Reload(High) Register.
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*
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* Set the most significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T4RELOADHI 0x24
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/** \brief Timer4 Reload(Low) Register.
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*
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* Set the least significant byte of the Reload-Value.
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*/
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#define PHHAL_HW_RC663_REG_T4RELOADLO 0x25
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/** \brief Timer4 Counter(High) Register.
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*
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* Get the most significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T4COUNTERVALHI 0x26
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/** \brief Timer4 Counter(Low) Register.
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*
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* Get the least significant byte of the Counter-Value.
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*/
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#define PHHAL_HW_RC663_REG_T4COUNTERVALLO 0x27
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/*@}*/
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/** \brief Driver Mode Register.
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*
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* Enable / Invert the Tx-Driver and set the Clock Mode.
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*/
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#define PHHAL_HW_RC663_REG_DRVMODE 0x28
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/** \brief Tx Amplifier Register.
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*
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* Modify Amplitude and Carrier settings.
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*/
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#define PHHAL_HW_RC663_REG_TXAMP 0x29
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/** \brief Driver Control Register.
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*
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* Select / Invert drivers.
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*/
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#define PHHAL_HW_RC663_REG_DRVCON 0x2A
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/** \brief TxI Register.
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*
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* Contains Overshoot prevention and current control settings.
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*/
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#define PHHAL_HW_RC663_REG_TXI 0x2B
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/** \brief Tx-CRC Control Register.
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*
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* Configure CRC parameters transmission.
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*/
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#define PHHAL_HW_RC663_REG_TXCRCCON 0x2C
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/** \brief Rx-CRC Control Register.
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*
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* Configure CRC parameters for reception.
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*/
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#define PHHAL_HW_RC663_REG_RXCRCCON 0x2D
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/** \brief Tx-DataNum Register.
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*
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* Set TxLastBits and configure KeepBitGrid functionality.
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*/
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#define PHHAL_HW_RC663_REG_TXDATANUM 0x2E
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/** \brief Tx-Modwidth Register.
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*
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* Set the modulation width.
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*/
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#define PHHAL_HW_RC663_REG_TXMODWIDTH 0x2F
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/** \brief Symbol 0 and 1 Register.
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*
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* Configure Burst-lengths of both symbols.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM10BURSTLEN 0x30
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/** \brief Tx-Wait Control Register.
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*
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* Enable / Configure Tx Waiting-Time.
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*/
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#define PHHAL_HW_RC663_REG_TXWAITCTRL 0x31
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/** \brief TxWaitLo Register.
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*
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* Contains the Least-Significant-Bits for the Tx Waiting-Time.
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*/
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#define PHHAL_HW_RC663_REG_TXWAITLO 0x32
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/** \brief Frame control register.
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*
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* Contains active Start/Stop symbol and Parity settings.
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*/
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#define PHHAL_HW_RC663_REG_FRAMECON 0x33
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/** \brief RxSOFD Register.
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*
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* Contains Start-of-Frame and subcarrier detection bits.
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*/
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#define PHHAL_HW_RC663_REG_RXSOFD 0x34
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/** \brief Rx Control Register.
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*
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* Configure Receiver settings such as baudrate and EMD-suppression feature.
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*/
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#define PHHAL_HW_RC663_REG_RXCTRL 0x35
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/** \brief Rx-Wait Register.
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*
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* Configure Receiver Deaf-Time.
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*/
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#define PHHAL_HW_RC663_REG_RXWAIT 0x36
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/** \brief Rx-Threshold Register.
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*
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* Configure Receiver Threshold.
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*/
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#define PHHAL_HW_RC663_REG_RXTHRESHOLD 0x37
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/** \brief Receiver Register.
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*
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* Configure Collision-Level and other features.
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*/
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#define PHHAL_HW_RC663_REG_RCV 0x38
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/** \brief Rx-Analog Register.
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*
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* Configure analog settings and parameters for Receiver circuitry.
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*/
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#define PHHAL_HW_RC663_REG_RXANA 0x39
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/** \brief Serial Speed Register.
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*
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* Configure serial baudrates.
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*/
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#define PHHAL_HW_RC663_REG_SERIALSPEED 0x3B
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/** \brief LPO_TRIMM Register.
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*
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* Trimm Control Input for Low Power Oscillator.
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*/
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#define PHHAL_HW_RC663_REG_LPO_TRIMM 0x3C
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/** \brief PLL Control Register.
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*
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* Configure PLL settings.
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*/
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#define PHHAL_HW_RC663_REG_PLL_CTRL 0x3D
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/** \brief PLL DivO Register.
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*
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* Contains PLL output.
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*/
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#define PHHAL_HW_RC663_REG_PLL_DIV 0x3E
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/** \brief LPCD QMin Register.
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*
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* Configure IMax(2) and QMin values for LPCD.
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*/
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#define PHHAL_HW_RC663_REG_LPCD_QMIN 0x3F
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/** \brief LPCD QMax Register.
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*
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* Configure IMax(1) and QMax values for LPCD.
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*/
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#define PHHAL_HW_RC663_REG_LPCD_QMAX 0x40
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/** \brief LPCD IMin Register.
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*
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* Configure IMax(0) and IMin values for LPCD.
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*/
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#define PHHAL_HW_RC663_REG_LPCD_IMIN 0x41
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/** \brief LPCD Result(I) Register.
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*
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* Contains I-Channel results of LPCD.
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*/
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#define PHHAL_HW_RC663_REG_LPCD_RESULT_I 0x42
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/** \brief LPCD Result(Q) Register.
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*
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* Contains Q-Channel results of LPCD.
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*/
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#define PHHAL_HW_RC663_REG_LPCD_RESULT_Q 0x43
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/** \brief Transmitter bit modulus Register.
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*
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* Define Tx data interpretation.
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*/
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#define PHHAL_HW_RC663_TXBITMOD 0x48
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/** \brief Transmitter data configuration register.
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*
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* Contains Type of data encoding, subcarrier frequency of envelope and frequency of bitstream.
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*/
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#define PHHAL_HW_RC663_REG_TXDATACON 0x4A
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/** \brief Transmitter data modulation Register.
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*
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* Configure Frame step, miller coding, Pulse type, Inversion of envelop
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* of data and Envelop type
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*/
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#define PHHAL_HW_RC663_REG_TXDATAMOD 0x4B
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/** \brief Transmitter Symbol Frequency.
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*
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* Configure Frequency for Transmitter symbol
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*/
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#define PHHAL_HW_RC663_REG_TXSYMFREQ 0x4C
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/** \brief Transmitter Symbol 0 High Register.
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*
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* Contains value for Transmitter Symbol 0.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM0H 0x4D
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/** \brief Transmitter Symbol 0 Low Register.
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*
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* Contains value for Transmitter Symbol 0.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM0L 0x4E
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/** \brief Transmitter Symbol 1 High Register.
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*
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* Contains value for Transmitter Symbol 1.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM1H 0x4F
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/** \brief Transmitter Symbol 1 Low Register.
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*
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* Contains value for Transmitter Symbol 1.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM1L 0x50
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/** \brief Tx Symbol 2 Register.
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*
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* Contains Symbol definition for Symbol 2.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM2 0x51
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/** \brief Tx Symbol 3 Register.
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*
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* Contains Symbol definition for Symbol 3.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM3 0x52
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/** \brief Transmitter Symbol 0 + Symbol 1 Length Register.
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*
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* Contains Length of Transmitter Symbol 0 + Symbol 1.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM10LEN 0x53
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/** \brief Transmitter symbol 3 + symbol 2 length register.
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*
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* Contains No. of Valid bits in Tx Symbol 2 and Tx Symbol 3 registers.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM32LEN 0x54
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/** \brief Symbol 0 and 1 Register.
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*
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* Configure Burst-control of both symbols.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM10BURSTCTRL 0x55
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/** \brief Symbol 0 and 1 Register.
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*
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* Configure Modulation Register of both symbols.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM10MOD 0x56
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/** \brief Transmitter symbol 3 + symbol 2 modulation register.
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*
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* Configures Miller encoding, Pulse type and Envelope type.
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*/
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#define PHHAL_HW_RC663_REG_TXSYM32MOD 0x57
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/** \brief Receiver bit modulation register.
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*
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* Contains Receiver data configurations.
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|
*/
|
|
#define PHHAL_HW_RC663_REG_RXBITMOD 0x58
|
|
|
|
/** \brief Receiver end of frame symbol register.
|
|
*
|
|
* This Register defines the pattern of the EOF symbol.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXEOFSYM 0x59
|
|
|
|
/** \brief Receiver synchronisation value high register.
|
|
*
|
|
* Defines the high byte of the Start Of Frame (SOF) pattern, which must
|
|
* be in front of the receiving data.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXSYNCVAlH 0x5A
|
|
|
|
/** \brief Receiver synchronisation value low register.
|
|
*
|
|
* Defines the low byte of the Start Of Frame (SOF) Pattern, which must
|
|
* be in front of the receiving data.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXSYNCVAlL 0x5B
|
|
|
|
/** \brief Receiver synchronisation mode register.
|
|
*
|
|
* Contains Rx sync values.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXSYNCMOD 0x5C
|
|
|
|
/** \brief Receiver modulation register.
|
|
*
|
|
* Contains Reciever configuration registers.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXMOD 0x5D
|
|
|
|
/** \brief Receiver Correlation Register.
|
|
*
|
|
* Contains Correlation Frequency, Correlation Speed and Correlation Length.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXCORR 0x5E
|
|
|
|
/** \brief Calibration register of the receiver.
|
|
*
|
|
* Contains Fabrication calibration of the receiver.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_RXSVETTE 0x5F
|
|
|
|
/** \brief DAC value Register.
|
|
*
|
|
* Contains DAC Value.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_DACVAL 0x64
|
|
|
|
/** \brief Test mode Register.
|
|
*
|
|
* Contains Test Level enable and Test mode configuration.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_TESTMOD 0x66
|
|
|
|
/** \brief Analog Xtal register.
|
|
*
|
|
* Contains Xtal mode and Xtal bypassreg.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_ANAXTAL 0x71
|
|
|
|
/** \brief EPCv2 mode Register.
|
|
*
|
|
* Enables or Disables Testmode Rx and EPCv2 mode.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_SIGPROTEST 0x72
|
|
|
|
/** \brief Version Register.
|
|
*
|
|
* Contains IC Version and Subversion.
|
|
*/
|
|
#define PHHAL_HW_RC663_REG_VERSION 0x7F
|
|
|
|
/** \name Command Register Contents (0x00)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_STANDBY 0x80U /**< Standby bit; If set, the IC transits to standby mode. */
|
|
#define PHHAL_HW_RC663_CMD_IDLE 0x00U /**< No action; cancels current command execution. */
|
|
#define PHHAL_HW_RC663_CMD_LPCD 0x01U /**< Low Power Card Detection. */
|
|
#define PHHAL_HW_RC663_CMD_LOADKEY 0x02U /**< Reads a key from the FIFO buffer and puts it into the key buffer. */
|
|
#define PHHAL_HW_RC663_CMD_MFAUTHENT 0x03U /**< Performs the Mifare standard authentication (in Mifare Reader/Writer mode only). */
|
|
#define PHHAL_HW_RC663_CMD_ACKREQ 0x04U /**< Performs a Query, a Ack and a Req-Rn for EPC V2. */
|
|
#define PHHAL_HW_RC663_CMD_RECEIVE 0x05U /**< Activates the receiver circuitry. */
|
|
#define PHHAL_HW_RC663_CMD_TRANSMIT 0x06U /**< Transmits data from the FIFO buffer to Card. */
|
|
#define PHHAL_HW_RC663_CMD_TRANSCEIVE 0x07U /**< Like #PHHAL_HW_RC663_CMD_TRANSMIT but automatically activates the receiver after transmission is finished. */
|
|
#define PHHAL_HW_RC663_CMD_WRITEE2 0x08U /**< Gets one byte from FIFO buffer and writes it to the internal EEPROM. */
|
|
#define PHHAL_HW_RC663_CMD_WRITEE2PAGE 0x09U /**< Gets up to 64 Bytes from FIFO buffer and writes it to the EEPROM. */
|
|
#define PHHAL_HW_RC663_CMD_READE2 0x0AU /**< Reads data from EEPROM and puts it into the FIFO buffer. */
|
|
#define PHHAL_HW_RC663_CMD_LOADREG 0x0CU /**< Reads data from EEPROM and initializes the registers. */
|
|
#define PHHAL_HW_RC663_CMD_LOADPROTOCOL 0x0DU /**< Reads data from EEPROM and initializes the registers needed for a protocol change. */
|
|
#define PHHAL_HW_RC663_CMD_LOADKEYE2 0x0EU /**< Copies a Mifare key from the EEPROM into the key buffer. */
|
|
#define PHHAL_HW_RC663_CMD_STOREKEYE2 0x0FU /**< Stores a Mifare key into the EEPROM. */
|
|
#define PHHAL_HW_RC663_CMD_SOFTRESET 0x1FU /**< Resets the IC. */
|
|
#define PHHAL_HW_RC663_MASK_COMMAND 0x1FU /**< Mask for Command-bits. */
|
|
/*@}*/
|
|
|
|
/** \name Host-Control Register Contents (0x01)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_REGEN 0x80U
|
|
#define PHHAL_HW_RC663_BIT_BUSHOST 0x40U
|
|
#define PHHAL_HW_RC663_BIT_BUSSAM 0x20U
|
|
#define PHHAL_HW_RC663_MASK_SAMINTERFACE 0x0CU
|
|
/*@}*/
|
|
|
|
/** \name FIFO-Control Register Contents (0x02)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_FIFOSIZE 0x80U
|
|
#define PHHAL_HW_RC663_BIT_HIALERT 0x40U
|
|
#define PHHAL_HW_RC663_BIT_LOALERT 0x20U
|
|
#define PHHAL_HW_RC663_BIT_FLUSHFIFO 0x10U
|
|
#define PHHAL_HW_RC663_BIT_WATERLEVEL_HI 0x04U
|
|
#define PHHAL_HW_RC663_MASK_FIFOLENGTH_HI 0x03U
|
|
/*@}*/
|
|
|
|
/** \name IRQ0 Register(s) Contents (0x06/0x08)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_SET 0x80U
|
|
#define PHHAL_HW_RC663_BIT_IRQINV 0x80U
|
|
#define PHHAL_HW_RC663_BIT_HIALERTIRQ 0x40U
|
|
#define PHHAL_HW_RC663_BIT_LOALERTIRQ 0x20U
|
|
#define PHHAL_HW_RC663_BIT_IDLEIRQ 0x10U
|
|
#define PHHAL_HW_RC663_BIT_TXIRQ 0x08U
|
|
#define PHHAL_HW_RC663_BIT_RXIRQ 0x04U
|
|
#define PHHAL_HW_RC663_BIT_ERRIRQ 0x02U
|
|
#define PHHAL_HW_RC663_BIT_EMDIRQ 0x01U
|
|
/*@}*/
|
|
|
|
/** \name IRQ1 Register(s) Contents (0x07/0x09)
|
|
*/
|
|
/*@{*/
|
|
/* #define PHHAL_HW_RC663_BIT_SET 0x80U */
|
|
#define PHHAL_HW_RC663_BIT_IRQPUSHPULL 0x80U
|
|
#define PHHAL_HW_RC663_BIT_GLOBALIRQ 0x40U
|
|
#define PHHAL_HW_RC663_BIT_IRQPINEN 0x40U
|
|
#define PHHAL_HW_RC663_BIT_LPCDIRQ 0x20U
|
|
#define PHHAL_HW_RC663_BIT_TIMER4IRQ 0x10U
|
|
#define PHHAL_HW_RC663_BIT_TIMER3IRQ 0x08U
|
|
#define PHHAL_HW_RC663_BIT_TIMER2IRQ 0x04U
|
|
#define PHHAL_HW_RC663_BIT_TIMER1IRQ 0x02U
|
|
#define PHHAL_HW_RC663_BIT_TIMER0IRQ 0x01U
|
|
/*@}*/
|
|
|
|
/** \name Error Register Contents (0x0A)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_EE_ERR 0x80U
|
|
#define PHHAL_HW_RC663_BIT_FIFOWRERR 0x40U
|
|
#define PHHAL_HW_RC663_BIT_FIFOOVL 0x20U
|
|
#define PHHAL_HW_RC663_BIT_MINFRAMEERR 0x10U
|
|
#define PHHAL_HW_RC663_BIT_NODATAERR 0x08U
|
|
#define PHHAL_HW_RC663_BIT_COLLDET 0x04U
|
|
#define PHHAL_HW_RC663_BIT_PROTERR 0x02U
|
|
#define PHHAL_HW_RC663_BIT_INTEGERR 0x01U
|
|
/*@}*/
|
|
|
|
/** \name Status Register Contents (0x0B)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_CRYPTO1ON 0x20U
|
|
#define PHHAL_HW_RC663_MASK_COMMSTATE 0x07U
|
|
/*@}*/
|
|
|
|
/** \name Rx-Bit-Control Register Contents (0x0C)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_VALUESAFTERCOLL 0x80U
|
|
#define PHHAL_HW_RC663_BIT_NOCOLL 0x08U
|
|
#define PHHAL_HW_RC663_MASK_RXALIGN 0x70U
|
|
#define PHHAL_HW_RC663_MASK_RXLASTBITS 0x07U
|
|
/*@}*/
|
|
|
|
/** \name Rx-Coll Register Contents (0x0D)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_COLLPOSVALID 0x80U
|
|
#define PHHAL_HW_RC663_MASK_COLLPOS 0x7FU
|
|
/*@}*/
|
|
|
|
/** \name Timer-Control Register Contents (0x0E)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_T3RUNNING 0x80U
|
|
#define PHHAL_HW_RC663_BIT_T2RUNNING 0x40U
|
|
#define PHHAL_HW_RC663_BIT_T1RUNNING 0x20U
|
|
#define PHHAL_HW_RC663_BIT_T0RUNNING 0x10U
|
|
#define PHHAL_HW_RC663_BIT_T3STARTSTOPNOW 0x08U
|
|
#define PHHAL_HW_RC663_BIT_T2STARTSTOPNOW 0x04U
|
|
#define PHHAL_HW_RC663_BIT_T1STARTSTOPNOW 0x02U
|
|
#define PHHAL_HW_RC663_BIT_T0STARTSTOPNOW 0x01U
|
|
/*@}*/
|
|
|
|
/** \name T[0-3]-Control Register Contents (0x0F/0x14/0x19/0x1E)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_TSTOP_RX 0x80U /**< Stop timer on receive interrupt. */
|
|
#define PHHAL_HW_RC663_BIT_TAUTORESTARTED 0x08U /**< Auto-restart timer after underflow. */
|
|
#define PHHAL_HW_RC663_BIT_TSTART_TX 0x10U /**< Start timer on transmit interrupt. */
|
|
#define PHHAL_HW_RC663_BIT_TSTART_LFO 0x20U /**< Use this timer for LFO trimming. */
|
|
#define PHHAL_HW_RC663_BIT_TSTART_LFO_UV 0x30U /**< Use this timer for LFO trimming (generate UV at a trimming event). */
|
|
#define PHHAL_HW_RC663_MASK_TSTART 0x30U /**< Mask for TSTART bits. */
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_1356_MHZ 0x00U /**< Use 13.56MHz as input clock. */
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_212_KHZ 0x01U /**< Use 212KHz as input clock. */
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_T0 0x02U /**< Use timer0 as input clock. */
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_T1 0x03U /**< Use timer1 as input clock. */
|
|
/*@}*/
|
|
|
|
/** \name T4-Control Register Contents (0x23)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_T4RUNNING 0x80U
|
|
#define PHHAL_HW_RC663_BIT_T4STARTSTOPNOW 0x40U
|
|
#define PHHAL_HW_RC663_BIT_T4AUTOTRIMM 0x20U
|
|
#define PHHAL_HW_RC663_BIT_T4AUTOLPCD 0x10U
|
|
#define PHHAL_HW_RC663_BIT_T4AUTORESTARTED 0x08U
|
|
#define PHHAL_HW_RC663_BIT_T4AUTOWAKEUP 0x04U
|
|
/*#define PHHAL_HW_RC663_MASK_TSTART 0x30U*/
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_LFO_64_KHZ 0x00U
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_LFO_8_KHZ 0x01U
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_LFO_4_KHZ 0x02U
|
|
#define PHHAL_HW_RC663_VALUE_TCLK_LFO_2_KHZ 0x03U
|
|
/*@}*/
|
|
|
|
/** \name Driver Mode Register Contents (0x28)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_TX2INV 0x80U
|
|
#define PHHAL_HW_RC663_BIT_TX1INV 0x40U
|
|
#define PHHAL_HW_RC663_BIT_TXEN 0x08U
|
|
#define PHHAL_HW_RC663_BIT_RFON 0x04U
|
|
#define PHHAL_HW_RC663_BIT_TPUSHON 0x02U
|
|
#define PHHAL_HW_RC663_BIT_TPULLON 0x01U
|
|
/*@}*/
|
|
|
|
/** \name Tx Amplifier Register Contents (0x29)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_MASK_CW_AMPLITUDE 0xC0U
|
|
#define PHHAL_HW_RC663_MASK_RESIDUAL_CARRIER 0x1FU
|
|
/*@}*/
|
|
|
|
/** \name Driver Control Register Contents (0x2A)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_CWMAX 0x10U
|
|
#define PHHAL_HW_RC663_BIT_DISOVSHTPREV 0x08U
|
|
#define PHHAL_HW_RC663_BIT_DRIVERINV 0x04U
|
|
#define PHHAL_HW_RC663_VALUE_DRIVERSEL_LOW 0x00U
|
|
#define PHHAL_HW_RC663_VALUE_DRIVERSEL_TXENV 0x01U
|
|
#define PHHAL_HW_RC663_VALUE_DRIVERSEL_SIGIN 0x02U
|
|
/*@}*/
|
|
|
|
/** \name Tx-/Rx-CRC Control Register Contents (0x2C/0x2D)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RXFORCECRCWRITE 0x80U
|
|
#define PHHAL_HW_RC663_BIT_CRCINVERT 0x02U
|
|
#define PHHAL_HW_RC663_BIT_CRCEN 0x01U
|
|
#define PHHAL_HW_RC663_MASK_CRCPRESETVAL 0x70U
|
|
#define PHHAL_HW_RC663_MASK_CRCTYPE 0x0CU
|
|
#define PHHAL_HW_RC663_MASK_CRCTYPE5 0x00U
|
|
#define PHHAL_HW_RC663_MASK_CRCTYPE16 0x08U
|
|
/*@}*/
|
|
|
|
/** \name Tx-DataNum Register Contents (0x2E)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_KEEPBITGRID 0x10U
|
|
#define PHHAL_HW_RC663_BIT_DATAEN 0x08U
|
|
#define PHHAL_HW_RC663_MASK_TXLASTBITS 0x07U
|
|
#define PHHAL_HW_RC663_MASK_SYMBOL_SEND 0x08U
|
|
/*@}*/
|
|
|
|
/** \name Tx-Wait Control Register Contents (0x31)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_TXWAIT_START_RX 0x80U
|
|
#define PHHAL_HW_RC663_BIT_TXWAIT_DBFREQ 0x40U
|
|
#define PHHAL_HW_RC663_MASK_TXWAITHI 0x38U
|
|
#define PHHAL_HW_RC663_MASK_TXSTOPBITLEN 0x07U
|
|
/*@}*/
|
|
|
|
/** \name Frame Control Register Contents (0x33)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_TXPARITYEN 0x80U
|
|
#define PHHAL_HW_RC663_BIT_RXPARITYEN 0x40U
|
|
#define PHHAL_HW_RC663_VALUE_STOP_SYM3 0x0CU
|
|
#define PHHAL_HW_RC663_VALUE_STOP_SYM2 0x08U
|
|
#define PHHAL_HW_RC663_VALUE_STOP_SYM1 0x04U
|
|
#define PHHAL_HW_RC663_VALUE_START_SYM2 0x03U
|
|
#define PHHAL_HW_RC663_VALUE_START_SYM1 0x02U
|
|
#define PHHAL_HW_RC663_VALUE_START_SYM0 0x01U
|
|
#define PHHAL_HW_RC663_MASK_STARTSYM 0x03U
|
|
#define PHHAL_HW_RC663_MASK_STOPSYM 0x0CU
|
|
/*@}*/
|
|
|
|
/** \name Rx Control Register Contents (0x35)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RXALLOWBITS 0x80U
|
|
#define PHHAL_HW_RC663_BIT_RXMULTIPLE 0x40U
|
|
#define PHHAL_HW_RC663_BIT_RXEOFTYPE 0x20U
|
|
#define PHHAL_HW_RC663_BIT_EGT_CHECK 0x10U
|
|
#define PHHAL_HW_RC663_BIT_EMD_SUPPRESSION 0x08U
|
|
#define PHHAL_HW_RC663_MASK_RXBAUDRATE 0x07U
|
|
/*@}*/
|
|
|
|
/** \name Rx-Wait Register Contents (0x36)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RXWAITDBFREQ 0x80U
|
|
#define PHHAL_HW_RC663_MASK_RXWAIT 0x7FU
|
|
/*@}*/
|
|
|
|
/** \name Rx-Threshold Register Contents (0x37)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_MASK_MINLEVEL 0xF0U
|
|
#define PHHAL_HW_RC663_MASK_MINLEVELP 0x0FU
|
|
/*@}*/
|
|
|
|
/** \name Rx-Receiver Register Contents (0x38)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RX_SINGLE 0x80U
|
|
#define PHHAL_HW_RC663_BIT_RX_SHORT_MIX2ADC 0x40U
|
|
#define PHHAL_HW_RC663_BIT_USE_SMALL_EVAL 0x04U
|
|
#define PHHAL_HW_RC663_MASK_RX_SIGPRO_IN_SEL 0x30U
|
|
#define PHHAL_HW_RC663_MASK_COLLLEVEL 0x03U
|
|
/*@}*/
|
|
|
|
/** \name Rx-Analog Register Contents (0x39)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RX_OC_ENABLE 0x20U
|
|
#define PHHAL_HW_RC663_BIT_RX_HP_LOWF 0x10U
|
|
#define PHHAL_HW_RC663_MASK_VMID_R_SEL 0xC0U
|
|
#define PHHAL_HW_RC663_MASK_RCV_HPCF 0x0CU
|
|
#define PHHAL_HW_RC663_MASK_RCV_GAIN 0x03U
|
|
/*@}*/
|
|
|
|
/** \name Serial-Speed Register Contents (0x3B)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_MASK_BR_T0 0xE0U
|
|
#define PHHAL_HW_RC663_MASK_BR_T1 0x1FU
|
|
/*@}*/
|
|
|
|
|
|
/** \name LPCD Result(Q) Register Contents (0x43)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_LPCDIRQ_CLR 0x40U
|
|
/*@}*/
|
|
|
|
/** \name Tx-BitMod Register Contents (0x48)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_TXMSBFIRST 0x80U
|
|
#define PHHAL_HW_RC663_BIT_TXPARITYTYPE 0x20U
|
|
#define PHHAL_HW_RC663_BIT_TXSTOPBITTYPE 0x08U
|
|
#define PHHAL_HW_RC663_BIT_TXSTARTBITTYPE 0x02U
|
|
#define PHHAL_HW_RC663_BIT_TXSTARTBITEN 0x01U
|
|
/*@}*/
|
|
|
|
/** \name Rx-BitMod Register Contents (0x58)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_RXSTOPONINVPAR 0x20U
|
|
#define PHHAL_HW_RC663_BIT_RXSTOPONLEN 0x10U
|
|
#define PHHAL_HW_RC663_BIT_RXMSBFIRST 0x08U
|
|
#define PHHAL_HW_RC663_BIT_RXSTOPBITEN 0x04U
|
|
#define PHHAL_HW_RC663_BIT_RXPARITYTYPE 0x02U
|
|
/*@}*/
|
|
|
|
/** \name Rx-Mod Register Contents (0x5D)
|
|
*/
|
|
/*@{*/
|
|
#define PHHAL_HW_RC663_BIT_PREFILTER 0x20U
|
|
#define PHHAL_HW_RC663_BIT_RECTFILTER 0x10U
|
|
#define PHHAL_HW_RC663_BIT_SYNCHIGH 0x08U
|
|
#define PHHAL_HW_RC663_BIT_CORRINV 0x04U
|
|
#define PHHAL_HW_RC663_BIT_FSK 0x02U
|
|
#define PHHAL_HW_RC663_BIT_BPSK 0x01U
|
|
/*@}*/
|
|
|
|
/**
|
|
* \brief Write to 8bit address of CL front-end register.
|
|
*
|
|
* \return Status code
|
|
* \retval #PH_ERR_SUCCESS Operation successful.
|
|
* \retval #PH_ERR_INTERFACE_ERROR Hardware problem
|
|
*/
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phStatus_t phhalHw_Rc663_WriteRegister(
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|
phhalHw_Rc663_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
|
uint8_t bAddress, /**< [In] Register Address. */
|
|
uint8_t bValue /**< [In] Register Value. */
|
|
);
|
|
|
|
/**
|
|
* \brief Read 8bit register address from CL front-ends.
|
|
*
|
|
* \return Status code
|
|
* \retval #PH_ERR_SUCCESS Operation successful.
|
|
* \retval #PH_ERR_INTERFACE_ERROR Hardware problem
|
|
*/
|
|
phStatus_t phhalHw_Rc663_ReadRegister(
|
|
phhalHw_Rc663_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
|
uint8_t bAddress, /**< [In] Register Address. */
|
|
uint8_t * pValue /**< [Out] Register Value. */
|
|
);
|
|
|
|
/** @}
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|
* end of phhalHw_Rc663_Reg group
|
|
*/
|
|
#endif /* NXPBUILD__PHHAL_HW_RC663 */
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|
|
|
#ifdef __cplusplus
|
|
} /* Extern C */
|
|
#endif
|
|
|
|
#endif /* PHHALHW_RC663_REG_H */
|