313 lines
11 KiB
C
313 lines
11 KiB
C
/*
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* Copyright (c), NXP Semiconductors Gratkorn / Austria
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*
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* (C)NXP Semiconductors
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* All rights are reserved. Reproduction in whole or in part is
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* prohibited without the written consent of the copyright owner.
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* NXP reserves the right to make changes without notice at any time.
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* NXP makes no warranty, expressed, implied or statutory, including but
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* not limited to any implied warranty of merchantability or fitness for any
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* particular purpose, or that the use will not infringe any third party patent,
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* copyright or trademark. NXP must not be liable for any loss or damage
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* arising from its use.
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*/
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/** \file
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* Build System Definitions for Reader Library Framework.
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* $Author: Purnank G (ing05193) $
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* $Revision: 5919 $ (v4.040.05.011646)
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* $Date: 2016-09-15 12:13:49 +0530 (Thu, 15 Sep 2016) $
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*
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* History:
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* MK: Generated 15. October 2009
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*
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*/
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#ifndef PH_NXPBUILD_PC_H
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#define PH_NXPBUILD_PC_H
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#ifdef _WIN32 /* For compilation on PC */
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/** \defgroup ph_NxpBuild NXP Build
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* \brief Controls build behaviour of components.
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* @{
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*/
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/* NXPBUILD_DELETE: included code lines should be always removed from code */
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/* NXP Build defines */
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/* use #define to include components */
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/* comment out #define to exclude components */
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/* DEBUG build mode */
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#define NXPBUILD__PH_DEBUG /**< DEBUG build definition */
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/* BAL components */
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/*#define NXPBUILD__PHBAL_REG_STUB*/ /**< Stub BAL definition */
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#define NXPBUILD__PHBAL_REG_SERIALWIN /**< SerialWin BAL definition */
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#define NXPBUILD__PHBAL_REG_ABEND /**< PN5180 via ABEND */
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#define NXPBUILD__PHBAL_REG_PCSCWIN /**< PcscWin BAL definition */
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#define NXPBUILD__PHBAL_REG_RD70XUSBWIN /**< Rd70X_UsbWin BAL definition */
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#define NXPBUILD__PHBAL_REG_SOCKETWIN
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/* Commenting as this BAL would be available only for LPC platform */
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/*#define NXPBUILD__PHBAL_REG_LPCOPEN_SPI*/ /**< Lpc17xx BAL definition */
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/*#define NXPBUILD__PHBAL_REG_LPCOPEN_I2C*/
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/* HAL components */
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//#define NXPBUILD__PHHAL_HW_RC523 /**< Rc523 HAL definition */
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//#define NXPBUILD__PHHAL_HW_RD70X /**< Rd70X HAL definition */
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//#define NXPBUILD__PHHAL_HW_RC632 /**< Rc632 HAL definition */
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#define NXPBUILD__PHHAL_HW_PN5180 /**< PN5180 HAL definition */
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#define NXPBUILD__PHHAL_HW_CALLBACK /**< Callback HAL definition */
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//#define NXPBUILD__PHHAL_HW_RC663 /**< Rc663 HAL definition */
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//#define NXPBUILD__PHHAL_HW_RD710 /**< Rd710 HAL definition */
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//#define NXPBUILD__PHHAL_HW_UHOST /**< UHOST HAL. */
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#define NXPBUILD__PHHAL_HW_DUT /**< DUT HAL. */
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//#define NXPBUILD__PHHAL_HW_MFCCRYPTO /**Pallavi: < MfcCrypto HAL. */
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//#define NXPBUILD__PHHAL_HW_SAMAV2
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/* PAL ISO 14443-3A components */
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#define NXPBUILD__PHPAL_I14443P3A_SW /**< Software PAL ISO 14443-3A definition */
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//#define NXPBUILD__PHPAL_I14443P3A_RD70X /**< Rd70X PAL ISO 14443-3A definition */
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//#define NXPBUILD__PHPAL_I14443P3A_RD710 /**< Rd710 PAL ISO 14443-3A definition */
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//#define NXPBUILD__PHPAL_I14443P3A_DUT
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/* PAL ISO 14443-3B components */
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#define NXPBUILD__PHPAL_I14443P3B_SW /**< Software PAL ISO 14443-3B definition */
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//#define NXPBUILD__PHPAL_I14443P3B_DUT /**< Rd710 PAL ISO 14443-3B definition */
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//
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//
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///* PAL ISO 14443-4A components */
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//
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#define NXPBUILD__PHPAL_I14443P4A_SW /**< Software PAL ISO 14443-4A definition */
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//#define NXPBUILD__PHPAL_I14443P4A_RD710 /**< Rd710 PAL ISO 14443-4A definition */
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//#define NXPBUILD__PHPAL_I14443P4A_DUT /**< DUT PAL ISO 14443-4A definition */
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//
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///* PAL ISO 14443-4 components */
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//
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#define NXPBUILD__PHPAL_I14443P4_SW /**< Software PAL ISO 14443-4 definition */
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//#define NXPBUILD__PHPAL_I14443P4_RD710 /**< Rd710 PAL ISO 14443-4 definition */
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//#define NXPBUILD__PHPAL_I14443P4_DUT
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//
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//
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///* PAL ISO 18092 Target component */
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//#define NXPBUILD__PHPAL_I14443P4MC_SW /**< Software implementation of ISO 18092 target mode */
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/* PAL MIFARE components */
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//#define NXPBUILD__PHPAL_MIFARE_STUB /**< Stub PAL MIFARE */
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#define NXPBUILD__PHPAL_MIFARE_SW /**< Software PAL MIFARE */
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//#define NXPBUILD__PHPAL_MIFARE_RD710 /**< Rd710 PAL MIFARE */
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//#define NXPBUILD__PHPAL_MIFARE_DUT /**< DUT PAL MIFARE */
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//#define NXPBUILD__PHPAL_MIFARE_SAMAV2_X /**< SAMAV2 */
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/* PAL ISO15693 ICode SLI components */
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#define NXPBUILD__PHPAL_SLI15693_SW /**< Software PAL Sli 15693 */
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//#define NXPBUILD__PHPAL_SLI15693_DUT
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//
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//
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///* PAL Felica components */
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//
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#define NXPBUILD__PHPAL_FELICA_SW /**< Software PAL Felica */
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///*#define NXPBUILD__PHPAL_FELICA_DUT */ /**< DUT PAL Felica */
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//
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///* PAL ICode EPC/UID components */
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//
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#define NXPBUILD__PHPAL_EPCUID_SW /**< Software ICode EPC/UID */
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/* PAL I18000p3m3 components */
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#define NXPBUILD__PHPAL_I18000P3M3_SW /**< Software I18000p3m3 */
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//#define NXPBUILD__PHPAL_I18000P3M3_DUT /**< DUT PAL ISO 18000-3M3 definition */
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//
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//
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///* PAL ISO 18092 components */
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//
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#define NXPBUILD__PHPAL_I18092MPI_SW /**< Software PAL ISO 18092 definition */
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//#define NXPBUILD__PHPAL_I18092MPI_DUT /**< DUT PAL ISO 18092 definition */
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//
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//
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///* PAL ISO 18092 Target component */
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//#define NXPBUILD__PHPAL_I18092MT_SW /**< Software implementation of ISO 18092 target mode */
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/* AC dicover loop component */
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//#define NXPBUILD__PHAC_DISCLOOP_TARGET
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//
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//#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery loop software componenet */
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//
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< Detect type A I3p3 cards */
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< Detect type A jewel cards */
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< Detect type A I3p4 cards */
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< Detect type A P2P tags */
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//
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//
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS /**< Detect Type F tags */
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//
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< Detect Type F P2P tags */
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//
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//
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< Detect TypeB, I3P3B tags */
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< Detect TypeB, I3P4B tags */
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEB_BPRIME_TAGS /**< Detect TypeB, B Prime tags */
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//
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//#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< Detect TypeV Tags */
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//
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//#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< Detect 18000p3m3 Tags */
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///* OSAL components */
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#define NXPBUILD__PH_OSAL_WINOS /**< Software OSAL for WinOs */
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//
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///* AL Felica components */
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#define NXPBUILD__PHAL_FELICA_SW /**< Software AL Felica */
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//
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///* AL MIFARE Classic components */
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//
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#define NXPBUILD__PHAL_MFC_SW /**< Software MIFARE Classic */
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//
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//
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///* AL MIFARE Plus components */
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//
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#define NXPBUILD__PHAL_MFP_SW /**< Software MIFARE Plus */
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//#define NXPBUILD__PHAL_MFP_SAMAV2_X
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//#define NXPBUILD__PHAL_MFP_SAMAV2
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//
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//
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#define NXPBUILD__PHAL_MFDF_SW /**< Software MIFARE DESFire */
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//
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//#define NXPBUILD__PHAL_MFDFEV2_SW /**< Software MIFARE DESFire EV2 */
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/* AL MIFARE Ultralight components */
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#define NXPBUILD__PHAL_MFUL_SW /**< Software MIFARE Ultralight */
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//
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///* AL T1T components */
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//
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#define NXPBUILD__PHAL_T1T_SW /**< Software Type 1 Tag */
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//
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///* AL TOP components */
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//
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#define NXPBUILD__PHAL_TOP_SW /**< Software Tag OPerations */
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//
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//
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///* AL Virtual Card Architecture components */
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//
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#define NXPBUILD__PHAL_VCA_SW /**< Software Virtual Card Architecture */
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/* DL FPGA Box components */
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/* #define NXPBUILD__PHDL_RDFPGA_V6 */ /**< FPGA Box measurement reader */
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/* DL Amplifier components */
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/*#define NXPBUILD__PHDL_AMP_AR75A250 **< AR75A250 Amplifier */
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/* DL Thermostream components */
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/*#define NXPBUILD__PHDL_THSTRM_TP04030 **< TP04030 Thermostream */
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/* DL Oscilloscope components */
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/* DL Master Amplifier Oscilloscope components */
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/*#define NXPBUILD__PHDL_MSTAMPOSC_AR75A250 **< Software Master Amplifier Oscilloscope */
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/*#define NXPBUILD__PHDL_MSTAMPOSC_ISOSETUP **< ISO Setup Master Amplifier Oscilloscope */
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/* DL Stepper components */
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/*#define NXPBUILD__PHDL_STEPPER_V1 **< V1 Stepper */
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/* AL I15693 components */
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#define NXPBUILD__PHAL_I15693_SW /**< Software AL I15693 */
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//
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///* AL Sli components */
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//
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#define NXPBUILD__PHAL_SLI_SW /**< Software AL Sli */
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//
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//
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///* AL ISO 18000P3M3 components */
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//
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#define NXPBUILD__PHAL_I18000P3M3_SW /**< Software AL I18000p3m3 */
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//
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//
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///* AL P40 PrivateCommands components */
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//#define NXPBUILD__PHAL_P40CMDPRIV_SW /**< Software AL P40 PrivateCommands*/
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//
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///* AL P40 PublicCommand components */
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//#define NXPBUILD__PHAL_P40CMDPUB_SW /**< Software AL P40 PublicCommand*/
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//
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//
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///* CE T4AT Card Emulation components */
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//#define NXPBUILD__PHCE_T4T_SW /**< Software Tag OPerations */
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//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< Proprietary file support */
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//
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//
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///* CID Manager components */
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//
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#define NXPBUILD__PH_CIDMANAGER_SW /**< Software CID Manager */
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//#define NXPBUILD__PH_CIDMANAGER_RD710 /**< Rd710 CID Manager */
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/* Crypto components */
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#define NXPBUILD__PH_NDA_MFDF /**< Mifare DESFire implementation under NDA */
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#define NXPBUILD__PH_CRYPTOSYM_SW /**< Software Crypto Sym */
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//#define NXPBUILD__PH_CRYPTOSYM_STUB /**< Stub Crypto Sym */
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//
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//
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///* CryptoRng components */
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//
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#define NXPBUILD__PH_CRYPTORNG_SW /**< Software CryptoRng */
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//#define NXPBUILD__PH_CRYPTORNG_STUB /**< Stub CryptoRng */
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/* KeyStore components */
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#define NXPBUILD__PH_KEYSTORE_SW /**< Software KeyStore */
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//#define NXPBUILD__PH_KEYSTORE_RC632 /**< RC632 KeyStore */
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//#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore */
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//#define NXPBUILD__PH_KEYSTORE_RD710 /**< Rd710 KeyStore */
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//
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///* LN components */
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//
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///* #define NXPBUILD__PHLN_LLCP_FRI */ /**< Software Link layer */
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//
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///* SNEP components */
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//
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///* #define NXPBUILD__PHNP_SNEP_FRI */ /**< SNEP FRI definition */
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//
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//
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///* TMIUtils component */
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//#define NXPBUILD__PH_TMIUTILS
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///* Log component */
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//
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#define NXPBUILD__PH_LOG
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/* Enable/disable Debugging */
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/*#define NXPBUILD__PH_DEBUG*/
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/** @}
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* end of ph_NxpBuild
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*/
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#endif /* _WIN32 */
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#endif /* PH_NXPBUILD_PC_H */
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