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Updated FDMA structs.

This commit is contained in:
imi415 2022-08-14 12:47:48 +08:00
parent d82bb3fb7e
commit 029f336438
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
5 changed files with 207 additions and 53 deletions
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86
include/stx7105.h
View File

@ -129,7 +129,7 @@ typedef struct {
__IO uint32_t BDMRB; /* Offset: 0x2001C, Break data mask register B */
__IO uint16_t BRCR; /* Offset: 0x20020, Break control register */
uint8_t UNUSED9[2]; /* Offset: 0x20022 */
} CSR_TypeDef;
} CSP_TypeDef;
/* drivers/stm/stx7105.c */
typedef struct {
@ -154,39 +154,67 @@ typedef struct {
__IO uint8_t SLIM_IMEM[16384]; /* Offset: 0xC000, SLIM CPU instruction memory */
} FDMA_TypeDef;
#define PIO0_BASE (0xFD020000U)
#define PIO1_BASE (0xFD021000U)
#define PIO2_BASE (0xFD022000U)
#define PIO3_BASE (0xFD023000U)
#define PIO4_BASE (0xFD024000U)
#define PIO5_BASE (0xFD025000U)
#define PIO6_BASE (0xFD026000U)
#define ASC0_BASE (0xFD030000U)
#define ASC1_BASE (0xFD031000U)
#define ASC2_BASE (0xFD032000U)
#define ASC3_BASE (0xFD033000U)
/* WARNING: THE CLKGENA is different from other ST40s' */
typedef struct {
__IO uint32_t PLL0_CFG; /* Offset: 0x0000 */
__IO uint32_t PLL1_CFG; /* Offset: 0x0004 */
uint32_t UNUSED0[2]; /* Offset: 0x0008 */
__IO uint32_t POWER_CFG; /* Offset: 0x0010 */
__IO uint32_t CLKOPSRC_SWITCH_CFG; /* Offset: 0x0014 */
uint32_t UNUSED1[4]; /* Offset: 0x0018 */
__IO uint32_t CLKOPSRC_SWITCH_CFG2; /* Offset: 0x0024 */
uint32_t UNUSED2[2]; /* Offset: 0x0028 */
__IO uint32_t CLKOBS_MUX1_CFG; /* Offset: 0x0030 */
__IO uint32_t CLKOBS_MASTER_MAXCOUNT; /* Offset: 0x0034 */
__IO uint32_t CLKOBS_CMD; /* Offset: 0x0038 */
__IO uint32_t CLKOBS_STATUS; /* Offset: 0x003C */
__IO uint32_t CLKOBS_SLAVE0_COUNT; /* Offset: 0x0040 */
__IO uint32_t OSCMUX_DEBUG; /* Offset: 0x0044 */
__IO uint32_t CLKOBS_MUX2_CFG; /* Offset: 0x0048 */
__IO uint32_t LOW_POWER_CTRL; /* Offset: 0x004C */
} CKGA_TypeDef;
#define PIO0_BASE (0xFD020000U)
#define PIO1_BASE (0xFD021000U)
#define PIO2_BASE (0xFD022000U)
#define PIO3_BASE (0xFD023000U)
#define PIO4_BASE (0xFD024000U)
#define PIO5_BASE (0xFD025000U)
#define PIO6_BASE (0xFD026000U)
#define ASC0_BASE (0xFD030000U)
#define ASC1_BASE (0xFD031000U)
#define ASC2_BASE (0xFD032000U)
#define ASC3_BASE (0xFD033000U)
#define CKGA_BASE (0xFE213000U)
#define FDMA0_BASE (0xFE220000U)
#define FDMA1_BASE (0xFE410000U)
#define CSR_BASE (0xFF000000U)
#define INTC_BASE (0xFFD00000U)
#define TMU_BASE (0xFFD80000U)
#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
#define CSR ((CSR_TypeDef *)CSR_BASE)
#define CSP_BASE (0xFF000000U)
#define INTC_BASE (0xFFD00000U)
#define TMU_BASE (0xFFD80000U)
#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
#define CKGA ((CKGA_TypeDef *)CKGA_BASE)
#define FDMA0 ((FDMA_TypeDef *)FDMA0_BASE)
#define FDMA1 ((FDMA_TypeDef *)FDMA1_BASE)
#define INTC ((INTC_TypeDef *)INTC_BASE)
#define TMU ((TMU_TypeDef *)TMU_BASE)
#define CSP ((CSP_TypeDef *)CSP_BASE)
#define INTC ((INTC_TypeDef *)INTC_BASE)
#define TMU ((TMU_TypeDef *)TMU_BASE)
#define TMU_TSTR_STR0_Pos 0
#define TMU_TSTR_STR0_Msk (1U << TMU_TSTR_STR0_Pos)

66
include/stx7105_fdma.h Normal file
View File

@ -0,0 +1,66 @@
#ifndef STX7105_FDMA_H
#define STX7105_FDMA_H
#include "stx7105.h"
typedef enum {
FDMA_CMD_START_CHANNEL = 1U,
FDMA_CMD_PAUSE_CHANNEL = 2U,
FDMA_CMD_FLUSH_CHANNEL = 3U,
} FDMA_Command_TypeDef;
typedef enum {
FDMA_STAT_CHANNEL_IDLE = 0U,
FDMA_STAT_CHANNEL_RUNNING = 2U,
FDMA_STAT_CHANNEL_PAUSED = 3U,
} FDMA_Status_TypeDef;
typedef enum {
FDMA_REQ_CTL_OP_LDST1 = 0U,
FDMA_REQ_CTL_OP_LDST2 = 1U,
FDMA_REQ_CTL_OP_LDST4 = 2U,
FDMA_REQ_CTL_OP_LDST8 = 3U,
FDMA_REQ_CTL_OP_LDST16 = 4U,
FDMA_REQ_CTL_OP_LDST32 = 5U,
} FDMA_ReqCtl_Opcode_TypeDef;
typedef struct {
__IO uint32_t PTRN; /* Offset: 0x0000 */
uint32_t UNUSED2; /* Offset: 0x0004 */
__IO uint32_t CNTN; /* Offset: 0x0008 */
__IO uint32_t SADDRN; /* Offset: 0x000C */
__IO uint32_t DADDRN; /* Offset: 0x0010 */
} FDMA_FwRegs_Channel_TypeDef;
/* Firmware regs, implemented on the base of DMEM */
typedef struct {
__IO uint32_t REVID; /* Offset: 0x8000 */
uint32_t UNUSED0[1103]; /* Offset: 0x8004 */
__IO uint32_t CMD_STATN[16]; /* Offset: 0x9140 */
__IO uint32_t REQ_CTLN[16]; /* Offset: 0x9180 */
uint32_t UNUSED1[240]; /* Offset: 0x91C0 */
FDMA_FwRegs_Channel_TypeDef CHANNELN[16]; /* Offset: 0x9580 */
} FDMA_FWRegs_TypeDef;
#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_Pos 0U
#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_
#define FDMA_FwRegs_REQ_CTLN_OPCODE_Pos 4U
#define FDMA_FwRegs_REQ_CTLN_OPCODE_Msk (0x0FU << FDMA_FwRegs_REQ_CTLN_OPCODE_Pos)
#define FDMA_FwRegs_REQ_CTLN_WNR_Pos 14U
#define FDMA_FwRegs_REQ_CTLN_WNR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
#define FDMA_FwRegs_REQ_CTLN_DATA_SWAP_Pos 17U
#define FDMA_FwRegs_REQ_CTLN_DATA_SWAP_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
#define FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos 21U
#define FDMA_FwRegs_REQ_CTLN_INC_ADDR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
#define FDMA_FwRegs_REQ_CTLN_INITIATOR_Pos 22U
#define FDMA_FwRegs_REQ_CTLN_INITIATOR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INITIATOR_Pos)
#define FDMA_FwRegs_REQ_CTLN_NUM_OPS_Pos 24U
#define FDMA_FwRegs_REQ_CTLN_NUM_OPS_Msk (0xFFU << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
#endif

68
src/main.c
View File

@ -3,6 +3,7 @@
#include <string.h>
#include "stx7105.h"
#include "stx7105_fdma.h"
#include "stx7105_fdma_fw.h"
#include "stx7105_utils.h"
@ -20,6 +21,10 @@
#define MEMTEST_START 0x82000000
#define MEMTEST_END 0x8F000000
#define DMA_BUFFER_SIZE 1024
uint8_t src_buffer[DMA_BUFFER_SIZE];
uint8_t dst_buffer[DMA_BUFFER_SIZE];
void uart_init(void) {
PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
PIO4->SET_PC1 = 1U;
@ -35,25 +40,15 @@ void uart_init(void) {
CONSOLE_ASC->CTRL = 0x1589UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */
}
int main(void) {
init_led(LED_RED_GPIO, LED_RED_PIN, 0U);
init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U);
setbuf(stdout, NULL);
setbuf(stderr, NULL);
uart_init();
printf("Hello world\r\n");
static void configure_fdma0(void) {
FDMA0->SLIM_CLK_GATE |= (FDMA_SLIM_CLK_GATE_DIS_Msk | FDMA_SLIM_CLK_GATE_RESET_Msk);
FDMA0->PERIPH_STBUS_SYNC |= FDMA_PERIPH_STBUS_SYNC_DIS_Msk;
for(uint32_t i = 0; i < stx7105_fdma0_fw.text_size; i++) {
for (uint32_t i = 0; i < stx7105_fdma0_fw.text_size; i++) {
FDMA0->SLIM_IMEM[i] = stx7105_fdma0_fw.text[i];
}
for(uint32_t i = 0; i < stx7105_fdma0_fw.data_size; i++) {
for (uint32_t i = 0; i < stx7105_fdma0_fw.data_size; i++) {
FDMA0->SLIM_DMEM[i] = stx7105_fdma0_fw.data[i];
}
@ -65,6 +60,53 @@ int main(void) {
printf("FDMA0 SLIM ID: 0x%08lx\r\n", FDMA0->SLIM_ID);
printf("FDMA0 SLIM Version: 0x%08lx\r\n", FDMA0->SLIM_VER);
}
static void configure_fdma1(void) {
FDMA1->SLIM_CLK_GATE |= (FDMA_SLIM_CLK_GATE_DIS_Msk | FDMA_SLIM_CLK_GATE_RESET_Msk);
FDMA1->PERIPH_STBUS_SYNC |= FDMA_PERIPH_STBUS_SYNC_DIS_Msk;
for (uint32_t i = 0; i < stx7105_fdma1_fw.text_size; i++) {
FDMA1->SLIM_IMEM[i] = stx7105_fdma1_fw.text[i];
}
for (uint32_t i = 0; i < stx7105_fdma1_fw.data_size; i++) {
FDMA1->SLIM_DMEM[i] = stx7105_fdma1_fw.data[i];
}
FDMA1->SLIM_CLK_GATE &= ~FDMA_SLIM_CLK_GATE_DIS_Msk;
FDMA1->PERIPH_INT_CLR = 0xFFFFFFFFU;
FDMA1->PERIPH_CMD_CLR = 0xFFFFFFFFU;
FDMA1->SLIM_EN |= FDMA_SLIM_EN_RUN_Msk;
printf("FDMA1 SLIM ID: 0x%08lx\r\n", FDMA1->SLIM_ID);
printf("FDMA1 SLIM Version: 0x%08lx\r\n", FDMA1->SLIM_VER);
}
int main(void) {
init_led(LED_RED_GPIO, LED_RED_PIN, 0U);
init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U);
setbuf(stdout, NULL);
setbuf(stderr, NULL);
uart_init();
printf("Hello world\r\n");
printf("CKGA Opts 1: 0x%08lx\r\n", CKGA->CLKOPSRC_SWITCH_CFG);
printf("CKGA Opts 2: 0x%08lx\r\n", CKGA->CLKOPSRC_SWITCH_CFG2);
configure_fdma0();
configure_fdma1();
FDMA_FWRegs_TypeDef *fdma0_fwregs = (FDMA_FWRegs_TypeDef *)(FDMA0->SLIM_DMEM);
fdma0_fwregs->CHANNELN[0].CNTN = DMA_BUFFER_SIZE;
fdma0_fwregs->CHANNELN[0].SADDRN = src_buffer;
fdma0_fwregs->CHANNELN[0].DADDRN = dst_buffer;
fdma0_fwregs->REQ_CTLN[0] =
delay_ms(5000);

33
src/stx7105_exc.c
View File

@ -9,28 +9,39 @@ typedef enum {
} expevt_type_t;
typedef enum {
INT_TYPE_TMU_TNUI0 = 0x400,
INT_TYPE_TMU_TNUI1 = 0x420,
INT_TYPE_TMU_TNUI2 = 0x440,
INT_TYPE_TMU_TICPI2 = 0x460,
INT_TYPE_TMU_TNUI0 = 0x400,
INT_TYPE_TMU_TNUI1 = 0x420,
INT_TYPE_TMU_TNUI2 = 0x440,
INT_TYPE_TMU_TICPI2 = 0x460,
INT_TYPE_FDMA_0_MBOX = 0x1380,
INT_TYPE_FDMA_1_MBOX = 0x13A0,
} intevt_type_t;
typedef enum {
TRA_TYPE_SYSCALL = 34,
} tra_type_t;
__WEAK int tuni0_handler(void) {
/* Does nothing */
return 0;
}
__WEAK int fdma0_mbox_handler(void) {
/* Does nothing */
return 0;
}
__WEAK int fdma1_mbox_handler(void) {
/* Does nothing */
return 0;
}
__WEAK int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
return 0;
}
__WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
tra_type_t tra = CSR->TRA;
tra_type_t tra = CSP->TRA;
switch (tra) {
case TRA_TYPE_SYSCALL:
@ -44,7 +55,7 @@ __WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
}
__WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
expevt_type_t expevt = CSR->EXPEVT;
expevt_type_t expevt = CSP->EXPEVT;
switch (expevt) {
case EXP_TYPE_TRAP:
return trap_handler(p1, p2, p3, p4);
@ -57,11 +68,17 @@ __WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32
}
__WEAK_IRQ int general_int_handler(void) {
intevt_type_t intevt = CSR->INTEVT;
intevt_type_t intevt = CSP->INTEVT;
switch (intevt) {
case INT_TYPE_TMU_TNUI0:
return tuni0_handler();
break;
case INT_TYPE_FDMA_0_MBOX:
return fdma0_mbox_handler();
break;
case INT_TYPE_FDMA_1_MBOX:
return fdma1_mbox_handler();
break;
default:
break;
}

7
tools/fdmafwextract/fdmafwextract.c
View File

@ -2,6 +2,7 @@
#include <fcntl.h>
#include <gelf.h>
#include <libelf.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
@ -70,7 +71,7 @@ static int get_section_idx_by_name(Elf *handle, char *name) {
return -1;
}
static int dump_section_as_c_array(Elf *handle, int idx) {
static int dump_section_as_c_array(Elf *handle, int idx, bool pad_32) {
Elf_Scn *scn = elf_getscn(handle, idx);
if (scn == NULL) {
int es = elf_errno();
@ -141,7 +142,7 @@ int main(int argc, const char *argv[]) {
goto elf_out;
}
ret = dump_section_as_c_array(e_handle, ret);
ret = dump_section_as_c_array(e_handle, ret, true);
ret = get_section_idx_by_name(e_handle, ".data");
if (ret < 0) {
@ -151,7 +152,7 @@ int main(int argc, const char *argv[]) {
goto elf_out;
}
ret = dump_section_as_c_array(e_handle, ret);
ret = dump_section_as_c_array(e_handle, ret, false);
elf_out:
elf_end(e_handle);