Added basic exception handler.
This commit is contained in:
parent
f28dda7542
commit
2de08ba3ee
GPG Key ID:
885EC2B5A8A6F8A7
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@ -8,6 +8,7 @@ set(TARGET_LDSCRIPT "${CMAKE_SOURCE_DIR}/stx7105.ld")
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set(TARGET_SOURCES
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"src/main.c"
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"src/stx7105_exc.c"
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"startup_stx7105.S"
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"startup_stx7105_init_ram.S"
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)
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@ -16,7 +17,7 @@ set(TARGET_INCLUDES
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"include"
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)
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set(TARGET_FLAGS_HARDWARE "-m4-300 -ml")
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set(TARGET_FLAGS_HARDWARE "-m4a -ml")
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set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -g -O0")
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set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -g -O0")
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@ -26,12 +27,12 @@ set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
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set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O2 -flto")
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set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto")
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set(CMAKE_C_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall")
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set(CMAKE_CXX_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall")
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set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall -lc -lm -nostartfiles -Wl,--print-memory-usage")
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set(CMAKE_C_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall -ffunction-sections -fdata-sections")
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set(CMAKE_CXX_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall -ffunction-sections -fdata-sections")
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set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS_HARDWARE} -Wall -lc -lm -nostartfiles -Wl,--print-memory-usage -Wl,--gc-sections")
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add_compile_definitions(TARGET_DEFS)
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include_directories(TARGET_INCLUDES)
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add_compile_definitions(${TARGET_DEFS})
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include_directories(${TARGET_INCLUDES})
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add_executable(${CMAKE_PROJECT_NAME}.elf ${TARGET_SOURCES})
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target_link_options(${CMAKE_PROJECT_NAME}.elf
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@ -0,0 +1,99 @@
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#ifndef STX7105_H
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#define STX7105_H
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#include <stdint.h>
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#define __PACKED __attribute__((packed, aligned(1)))
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#define __IO volatile
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typedef struct __PACKED {
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__IO uint8_t POUT; /* Offset: 0x00, GPIO pin output register */
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__IO uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t SET_POUT; /* Offset: 0x04, GPIO pin output set register */
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__IO uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint8_t CLR_POUT; /* Offset: 0x08, GPIO pin output clear register */
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__IO uint8_t UNUSED2[7]; /* Offset: 0x09 */
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__IO uint8_t PIN; /* Offset: 0x10, GPIO pin input register */
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__IO uint8_t UNUSED3[15]; /* Offset: 0x11 */
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__IO uint8_t PC0; /* Offset: 0x20, GPIO pin config register 0 */
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__IO uint8_t UNUSED4[3]; /* Offset: 0x21 */
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__IO uint8_t SET_PC0; /* Offset: 0x24, GPIO pin config set register 0 */
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__IO uint8_t UNUSED5[3]; /* Offset: 0x25 */
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__IO uint8_t CLR_PC0; /* Offset: 0x28, GPIO pin config clear register 0 */
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__IO uint8_t UNUSED6[7]; /* Offset: 0x29 */
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__IO uint8_t PC1; /* Offset: 0x30, GPIO pin config register 1 */
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__IO uint8_t UNUSED7[3]; /* Offset: 0x31 */
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__IO uint8_t SET_PC1; /* Offset: 0x34, GPIO pin config set register 1 */
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__IO uint8_t UNUSED8[3]; /* Offset: 0x35 */
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__IO uint8_t CLR_PC1; /* Offset: 0x38, GPIO pin config clear register 1 */
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__IO uint8_t UNUSED9[7]; /* Offset: 0x39 */
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__IO uint8_t PC2; /* Offset: 0x40, GPIO pin config register 2 */
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__IO uint8_t UNUSED10[3]; /* Offset: 0x41 */
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__IO uint8_t SET_PC2; /* Offset: 0x44, GPIO pin config set register 2 */
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__IO uint8_t UNUSED11[3]; /* Offset: 0x45 */
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__IO uint8_t CLR_PC2; /* Offset: 0x48, GPIO pin config clear register 2 */
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__IO uint8_t UNUSED12[7]; /* Offset: 0x49 */
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__IO uint8_t PCOMP; /* Offset: 0x50, GPIO pin input comparison register */
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__IO uint8_t UNUSED13[3]; /* Offset: 0x51 */
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__IO uint8_t SET_PCOMP; /* Offset: 0x54, GPIO pin input comparison set regiser */
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__IO uint8_t UNUSED14[3]; /* Offset: 0x55 */
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__IO uint8_t CLR_PCOMP; /* Offset: 0x58, GPIO pin input comparison clear regiser */
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__IO uint8_t UNUSED15[7]; /* Offset: 0x59 */
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__IO uint8_t PMASK; /* Offset: 0x60, GPIO pin input comparison mask register */
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__IO uint8_t UNUSED16[3]; /* Offset: 0x61 */
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__IO uint8_t SET_PMASK; /* Offset: 0x64, GPIO pin input comparison mask set regiser */
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__IO uint8_t UNUSED17[3]; /* Offset: 0x65 */
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__IO uint8_t CLR_PMASK; /* Offset: 0x68, GPIO pin input comparison mask clear regiser */
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} PIO_TypeDef;
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typedef struct __PACKED {
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__IO uint32_t BAUDRATE; /* Offset: 0x00, ASCn baud rate generator register */
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__IO uint32_t TX_BUF; /* Offset: 0x04, ASCn transmit buffer register */
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__IO uint32_t RX_BUF; /* Offset: 0x08, ASCn receive buffer register */
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__IO uint32_t CTRL; /* Offset: 0x0C, ASCn control register */
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__IO uint32_t INT_EN; /* Offset: 0x10, ASCn interrupt enable register */
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__IO uint32_t STA; /* Offset: 0x14, ASCn interrupt status register */
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__IO uint32_t GUARDTIME; /* Offset: 0x18, ASCn guard time register */
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__IO uint32_t TIMEOUT; /* Offset: 0x1C, ASCn time out register */
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__IO uint32_t TX_RST; /* Offset: 0x20, ASCn transmit FIFO reset register */
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__IO uint32_t RX_RST; /* Offset: 0x24, ASCn receive FIFO reset register */
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__IO uint32_t RETRIES; /* Offset: 0x28, ASCn number of retries on transmission register */
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} ASC_TypeDef;
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typedef struct __PACKED {
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__IO uint8_t TOCR; /* Offset: 0x00, Timer output control register */
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__IO uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t TSTR; /* Offset: 0x04, Timer start register */
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__IO uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint32_t TCOR0; /* Offset: 0x08, Timer constant register 0 */
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__IO uint32_t TCNT0; /* Offset: 0x0C, Timer counter 0 */
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__IO uint16_t TCR0; /* Offset: 0x10, Timer control register 0 */
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__IO uint8_t UNUSED2[2]; /* Offset: 0x11 */
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__IO uint32_t TCOR1; /* Offset: 0x14, Timer constant register 1 */
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__IO uint32_t TCNT1; /* Offset: 0x18, Timer counter 1 */
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__IO uint16_t TCR1; /* Offset: 0x1C, Timer control register 1 */
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__IO uint8_t UNUSED3[2]; /* Offset: 0x1D */
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__IO uint32_t TCOR2; /* Offset: 0x20, Timer constant register 2 */
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__IO uint32_t TCNT2; /* Offset: 0x24, Timer counter 2 */
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__IO uint16_t TCR2; /* Offset: 0x28, Timer control register 2 */
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__IO uint8_t UNUSED4[2]; /* Offset: 0x29 */
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__IO uint32_t TCPR2; /* Offset: 0x2C */
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} TMU_TypeDef;
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#define PIO0_BASE (0xFD020000U)
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#define PIO4_BASE (0xFD024000U)
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#define ASC0_BASE (0xFD030000U)
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#define ASC1_BASE (0xFD031000U)
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#define ASC2_BASE (0xFD032000U)
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#define ASC3_BASE (0xFD033000U)
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#define TMU_BASE (0xFFD80000U)
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#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
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#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
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#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
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#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
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#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
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#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
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#define TMU ((TMU_TypeDef *)TMU_BASE)
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#endif
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119
src/main.c
119
src/main.c
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@ -1,82 +1,101 @@
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#include <stdint.h>
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#include <stdio.h>
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#define ST_GPIO0_BASE_ADDR (0xFD020000)
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#define ST_GPIO0_OFFSET_POUT 0x00U
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#define ST_GPIO0_OFFSET_SET_POUT 0x04U
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#define ST_GPIO0_OFFSET_CLR_POUT 0x08U
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#define ST_GPIO0_OFFSET_PC0 0x20U
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#define ST_GPIO0_OFFSET_SET_PC0 0x24U
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#define ST_GPIO0_OFFSET_CLR_PC0 0x28U
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#define ST_GPIO0_OFFSET_PC1 0x30U
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#define ST_GPIO0_OFFSET_SET_PC1 0x34U
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#define ST_GPIO0_OFFSET_CLR_PC1 0x38U
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#define ST_GPIO0_OFFSET_PC2 0x40U
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#define ST_GPIO0_OFFSET_SET_PC2 0x44U
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#define ST_GPIO0_OFFSET_CLR_PC2 0x48U
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#define SH_TMU_BASE_ADDR (0xFFD80000)
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#define SH_TMU_OFFSET_TOCR 0x00U
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#define SH_TMU_OFFSET_TSTR 0x04U
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#define SH_TMU_OFFSET_TCOR0 0x08U
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#define SH_TMU_OFFSET_TCNT0 0x0CU
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#define SH_TMU_OFFSET_TCR0 0x10U
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#define SH_TMU_OFFSET_TCOR1 0x14U
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#define SH_TMU_OFFSET_TCNT1 0x18U
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#define SH_TMU_OFFSET_TCR1 0x1CU
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#define SH_TMU_OFFSET_TCOR2 0x20U
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#define SH_TMU_OFFSET_TCNT2 0x24U
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#define SH_TMU_OFFSET_TCR2 0x28U
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#define SH_TMU_OFFSET_TCPR2 0x2CU
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#include "stx7105.h"
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#define LED_RED_GPIO PIO0
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#define LED_RED_PIN 5U
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#define LED_BLUE_PIN 4U
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static void init_led(uint8_t pin) {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_CLR_PC0) = (1 << pin);
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_SET_PC1) = (1 << pin);
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_CLR_PC2) = (1 << pin);
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#define LED_BLUE_GPIO PIO0
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#define LED_BLUE_PIN 4U
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#define CONSOLE_ASC ASC2
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#define SYSTEM_DEVID (0xFE001000U) /* DEVID */
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#define SYSTEM_CONFIG34 (0xFE001188U) /* PIO4 */
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#define SYSTEM_CONFIG7 (0xFE00111CU) /* RXSEL */
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static void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val);
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static void init_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t init_value) {
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gpiox->CLR_PC0 = 1 << pin;
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gpiox->SET_PC1 = 1 << pin;
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gpiox->CLR_PC2 = 1 << pin;
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set_led(gpiox, pin, init_value);
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}
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static void set_led(uint8_t pin, uint8_t val) {
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static void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val) {
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if (val) {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_SET_POUT) = (1 << pin);
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gpiox->SET_POUT = (1 << pin);
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} else {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_CLR_POUT) = (1 << pin);
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gpiox->CLR_POUT = (1 << pin);
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}
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}
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static void delay_ms(uint32_t msec) {
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/* Initialize TMU and count to zero */
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/* TMU clock is from Peripheral clock, approx. 66MHz */
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/* Prescale to 450kHz for convenience (TMUs can only divide by max. 1024) */
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/* Prescale to 66kHz for convenience (TMUs can only divide by max. 1024) */
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*(uint8_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TSTR) &= ~1U; /* Stop counter */
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*(uint16_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TCR0) = 0x04U; /* 1024 prescale */
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*(uint32_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TCNT0) = (msec * 66); /* 66kHz */
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*(uint8_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TSTR) |= 1U; /* Start counter */
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uint32_t reload_value = msec * 66 - 1;
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TMU->TSTR &= ~1U; /* Stop counter */
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TMU->TCR0 = 0x04U; /* 1024 prescale */
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TMU->TCNT0 = reload_value; /* 66kHz */
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TMU->TCOR0 = reload_value; /* Reload register */
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TMU->TSTR |= 1U; /* Start counter */
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/* Wait until underflow occurs */
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uint16_t tcr0 = 0U;
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do {
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tcr0 = *(uint16_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TCR0);
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tcr0 = TMU->TCR0;
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} while ((tcr0 & 0x100) == 0);
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*(uint8_t *)(SH_TMU_BASE_ADDR + SH_TMU_OFFSET_TSTR) &= ~1U; /* Stop counter */
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TMU->TSTR &= ~1U; /* Stop counter */
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}
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static void uart_init(void) {
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PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
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PIO4->SET_PC1 = 1U;
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PIO4->SET_PC2 = 1U;
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// *(uint32_t *)SYSTEM_CONFIG34 = 0x00000100UL; /* BIT[8,0] = 10, AF 3 */
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// *(uint32_t *)SYSTEM_CONFIG7 &= ~(0x00000006UL); /* BIT[2:1], UART2 RX SEL */
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// CONSOLE_ASC->CTRL = 0x1509UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */
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// CONSOLE_ASC->BAUDRATE = 0x04B8UL; /* 115200 in baud mode 1, assuming Fcomm=100MHz */
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// CONSOLE_ASC->TX_RST = 0x01UL; /* Reset TX FIFO, any value OK */
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// CONSOLE_ASC->RX_RST = 0x01UL; /* Reset RX FIFO, any value OK */
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// CONSOLE_ASC->CTRL = 0x1589UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */
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}
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int main(void) {
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init_led(LED_RED_PIN);
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init_led(LED_BLUE_PIN);
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// init_led(LED_RED_GPIO, LED_RED_PIN, 0U);
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// init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U);
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set_led(LED_RED_PIN, 0);
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set_led(LED_BLUE_PIN, 0);
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// if(*(uint32_t *)SYSTEM_DEVID != 0x2D43E041UL) {
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// set_led(LED_RED_GPIO, LED_RED_PIN, 1U);
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// }
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*(uint32_t *)SYSTEM_CONFIG34 = 0x00000100UL; /* BIT[8,0] = 10, AF 3 */
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uart_init();
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// for (uint16_t i = 0; i < 65534; i++) {
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// CONSOLE_ASC->TX_BUF = i;
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// while (CONSOLE_ASC->STA & 0x200) {
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// /**/
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// }
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// }
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// printf("Hello world\r\n");
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for (;;) {
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/* Dead loop */
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set_led(LED_BLUE_PIN, 1);
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delay_ms(1);
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set_led(LED_BLUE_PIN, 0);
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delay_ms(1);
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// set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 1);
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// delay_ms(1000);
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// set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0);
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// delay_ms(1000);
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}
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}
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@ -0,0 +1,61 @@
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#include "stx7105.h"
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#define EXPEVT_BASE 0xFF000024
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#define TRA_BASE 0xFF000020
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typedef enum {
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EXP_TYPE_TRAP = 0x160,
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} expevt_type_t;
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typedef enum {
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TRA_TYPE_SYSCALL = 34,
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} tra_type_t;
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static int uart_write(char *ptr, int len) {
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for (int i = 0; i < len; i++) {
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while (ASC2->STA & 0x200) {
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/* TX FIFO full... */
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}
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ASC2->TX_BUF = (uint8_t)ptr[i];
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}
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return len;
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}
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static int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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if (p1 == 4) {
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return uart_write((char *)p3, (int)p4);
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}
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return 0;
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}
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static int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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tra_type_t tra = *(uint32_t *)TRA_BASE;
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switch (tra) {
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case TRA_TYPE_SYSCALL:
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return syscall_handler(p1, p2, p3, p4);
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break;
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default:
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break;
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}
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return 0;
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}
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__attribute__((interrupt_handler)) int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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expevt_type_t expevt = *(uint32_t *)EXPEVT_BASE;
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PIO0->SET_POUT = (1 << 5);
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switch (expevt) {
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case EXP_TYPE_TRAP:
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trap_handler(p1, p2, p3, p4);
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break;
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default:
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break;
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}
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return 0;
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}
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@ -30,6 +30,7 @@ _start:
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mov.l r0, @r1
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mov.l _gpio_clr_pc2_k, r1
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mov.l r0, @r1
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mov.l _sr_k, r0
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ldc r0, sr
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mov.l _stack_k, sp /* Setup R15(SP) */
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@ -144,7 +145,12 @@ _enable_se_mode:
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mov.l _ccn_pascr_value_k, r1
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mov.l r1, @r0
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mova _copy_data, r0
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_setup_irq:
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mov.l _exc_base_k, r0
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ldc r0, vbr
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_go_non_privileged:
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mov.l _crt0_entry, r0
|
||||
ldc r0, spc
|
||||
stc sr, r0
|
||||
ldc r0, ssr
|
||||
|
|
@ -162,7 +168,7 @@ _loop_copy_data:
|
|||
mov.l @r0+, r3 /* Load a word to r3 from [sidata], with post-increment of 4 */
|
||||
mov.l r3, @r1 /* Store the word in r3 to [sdata] */
|
||||
add #4, r1 /* Increment sdata pointer */
|
||||
cmp/ge r1, r2
|
||||
cmp/gt r1, r2 /* r2 greater or equal than r1? */
|
||||
bt _loop_copy_data
|
||||
|
||||
_zero_bss:
|
||||
|
|
@ -173,7 +179,7 @@ _zero_bss:
|
|||
_loop_zero_bss:
|
||||
mov.l r2, @r0
|
||||
add #4, r0
|
||||
cmp/ge r0, r1
|
||||
cmp/gt r0, r1
|
||||
bt _loop_zero_bss
|
||||
|
||||
/* Turn on Blue LED */
|
||||
|
|
@ -187,11 +193,6 @@ _setup_fpu:
|
|||
mov #0, r4
|
||||
lds r3, fpscr
|
||||
|
||||
/* Turn on Red LED */
|
||||
mov #32, r7
|
||||
mov.l _gpio_set_k, r8
|
||||
mov.l r7, @r8
|
||||
|
||||
_main_entry:
|
||||
mov.l _main_k, r0
|
||||
jsr @r0
|
||||
|
|
@ -284,6 +285,9 @@ _gpio_set_pc1_k:
|
|||
_gpio_clr_pc2_k:
|
||||
.long 0xFD020048
|
||||
|
||||
_crt0_entry:
|
||||
.long _copy_data
|
||||
|
||||
/* libc FPU routine */
|
||||
_set_fpscr_k:
|
||||
.long ___set_fpscr
|
||||
|
|
@ -307,3 +311,19 @@ _main_k:
|
|||
.long _main /* Same address as main */
|
||||
_exit_k:
|
||||
.long _exit
|
||||
_exc_base_k:
|
||||
.long _exc_base
|
||||
|
||||
|
||||
.section .text.exc, "ax"
|
||||
.align 4
|
||||
_exc_base:
|
||||
.org 0x100, 0x00
|
||||
_exc_grnl_vector:
|
||||
mov.l _exc_grnl_entry, r0
|
||||
jmp @r0
|
||||
nop
|
||||
|
||||
.align 4
|
||||
_exc_grnl_entry:
|
||||
.long _general_exc_handler
|
||||
|
|
@ -15,6 +15,7 @@ SECTIONS {
|
|||
.text : {
|
||||
. = ALIGN(4);
|
||||
*(.text.init)
|
||||
*(.text.exc)
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
|
|
@ -22,23 +23,25 @@ SECTIONS {
|
|||
. = ALIGN(4);
|
||||
} >EMI
|
||||
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.data : {
|
||||
. = ALIGN(4);
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
_edata = .;
|
||||
} >LMI AT >EMI
|
||||
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
_end = ALIGN(8);
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
__end = _end;
|
||||
} >LMI
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
#!/bin/sh
|
||||
|
||||
IMAGE_NAME=$1
|
||||
|
||||
if [ -z "${IMAGE_NAME}" ] ; then
|
||||
IMAGE_NAME=image.bin
|
||||
fi
|
||||
|
||||
if [ ! -f "${IMAGE_NAME}" ] ; then
|
||||
echo "binary not exist."
|
||||
exit -1
|
||||
fi
|
||||
|
||||
flashrom --programmer ch341a_spi -w "${IMAGE_NAME}"
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#!/bin/sh
|
||||
|
||||
FLASH_SIZE=1048576
|
||||
|
||||
INPUT_IMAGE="$1"
|
||||
BINARY_NAME="$2"
|
||||
|
||||
# ELF name not a valid name.
|
||||
if [ ! -f "${INPUT_IMAGE}" ] ; then
|
||||
echo "No such file."
|
||||
exit -1
|
||||
fi
|
||||
|
||||
# Output name not set..
|
||||
if [ -z "${BINARY_NAME}" ] ; then
|
||||
echo "Binary name not set, using default"
|
||||
BINARY_NAME="image.bin"
|
||||
fi
|
||||
|
||||
# Create binary file from ELF
|
||||
sh-unknown-elf-objcopy -O binary ${INPUT_IMAGE} ${BINARY_NAME}
|
||||
if [ "$?" -lt "0" ] ; then
|
||||
exit -2
|
||||
fi
|
||||
|
||||
# Calculate size and padding length
|
||||
BINARY_SIZE=`stat --format "%s" ${BINARY_NAME}`
|
||||
PAD_SIZE=$((${FLASH_SIZE} - ${BINARY_SIZE}))
|
||||
|
||||
echo "Output binary size: ${BINARY_SIZE}, additional padding: ${PAD_SIZE}."
|
||||
|
||||
# Pad output file using `dd`
|
||||
tr '\0' '\377' < /dev/zero | dd bs=1 count=${PAD_SIZE} of=${BINARY_NAME} conv=notrunc seek=${BINARY_SIZE}
|
||||
Loading…
Reference in New Issue