Initial interrupt routine support.
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9c9ea29157
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@ -80,6 +80,29 @@ typedef struct {
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uint32_t TCPR2; /* Offset: 0x2C */
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} TMU_TypeDef;
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typedef struct {
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__IO uint32_t PTEH; /* Offset: 0x00, Page table entry high register */
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__IO uint32_t PTEL; /* Offset: 0x04, Page table entry low register */
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__IO uint32_t TTB; /* Offset: 0x08, Translation table base register */
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__IO uint32_t TEA; /* Offset: 0x0C, TLB exception address register */
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__IO uint32_t MMUCR; /* Offset: 0x10, MMU control register */
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__IO uint8_t BASRA; /* Offset: 0x14, Break ASID register A*/
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uint8_t UNUSED0[3]; /* Offset: 0x15 */
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__IO uint8_t BASRB; /* Offset: 0x18, Break ASID register B*/
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uint8_t UNUSED1[3]; /* Offset: 0x19 */
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__IO uint32_t CCR; /* Offset: 0x1C, Cache control register */
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__IO uint32_t TRA; /* Offset: 0x20, TRAPA exception register */
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__IO uint32_t EXPEVT; /* Offset: 0x24, Exception event register */
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__IO uint32_t INTEVT; /* Offset: 0x28, Interrupt event register */
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uint32_t UNUSED2[3]; /* Offset: 0x2C */
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__IO uint32_t QACR0; /* Offset: 0x38, Queue address control register 0 */
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__IO uint32_t QACR1; /* Offset: 0x3C, Queue address control register 1 */
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uint32_t UNUSED3[12]; /* Offset: 0x40 */
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__IO uint32_t PASCR; /* Offset: 0x70, Physical address space control register */
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__IO uint32_t RAMCR; /* Offset: 0x74, On-chip memory control register */
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__IO uint32_t IRMCR; /* Offset: 0x78, Instruction refetch inhibit control register */
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} CSR_TypeDef;
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#define XX sizeof(TMU_TypeDef)
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#define PIO0_BASE (0xFD020000U)
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@ -88,6 +111,7 @@ typedef struct {
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#define ASC1_BASE (0xFD031000U)
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#define ASC2_BASE (0xFD032000U)
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#define ASC3_BASE (0xFD033000U)
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#define CSR_BASE (0xFF000000U)
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#define TMU_BASE (0xFFD80000U)
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#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
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@ -96,6 +120,7 @@ typedef struct {
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#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
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#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
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#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
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#define CSR ((CSR_TypeDef *)CSR_BASE)
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#define TMU ((TMU_TypeDef *)TMU_BASE)
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#endif
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@ -0,0 +1,13 @@
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# The magic number below is the point where bootloader has completed initializing the LMI.
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define box_setup
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sh4tp STMCLT2333_A:iptv7105:st40,no_pokes=1
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hbreak *0xA000008C
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continue
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delete breakpoint 1
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load
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hbreak _main
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end
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box_setup
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@ -1,12 +1,17 @@
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#include "stx7105.h"
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#define EXPEVT_BASE 0xFF000024
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#define TRA_BASE 0xFF000020
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#define __WEAK __attribute__((weak))
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#define __IRQ __attribute__((interrupt_handler))
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#define __WEAK_IRQ __attribute__((weak, interrupt_handler))
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typedef enum {
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EXP_TYPE_TRAP = 0x160,
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} expevt_type_t;
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typedef enum {
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INT_TYPE_TMU = 0x000,
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} intevt_type_t;
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typedef enum {
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TRA_TYPE_SYSCALL = 34,
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} tra_type_t;
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@ -22,7 +27,7 @@ static int uart_write(char *ptr, int len) {
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return len;
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}
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static int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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__WEAK int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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if (p1 == 4) {
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return uart_write((char *)p3, (int)p4);
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}
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@ -30,8 +35,8 @@ static int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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return 0;
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}
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static int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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tra_type_t tra = *(uint32_t *)TRA_BASE;
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__WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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tra_type_t tra = CSR->TRA;
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switch (tra) {
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case TRA_TYPE_SYSCALL:
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@ -44,11 +49,8 @@ static int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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return 0;
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}
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__attribute__((interrupt_handler)) int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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expevt_type_t expevt = *(uint32_t *)EXPEVT_BASE;
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PIO0->SET_POUT = (1 << 5);
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__WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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expevt_type_t expevt = CSR->EXPEVT;
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switch (expevt) {
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case EXP_TYPE_TRAP:
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trap_handler(p1, p2, p3, p4);
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@ -57,5 +59,9 @@ __attribute__((interrupt_handler)) int general_exc_handler(uint32_t p1, uint32_t
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break;
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}
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return 0;
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}
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__WEAK_IRQ int general_int_handler(void) {
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return 0;
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}
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@ -1,7 +1,8 @@
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/*
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* This section is read by bootloader, then the application will be copied.
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* DO NOT REMOVE.
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* See SPL README for details.
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* This section is read by bootloader,
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* then the application will be copied according to the contents.
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* !!DO NOT REMOVE!!
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* See SPL project README for details.
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*/
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.section .text.vtors, "ax"
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@ -9,12 +10,10 @@ _vtors:
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.long _eidata
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.long _start
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/* Startup code, we can't use non-PIC code nor RAM before the LMI is initialized:
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* The CPU starts with physical address 0x0, however the linker is linked to virtual
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* addresses and LMI.
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* Non-PIC code means any indirect addressing other than relative to PC.
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/*
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* Startup code (CRT0)
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*/
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.section .text.init
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.section .text.init, "ax"
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.global _start
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_start:
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@ -49,6 +48,15 @@ _setup_fpu:
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mov #0, r4
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lds r3, fpscr
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_setup_irq:
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mov.l _exc_base_k, r0
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ldc r0, vbr
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stc sr, r0 /* Store SR into R0 */
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mov.l _exc_imask_k, r1
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and r1, r0
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ldc r0, sr
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.align 2
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_main_entry:
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mov.l _main_k, r0
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@ -84,17 +92,34 @@ _exit_k:
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.long _exit
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_exc_base_k:
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.long _exc_base
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_exc_imask_k:
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.long 0xFFFFFF0F /* Clear IMASK (SR[7:4]) to 0, enable all exception levels */
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/*
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* Exception handlers
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* These handlers are placed at VBR related addresses
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*/
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.section .text.exc, "ax"
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.align 4
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_exc_base:
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.org 0x100, 0x00
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_exc_grnl_vector:
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mov.l _exc_grnl_entry, r0
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mov.l _exc_grnl_entry_k, r0
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jmp @r0
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nop
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.align 4
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_exc_grnl_entry:
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.long _general_exc_handler
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_exc_grnl_entry_k:
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.long _general_exc_handler
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_int_base:
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.org 0x600, 0x00
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_int_grnl_vector:
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mov.l _int_grnl_entry_k, r0
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jmp @r0
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nop
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.align 4
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_int_grnl_entry_k:
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.long _general_int_handler
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