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Updated struct names.

This commit is contained in:
imi415 2022-09-04 19:47:08 +08:00
parent 2c021cbf5f
commit 782308d696
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
2 changed files with 95 additions and 37 deletions
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126
include/stx7105.h
View File

@ -129,46 +129,92 @@ typedef struct {
__IO uint32_t BDMRB; /* Offset: 0x2001C, Break data mask register B */
__IO uint16_t BRCR; /* Offset: 0x20020, Break control register */
uint8_t UNUSED9[2]; /* Offset: 0x20022 */
} CSR_TypeDef;
} CSP_TypeDef;
/* drivers/stm/stx7105.c */
typedef struct {
__IO uint32_t SLIM_ID; /* Offset: 0x0000, SLIM CPU ID register */
__IO uint32_t SLIM_VER; /* Offset: 0x0004, SLIM CPU version register */
__IO uint32_t SLIM_EN; /* Offset: 0x0008, SLIM CPU enable control register */
__IO uint32_t SLIM_CLK_GATE; /* Offset: 0x000C, SLIM CPU clock gate register */
__IO uint32_t SLIM_ID; /* Offset: 0x0000, SLIM CPU ID register */
__IO uint32_t SLIM_VER; /* Offset: 0x0004, SLIM CPU version register */
__IO uint32_t SLIM_EN; /* Offset: 0x0008, SLIM CPU enable control register */
__IO uint32_t SLIM_CLK_GATE; /* Offset: 0x000C, SLIM CPU clock gate register */
uint32_t UNUSED0[8188]; /* Offset: 0x0010 */
__IO uint8_t SLIM_DMEM[8192]; /* Offset: 0x8000, SLIM CPU data memory */
uint32_t UNUSED1[2018]; /* Offset: 0xA000 */
__IO uint32_t PERIPH_STBUS_SYNC; /* Offset: 0xBF88, STBus sync control register */
uint32_t UNUSED2[13]; /* Offset: 0xBF8C */
__IO uint32_t PERIPH_CMD_STA; /* Offset: 0xBFC0, Command mailbox */
__IO uint32_t PERIPH_CMD_SET; /* Offset: 0xBFC4, Command mailbox */
__IO uint32_t PERIPH_CMD_CLR; /* Offset: 0xBFC8, Command mailbox */
__IO uint32_t PERIPH_CMD_MASK; /* Offset: 0xBFCC, Command mailbox */
__IO uint32_t PERIPH_INT_STA; /* Offset: 0xBFD0, Interrupt mailbox */
__IO uint32_t PERIPH_INT_SET; /* Offset: 0xBFD4, Interrupt mailbox */
__IO uint32_t PERIPH_INT_CLR; /* Offset: 0xBFD8, Interrupt mailbox */
__IO uint32_t PERIPH_INT_MASK; /* Offset: 0xBFDC, Interrupt mailbox */
uint32_t UNUSED3[8]; /* Offset: 0xBFE0 */
__IO uint8_t SLIM_IMEM[16384]; /* Offset: 0xC000, SLIM CPU instruction memory */
} FDMA_TypeDef;
#define PIO0_BASE (0xFD020000U)
#define PIO1_BASE (0xFD021000U)
#define PIO2_BASE (0xFD022000U)
#define PIO3_BASE (0xFD023000U)
#define PIO4_BASE (0xFD024000U)
#define PIO5_BASE (0xFD025000U)
#define PIO6_BASE (0xFD026000U)
#define ASC0_BASE (0xFD030000U)
#define ASC1_BASE (0xFD031000U)
#define ASC2_BASE (0xFD032000U)
#define ASC3_BASE (0xFD033000U)
#define FDMA0_BASE (0xFE220000U)
#define CSR_BASE (0xFF000000U)
#define INTC_BASE (0xFFD00000U)
#define TMU_BASE (0xFFD80000U)
/* WARNING: THE CLKGENA is different from other ST40s' */
typedef struct {
__IO uint32_t PLL0_CFG; /* Offset: 0x0000 */
__IO uint32_t PLL1_CFG; /* Offset: 0x0004 */
uint32_t UNUSED0[2]; /* Offset: 0x0008 */
__IO uint32_t POWER_CFG; /* Offset: 0x0010 */
__IO uint32_t CLKOPSRC_SWITCH_CFG; /* Offset: 0x0014 */
uint32_t UNUSED1[4]; /* Offset: 0x0018 */
__IO uint32_t CLKOPSRC_SWITCH_CFG2; /* Offset: 0x0024 */
uint32_t UNUSED2[2]; /* Offset: 0x0028 */
__IO uint32_t CLKOBS_MUX1_CFG; /* Offset: 0x0030 */
__IO uint32_t CLKOBS_MASTER_MAXCOUNT; /* Offset: 0x0034 */
__IO uint32_t CLKOBS_CMD; /* Offset: 0x0038 */
__IO uint32_t CLKOBS_STATUS; /* Offset: 0x003C */
__IO uint32_t CLKOBS_SLAVE0_COUNT; /* Offset: 0x0040 */
__IO uint32_t OSCMUX_DEBUG; /* Offset: 0x0044 */
__IO uint32_t CLKOBS_MUX2_CFG; /* Offset: 0x0048 */
__IO uint32_t LOW_POWER_CTRL; /* Offset: 0x004C */
} CKGA_TypeDef;
#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
#define CSR ((CSR_TypeDef *)CSR_BASE)
#define PIO0_BASE (0xFD020000U)
#define PIO1_BASE (0xFD021000U)
#define PIO2_BASE (0xFD022000U)
#define PIO3_BASE (0xFD023000U)
#define PIO4_BASE (0xFD024000U)
#define PIO5_BASE (0xFD025000U)
#define PIO6_BASE (0xFD026000U)
#define ASC0_BASE (0xFD030000U)
#define ASC1_BASE (0xFD031000U)
#define ASC2_BASE (0xFD032000U)
#define ASC3_BASE (0xFD033000U)
#define CKGA_BASE (0xFE213000U)
#define FDMA0_BASE (0xFE220000U)
#define FDMA1_BASE (0xFE410000U)
#define CSP_BASE (0xFF000000U)
#define INTC_BASE (0xFFD00000U)
#define TMU_BASE (0xFFD80000U)
#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
#define CKGA ((CKGA_TypeDef *)CKGA_BASE)
#define FDMA0 ((FDMA_TypeDef *)FDMA0_BASE)
#define INTC ((INTC_TypeDef *)INTC_BASE)
#define TMU ((TMU_TypeDef *)TMU_BASE)
#define FDMA1 ((FDMA_TypeDef *)FDMA1_BASE)
#define CSP ((CSP_TypeDef *)CSP_BASE)
#define INTC ((INTC_TypeDef *)INTC_BASE)
#define TMU ((TMU_TypeDef *)TMU_BASE)
#define TMU_TSTR_STR0_Pos 0
#define TMU_TSTR_STR0_Msk (1U << TMU_TSTR_STR0_Pos)
@ -188,4 +234,16 @@ typedef struct {
#define INTC_IPRA_IPR_TMU0_Pos 12
#define INTC_IPRA_IPR_TMU0_Msk (0x0FU << INTC_IPRA_IPR_TMU0_Pos)
#define FDMA_SLIM_EN_RUN_Pos 0
#define FDMA_SLIM_EN_RUN_Msk (1U << FDMA_SLIM_EN_RUN_Pos)
#define FDMA_SLIM_CLK_GATE_DIS_Pos 0
#define FDMA_SLIM_CLK_GATE_DIS_Msk (1U << FDMA_SLIM_CLK_GATE_DIS_Pos)
#define FDMA_SLIM_CLK_GATE_RESET_Pos 2
#define FDMA_SLIM_CLK_GATE_RESET_Msk (1U << FDMA_SLIM_CLK_GATE_RESET_Pos)
#define FDMA_PERIPH_STBUS_SYNC_DIS_Pos 0
#define FDMA_PERIPH_STBUS_SYNC_DIS_Msk (1U << FDMA_PERIPH_STBUS_SYNC_DIS_Pos)
#endif

6
src/stx7105_exc.c
View File

@ -30,7 +30,7 @@ __WEAK int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
}
__WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
tra_type_t tra = CSR->TRA;
tra_type_t tra = CSP->TRA;
switch (tra) {
case TRA_TYPE_SYSCALL:
@ -44,7 +44,7 @@ __WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
}
__WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
expevt_type_t expevt = CSR->EXPEVT;
expevt_type_t expevt = CSP->EXPEVT;
switch (expevt) {
case EXP_TYPE_TRAP:
return trap_handler(p1, p2, p3, p4);
@ -57,7 +57,7 @@ __WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32
}
__WEAK_IRQ int general_int_handler(void) {
intevt_type_t intevt = CSR->INTEVT;
intevt_type_t intevt = CSP->INTEVT;
switch (intevt) {
case INT_TYPE_TMU_TNUI0:
return tuni0_handler();